2 * Copyright (c) 2010 Isilon Systems, Inc.
3 * Copyright (c) 2010 iX Systems, Inc.
4 * Copyright (c) 2010 Panasas, Inc.
5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #define CONFIG_PCI_MSI
36 #include <linux/types.h>
38 #include <sys/param.h>
40 #include <sys/pciio.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pci_private.h>
46 #include <machine/resource.h>
48 #include <linux/list.h>
49 #include <linux/dmapool.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/compiler.h>
52 #include <linux/errno.h>
53 #include <asm/atomic.h>
54 #include <linux/device.h>
56 struct pci_device_id {
62 uintptr_t driver_data;
65 #define MODULE_DEVICE_TABLE(bus, table)
66 #define PCI_ANY_ID (-1)
67 #define PCI_VENDOR_ID_APPLE 0x106b
68 #define PCI_VENDOR_ID_ASUSTEK 0x1043
69 #define PCI_VENDOR_ID_ATI 0x1002
70 #define PCI_VENDOR_ID_DELL 0x1028
71 #define PCI_VENDOR_ID_HP 0x103c
72 #define PCI_VENDOR_ID_IBM 0x1014
73 #define PCI_VENDOR_ID_INTEL 0x8086
74 #define PCI_VENDOR_ID_MELLANOX 0x15b3
75 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
76 #define PCI_VENDOR_ID_SERVERWORKS 0x1166
77 #define PCI_VENDOR_ID_SONY 0x104d
78 #define PCI_VENDOR_ID_TOPSPIN 0x1867
79 #define PCI_VENDOR_ID_VIA 0x1106
80 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
81 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
82 #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
83 #define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46
84 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
85 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282
86 #define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
87 #define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274
88 #define PCI_SUBDEVICE_ID_QEMU 0x1100
90 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
91 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
92 #define PCI_FUNC(devfn) ((devfn) & 0x07)
94 #define PCI_VDEVICE(_vendor, _device) \
95 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \
96 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
97 #define PCI_DEVICE(_vendor, _device) \
98 .vendor = (_vendor), .device = (_device), \
99 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
101 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
103 #define PCI_VENDOR_ID PCIR_DEVVENDOR
104 #define PCI_COMMAND PCIR_COMMAND
105 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */
106 #define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */
107 #define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */
108 #define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */
109 #define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */
110 #define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */
111 #define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */
112 #define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */
113 #define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */
114 #define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */
115 #define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */
116 #define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */
117 #define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */
118 #define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */
119 #define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */
120 #define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */
121 #define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */
122 #define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */
123 #define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */
124 #define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */
125 #define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */
126 #define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */
127 #define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */
128 #define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */
129 #define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */
130 #define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */
131 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */
132 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */
133 #define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */
134 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */
135 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */
136 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */
138 #define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD
139 #define PCI_EXP_LNKCAP_CLKPM 0x00040000
140 #define PCI_EXP_DEVSTA_TRPND 0x0020
142 #define IORESOURCE_MEM (1 << SYS_RES_MEMORY)
143 #define IORESOURCE_IO (1 << SYS_RES_IOPORT)
144 #define IORESOURCE_IRQ (1 << SYS_RES_IRQ)
147 PCI_SPEED_UNKNOWN = -1,
153 enum pcie_link_width {
154 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
157 typedef int pci_power_t;
159 #define PCI_D0 PCI_POWERSTATE_D0
160 #define PCI_D1 PCI_POWERSTATE_D1
161 #define PCI_D2 PCI_POWERSTATE_D2
162 #define PCI_D3hot PCI_POWERSTATE_D3
165 #define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN
170 struct list_head links;
172 const struct pci_device_id *id_table;
173 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
174 void (*remove)(struct pci_dev *dev);
175 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
176 int (*resume) (struct pci_dev *dev); /* Device woken up */
177 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */
180 const struct pci_error_handlers *err_handler;
183 extern struct list_head pci_drivers;
184 extern struct list_head pci_devices;
185 extern spinlock_t pci_lock;
187 #define __devexit_p(x) x
191 struct list_head links;
192 struct pci_driver *pdrv;
201 static inline struct resource_list_entry *
202 linux_pci_get_rle(struct pci_dev *pdev, int type, int rid)
204 struct pci_devinfo *dinfo;
205 struct resource_list *rl;
207 dinfo = device_get_ivars(pdev->dev.bsddev);
208 rl = &dinfo->resources;
209 return resource_list_find(rl, type, rid);
212 static inline struct resource_list_entry *
213 linux_pci_get_bar(struct pci_dev *pdev, int bar)
215 struct resource_list_entry *rle;
218 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL)
219 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar);
223 static inline struct device *
224 linux_pci_find_irq_dev(unsigned int irq)
226 struct pci_dev *pdev;
227 struct device *found;
230 spin_lock(&pci_lock);
231 list_for_each_entry(pdev, &pci_devices, links) {
232 if (irq == pdev->dev.irq ||
233 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) {
238 spin_unlock(&pci_lock);
242 static inline unsigned long
243 pci_resource_start(struct pci_dev *pdev, int bar)
245 struct resource_list_entry *rle;
247 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
252 static inline unsigned long
253 pci_resource_len(struct pci_dev *pdev, int bar)
255 struct resource_list_entry *rle;
257 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
263 pci_resource_type(struct pci_dev *pdev, int bar)
267 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar));
271 if (PCI_BAR_IO(pm->pm_value))
272 return (SYS_RES_IOPORT);
274 return (SYS_RES_MEMORY);
278 * All drivers just seem to want to inspect the type not flags.
281 pci_resource_flags(struct pci_dev *pdev, int bar)
285 type = pci_resource_type(pdev, bar);
291 static inline const char *
292 pci_name(struct pci_dev *d)
295 return device_get_desc(d->dev.bsddev);
299 pci_get_drvdata(struct pci_dev *pdev)
302 return dev_get_drvdata(&pdev->dev);
306 pci_set_drvdata(struct pci_dev *pdev, void *data)
309 dev_set_drvdata(&pdev->dev, data);
313 pci_enable_device(struct pci_dev *pdev)
316 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
317 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
322 pci_disable_device(struct pci_dev *pdev)
325 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT);
326 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY);
330 pci_set_master(struct pci_dev *pdev)
333 pci_enable_busmaster(pdev->dev.bsddev);
338 pci_set_power_state(struct pci_dev *pdev, int state)
341 pci_set_powerstate(pdev->dev.bsddev, state);
346 pci_clear_master(struct pci_dev *pdev)
349 pci_disable_busmaster(pdev->dev.bsddev);
354 pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
359 type = pci_resource_type(pdev, bar);
363 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid,
370 pci_release_region(struct pci_dev *pdev, int bar)
372 struct resource_list_entry *rle;
374 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL)
376 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res);
380 pci_release_regions(struct pci_dev *pdev)
384 for (i = 0; i <= PCIR_MAX_BAR_0; i++)
385 pci_release_region(pdev, i);
389 pci_request_regions(struct pci_dev *pdev, const char *res_name)
394 for (i = 0; i <= PCIR_MAX_BAR_0; i++) {
395 error = pci_request_region(pdev, i, res_name);
396 if (error && error != -ENODEV) {
397 pci_release_regions(pdev);
405 pci_disable_msix(struct pci_dev *pdev)
408 pci_release_msi(pdev->dev.bsddev);
411 static inline bus_addr_t
412 pci_bus_address(struct pci_dev *pdev, int bar)
415 return (pci_resource_start(pdev, bar));
418 #define PCI_CAP_ID_EXP PCIY_EXPRESS
419 #define PCI_CAP_ID_PCIX PCIY_PCIX
420 #define PCI_CAP_ID_AGP PCIY_AGP
421 #define PCI_CAP_ID_PM PCIY_PMG
423 #define PCI_EXP_DEVCTL PCIER_DEVICE_CTL
424 #define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
425 #define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST
426 #define PCI_EXP_LNKCTL PCIER_LINK_CTL
427 #define PCI_EXP_LNKSTA PCIER_LINK_STA
430 pci_find_capability(struct pci_dev *pdev, int capid)
434 if (pci_find_cap(pdev->dev.bsddev, capid, ®))
439 static inline int pci_pcie_cap(struct pci_dev *dev)
441 return pci_find_capability(dev, PCI_CAP_ID_EXP);
446 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val)
449 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);
454 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val)
457 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2);
462 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val)
465 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4);
470 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val)
473 pci_write_config(pdev->dev.bsddev, where, val, 1);
478 pci_write_config_word(struct pci_dev *pdev, int where, u16 val)
481 pci_write_config(pdev->dev.bsddev, where, val, 2);
486 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val)
489 pci_write_config(pdev->dev.bsddev, where, val, 4);
493 extern int pci_register_driver(struct pci_driver *pdrv);
494 extern void pci_unregister_driver(struct pci_driver *pdrv);
502 * Enable msix, positive errors indicate actual number of available
503 * vectors. Negative errors are failures.
505 * NB: define added to prevent this definition of pci_enable_msix from
506 * clashing with the native FreeBSD version.
508 #define pci_enable_msix linux_pci_enable_msix
510 pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq)
512 struct resource_list_entry *rle;
517 avail = pci_msix_count(pdev->dev.bsddev);
524 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0)
527 * Handle case where "pci_alloc_msix()" may allocate less
528 * interrupts than available and return with no error:
531 pci_release_msi(pdev->dev.bsddev);
534 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1);
535 pdev->dev.msix = rle->start;
536 pdev->dev.msix_max = rle->start + avail;
537 for (i = 0; i < nreq; i++)
538 entries[i].vector = pdev->dev.msix + i;
542 #define pci_enable_msix_range linux_pci_enable_msix_range
544 pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
545 int minvec, int maxvec)
554 rc = pci_enable_msix(dev, entries, nvec);
566 static inline int pci_channel_offline(struct pci_dev *pdev)
571 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
575 static inline void pci_disable_sriov(struct pci_dev *dev)
579 #define DEFINE_PCI_DEVICE_TABLE(_table) \
580 const struct pci_device_id _table[] __devinitdata
583 /* XXX This should not be necessary. */
584 #define pcix_set_mmrbc(d, v) 0
585 #define pcix_get_max_mmrbc(d) 0
586 #define pcie_set_readrq(d, v) 0
588 #define PCI_DMA_BIDIRECTIONAL 0
589 #define PCI_DMA_TODEVICE 1
590 #define PCI_DMA_FROMDEVICE 2
591 #define PCI_DMA_NONE 3
593 #define pci_pool dma_pool
594 #define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__)
595 #define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__)
596 #define pci_pool_free(...) dma_pool_free(__VA_ARGS__)
597 #define pci_pool_create(_name, _pdev, _size, _align, _alloc) \
598 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc)
599 #define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \
600 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
601 _size, _vaddr, _dma_handle)
602 #define pci_map_sg(_hwdev, _sg, _nents, _dir) \
603 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
604 _sg, _nents, (enum dma_data_direction)_dir)
605 #define pci_map_single(_hwdev, _ptr, _size, _dir) \
606 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \
607 (_ptr), (_size), (enum dma_data_direction)_dir)
608 #define pci_unmap_single(_hwdev, _addr, _size, _dir) \
609 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
610 _addr, _size, (enum dma_data_direction)_dir)
611 #define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \
612 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
613 _sg, _nents, (enum dma_data_direction)_dir)
614 #define pci_map_page(_hwdev, _page, _offset, _size, _dir) \
615 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\
616 _offset, _size, (enum dma_data_direction)_dir)
617 #define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \
618 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \
619 _dma_address, _size, (enum dma_data_direction)_dir)
620 #define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask))
621 #define pci_dma_mapping_error(_pdev, _dma_addr) \
622 dma_mapping_error(&(_pdev)->dev, _dma_addr)
623 #define pci_set_consistent_dma_mask(_pdev, _mask) \
624 dma_set_coherent_mask(&(_pdev)->dev, (_mask))
625 #define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x);
626 #define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x);
627 #define pci_unmap_addr dma_unmap_addr
628 #define pci_unmap_addr_set dma_unmap_addr_set
629 #define pci_unmap_len dma_unmap_len
630 #define pci_unmap_len_set dma_unmap_len_set
632 typedef unsigned int __bitwise pci_channel_state_t;
633 typedef unsigned int __bitwise pci_ers_result_t;
635 enum pci_channel_state {
636 pci_channel_io_normal = 1,
637 pci_channel_io_frozen = 2,
638 pci_channel_io_perm_failure = 3,
641 enum pci_ers_result {
642 PCI_ERS_RESULT_NONE = 1,
643 PCI_ERS_RESULT_CAN_RECOVER = 2,
644 PCI_ERS_RESULT_NEED_RESET = 3,
645 PCI_ERS_RESULT_DISCONNECT = 4,
646 PCI_ERS_RESULT_RECOVERED = 5,
650 /* PCI bus error event callbacks */
651 struct pci_error_handlers {
652 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
653 enum pci_channel_state error);
654 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
655 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
656 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
657 void (*resume)(struct pci_dev *dev);
660 /* FreeBSD does not support SRIOV - yet */
661 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
666 static inline bool pci_is_pcie(struct pci_dev *dev)
668 return !!pci_pcie_cap(dev);
671 static inline u16 pcie_flags_reg(struct pci_dev *dev)
676 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
680 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16);
686 static inline int pci_pcie_type(struct pci_dev *dev)
688 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
691 static inline int pcie_cap_version(struct pci_dev *dev)
693 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS;
696 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev)
698 int type = pci_pcie_type(dev);
700 return pcie_cap_version(dev) > 1 ||
701 type == PCI_EXP_TYPE_ROOT_PORT ||
702 type == PCI_EXP_TYPE_ENDPOINT ||
703 type == PCI_EXP_TYPE_LEG_END;
706 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev)
711 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev)
713 int type = pci_pcie_type(dev);
715 return pcie_cap_version(dev) > 1 ||
716 type == PCI_EXP_TYPE_ROOT_PORT ||
717 (type == PCI_EXP_TYPE_DOWNSTREAM &&
718 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT);
721 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev)
723 int type = pci_pcie_type(dev);
725 return pcie_cap_version(dev) > 1 ||
726 type == PCI_EXP_TYPE_ROOT_PORT ||
727 type == PCI_EXP_TYPE_RC_EC;
730 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
732 if (!pci_is_pcie(dev))
736 case PCI_EXP_FLAGS_TYPE:
741 return pcie_cap_has_devctl(dev);
745 return pcie_cap_has_lnkctl(dev);
749 return pcie_cap_has_sltctl(dev);
753 return pcie_cap_has_rtctl(dev);
754 case PCI_EXP_DEVCAP2:
755 case PCI_EXP_DEVCTL2:
756 case PCI_EXP_LNKCAP2:
757 case PCI_EXP_LNKCTL2:
758 case PCI_EXP_LNKSTA2:
759 return pcie_cap_version(dev) > 1;
766 pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
771 if (!pcie_capability_reg_implemented(dev, pos))
774 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
778 pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst)
783 if (!pcie_capability_reg_implemented(dev, pos))
786 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst);
790 pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
795 if (!pcie_capability_reg_implemented(dev, pos))
798 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
801 static inline int pcie_get_minimum_link(struct pci_dev *dev,
802 enum pci_bus_speed *speed, enum pcie_link_width *width)
804 *speed = PCI_SPEED_UNKNOWN;
805 *width = PCIE_LNK_WIDTH_UNKNOWN;
810 pci_num_vf(struct pci_dev *dev)
815 #endif /* _LINUX_PCI_H_ */