2 ********************************************************************************
3 Copyright (C) 2015 Annapurna Labs Ltd.
5 This file may be licensed under the terms of the Annapurna Labs Commercial
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
12 Alternatively, redistribution and use in source and binary forms, with or
13 without modification, are permitted provided that the following conditions are
16 * Redistributions of source code must retain the above copyright notice,
17 this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in
21 the documentation and/or other materials provided with the
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *******************************************************************************/
38 #ifndef __AL_PCIE_HAL_AXI_REG_H__
39 #define __AL_PCIE_HAL_AXI_REG_H__
41 #include "al_hal_plat_types.h"
52 struct al_pcie_rev1_2_axi_ctrl {
63 uint32_t master_arctl;
65 uint32_t master_awctl;
78 struct al_pcie_rev3_axi_ctrl {
89 uint32_t master_arctl;
91 uint32_t master_awctl;
103 struct al_pcie_rev1_axi_ob_ctrl {
105 uint32_t cfg_target_bus;
107 uint32_t cfg_control;
117 uint32_t msg_start_l;
119 uint32_t msg_start_h;
121 uint32_t msg_limit_l;
123 uint32_t msg_limit_h;
126 struct al_pcie_rev2_axi_ob_ctrl {
128 uint32_t cfg_target_bus;
130 uint32_t cfg_control;
140 uint32_t msg_start_l;
142 uint32_t msg_start_h;
144 uint32_t msg_limit_l;
146 uint32_t msg_limit_h;
148 * [0x28] this register override the Target-ID field in the AXUSER [19:4],
149 * for the AXI master port.
151 uint32_t tgtid_reg_ovrd;
152 /* [0x2c] this register override the ADDR[63:32] AXI master port. */
153 uint32_t addr_high_reg_ovrd_value;
154 /* [0x30] this register override the ADDR[63:32] AXI master port. */
155 uint32_t addr_high_reg_ovrd_sel;
157 * [0x34] Define the size to replace in the master axi address bits
160 uint32_t addr_size_replace;
163 struct al_pcie_rev3_axi_ob_ctrl {
165 uint32_t cfg_target_bus;
167 uint32_t cfg_control;
177 uint32_t aw_msg_start_l;
179 uint32_t aw_msg_start_h;
181 uint32_t aw_msg_limit_l;
183 uint32_t aw_msg_limit_h;
185 uint32_t ar_msg_start_l;
187 uint32_t ar_msg_start_h;
189 uint32_t ar_msg_limit_l;
191 uint32_t ar_msg_limit_h;
193 uint32_t io_addr_mask_h;
195 uint32_t ar_msg_addr_mask_h;
197 uint32_t aw_msg_addr_mask_h;
199 * [0x44] this register override the Target-ID field in the AXUSER [19:4],
200 * for the AXI master port.
202 uint32_t tgtid_reg_ovrd;
203 /* [0x48] this register override the ADDR[63:32] AXI master port. */
204 uint32_t addr_high_reg_ovrd_value;
205 /* [0x4c] this register override the ADDR[63:32] AXI master port. */
206 uint32_t addr_high_reg_ovrd_sel;
208 * [0x50] Define the size to replace in the master axi address bits
211 uint32_t addr_size_replace;
214 struct al_pcie_revx_axi_msg {
222 struct al_pcie_revx_axi_pcie_status {
226 struct al_pcie_revx_axi_rd_parity {
232 struct al_pcie_revx_axi_rd_cmpl {
234 uint32_t cmpl_log_high;
236 uint32_t cmpl_log_low;
238 struct al_pcie_revx_axi_rd_to {
240 uint32_t to_log_high;
244 struct al_pcie_revx_axi_wr_cmpl {
246 uint32_t wr_cmpl_log_high;
248 uint32_t wr_cmpl_log_low;
250 struct al_pcie_revx_axi_wr_to {
252 uint32_t wr_to_log_high;
254 uint32_t wr_to_log_low;
256 struct al_pcie_revx_axi_pcie_global {
260 struct al_pcie_rev1_2_axi_status {
270 struct al_pcie_rev3_axi_status {
289 struct al_pcie_rev1_2_axi_conf {
307 struct al_pcie_rev3_axi_conf {
343 struct al_pcie_revx_axi_msg_attr_axuser_table {
344 /* [0x0] 4 option, the index comes from */
348 struct al_pcie_revx_axi_parity {
354 struct al_pcie_revx_axi_pos_logged {
360 struct al_pcie_revx_axi_ordering {
364 struct al_pcie_revx_axi_link_down {
366 uint32_t reset_extend;
368 struct al_pcie_revx_axi_pre_configuration {
370 uint32_t pcie_core_setup;
372 struct al_pcie_revx_axi_init_fc {
375 * [0x0] The sum of all the fields below must be 97
377 * [0x0] The sum of all the fields below must be 259
381 struct al_pcie_revx_axi_int_grp_a_axi {
383 * [0x0] Interrupt Cause Register
385 * - If MSI-X is enabled, and auto_clear control bit =TRUE,
386 * automatically cleared after MSI-X message associated with this
387 * specific interrupt bit is sent (MSI-X acknowledge is received).
388 * - Software can set a bit in this register by writing 1 to the
389 * associated bit in the Interrupt Cause Set register.
390 * Write-0 clears a bit. Write-1 has no effect.
391 * - On CPU Read -- If clear_on_read control bit =TRUE, automatically
392 * cleared (all bits are cleared).
393 * When there is a conflict, and on the same clock cycle hardware tries
394 * to set a bit in the Interrupt Cause register, the specific bit is set
395 * to ensure the interrupt indication is not lost.
400 * [0x8] Interrupt Cause Set Register
401 * Writing 1 to a bit in this register sets its corresponding cause bit,
402 * enabling software to generate a hardware interrupt. Write 0 has no
408 * [0x10] Interrupt Mask Register
409 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X
410 * message associate to the associate interrupt bit is sent (AXI write
411 * acknowledge is received)
416 * [0x18] Interrupt Mask Clear Register
417 * Used when auto-mask control bit=True. It enables the CPU to clear a
418 * specific bit, preventing a scenario in which the CPU overrides
419 * another bit with 1 (old value) that hardware has just cleared to 0.
420 * Writing 0 to this register clears its corresponding mask bit. Write 1
426 * [0x20] Interrupt Status Register
427 * This register latches the status of the interrupt source.
431 /* [0x28] Interrupt Control Register */
435 * [0x30] Interrupt Mask Register
436 * Each bit in this register masks the corresponding cause bit for
437 * generating an Abort signal. Its default value is determined by unit
439 * Abort = Wire-OR of Cause & !Interrupt_Abort_Mask).
440 * This register provides an error handling configuration for error
446 * [0x38] Interrupt Log Register
447 * Each bit in this register masks the corresponding cause bit for
448 * capturing the log registers. Its default value is determined by unit
450 * Log_capture = Wire-OR of Cause & !Interrupt_Log_Mask).
451 * This register provides an error handling configuration for error
458 struct al_pcie_rev3_axi_eq_ovrd_tx_rx_values {
485 struct al_pcie_rev3_axi_dbg_outstading_trans_axi {
487 uint32_t read_master_counter;
489 uint32_t write_master_counter;
491 uint32_t read_slave_counter;
493 struct al_pcie_revx_axi_device_id {
495 uint32_t device_rev_id;
497 struct al_pcie_revx_axi_power_mang_ovrd_cntl {
499 uint32_t cfg_static_nof_elidle;
501 uint32_t cfg_l0s_wait_ovrd;
503 uint32_t cfg_l12_wait_ovrd;
505 uint32_t cfg_l0s_delay_in_p0s;
507 uint32_t cfg_l12_delay_in_p12;
509 uint32_t cfg_l12_delay_in_p12_clk_rst;
511 uint32_t cfg_delay_powerdown_bus;
514 struct al_pcie_rev3_axi_dbg_outstading_trans_axi_write {
516 uint32_t slave_counter;
518 struct al_pcie_rev3_axi_attr_ovrd {
520 * [0x0] In case of hit on the io message bar and
521 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
524 uint32_t write_msg_ctrl_0;
525 /* [0x4] in case of message this register set the below attributes */
526 uint32_t write_msg_ctrl_1;
528 * [0x8] In case of hit on the io message bar and
529 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
532 uint32_t read_msg_ctrl_0;
533 /* [0xc] in case of message this register set the below attributes */
534 uint32_t read_msg_ctrl_1;
535 /* [0x10] in case of message this register set the below attributes */
539 struct al_pcie_rev3_axi_pf_axi_attr_ovrd {
541 * [0x0] In case of hit on the io message bar and
542 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
545 uint32_t func_ctrl_0;
546 /* [0x4] in case of message this register set the below attributes */
547 uint32_t func_ctrl_1;
549 * [0x8] In case of hit on the io message bar and
550 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
553 uint32_t func_ctrl_2;
555 * [0xc] In case of hit on the io message bar and
556 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
559 uint32_t func_ctrl_3;
561 * [0x10] In case of hit on the io message bar and
562 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
565 uint32_t func_ctrl_4;
567 * [0x14] In case of hit on the io message bar and
568 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
571 uint32_t func_ctrl_5;
573 * [0x18] In case of hit on the io message bar and
574 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
577 uint32_t func_ctrl_6;
579 * [0x1c] In case of hit on the io message bar and
580 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
583 uint32_t func_ctrl_7;
585 * [0x20] In case of hit on the io message bar and
586 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
589 uint32_t func_ctrl_8;
591 * [0x24] In case of hit on the io message bar and
592 * a*_cfg_outbound_msg_no_snoop_n, the message attributes come from this
595 uint32_t func_ctrl_9;
599 struct al_pcie_revx_axi_regs {
600 uint32_t rsrvd_0[91];
601 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
604 struct al_pcie_rev1_axi_regs {
605 struct al_pcie_rev1_2_axi_ctrl ctrl; /* [0x0] */
606 struct al_pcie_rev1_axi_ob_ctrl ob_ctrl; /* [0x40] */
608 struct al_pcie_revx_axi_msg msg; /* [0x90] */
609 struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
610 struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
611 struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
612 struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
613 struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
614 struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
615 struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
616 struct al_pcie_rev1_2_axi_status status; /* [0xcc] */
617 struct al_pcie_rev1_2_axi_conf conf; /* [0xdc] */
618 struct al_pcie_revx_axi_parity parity; /* [0xfc] */
619 struct al_pcie_revx_axi_pos_logged pos_logged; /* [0x104] */
620 struct al_pcie_revx_axi_ordering ordering; /* [0x10c] */
621 struct al_pcie_revx_axi_link_down link_down; /* [0x110] */
622 struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
623 struct al_pcie_revx_axi_init_fc init_fc; /* [0x118] */
624 uint32_t rsrvd_1[20];
625 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
626 uint32_t rsrvd_2[36];
627 struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
630 struct al_pcie_rev2_axi_regs {
631 struct al_pcie_rev1_2_axi_ctrl ctrl; /* [0x0] */
632 struct al_pcie_rev2_axi_ob_ctrl ob_ctrl; /* [0x40] */
634 struct al_pcie_revx_axi_msg msg; /* [0x90] */
635 struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
636 struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
637 struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
638 struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
639 struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
640 struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
641 struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
642 struct al_pcie_rev1_2_axi_status status; /* [0xcc] */
643 struct al_pcie_rev1_2_axi_conf conf; /* [0xdc] */
644 struct al_pcie_revx_axi_parity parity; /* [0xfc] */
645 struct al_pcie_revx_axi_pos_logged pos_logged; /* [0x104] */
646 struct al_pcie_revx_axi_ordering ordering; /* [0x10c] */
647 struct al_pcie_revx_axi_link_down link_down; /* [0x110] */
648 struct al_pcie_revx_axi_pre_configuration pre_configuration; /* [0x114] */
649 struct al_pcie_revx_axi_init_fc init_fc; /* [0x118] */
650 uint32_t rsrvd_1[20];
651 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
652 uint32_t rsrvd_2[36];
653 struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x200] */
656 struct al_pcie_rev3_axi_regs {
657 struct al_pcie_rev3_axi_ctrl ctrl; /* [0x0] */
658 struct al_pcie_rev3_axi_ob_ctrl ob_ctrl;/* [0x30] */
659 struct al_pcie_revx_axi_msg msg; /* [0x90] */
660 struct al_pcie_revx_axi_pcie_status pcie_status; /* [0x9c] */
661 struct al_pcie_revx_axi_rd_parity rd_parity; /* [0xa0] */
662 struct al_pcie_revx_axi_rd_cmpl rd_cmpl; /* [0xa8] */
663 struct al_pcie_revx_axi_rd_to rd_to; /* [0xb0] */
664 struct al_pcie_revx_axi_wr_cmpl wr_cmpl; /* [0xb8] */
665 struct al_pcie_revx_axi_wr_to wr_to; /* [0xc0] */
666 struct al_pcie_revx_axi_pcie_global pcie_global; /* [0xc8] */
668 struct al_pcie_revx_axi_parity parity; /* [0xd0] */
669 struct al_pcie_revx_axi_pos_logged pos_logged; /* [0xd8] */
670 struct al_pcie_revx_axi_ordering ordering; /* [0xe0] */
671 struct al_pcie_revx_axi_link_down link_down; /* [0xe4] */
672 struct al_pcie_revx_axi_pre_configuration pre_configuration;/* [0xe8] */
673 struct al_pcie_revx_axi_init_fc init_fc; /* [0xec] */
675 struct al_pcie_rev3_axi_eq_ovrd_tx_rx_values eq_ovrd_tx_rx_values;/* [0x100] */
676 struct al_pcie_rev3_axi_dbg_outstading_trans_axi dbg_outstading_trans_axi;/* [0x160] */
677 struct al_pcie_revx_axi_device_id device_id; /* [0x16c] */
678 struct al_pcie_revx_axi_power_mang_ovrd_cntl power_mang_ovrd_cntl;/* [0x170] */
679 struct al_pcie_rev3_axi_dbg_outstading_trans_axi_write dbg_outstading_trans_axi_write;/* [0x190] */
681 struct al_pcie_rev3_axi_attr_ovrd axi_attr_ovrd; /* [0x1a0] */
682 struct al_pcie_rev3_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS];/* [0x1c0] */
683 uint32_t rsrvd_3[64];
684 struct al_pcie_rev3_axi_status status; /* [0x3c0] */
685 struct al_pcie_rev3_axi_conf conf; /* [0x400] */
686 uint32_t rsrvd_4[32];
687 struct al_pcie_revx_axi_msg_attr_axuser_table msg_attr_axuser_table; /* [0x500] */
688 uint32_t rsrvd_5[191];
689 struct al_pcie_revx_axi_int_grp_a_axi int_grp_a; /* [0x800] */
696 /**** Device ID register ****/
697 #define PCIE_AXI_DEVICE_ID_REG_DEV_ID_MASK AL_FIELD_MASK(31, 16)
698 #define PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT 16
699 #define PCIE_AXI_DEVICE_ID_REG_DEV_ID_X4 (0 << PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT)
700 #define PCIE_AXI_DEVICE_ID_REG_DEV_ID_X8 (2 << PCIE_AXI_DEVICE_ID_REG_DEV_ID_SHIFT)
701 #define PCIE_AXI_DEVICE_ID_REG_REV_ID_MASK AL_FIELD_MASK(15, 0)
702 #define PCIE_AXI_DEVICE_ID_REG_REV_ID_SHIFT 0
704 /**** Global register ****/
707 * Disable completion after inbound posted ordering enforcement to AXI bridge.
709 #define PCIE_AXI_CTRL_GLOBAL_CPL_AFTER_P_ORDER_DIS (1 << 0)
712 * Enforce completion after write ordering on AXI bridge. Only for CPU read
715 #define PCIE_AXI_CTRL_GLOBAL_CPU_CPL_ONLY_EN (1 << 1)
716 /* When linked down, map all transactions to PCIe to DEC ERR. */
717 #define PCIE_AXI_CTRL_GLOBAL_BLOCK_PCIE_SLAVE_EN (1 << 2)
719 * Wait for the NIC to flush before enabling reset to the PCIe core, on a link
722 #define PCIE_AXI_CTRL_GLOBAL_WAIT_SLV_FLUSH_EN (1 << 3)
724 * When the BME is cleared and this bit is set, it causes all transactions that
725 * do not get to the PCIe to be returned with DECERR.
727 #define PCIE_REV1_2_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR (1 << 4)
728 #define PCIE_REV3_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR_MASK 0x00000FF0
729 #define PCIE_REV3_AXI_CTRL_GLOBAL_MEM_BAR_MAP_TO_ERR_SHIFT 4
731 * Wait for the DBI port (the port that enables access to the internal PCIe core
732 * registers) to flush before enabling reset to the PCIe core on link down
735 #define PCIE_REV1_2_AXI_CTRL_GLOBAL_WAIT_DBI_FLUSH_EN (1 << 5)
736 #define PCIE_REV3_AXI_CTRL_GLOBAL_WAIT_DBI_FLUSH_EN (1 << 12)
737 /* Reserved. Read undefined; must read as zeros. */
738 #define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_FLUSH_DBI_AXI (1 << 13)
739 /* Reserved. Read undefined; must read as zeros. */
740 #define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_HOLD_LNKDWN_RESET_SW (1 << 14)
741 /* Reserved. Read undefined; must read as zeros. */
742 #define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_MASK_CORECLK_ACT_CLK_RST (1 << 15)
743 /* Reserved. Read undefined; must read as zeros. */
744 #define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_MASK_RXELECIDLE_CLK_RST (1 << 16)
745 /* Reserved. Read undefined; must read as zeros. */
746 #define PCIE_REV3_AXI_CTRL_GLOBAL_CFG_ALLOW_NONSTICKY_RESET_WHEN_LNKDOWN_CLK_RST (1 << 17)
749 * When set, adds parity on the write and read address channels, and write data
752 #define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR (1 << 16)
753 #define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_MSTR (1 << 18)
754 /* When set, enables parity check on the read data. */
755 #define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD (1 << 17)
756 #define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_RD (1 << 19)
758 * When set, adds parity on the RD data channel.
760 #define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV (1 << 18)
761 #define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_CALC_EN_SLV (1 << 20)
763 * When set, enables parity check on the write data.
765 #define PCIE_REV1_2_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR (1 << 19)
766 #define PCIE_REV3_AXI_CTRL_GLOBAL_PARITY_ERR_EN_WR (1 << 21)
768 * When set, error track for timeout and parity is disabled, i.e., the logged
769 * address for parity/timeout/cmpl errors on the AXI master port is not valid,
770 * and timeout and completion errors check are disabled.
772 #define PCIE_REV1_2_AXI_CTRL_GLOBAL_ERROR_TRACK_DIS (1 << 20)
773 #define PCIE_REV3_AXI_CTRL_GLOBAL_ERROR_TRACK_DIS (1 << 22)
775 /**** Master_Arctl register ****/
776 /* override arcache */
777 #define PCIE_AXI_CTRL_MASTER_ARCTL_OVR_ARCACHE (1 << 0)
779 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARACHE_VA_MASK 0x0000001E
780 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARACHE_VA_SHIFT 1
781 /* arprot override */
782 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_OVR (1 << 5)
784 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_MASK 0x000001C0
785 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARPROT_VALUE_SHIFT 6
787 #define PCIE_AXI_CTRL_MASTER_ARCTL_TGTID_VAL_MASK 0x01FFFE00
788 #define PCIE_AXI_CTRL_MASTER_ARCTL_TGTID_VAL_SHIFT 9
790 #define PCIE_AXI_CTRL_MASTER_ARCTL_IPA_VAL (1 << 25)
791 /* overide snoop inidcation, if not set take it from mstr_armisc ... */
792 #define PCIE_AXI_CTRL_MASTER_ARCTL_OVR_SNOOP (1 << 26)
794 snoop indication value when override */
795 #define PCIE_AXI_CTRL_MASTER_ARCTL_SNOOP (1 << 27)
798 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_MASK 0xF0000000
799 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_SHIFT 28
800 #define PCIE_AXI_CTRL_MASTER_ARCTL_ARQOS_VAL_MAX 15
802 /**** Master_Awctl register ****/
803 /* override arcache */
804 #define PCIE_AXI_CTRL_MASTER_AWCTL_OVR_ARCACHE (1 << 0)
806 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWACHE_VA_MASK 0x0000001E
807 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWACHE_VA_SHIFT 1
808 /* awprot override */
809 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_OVR (1 << 5)
811 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_MASK 0x000001C0
812 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWPROT_VALUE_SHIFT 6
814 #define PCIE_AXI_CTRL_MASTER_AWCTL_TGTID_VAL_MASK 0x01FFFE00
815 #define PCIE_AXI_CTRL_MASTER_AWCTL_TGTID_VAL_SHIFT 9
817 #define PCIE_AXI_CTRL_MASTER_AWCTL_IPA_VAL (1 << 25)
818 /* overide snoop inidcation, if not set take it from mstr_armisc ... */
819 #define PCIE_AXI_CTRL_MASTER_AWCTL_OVR_SNOOP (1 << 26)
821 snoop indication value when override */
822 #define PCIE_AXI_CTRL_MASTER_AWCTL_SNOOP (1 << 27)
825 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_MASK 0xF0000000
826 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_SHIFT 28
827 #define PCIE_AXI_CTRL_MASTER_AWCTL_AWQOS_VAL_MAX 15
829 /**** slv_ctl register ****/
830 #define PCIE_AXI_CTRL_SLV_CTRL_IO_BAR_EN (1 << 6)
832 /**** Cfg_Target_Bus register ****/
834 * Defines which MSBs to complete the number of the bust that arrived from ECAM.
835 * If set to 0, take the bit from the ECAM bar, otherwise from the busnum of
837 * The LSB for the bus number comes on the addr[*:20].
839 #define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_MASK 0x000000FF
840 #define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_MASK_SHIFT 0
841 /* Target bus number for outbound configuration type0 and type1 access */
842 #define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_MASK 0x0000FF00
843 #define PCIE_AXI_MISC_OB_CTRL_CFG_TARGET_BUS_BUSNUM_SHIFT 8
845 /**** Cfg_Control register ****/
846 /* Primary bus number */
847 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_MASK 0x000000FF
848 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_PBUS_SHIFT 0
851 * Subordinate bus number
853 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_MASK 0x0000FF00
854 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SUBBUS_SHIFT 8
855 /* Secondary bus nnumber */
856 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_MASK 0x00FF0000
857 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_SEC_BUS_SHIFT 16
858 /* Enable outbound configuration access through iATU. */
859 #define PCIE_AXI_MISC_OB_CTRL_CFG_CONTROL_IATU_EN (1 << 31)
861 /**** IO_Start_H register ****/
864 * Outbound ATIU I/O start address high
866 #define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_MASK 0x000003FF
867 #define PCIE_AXI_MISC_OB_CTRL_IO_START_H_ADDR_SHIFT 0
869 /**** IO_Limit_H register ****/
872 * Outbound ATIU I/O limit address high
874 #define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_MASK 0x000003FF
875 #define PCIE_AXI_MISC_OB_CTRL_IO_LIMIT_H_ADDR_SHIFT 0
877 /**** Msg_Start_H register ****/
880 * Outbound ATIU msg-no-data start address high
882 #define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_MASK 0x000003FF
883 #define PCIE_AXI_MISC_OB_CTRL_MSG_START_H_ADDR_SHIFT 0
885 /**** Msg_Limit_H register ****/
888 * Outbound ATIU msg-no-data limit address high
890 #define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_MASK 0x000003FF
891 #define PCIE_AXI_MISC_OB_CTRL_MSG_LIMIT_H_ADDR_SHIFT 0
893 /**** tgtid_reg_ovrd register ****/
895 * select if to take the value from register or from address[63:48]:
896 * 1'b1: register value.
897 * 1'b0: from address[63:48]
899 #define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_SEL_MASK 0x0000FFFF
900 #define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_SEL_SHIFT 0
901 /* tgtid override value. */
902 #define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_VALUE_MASK 0xFFFF0000
903 #define PCIE_AXI_MISC_OB_CTRL_TGTID_REG_OVRD_VALUE_SHIFT 16
905 /**** addr_size_replace register ****/
907 * Size in bits to replace from bit [63:64-N], when equal zero no replace is
910 #define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_MASK 0x0000FFFF
911 #define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_VALUE_SHIFT 0
913 #define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_RSRVD_MASK 0xFFFF0000
914 #define PCIE_AXI_MISC_OB_CTRL_ADDR_SIZE_REPLACE_RSRVD_SHIFT 16
916 /**** type register ****/
917 /* Type of message */
918 #define PCIE_AXI_MISC_MSG_TYPE_TYPE_MASK 0x00FFFFFF
919 #define PCIE_AXI_MISC_MSG_TYPE_TYPE_SHIFT 0
921 #define PCIE_AXI_MISC_MSG_TYPE_RSRVD_MASK 0xFF000000
922 #define PCIE_AXI_MISC_MSG_TYPE_RSRVD_SHIFT 24
924 /**** debug register ****/
925 /* Causes ACI PCIe reset, including ,master/slave/DBI (registers). */
926 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_AXI_BRIDGE_RESET (1 << 0)
928 * Causes reset of the entire PCIe core (including the AXI bridge).
929 * When set, the software must not address the PCI core (through the MEM space
932 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_CORE_RESET (1 << 1)
934 * Indicates that the SB is empty from the request to the PCIe (not including
937 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_SB_FLUSH_OB_STATUS (1 << 2)
938 /* MAP and transaction to the PCIe core to ERROR. */
939 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_SB_MAP_TO_ERR (1 << 3)
940 /* Indicates that the pcie_core clock is gated off */
941 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_CORE_CLK_GATE_OFF (1 << 4)
943 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_RSRVD_MASK 0xFFFFFFE0
944 #define PCIE_AXI_MISC_PCIE_STATUS_DEBUG_RSRVD_SHIFT 5
946 /**** conf register ****/
949 * Indicates the specific type of this PCI Express Function. It is also used to
951 * Device/Port Type field.
953 * 4'b0000: PCI Express Endpoint
954 * 4'b0001: Legacy PCI Express Endpoint
955 * 4'b0100: Root Port of PCI Express Root Complex
957 * Must be programmed before link training sequence, according to the reset
959 * Change this register should be when the pci_exist (in the PBS regfile) is
962 #define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_MASK 0x0000000F
963 #define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_SHIFT 0
965 * [i] - Lane i active
966 * Change this register should be when the pci_exist (in the PBS regfile) is
969 #define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000000F0
970 #define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFFFFF00
971 #define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_SHIFT 8
972 #define PCIE_REVX_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_SHIFT 4
973 #define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_NOF_ACT_LANES_MASK 0x000FFFF0
974 #define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_MASK 0xFFF00000
975 #define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_RESERVED_SHIFT 20
977 #define PCIE_REV1_2_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100
978 #define PCIE_REV3_AXI_MISC_PCIE_GLOBAL_CONF_MEM_SHUTDOWN 0x100000
980 /**** laneX register ****/
981 #define PCIE_AXI_STATUS_LANE_IS_RESET AL_BIT(13)
982 #define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_MASK AL_FIELD_MASK(2, 0)
983 #define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_SHIFT 0
985 /**** zero_laneX register ****/
986 /* phy_mac_local_fs */
987 #define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_MASK 0x0000003f
988 #define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_FS_SHIFT 0
989 /* phy_mac_local_lf */
990 #define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_MASK 0x00000fc0
991 #define PCIE_AXI_MISC_ZERO_LANEX_PHY_MAC_LOCAL_LF_SHIFT 6
993 /**** en_axi register ****/
995 #define PCIE_AXI_PARITY_EN_AXI_U4_RAM2P AL_BIT(1)
997 /**** pos_cntl register ****/
999 #define PCIE_AXI_POS_ORDER_AXI_POS_BYPASS (1 << 0)
1000 /* Clear the POS data structure. */
1001 #define PCIE_AXI_POS_ORDER_AXI_POS_CLEAR (1 << 1)
1002 /* Read push all write. */
1003 #define PCIE_AXI_POS_ORDER_AXI_POS_RSO_ENABLE (1 << 2)
1005 * Causes the PCIe core to wait for all the BRESPs before issuing a read
1008 #define PCIE_AXI_POS_ORDER_AXI_DW_RD_FLUSH_WR (1 << 3)
1010 * When set, to 1'b1 supports interleaving data return from the PCIe core. Valid
1011 * only when cfg_bypass_cmpl_after_write_fix is set.
1013 #define PCIE_AXI_POS_ORDER_RD_CMPL_AFTER_WR_SUPPORT_RD_INTERLV (1 << 4)
1014 /* When set, to 1'b1 disables read completion after write ordering. */
1015 #define PCIE_AXI_POS_ORDER_BYPASS_CMPL_AFTER_WR_FIX (1 << 5)
1017 * When set, disables EP mode read cmpl on the master port push slave writes,
1018 * when each read response from the master is not interleaved.
1020 #define PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_DIS (1 << 6)
1021 /* When set, disables EP mode read cmpl on the master port push slave writes. */
1022 #define PCIE_AXI_POS_ORDER_EP_CMPL_AFTER_WR_SUPPORT_INTERLV_DIS (1 << 7)
1023 /* should be zero */
1024 #define PCIE_AXI_POS_ORDER_9_8 AL_FIELD_MASK(9, 8)
1025 /* Give the segmentation buffer not to wait for P writes to end in the AXI
1026 * bridge before releasing the CMPL.
1028 #define PCIE_AXI_POS_ORDER_SEGMENT_BUFFER_DONT_WAIT_FOR_P_WRITES AL_BIT(10)
1029 /* should be zero */
1030 #define PCIE_AXI_POS_ORDER_11 AL_BIT(11)
1032 * When set cause pcie core to send ready in the middle of the read data
1033 * burst returning from the DRAM to the PCIe core
1035 #define PCIE_AXI_POS_ORDER_SEND_READY_ON_READ_DATA_BURST AL_BIT(12)
1036 /* When set disable the ATS CAP. */
1037 #define PCIE_AXI_CORE_SETUP_ATS_CAP_DIS AL_BIT(13)
1038 /* When set disable D3/D2/D1 PME support */
1039 #define PCIE_AXI_POS_ORDER_DISABLE_DX_PME AL_BIT(14)
1040 /* When set enable nonsticky reset when linkdown hot reset */
1041 #define PCIE_AXI_POS_ORDER_ENABLE_NONSTICKY_RESET_ON_HOT_RESET AL_BIT(15)
1042 /* When set, terminate message with data as UR request */
1043 #define PCIE_AXI_TERMINATE_DATA_MSG_AS_UR_REQ AL_BIT(16)
1045 /**** pcie_core_setup register ****/
1047 * This Value delay the rate change to the serdes, until the EIOS is sent by the
1048 * serdes. Should be program before the pcie_exist, is asserted.
1050 #define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_MASK 0x000000FF
1051 #define PCIE_AXI_CORE_SETUP_DELAY_MAC_PHY_RATE_SHIFT 0
1053 * Limit the number of outstanding AXI reads that the PCIe core can get. Should
1054 * be program before the pcie_exist, is asserted.
1056 #define PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_MASK 0x0000FF00
1057 #define PCIE_AXI_CORE_SETUP_NOF_READS_ONSLAVE_INTRF_PCIE_CORE_SHIFT 8
1058 /* Enable the sriov feature. */
1059 #define PCIE_AXI_REV1_2_CORE_SETUP_SRIOV_ENABLE AL_BIT(16)
1061 #define PCIE_AXI_REV3_CORE_SETUP_NOT_IN_USE (1 << 16)
1062 /* Reserved. Read undefined; must read as zeros. */
1063 #define PCIE_AXI_REV3_CORE_SETUP_CFG_DELAY_AFTER_PCIE_EXIST_MASK 0x0FFE0000
1064 #define PCIE_AXI_REV3_CORE_SETUP_CFG_DELAY_AFTER_PCIE_EXIST_SHIFT 17
1066 /**** cfg register ****/
1067 /* This value set the possible out standing headers writes (post ... */
1068 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_MASK 0x0000007F
1069 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
1070 /* This value set the possible out standing headers reads (non-p ... */
1071 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_MASK 0x00003F80
1072 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_NP_HDR_SHIFT 7
1073 /* This value set the possible out standing headers CMPLs , the ... */
1074 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x001FC000
1075 #define PCIE_AXI_REV1_2_INIT_FC_CFG_NOF_CPL_HDR_SHIFT 14
1077 #define PCIE_AXI_REV1_2_INIT_FC_CFG_RSRVD_MASK 0xFFE00000
1078 #define PCIE_AXI_REV1_2_INIT_FC_CFG_RSRVD_SHIFT 21
1080 /* This value set the possible out standing headers writes (post ... */
1081 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_MASK 0x000001FF
1082 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_P_HDR_SHIFT 0
1083 /* This value set the possible out standing headers reads (non-p ... */
1084 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_MASK 0x0003FE00
1085 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_NP_HDR_SHIFT 9
1086 /* This value set the possible out standing headers CMPLs , the ... */
1087 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_MASK 0x07FC0000
1088 #define PCIE_AXI_REV3_INIT_FC_CFG_NOF_CPL_HDR_SHIFT 18
1090 * [27] cfg_cpl_p_rr: do round robin on the SB output btw Posted and CPL.
1091 * [28] cfg_np_pass_p_rr, in case RR between CPL AND P, allow to pass NP in case
1093 * [29] cfg_np_part_of_rr_arb: NP also is a part of the round robin arbiter.
1095 #define PCIE_AXI_REV3_INIT_FC_CFG_RSRVD_MASK 0xF8000000
1096 #define PCIE_AXI_REV3_INIT_FC_CFG_RSRVD_SHIFT 27
1098 /**** write_msg_ctrl_0 register ****/
1100 * choose if 17 in the AXUSER indicate message hint (1'b1) or no snoop
1103 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
1104 /* this bit define if the message is with data or without */
1105 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_WITH_DATA (1 << 1)
1106 /* message code for message with data. */
1107 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_DATA_MASK 0x000003FC
1108 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_DATA_SHIFT 2
1109 /* message code for message without data. */
1110 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_MASK 0x0003FC00
1111 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_CODE_SHIFT 10
1112 /* message ST value */
1113 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_ST_MASK 0x03FC0000
1114 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_ST_SHIFT 18
1115 /* message NO-SNOOP */
1116 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_NO_SNOOP (1 << 26)
1117 /* message TH bit */
1118 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_TH (1 << 27)
1119 /* message PH bits */
1120 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_PH_MASK 0x30000000
1121 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_AW_CFG_MSG_PH_SHIFT 28
1123 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_RSRVD_MASK 0xC0000000
1124 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_0_RSRVD_SHIFT 30
1126 /**** write_msg_ctrl_1 register ****/
1128 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
1129 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
1130 /* this bit define if the message is with data or without */
1131 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
1132 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_TYPE_VALUE_SHIFT 5
1133 /* override axi size for message with no data. */
1134 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_OVRD (1 << 10)
1135 /* override the AXI size to the pcie core for message with no data. */
1136 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
1137 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_NO_DATA_AXI_SIZE_MSG_SHIFT 11
1138 /* override axi size for message with data. */
1139 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_OVRD (1 << 14)
1140 /* override the AXI size to the pcie core for message with data. */
1141 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
1142 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_AW_CFG_MSG_DATA_AXI_SIZE_MSG_SHIFT 15
1144 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
1145 #define PCIE_AXI_AXI_ATTR_OVRD_WR_MSG_CTRL_1_RSRVD_SHIFT 18
1147 /**** read_msg_ctrl_0 register ****/
1149 * choose if 17 in the AXUSER indicate message hint (1'b1) or no snoop
1152 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_OUTBOUND_MSG_NO_SNOOP_N (1 << 0)
1153 /* this bit define if the message is with data or without */
1154 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_WITH_DATA (1 << 1)
1155 /* message code for message with data. */
1156 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_DATA_MASK 0x000003FC
1157 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_DATA_SHIFT 2
1158 /* message code for message without data. */
1159 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_MASK 0x0003FC00
1160 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_CODE_SHIFT 10
1161 /* message ST value */
1162 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_ST_MASK 0x03FC0000
1163 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_ST_SHIFT 18
1164 /* message NO-SNOOP */
1165 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_NO_SNOOP (1 << 26)
1166 /* message TH bit */
1167 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_TH (1 << 27)
1168 /* message PH bits */
1169 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_PH_MASK 0x30000000
1170 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_AR_CFG_MSG_PH_SHIFT 28
1172 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_RSRVD_MASK 0xC0000000
1173 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_0_RSRVD_SHIFT 30
1175 /**** read_msg_ctrl_1 register ****/
1177 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_MASK 0x0000001F
1178 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MISC_MSG_TYPE_VALUE_SHIFT 0
1179 /* this bit define if the message is with data or without */
1180 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_TYPE_VALUE_MASK 0x000003E0
1181 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_TYPE_VALUE_SHIFT 5
1182 /* override axi size for message with no data. */
1183 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_OVRD (1 << 10)
1184 /* override the AXI size to the pcie core for message with no data. */
1185 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_MSG_MASK 0x00003800
1186 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_NO_DATA_AXI_SIZE_MSG_SHIFT 11
1187 /* override axi size for message with data. */
1188 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_OVRD (1 << 14)
1189 /* override the AXI size to the pcie core for message with data. */
1190 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_MSG_MASK 0x00038000
1191 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_AR_CFG_MSG_DATA_AXI_SIZE_MSG_SHIFT 15
1193 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_RSRVD_MASK 0xFFFC0000
1194 #define PCIE_AXI_AXI_ATTR_OVRD_READ_MSG_CTRL_1_RSRVD_SHIFT 18
1196 /**** pf_sel register ****/
1198 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_AXUSER (1 << 0)
1199 /* this bit define if the message is with data or without */
1200 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_OVRD_FROM_REG (1 << 1)
1201 /* override axi size for message with no data. */
1202 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_MASK 0x0000003C
1203 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT0_ADDR_OFFSET_SHIFT 2
1204 /* override the AXI size to the pcie core for message with no data. */
1205 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT0_OVRD (1 << 6)
1207 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_7 (1 << 7)
1209 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_AXUSER (1 << 8)
1210 /* this bit define if the message is with data or without */
1211 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_OVRD_FROM_REG (1 << 9)
1212 /* override axi size for message with no data. */
1213 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_MASK 0x00003C00
1214 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_PF_BIT1_ADDR_OFFSET_SHIFT 10
1215 /* override the AXI size to the pcie core for message with no data. */
1216 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_CFG_PF_BIT1_OVRD (1 << 14)
1218 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_MASK 0xFFFF8000
1219 #define PCIE_AXI_AXI_ATTR_OVRD_PF_SEL_RSRVD_SHIFT 15
1221 /**** func_ctrl_0 register ****/
1222 /* choose the field from the axuser */
1223 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_OVRD_FROM_AXUSER (1 << 0)
1224 /* choose the field from register */
1225 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_OVRD_FROM_REG (1 << 1)
1226 /* field offset from the address portions according to the spec */
1227 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_ADDR_OFFSET_MASK 0x0000003C
1228 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_TH_ADDR_OFFSET_SHIFT 2
1229 /* register value override */
1230 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_TH_OVRD (1 << 6)
1231 /* choose the field from the axuser */
1232 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_AXUSER_MASK 0x00007F80
1233 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_AXUSER_SHIFT 7
1234 /* choose the field from register */
1235 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_REG_MASK 0x007F8000
1236 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_PF_VEC_ST_VEC_OVRD_FROM_REG_SHIFT 15
1237 /* register value override */
1238 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_ST_VEC_OVRD_MASK 0x7F800000
1239 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_CFG_ST_VEC_OVRD_SHIFT 23
1241 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_0_RSRVD (1 << 31)
1243 /**** func_ctrl_2 register ****/
1244 /* choose the field from the axuser */
1245 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK 0x00000003
1246 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_SHIFT 0
1247 /* choose the field from register */
1248 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_REG_MASK 0x0000000C
1249 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_REG_SHIFT 2
1250 /* in case the field take from the address, offset field for each bit. */
1251 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_ADDR_OFFSET_MASK 0x00000FF0
1252 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_ADDR_OFFSET_SHIFT 4
1253 /* register value override */
1254 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_PH_VEC_OVRD_MASK 0x00003000
1255 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_PH_VEC_OVRD_SHIFT 12
1257 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_MASK 0x0000C000
1258 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_14_15_SHIFT 14
1259 /* choose the field from the axuser */
1260 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_AXUSER_MASK 0x00030000
1261 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_AXUSER_SHIFT 16
1262 /* choose the field from register */
1263 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_REG_MASK 0x000C0000
1264 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_OVRD_FROM_REG_SHIFT 18
1265 /* in case the field take from the address, offset field for each bit. */
1266 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_ADDR_OFFSET_MASK 0x0FF00000
1267 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_TGTID89_VEC_ADDR_OFFSET_SHIFT 20
1268 /* register value override */
1269 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_TGTID89_VEC_OVRD_MASK 0x30000000
1270 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_CFG_TGTID89_VEC_OVRD_SHIFT 28
1272 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_MASK 0xC0000000
1273 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_RSRVD_SHIFT 30
1275 /**** func_ctrl_3 register ****/
1277 * When set take the corresponding bit address from register
1278 * pf_vec_mem_addr44_53_ovrd
1280 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_MASK 0x000003FF
1281 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_SEL_SHIFT 0
1282 /* override value. */
1283 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_OVRD_MASK 0x000FFC00
1284 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR44_53_OVRD_SHIFT 10
1286 * When set take the corresponding bit address from register
1287 * pf_vec_mem_addr54_63_ovrd
1289 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR54_63_SEL_MASK 0x3FF00000
1290 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_PF_VEC_MEM_ADDR54_63_SEL_SHIFT 20
1292 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_MASK 0xC0000000
1293 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_3_RSRVD_SHIFT 30
1295 /**** func_ctrl_4 register ****/
1296 /* When set take the corresponding bit address from tgtid value. */
1297 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK 0x000003FF
1298 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_SHIFT 0
1299 /* override value. */
1300 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_MASK 0x000FFC00
1301 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_OVRD_SHIFT 10
1303 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_RSRVD_MASK 0xFFF00000
1304 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_RSRVD_SHIFT 20
1306 /**** func_ctrl_5 register ****/
1308 * When set take the corresponding bit address [63:44] from
1309 * aw_pf_vec_msg_addr_ovrd
1311 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
1312 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_AW_PF_VEC_MSG_ADDR_SEL_SHIFT 0
1314 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_RSRVD_MASK 0xFFF00000
1315 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_5_RSRVD_SHIFT 20
1317 /**** func_ctrl_6 register ****/
1318 /* override value. */
1319 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
1320 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_AW_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
1322 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_RSRVD_MASK 0xFFF00000
1323 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_6_RSRVD_SHIFT 20
1325 /**** func_ctrl_7 register ****/
1327 * When set take the corresponding bit address [63:44] from
1328 * ar_pf_vec_msg_addr_ovrd
1330 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_MASK 0x000FFFFF
1331 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_AR_PF_VEC_MSG_ADDR_SEL_SHIFT 0
1333 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_RSRVD_MASK 0xFFF00000
1334 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_7_RSRVD_SHIFT 20
1336 /**** func_ctrl_8 register ****/
1337 /* override value. */
1338 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_MASK 0x000FFFFF
1339 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_AR_PF_VEC_MSG_ADDR_OVRD_SHIFT 0
1341 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_RSRVD_MASK 0xFFF00000
1342 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_8_RSRVD_SHIFT 20
1344 /**** func_ctrl_9 register ****/
1345 /* no snoop override */
1346 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_NO_SNOOP_OVRD (1 << 0)
1347 /* no snoop override value */
1348 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_NO_SNOOP_OVRD_VALUE (1 << 1)
1349 /* atu bypass override */
1350 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_ATU_BYPASS_OVRD (1 << 2)
1351 /* atu bypass override value */
1352 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_PF_VEC_ATU_BYPASS_OVRD_VALUE (1 << 3)
1354 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_RSRVD_MASK 0xFFFFFFF0
1355 #define PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_9_RSRVD_SHIFT 4
1357 /**** entry_vec register ****/
1359 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_MASK 0x0000001F
1360 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_0_SHIFT 0
1362 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_1_MASK 0x000003E0
1363 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_1_SHIFT 5
1365 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_2_MASK 0x00007C00
1366 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_2_SHIFT 10
1368 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_3_MASK 0x000F8000
1369 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_ENTRY_3_SHIFT 15
1370 /* atu bypass for message "write" */
1371 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_AW_MSG_ATU_BYPASS (1 << 20)
1372 /* atu bypass for message "read" */
1373 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_AR_MSG_ATU_BYPASS (1 << 21)
1375 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_RSRVD_MASK 0xFFC00000
1376 #define PCIE_AXI_MSG_ATTR_AXUSER_TABLE_ENTRY_VEC_RSRVD_SHIFT 22
1378 /**** int_cause_grp_A_axi register ****/
1380 * Master Response Composer Lookup Error
1381 * Overflow that occurred in a lookup table of the Outbound responses. This
1382 * indicates that there was a violation for the number of outstanding NP
1383 * requests issued for the Inbound direction.
1384 * Write zero to clear.
1386 #define PCIE_AXI_INT_GRP_A_CAUSE_GM_COMPOSER_LOOKUP_ERR (1 << 0)
1388 * Indicates a PARITY ERROR on the master data read channel.
1389 * Write zero to clear.
1391 #define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_DATA_PATH_RD (1 << 2)
1393 * Indicates a PARITY ERROR on the slave addr read channel.
1394 * Write zero to clear.
1396 #define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_RD (1 << 3)
1398 * Indicates a PARITY ERROR on the slave addr write channel.
1399 * Write zero to clear.
1401 #define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_ADDR_WR (1 << 4)
1403 * Indicates a PARITY ERROR on the slave data write channel.
1404 * Write zero to clear.
1406 #define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERR_OUT_DATA_WR (1 << 5)
1408 #define PCIE_AXI_INT_GRP_A_CAUSE_RESERVED_6 (1 << 6)
1410 * Software error: ECAM write request with invalid bus number.
1411 * Write Zero to clear
1413 #define PCIE_AXI_INT_GRP_A_CAUSE_SW_ECAM_ERR_RD (1 << 7)
1415 * Software error: ECAM read request with invalid bus number.
1416 * Write Zero to clear.
1418 #define PCIE_AXI_INT_GRP_A_CAUSE_SW_ECAM_ERR_WR (1 << 8)
1419 /* Indicates an ERROR in the PCIe application cause register. */
1420 #define PCIE_AXI_INT_GRP_A_CAUSE_PCIE_CORE_INT (1 << 9)
1422 * Whenever the Master AXI finishes writing a message, it sets this bit.
1423 * Whenever the int is cleared, the message information MSG_* regs are no longer
1426 #define PCIE_AXI_INT_GRP_A_CAUSE_MSTR_AXI_GETOUT_MSG (1 << 10)
1427 /* Read AXI compilation has ERROR. */
1428 #define PCIE_AXI_INT_GRP_A_CAUSE_RD_CMPL_ERR (1 << 11)
1429 /* Write AXI compilation has ERROR. */
1430 #define PCIE_AXI_INT_GRP_A_CAUSE_WR_CMPL_ERR (1 << 12)
1431 /* Read AXI compilation has timed out. */
1432 #define PCIE_AXI_INT_GRP_A_CAUSE_RD_CMPL_TO (1 << 13)
1433 /* Write AXI compilation has timed out. */
1434 #define PCIE_AXI_INT_GRP_A_CAUSE_WR_CMPL_TO (1 << 14)
1435 /* Parity error AXI domain */
1436 #define PCIE_AXI_INT_GRP_A_CAUSE_PARITY_ERROR_AXI (1 << 15)
1437 /* POS error interrupt */
1438 #define PCIE_AXI_INT_GRP_A_CAUSE_POS_AXI_BRESP (1 << 16)
1439 /* The outstanding write counter become full should never happen */
1440 #define PCIE_AXI_INT_GRP_A_CAUSE_WRITE_CNT_FULL_ERR (1 << 17)
1441 /* BRESP received before the write counter increment. */
1442 #define PCIE_AXI_INT_GRP_A_CAUSE_BRESP_BEFORE_WR_CNT_INC_ERR (1 << 18)
1444 /**** int_control_grp_A_axi register ****/
1445 /* When Clear_on_Read =1, all bits of the Cause register are cleared on read. */
1446 #define PCIE_AXI_INT_GRP_A_CTRL_CLEAR_ON_READ (1 << 0)
1448 * (Must be set only when MSIX is enabled.)
1449 * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its
1450 * corresponding bit in the mask register is set, masking future interrupts.
1452 #define PCIE_AXI_INT_GRP_A_CTRL_AUTO_MASK (1 << 1)
1455 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared
1456 * after MSI-X is acknowledged. Must be used only if MSI-X is enabled.
1458 #define PCIE_AXI_INT_GRP_A_CTRL_AUTO_CLEAR (1 << 2)
1460 * When set,_on_Posedge =1, the bits in the Interrupt Cause register are set on
1461 * the posedge of the interrupt source, i.e., when interrupt source =1 and
1462 * Interrupt Status = 0.
1463 * When set,_on_Posedge =0, the bits in the Interrupt Cause register are set
1464 * when interrupt source =1.
1466 #define PCIE_AXI_INT_GRP_A_CTRL_SET_ON_POS (1 << 3)
1468 * When Moderation_Reset =1, all Moderation timers associated with the interrupt
1469 * cause bits are cleared to 0, enabling immediate interrupt assertion if any
1470 * unmasked cause bit is set to 1. This bit is self-negated.
1472 #define PCIE_AXI_INT_GRP_A_CTRL_MOD_RST (1 << 4)
1474 * When mask_msi_x =1, no MSI-X from this group is sent. This bit is set to 1
1475 * when the associate summary bit in this group is used to generate a single
1476 * MSI-X for this group.
1478 #define PCIE_AXI_INT_GRP_A_CTRL_MASK_MSI_X (1 << 5)
1479 /* MSI-X AWID value. Same ID for all cause bits. */
1480 #define PCIE_AXI_INT_GRP_A_CTRL_AWID_MASK 0x00000F00
1481 #define PCIE_AXI_INT_GRP_A_CTRL_AWID_SHIFT 8
1483 * This value determines the interval between interrupts. Writing ZERO disables
1486 #define PCIE_AXI_INT_GRP_A_CTRL_MOD_INTV_MASK 0x00FF0000
1487 #define PCIE_AXI_INT_GRP_A_CTRL_MOD_INTV_SHIFT 16
1489 * This value determines the Moderation_Timer_Clock speed.
1490 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS.
1491 * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS.
1492 * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS.
1494 #define PCIE_AXI_INT_GRP_A_CTRL_MOD_RES_MASK 0x0F000000
1495 #define PCIE_AXI_INT_GRP_A_CTRL_MOD_RES_SHIFT 24
1501 #endif /* __AL_HAL_pcie_axi_REG_H */
1503 /** @} end of ... group */