1 /*******************************************************************************
2 Copyright (C) 2015 Annapurna Labs Ltd.
4 This file may be licensed under the terms of the Annapurna Labs Commercial
7 Alternatively, this file can be distributed under the terms of the GNU General
8 Public License V2 as published by the Free Software Foundation and can be
9 found at http://www.gnu.org/licenses/gpl-2.0.html
11 Alternatively, redistribution and use in source and binary forms, with or
12 without modification, are permitted provided that the following conditions are
15 * Redistributions of source code must retain the above copyright notice,
16 this list of conditions and the following disclaimer.
18 * Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in
20 the documentation and/or other materials provided with the
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *******************************************************************************/
36 #include "al_hal_serdes_25g.h"
37 #include "al_hal_serdes_25g_regs.h"
38 #include "al_hal_serdes_25g_internal_regs.h"
40 #define AL_SERDES_MB_MAX_DATA_LEN 8
42 #define AL_SERDES_25G_WAIT_FOR_READY_TO 200
43 #define AL_SERDES_25G_RESET_TO 100
44 #define AL_SERDES_25G_RESET_NUM_RETRIES 5
46 #if (!defined(AL_SERDES_BASIC_SERVICES_ONLY)) || (AL_SERDES_BASIC_SERVICES_ONLY == 0)
47 #define AL_SRDS_ADV_SRVC(func) func
49 static void al_serdes_hssp_stub_func(void)
51 al_err("%s: not implemented service called!\n", __func__);
54 #define AL_SRDS_ADV_SRVC(func) ((typeof(func) *)al_serdes_hssp_stub_func)
57 /******************************************************************************/
58 /******************************************************************************/
59 static enum al_serdes_type al_serdes_25g_type_get(void)
61 return AL_SRDS_TYPE_25G;
64 /******************************************************************************/
65 /******************************************************************************/
66 static int al_serdes_25g_reg_read(
67 struct al_serdes_grp_obj *obj,
68 enum al_serdes_reg_page page,
69 enum al_serdes_reg_type type,
73 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
76 al_dbg("%s(%p, %d, %d, %u)\n", __func__, obj, page, type, offset);
82 case AL_SRDS_REG_PAGE_TOP:
83 addr = (SERDES_25G_TOP_BASE + offset);
85 case AL_SRDS_REG_PAGE_4_COMMON:
86 addr = (SERDES_25G_CM_BASE + offset);
88 case AL_SRDS_REG_PAGE_0_LANE_0:
89 case AL_SRDS_REG_PAGE_1_LANE_1:
90 addr = (SERDES_25G_LANE_BASE + (page * SERDES_25G_LANE_SIZE) + offset);
93 al_err("%s: wrong serdes type %d\n", __func__, type);
97 al_reg_write32(®s_base->gen.reg_addr, addr);
98 *data = al_reg_read32(®s_base->gen.reg_data);
100 al_dbg("%s: return(%u)\n", __func__, *data);
105 static int al_serdes_25g_reg_write(
106 struct al_serdes_grp_obj *obj,
107 enum al_serdes_reg_page page,
108 enum al_serdes_reg_type type,
112 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
115 al_dbg("%s(%p, %d, %d, %u)\n", __func__, obj, page, type, offset);
120 case AL_SRDS_REG_PAGE_TOP:
121 addr = (SERDES_25G_TOP_BASE + offset);
123 case AL_SRDS_REG_PAGE_4_COMMON:
124 addr = (SERDES_25G_CM_BASE + offset);
126 case AL_SRDS_REG_PAGE_0_LANE_0:
127 case AL_SRDS_REG_PAGE_1_LANE_1:
128 addr = (SERDES_25G_LANE_BASE + (page * SERDES_25G_LANE_SIZE) + offset);
131 al_err("%s: wrong serdes type %d\n", __func__, type);
135 al_reg_write32(®s_base->gen.reg_addr, addr);
136 al_reg_write32(®s_base->gen.reg_data, (data | SERDES_C_GEN_REG_DATA_STRB_MASK));
138 al_dbg("%s: write(%u)\n", __func__, data);
143 /******************************************************************************/
144 /******************************************************************************/
145 static int al_serdes_25g_reg_masked_read(
146 struct al_serdes_grp_obj *obj,
147 enum al_serdes_reg_page page,
156 status = al_serdes_25g_reg_read(obj, page, 0, offset, &val);
160 *data = AL_REG_FIELD_GET(val, mask, shift);
165 static int al_serdes_25g_reg_masked_write(
166 struct al_serdes_grp_obj *obj,
167 enum al_serdes_reg_page page,
176 status = al_serdes_25g_reg_read(obj, page, 0, offset, &val);
181 val |= (data << shift);
182 return al_serdes_25g_reg_write(obj, page, 0, offset, val);
185 /******************************************************************************/
186 /******************************************************************************/
187 #define SERDES_25G_MB_RESP_BYTES 16
188 #define SERDES_25G_MB_TIMEOUT 5000000 /* uSec */
190 static int al_serdes_25g_mailbox_send_cmd(
191 struct al_serdes_grp_obj *obj,
198 uint32_t timeout = SERDES_25G_MB_TIMEOUT;
200 if (data_len > AL_SERDES_MB_MAX_DATA_LEN) {
201 al_err("Cannot send command, data too long\n");
205 /* Wait for CMD_FLAG to clear */
207 al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
208 SERDES_25G_TOP_CMD_FLAG_ADDR, &val);
213 al_err("%s: timeout occurred waiting to CMD_FLAG\n", __func__);
221 for (i = 0; i < data_len; i++) {
222 al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0,
223 (SERDES_25G_TOP_CMD_DATA0_ADDR + i), data[i]);
226 /* this write will set CMD_FLAG automatically */
227 al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0, SERDES_25G_TOP_CMD_ADDR, cmd);
232 static int al_serdes_25g_mailbox_recv_rsp(
233 struct al_serdes_grp_obj *obj,
240 uint32_t timeout = SERDES_25G_MB_TIMEOUT;
242 /* wait for RSP_FLAG to set */
244 al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
245 SERDES_25G_TOP_RSP_FLAG_ADDR, &val);
250 al_err("%s: timeout occurred waiting to RSP_FLAG\n", __func__);
259 /* Grab the response code and data */
260 al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
261 SERDES_25G_TOP_RSP_ADDR, rsp_code);
263 for (i = 0; i < SERDES_25G_MB_RESP_BYTES; i++) {
264 al_serdes_25g_reg_read(obj, AL_SRDS_REG_PAGE_TOP, 0,
265 (SERDES_25G_TOP_RSP_DATA0_ADDR + i), &data[i]);
268 /* clear the RSP_FLAG (write 1 to clear) */
269 al_serdes_25g_reg_write(obj, AL_SRDS_REG_PAGE_TOP, 0,
270 SERDES_25G_TOP_RSP_FLAG_ADDR, 0x1);
272 *data_len = SERDES_25G_MB_RESP_BYTES;
277 /******************************************************************************/
278 /******************************************************************************/
279 static void al_serdes_25g_bist_rx_enable(
280 struct al_serdes_grp_obj *obj,
281 enum al_serdes_lane lane,
287 al_serdes_25g_reg_masked_write(
289 AL_SRDS_REG_PAGE_TOP,
290 SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR,
291 SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_MASK,
292 SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT,
294 al_serdes_25g_reg_masked_write(
296 AL_SRDS_REG_PAGE_TOP,
297 SERDES_25G_TOP_CLOCK_LN0_CLK_RX_ADDR,
298 SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_MASK,
299 SERDES_25G_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT,
303 al_serdes_25g_reg_masked_write(
305 AL_SRDS_REG_PAGE_TOP,
306 SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR,
307 SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_MASK,
308 SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT,
311 al_serdes_25g_reg_masked_write(
313 AL_SRDS_REG_PAGE_TOP,
314 SERDES_25G_TOP_CLOCK_LN1_CLK_RX_ADDR,
315 SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_MASK,
316 SERDES_25G_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT,
320 al_err("%s: Wrong serdes lane %d\n", __func__, lane);
324 al_serdes_25g_reg_masked_write(
326 (enum al_serdes_reg_page)lane,
327 SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_ADDR,
328 SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_MASK,
329 SERDES_25G_LANE_RX_BIST_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT,
331 al_serdes_25g_reg_masked_write(
333 (enum al_serdes_reg_page)lane,
334 SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
335 SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK,
336 SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT,
338 al_serdes_25g_reg_masked_write(
340 (enum al_serdes_reg_page)lane,
341 SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
342 SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_MASK,
343 SERDES_25G_LANE_RX_BIST_CTRL_PATTERN_SEL_SHIFT,
347 al_serdes_25g_reg_masked_write(
349 (enum al_serdes_reg_page)lane,
350 SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
351 SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK,
352 SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT,
355 al_serdes_25g_reg_masked_write(
357 (enum al_serdes_reg_page)lane,
358 SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
359 SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_MASK,
360 SERDES_25G_LANE_RX_BIST_CTRL_CLEAR_BER_SHIFT,
363 al_msleep(AL_SERDES_25G_WAIT_FOR_READY_TO);
366 al_serdes_25g_reg_masked_write(
368 (enum al_serdes_reg_page)lane,
369 SERDES_25G_LANE_RX_BIST_CTRL_ADDR,
370 SERDES_25G_LANE_RX_BIST_CTRL_EN_MASK,
371 SERDES_25G_LANE_RX_BIST_CTRL_EN_SHIFT,
376 // TODO: [Guy] change API to be per lane.
377 static void al_serdes_25g_bist_pattern_select(
378 struct al_serdes_grp_obj *obj,
379 enum al_serdes_bist_pattern pattern,
382 enum al_serdes_lane lane;
386 case AL_SRDS_BIST_PATTERN_USER:
387 al_assert(user_data);
388 val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS_USER;
390 case AL_SRDS_BIST_PATTERN_PRBS7:
391 val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS7;
393 case AL_SRDS_BIST_PATTERN_PRBS23:
394 val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS23;
396 case AL_SRDS_BIST_PATTERN_PRBS31:
397 val = SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_PRBS31;
399 case AL_SRDS_BIST_PATTERN_CLK1010:
401 al_err("%s: invalid pattern (%d)\n", __func__, pattern);
405 for (lane = AL_SRDS_LANE_0; lane <= AL_SRDS_LANE_1; lane++) {
406 if (pattern == AL_SRDS_BIST_PATTERN_USER) {
409 for (i = 0; i < SERDES_25G_LANE_TX_BIST_UDP_NUM_BYTES; i++)
410 al_serdes_25g_reg_write(
412 (enum al_serdes_reg_page)lane,
414 SERDES_25G_LANE_TX_BIST_UDP_ADDR(i),
418 al_serdes_25g_reg_masked_write(
420 (enum al_serdes_reg_page)lane,
421 SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
422 SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_MASK,
423 SERDES_25G_LANE_TX_BIST_CTRL_PATTERN_SEL_SHIFT,
428 static void al_serdes_25g_bist_tx_enable(
429 struct al_serdes_grp_obj *obj,
430 enum al_serdes_lane lane,
434 al_serdes_25g_reg_masked_write(
436 (enum al_serdes_reg_page)lane,
437 SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
438 SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK,
439 SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT,
441 al_serdes_25g_reg_masked_write(
443 (enum al_serdes_reg_page)lane,
444 SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_ADDR,
445 SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_MASK,
446 SERDES_25G_LANE_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_SHIFT,
451 al_serdes_25g_reg_masked_write(
453 AL_SRDS_REG_PAGE_TOP,
454 SERDES_25G_TOP_CLOCK_LN0_CLK_TX_ADDR,
455 SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_MASK,
456 SERDES_25G_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT,
460 al_serdes_25g_reg_masked_write(
462 AL_SRDS_REG_PAGE_TOP,
463 SERDES_25G_TOP_CLOCK_LN1_CLK_TX_ADDR,
464 SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_MASK,
465 SERDES_25G_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT,
469 al_err("%s: Wrong serdes lane %d\n", __func__, lane);
473 al_serdes_25g_reg_masked_write(
475 (enum al_serdes_reg_page)lane,
476 SERDES_25G_LANE_TX_BIST_CTRL_ADDR,
477 SERDES_25G_LANE_TX_BIST_CTRL_EN_MASK,
478 SERDES_25G_LANE_TX_BIST_CTRL_EN_SHIFT,
484 static void al_serdes_25g_bist_rx_status(
485 struct al_serdes_grp_obj *obj,
486 enum al_serdes_lane lane,
488 al_bool *err_cnt_overflow,
496 al_serdes_25g_reg_masked_read(
498 (enum al_serdes_reg_page)lane,
499 SERDES_25G_LANE_RX_BIST_STATUS_ADDR,
500 SERDES_25G_LANE_RX_BIST_STATUS_STATE_MASK,
501 SERDES_25G_LANE_RX_BIST_STATUS_STATE_SHIFT,
505 *is_locked = AL_FALSE;
509 *is_locked = AL_TRUE;
510 *err_cnt_overflow = AL_FALSE;
512 al_serdes_25g_reg_masked_read(
514 (enum al_serdes_reg_page)lane,
515 SERDES_25G_LANE_RX_BIST_BER_STATUS0_ADDR,
516 SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_MASK,
517 SERDES_25G_LANE_RX_BIST_BER_STATUS0_BIT_ERROR_COUNT_7_0_SHIFT,
520 al_serdes_25g_reg_masked_read(
522 (enum al_serdes_reg_page)lane,
523 SERDES_25G_LANE_RX_BIST_BER_STATUS1_ADDR,
524 SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_MASK,
525 SERDES_25G_LANE_RX_BIST_BER_STATUS1_BIT_ERROR_COUNT_15_8_SHIFT,
528 al_serdes_25g_reg_masked_read(
530 (enum al_serdes_reg_page)lane,
531 SERDES_25G_LANE_RX_BIST_BER_STATUS2_ADDR,
532 SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_MASK,
533 SERDES_25G_LANE_RX_BIST_BER_STATUS2_BIT_ERROR_COUNT_23_16_SHIFT,
536 *err_cnt = (err1 + (err2 << 8) + (err3 << 16));
539 #define SERDES_MB_CMD_SWING_CFG 0x83
540 #define SERDES_MB_CMD_SAMPLES_COUNT 0x84
541 #define SERDES_MB_CMD_START_MEASURE 0x82
543 #define SERDES_MB_RSP_CODE_0 0
544 #define SERDES_MB_RSP_CODE_1 1
545 #define SERDES_MB_RSP_CODE_2 2
547 static int al_serdes_25g_eye_diag_run(
548 struct al_serdes_grp_obj *obj,
549 enum al_serdes_lane lane,
565 uint8_t bits_left_curr_sample;
566 uint8_t bits_left_curr_byte;
569 uint32_t x_samples = (((x_stop - x_start) / x_step) + 1);
571 uint32_t y_samples = (((y_stop - y_start) / y_step) + 1);
572 uint8_t sample_width = (64 - __builtin_clzl(ber_target));
575 uint32_t samples_left = ((x_samples * y_samples));
578 al_assert(buf_size == (samples_left * sizeof(uint64_t)));
580 al_memset(buf, 0, buf_size);
601 rc = al_serdes_25g_mailbox_send_cmd(
603 SERDES_MB_CMD_SWING_CFG,
608 al_err("%s: Failed to send command %d to mailbox.\n",
609 __func__, SERDES_MB_CMD_SWING_CFG);
613 rc = al_serdes_25g_mailbox_recv_rsp(
619 if ((rc) || (rsp_code != SERDES_MB_RSP_CODE_0)) {
620 al_err("%s: Failed to send command %d to mailbox. rsp_code %d\n",
621 __func__, SERDES_MB_CMD_SWING_CFG, rsp_code);
626 al_assert(sample_width <= 40);
629 data[1] = ((ber_target >> 32) & 0xFF);
630 data[2] = ((ber_target >> 24) & 0xFF);
631 data[3] = ((ber_target >> 16) & 0xFF);
632 data[4] = ((ber_target >> 8) & 0xFF);
633 data[5] = (ber_target & 0xFF);
635 rc = al_serdes_25g_mailbox_send_cmd(
637 SERDES_MB_CMD_SAMPLES_COUNT,
642 al_err("%s: Failed to send command %d to mailbox.\n",
643 __func__, SERDES_MB_CMD_SAMPLES_COUNT);
647 rc = al_serdes_25g_mailbox_recv_rsp(
653 if ((rc) || (rsp_code != SERDES_MB_RSP_CODE_0)) {
654 al_err("%s: Failed to send command %d to mailbox. rsp_code %d\n",
655 __func__, SERDES_MB_CMD_SAMPLES_COUNT, rsp_code);
660 rc = al_serdes_25g_mailbox_send_cmd(
662 SERDES_MB_CMD_START_MEASURE,
666 bits_left_curr_sample = sample_width;
668 while (rsp_code != SERDES_MB_RSP_CODE_1) {
669 uint8_t num_bits = 0;
671 rc = al_serdes_25g_mailbox_recv_rsp(
677 if ((rc != 0) || (rsp_code > SERDES_MB_RSP_CODE_2)) {
678 al_err("%s: command %d return failure. rsp_code %d\n",
679 __func__, SERDES_MB_CMD_START_MEASURE, rsp_code);
684 total_bits = data_len * 8;
685 bits_left_curr_byte = 8;
686 while (total_bits > 0) {
687 num_bits = al_min_t(uint8_t, bits_left_curr_sample, bits_left_curr_byte);
689 buf[(y * x_samples) + x] <<= num_bits;
690 msb = bits_left_curr_byte - 1;
691 lsb = msb - num_bits + 1;
692 buf[(y * x_samples) + x] |= (data[byte] & AL_FIELD_MASK(msb, lsb) >> lsb);
694 total_bits -= num_bits;
696 bits_left_curr_byte -= num_bits;
697 if (!bits_left_curr_byte) {
698 bits_left_curr_byte = 8;
702 bits_left_curr_sample -= num_bits;
703 if (!bits_left_curr_sample) {
705 if (y == y_samples) {
711 bits_left_curr_sample = sample_width;
714 if (samples_left == 0)
718 if ((samples_left == 0) && (rsp_code != SERDES_MB_RSP_CODE_1)) {
719 rc = al_serdes_25g_mailbox_recv_rsp(
724 if ((rc) || (rsp_code == SERDES_MB_RSP_CODE_0)) {
725 al_err("%s: Parsed enough samples but f/w is still sending more\n",
734 if (samples_left > 0) {
735 al_err("%s: Still need more samples but f/w has stopped sending them!?!?!?\n",
744 #define SERDES_25G_EYE_X_MIN 1
745 #define SERDES_25G_EYE_X_MAX 127
746 #define SERDES_25G_EYE_Y_MIN -200
747 #define SERDES_25G_EYE_Y_MAX 200
748 #define SERDES_25G_EYE_SIZE_MAX_SAMPLES 401
749 #define SERDES_25G_EYE_SIZE_BER_TARGET 0xffff
750 #define SERDES_25G_EYE_SIZE_ERR_TH 10
752 static int al_serdes_25g_calc_eye_size(
753 struct al_serdes_grp_obj *obj,
754 enum al_serdes_lane lane,
758 uint64_t samples[SERDES_25G_EYE_SIZE_MAX_SAMPLES];
763 int mid_x = ((SERDES_25G_EYE_X_MIN + SERDES_25G_EYE_X_MAX) / 2);
764 int mid_y = ((SERDES_25G_EYE_Y_MIN + SERDES_25G_EYE_Y_MAX) / 2);
769 rc = al_serdes_25g_eye_diag_run(obj,
774 SERDES_25G_EYE_Y_MIN,
775 SERDES_25G_EYE_Y_MAX,
777 SERDES_25G_EYE_SIZE_BER_TARGET,
779 ((SERDES_25G_EYE_Y_MAX - SERDES_25G_EYE_Y_MIN + 1) *
783 al_err("%s: failed to run eye_diag\n", __func__);
787 for (i = (mid_y - SERDES_25G_EYE_Y_MIN);
788 ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) &&
789 (i < (SERDES_25G_EYE_Y_MAX - SERDES_25G_EYE_Y_MIN + 1)));
792 for (i = (mid_y - SERDES_25G_EYE_Y_MIN);
793 ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) && (i >= 0));
797 rc = al_serdes_25g_eye_diag_run(obj,
799 SERDES_25G_EYE_X_MIN,
800 SERDES_25G_EYE_X_MAX,
805 SERDES_25G_EYE_SIZE_BER_TARGET,
807 ((SERDES_25G_EYE_X_MAX - SERDES_25G_EYE_X_MIN + 1) *
811 al_err("%s: failed to run eye_diag\n", __func__);
815 for (i = (mid_x - SERDES_25G_EYE_X_MIN);
816 ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) &&
817 (i < (SERDES_25G_EYE_X_MAX - SERDES_25G_EYE_X_MIN + 1)));
820 for (i = (mid_x - SERDES_25G_EYE_X_MIN);
821 ((samples[i] < SERDES_25G_EYE_SIZE_ERR_TH) && (i >= 0));
832 static void al_serdes_25g_tx_advanced_params_set(struct al_serdes_grp_obj *obj,
833 enum al_serdes_lane lane,
836 struct al_serdes_adv_tx_params *params = tx_params;
837 uint32_t timeout = 5000;
840 al_serdes_25g_reg_masked_write(obj,
841 (enum al_serdes_reg_page)lane,
842 SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR,
843 SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK,
844 SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT,
847 al_serdes_25g_reg_masked_write(obj,
848 (enum al_serdes_reg_page)lane,
849 SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR,
850 SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK,
851 SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT,
854 al_serdes_25g_reg_masked_write(obj,
855 (enum al_serdes_reg_page)lane,
856 SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR,
857 SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK,
858 SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT,
859 params->total_driver_units);
861 al_serdes_25g_reg_masked_write(obj,
862 (enum al_serdes_reg_page)lane,
863 SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR,
864 SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK,
865 SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT,
869 /* wait for acknowledge */
871 al_serdes_25g_reg_masked_read(obj,
872 (enum al_serdes_reg_page)lane,
873 SERDES_25G_LANE_DRV_TXEQ_STATUS0_ADDR,
874 SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_MASK,
875 SERDES_25G_LANE_DRV_TXEQ_STATUS0_ACK_SHIFT,
881 al_err("%s: timeout occurred waiting to FW ack\n", __func__);
889 al_serdes_25g_reg_masked_write(obj,
890 (enum al_serdes_reg_page)lane,
891 SERDES_25G_LANE_DRV_TXEQ_CTRL0_ADDR,
892 SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_MASK,
893 SERDES_25G_LANE_DRV_TXEQ_CTRL0_REQ_SHIFT,
897 static void al_serdes_25g_tx_advanced_params_get(struct al_serdes_grp_obj *obj,
898 enum al_serdes_lane lane,
901 struct al_serdes_adv_tx_params *params = tx_params;
903 al_serdes_25g_reg_masked_read(obj,
904 (enum al_serdes_reg_page)lane,
905 SERDES_25G_LANE_DRV_TXEQ_CTRL3_ADDR,
906 SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_MASK,
907 SERDES_25G_LANE_DRV_TXEQ_CTRL3_TXEQ_CM1_SHIFT,
910 al_serdes_25g_reg_masked_read(obj,
911 (enum al_serdes_reg_page)lane,
912 SERDES_25G_LANE_DRV_TXEQ_CTRL1_ADDR,
913 SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_MASK,
914 SERDES_25G_LANE_DRV_TXEQ_CTRL1_TXEQ_C1_SHIFT,
917 al_serdes_25g_reg_masked_read(obj,
918 (enum al_serdes_reg_page)lane,
919 SERDES_25G_LANE_DRV_TXEQ_CTRL5_ADDR,
920 SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_MASK,
921 SERDES_25G_LANE_DRV_TXEQ_CTRL5_DRV_SWING_SHIFT,
922 ¶ms->total_driver_units);
925 static al_bool al_serdes_25g_cdr_is_locked(
926 struct al_serdes_grp_obj *obj,
927 enum al_serdes_lane lane)
931 al_serdes_25g_reg_masked_read(obj,
932 (enum al_serdes_reg_page)lane,
933 SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_ADDR,
934 SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_MASK,
935 SERDES_25G_LANE_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT,
942 static al_bool al_serdes_25g_rx_valid(
943 struct al_serdes_grp_obj *obj,
944 enum al_serdes_lane lane)
948 al_serdes_25g_reg_masked_read(obj,
949 (enum al_serdes_reg_page)lane,
950 SERDES_25G_LANE_TOP_LN_STAT_CTRL0_ADDR,
951 SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_MASK,
952 SERDES_25G_LANE_TOP_LN_STAT_CTRL0_RXVALID_SHIFT,
959 static al_bool al_serdes_25g_signal_is_detected(
960 struct al_serdes_grp_obj *obj,
961 enum al_serdes_lane lane)
963 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
965 al_bool signal_detect = AL_FALSE;
967 reg = al_reg_read32(®s_base->lane[lane].stat);
969 signal_detect = ((reg & (SERDES_C_LANE_STAT_LN_STAT_LOS |
970 SERDES_C_LANE_STAT_LN_STAT_LOS_DEGLITCH)) ?
973 return signal_detect;
977 static int al_serdes_25g_rx_equalization(
978 struct al_serdes_grp_obj *obj,
979 enum al_serdes_lane lane)
981 struct al_serdes_c_regs __iomem *regs_base = obj->regs_base;
982 uint32_t ready_mask = (SERDES_C_GEN_STATUS_CM0_RST_PD_READY | SERDES_C_GEN_STATUS_CM0_OK_O);
986 uint32_t retries = AL_SERDES_25G_RESET_NUM_RETRIES;
990 ready_mask |= SERDES_C_GEN_STATUS_LN0_RST_PD_READY;
991 reset_mask = SERDES_C_GEN_RST_LN0_RST_N;
993 ready_mask |= SERDES_C_GEN_STATUS_LN1_RST_PD_READY;
994 reset_mask = SERDES_C_GEN_RST_LN1_RST_N;
997 while (retries > 0) {
998 timeout = AL_SERDES_25G_WAIT_FOR_READY_TO;
1001 al_reg_write32_masked(®s_base->gen.rst, reset_mask, 0);
1003 al_msleep(AL_SERDES_25G_RESET_TO);
1005 al_serdes_25g_reg_masked_write(obj,
1006 (enum al_serdes_reg_page)lane,
1007 SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_ADDR,
1008 SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_MASK,
1009 SERDES_25G_LANE_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT,
1012 al_serdes_25g_reg_masked_write(obj,
1013 (enum al_serdes_reg_page)lane,
1014 SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR,
1015 SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_MASK,
1016 SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT,
1019 al_serdes_25g_reg_masked_write(obj,
1020 (enum al_serdes_reg_page)lane,
1021 SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_ADDR,
1022 SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_MASK,
1023 SERDES_25G_LANE_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT,
1026 al_msleep(AL_SERDES_25G_RESET_TO);
1028 al_reg_write32_masked(®s_base->gen.rst, reset_mask, reset_mask);
1031 reg_val = al_reg_read32(®s_base->gen.status);
1032 if ((reg_val & ready_mask) == ready_mask)
1039 al_err("%s: Timeout waiting for serdes ready\n", __func__);
1050 reg_val = al_reg_read32(®s_base->lane[lane].stat);
1051 reg_val &= (SERDES_C_LANE_STAT_LNX_STAT_OK |
1052 SERDES_C_LANE_STAT_LN_STAT_RXVALID);
1053 if (reg_val == (SERDES_C_LANE_STAT_LNX_STAT_OK |
1054 SERDES_C_LANE_STAT_LN_STAT_RXVALID))
1061 al_err("%s: TO waiting for lane ready (%x)\n", __func__, reg_val);
1075 al_err("%s: Failed to run equalization\n", __func__);
1083 #define AL_SERDES_25G_GCFSM2_READ_TIMEOUT 2000000 /* uSec */
1085 static int al_serdes_25g_gcfsm2_read(
1086 struct al_serdes_grp_obj *obj,
1087 enum al_serdes_lane lane,
1092 uint32_t timeout = AL_SERDES_25G_GCFSM2_READ_TIMEOUT;
1094 uint8_t data_low, data_high;
1098 /* Make sure GCFSM2 REQuest is off */
1099 al_serdes_25g_reg_masked_write(
1101 (enum al_serdes_reg_page)lane,
1102 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
1103 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
1104 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
1106 /* Write GCFSM2 CMD; CMD=0 for Read Request */
1107 al_serdes_25g_reg_masked_write(
1109 (enum al_serdes_reg_page)lane,
1110 SERDES_25G_LANE_GCFSM2_CMD_CTRL1_ADDR,
1111 SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_MASK,
1112 SERDES_25G_LANE_GCFSM2_CMD_CTRL1_CMD_SHIFT,
1114 /* Write GCFSM2 the Address we wish to read */
1115 al_serdes_25g_reg_write(
1117 (enum al_serdes_reg_page)lane,
1119 SERDES_25G_LANE_GCFSM2_CMD_CTRL2_ADDR,
1121 /* Issue a command REQuest */
1122 al_serdes_25g_reg_masked_write(
1124 (enum al_serdes_reg_page)lane,
1125 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
1126 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
1127 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
1129 /* Poll on GCFSM2 ACK */
1131 al_serdes_25g_reg_masked_read(
1133 (enum al_serdes_reg_page)lane,
1134 SERDES_25G_LANE_GCFSM2_CMD_STATUS_ADDR,
1135 SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_MASK,
1136 SERDES_25G_LANE_GCFSM2_CMD_STATUS_ACK_SHIFT,
1139 if (ack || (timeout == 0))
1147 /* Read 12bit of register value */
1148 al_serdes_25g_reg_read(
1150 (enum al_serdes_reg_page)lane,
1152 SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS0_ADDR,
1154 al_serdes_25g_reg_masked_read(
1156 (enum al_serdes_reg_page)lane,
1157 SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_ADDR,
1158 SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_MASK,
1159 SERDES_25G_LANE_GCFSM2_READ_SHADOW_DATA_STATUS1_11_8_SHIFT,
1161 *data = (data_high << 8) | data_low;
1163 al_err("%s: TO waiting for GCFSM2 req to complete (%x)\n", __func__, offset);
1167 /* Deassert the GCFSM2 REQuest */
1168 al_serdes_25g_reg_masked_write(
1170 (enum al_serdes_reg_page)lane,
1171 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_ADDR,
1172 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_MASK,
1173 SERDES_25G_LANE_GCFSM2_CMD_CTRL0_REQ_SHIFT,
1179 enum al_serdes_25g_rx_leq_fsm_opcode {
1180 AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ = 0x1,
1181 AL_SERDES_25G_RX_LEQ_FSM_OPCODE_WRITE = 0x2,
1184 enum al_serdes_25g_rx_leq_fsm_target {
1185 AL_SERDES_25G_RX_LEQ_FSM_TARGET_AGC_SOURCE = 0x1,
1186 AL_SERDES_25G_RX_LEQ_FSM_TARGET_PLE_ATT = 0x2,
1187 AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_LFG = 0x3,
1188 AL_SERDES_25G_RX_LEQ_FSM_TARGET_GN_APG = 0x4,
1189 AL_SERDES_25G_RX_LEQ_FSM_TARGET_GNEQ_CCL_LFG = 0x5,
1190 AL_SERDES_25G_RX_LEQ_FSM_TARGET_HFG_SQL = 0x6,
1191 AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBF = 0x8,
1192 AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBG = 0x9,
1193 AL_SERDES_25G_RX_LEQ_FSM_TARGET_VSCAN = 0xA,
1194 AL_SERDES_25G_RX_LEQ_FSM_TARGET_HSCAN = 0xB,
1195 AL_SERDES_25G_RX_LEQ_FSM_TARGET_EYE_INTF = 0xC,
1198 #define AL_SERDES_25G_RX_LEQ_FSM_TIMEOUT 2000000 /* uSec */
1200 static int al_serdes_25g_rx_leq_fsm_op(
1201 struct al_serdes_grp_obj *obj,
1202 enum al_serdes_lane lane,
1203 enum al_serdes_25g_rx_leq_fsm_opcode opcode,
1204 enum al_serdes_25g_rx_leq_fsm_target target,
1210 uint32_t timeout = AL_SERDES_25G_RX_LEQ_FSM_TIMEOUT;
1217 /* Write the OpCode & Target to LEQ FSM */
1218 reg = (target << 4) | opcode;
1219 al_serdes_25g_reg_write(
1221 (enum al_serdes_reg_page)lane,
1223 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD0_ADDR,
1226 /* Write 0 as MiscOption value to LEQ FSM */
1227 al_serdes_25g_reg_write(
1229 (enum al_serdes_reg_page)lane,
1231 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD2_ADDR,
1234 /* Write the ArgumentValue to LEQ FSM if needed*/
1235 if (opcode == AL_SERDES_25G_RX_LEQ_FSM_OPCODE_WRITE) {
1236 al_serdes_25g_reg_write(
1238 (enum al_serdes_reg_page)lane,
1240 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CMD1_ADDR,
1244 /* Issue an LEQ FSM Command Request */
1245 al_serdes_25g_reg_masked_write(
1247 (enum al_serdes_reg_page)lane,
1248 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR,
1249 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK,
1250 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT,
1253 /* Poll on LEQ FSM Command acknowledge */
1255 al_serdes_25g_reg_masked_read(
1257 (enum al_serdes_reg_page)lane,
1258 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_ADDR,
1259 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_MASK,
1260 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS5_LEQ_FSM_CMD_ACK_SHIFT,
1263 if (ack || (timeout == 0))
1272 al_serdes_25g_reg_read(
1274 (enum al_serdes_reg_page)lane,
1276 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_ADDR,
1280 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_MASK) >>
1281 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR1_SHIFT;
1283 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_MASK) >>
1284 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS0_LEQ_FSM_STATUS_ERROR2_SHIFT;
1287 al_err("%s: error in RX LEQ FSM req, err status 1=0x%x, err status 2=0x%x",
1288 __func__, err1, err2);
1292 /* Read LEQ FSM Command return Value */
1293 al_serdes_25g_reg_read(
1295 (enum al_serdes_reg_page)lane,
1297 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_STATUS3_ADDR,
1300 /* Clear an LEQ FSM Command Request */
1301 al_serdes_25g_reg_masked_write(
1303 (enum al_serdes_reg_page)lane,
1304 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_ADDR,
1305 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_MASK,
1306 SERDES_25G_LANE_LEQ_REFCLK_LEQ_FSM_CTRL0_LEQ_FSM_CMD_REQ_SHIFT,
1309 al_err("%s: TO waiting for RX LEQ FSM req to complete (opcode %x, target %x, val %x)\n",
1310 __func__, opcode, target, val);
1317 /* enum values correspond to HW values, don't change! */
1318 enum al_serdes_25g_tbus_obj {
1319 AL_SERDES_25G_TBUS_OBJ_TOP = 0,
1320 AL_SERDES_25G_TBUS_OBJ_CMU = 1,
1321 AL_SERDES_25G_TBUS_OBJ_LANE = 2,
1324 #define AL_SERDES_25G_TBUS_DELAY 1000 /* uSec */
1325 #define AL_SERDES_25G_TBUS_ADDR_HIGH_SHIFT 5
1327 static int al_serdes_25g_tbus_read(
1328 struct al_serdes_grp_obj *obj,
1329 enum al_serdes_lane lane,
1330 enum al_serdes_25g_tbus_obj tbus_obj,
1334 uint8_t addr_high, val_high, val_low;
1336 al_assert(lane < AL_SRDS_NUM_LANES);
1338 if (tbus_obj == AL_SERDES_25G_TBUS_OBJ_TOP)
1339 addr_high = AL_SERDES_25G_TBUS_OBJ_TOP;
1340 else if (tbus_obj == AL_SERDES_25G_TBUS_OBJ_CMU)
1341 addr_high = AL_SERDES_25G_TBUS_OBJ_CMU;
1343 addr_high = AL_SERDES_25G_TBUS_OBJ_LANE + lane;
1345 addr_high <<= AL_SERDES_25G_TBUS_ADDR_HIGH_SHIFT;
1347 al_serdes_25g_reg_write(
1349 AL_SRDS_REG_PAGE_TOP,
1351 SERDES_25G_TOP_TBUS_ADDR_7_0_ADDR,
1354 al_serdes_25g_reg_write(
1356 AL_SRDS_REG_PAGE_TOP,
1358 SERDES_25G_TOP_TBUS_ADDR_15_8_ADDR,
1361 al_udelay(AL_SERDES_25G_TBUS_DELAY);
1363 al_serdes_25g_reg_read(
1365 AL_SRDS_REG_PAGE_TOP,
1367 SERDES_25G_TOP_TBUS_DATA_7_0_ADDR,
1370 al_serdes_25g_reg_masked_read(
1372 AL_SRDS_REG_PAGE_TOP,
1373 SERDES_25G_TOP_TBUS_DATA_11_8_ADDR,
1374 SERDES_25G_TOP_TBUS_DATA_11_8_MASK,
1375 SERDES_25G_TOP_TBUS_DATA_11_8_SHIFT,
1378 *data = (val_high << 8) | val_low;
1383 #define AL_SERDES_25G_RX_ADV_PARAMS_ATT_MASK 0x07
1384 #define AL_SERDES_25G_RX_ADV_PARAMS_APG_MASK 0x03
1385 #define AL_SERDES_25G_RX_ADV_PARAMS_LFG_MASK 0x1F
1386 #define AL_SERDES_25G_RX_ADV_PARAMS_HFG_MASK 0x1F
1387 #define AL_SERDES_25G_RX_ADV_PARAMS_MBG_MASK 0x0F
1388 #define AL_SERDES_25G_RX_ADV_PARAMS_MBF_MASK 0x0F
1389 #define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT 8
1390 #define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_MASK 0x1F
1391 #define AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT 7
1393 static void al_serdes_25g_rx_advanced_params_get(
1394 struct al_serdes_grp_obj *obj,
1395 enum al_serdes_lane lane,
1398 struct al_serdes_25g_adv_rx_params *params = rx_params;
1402 int8_t *tap_ptr_arr[AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT];
1406 rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
1407 AL_SERDES_25G_RX_LEQ_FSM_TARGET_PLE_ATT, 0, &value, &err);
1409 al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read att, rc %d, err %d\n",
1413 params->att = value & AL_SERDES_25G_RX_ADV_PARAMS_ATT_MASK;
1415 rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
1416 AL_SERDES_25G_RX_LEQ_FSM_TARGET_GN_APG, 0, &value, &err);
1418 al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read apg, rc %d, err %d\n",
1422 params->apg = value & AL_SERDES_25G_RX_ADV_PARAMS_APG_MASK;
1424 rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
1425 AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_LFG, 0, &value, &err);
1427 al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read lfg, rc %d, err %d\n",
1431 params->lfg = value & AL_SERDES_25G_RX_ADV_PARAMS_LFG_MASK;
1433 rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
1434 AL_SERDES_25G_RX_LEQ_FSM_TARGET_HFG_SQL, 0, &value, &err);
1436 al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read hfg, rc %d, err %d\n",
1440 params->hfg = value & AL_SERDES_25G_RX_ADV_PARAMS_HFG_MASK;
1442 rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
1443 AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBG, 0, &value, &err);
1445 al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read mbg, rc %d, err %d\n",
1449 params->mbg = value & AL_SERDES_25G_RX_ADV_PARAMS_MBG_MASK;
1451 rc = al_serdes_25g_rx_leq_fsm_op(obj, lane, AL_SERDES_25G_RX_LEQ_FSM_OPCODE_READ,
1452 AL_SERDES_25G_RX_LEQ_FSM_TARGET_EQ_MBF, 0, &value, &err);
1454 al_err("%s: al_serdes_25g_rx_leq_fsm_op failed to read mbf, rc %d, err %d\n",
1458 params->mbf = value & AL_SERDES_25G_RX_ADV_PARAMS_MBF_MASK;
1460 tap_ptr_arr[0] = ¶ms->dfe_first_tap_even0_ctrl;
1461 tap_ptr_arr[1] = ¶ms->dfe_first_tap_even1_ctrl;
1462 tap_ptr_arr[2] = ¶ms->dfe_first_tap_odd0_ctrl;
1463 tap_ptr_arr[3] = ¶ms->dfe_first_tap_odd1_ctrl;
1464 tap_ptr_arr[4] = ¶ms->dfe_second_tap_ctrl;
1465 tap_ptr_arr[5] = ¶ms->dfe_third_tap_ctrl;
1466 tap_ptr_arr[6] = ¶ms->dfe_fourth_tap_ctrl;
1467 tap_ptr_arr[7] = ¶ms->dfe_fifth_tap_ctrl;
1469 for (i = 0; i < AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_CNT; i++) {
1470 al_serdes_25g_reg_read(
1472 (enum al_serdes_reg_page)lane,
1474 SERDES_25G_LANE_DFE_REFCLK_TAP_VAL_STATUS0_ADDR + i,
1477 tap_weight = value & AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_MASK;
1478 tap_sign = (value & AL_BIT(AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT)) >>
1479 AL_SERDES_25G_RX_ADV_PARAMS_DFE_TAP_SIGN_SHIFT;
1481 tap_weight = 0 - tap_weight;
1483 *tap_ptr_arr[i] = tap_weight;
1487 #define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_ADDR 0x0B
1488 #define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_MASK 0x3F
1489 #define AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT 7
1490 #define AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_ADDR 0x0C
1491 #define AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_MASK 0xFFF
1493 static void al_serdes_25g_tx_diag_info_get(
1494 struct al_serdes_grp_obj *obj,
1495 enum al_serdes_lane lane,
1498 struct al_serdes_25g_tx_diag_info *info = tx_info;
1499 uint8_t cal_x1, cal_x1_fixed, cal_x2, cal_xp5_fixed;
1500 uint16_t val16, sign;
1504 al_serdes_25g_reg_read(
1506 (enum al_serdes_reg_page)lane,
1508 SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_ADDR,
1510 info->regulated_supply = val8 & SERDES_25G_LANE_TOP_AFE_TXCP_CTRL0_REG_TXCP_TRIM_MASK;
1512 rc = al_serdes_25g_gcfsm2_read(
1515 AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_ADDR,
1518 al_err("%s: al_serdes_25g_gcfsm2_read failed to read dcd_trim, rc %d\n",
1523 abs = val16 & AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_MASK;
1524 sign = (val16 & AL_BIT(AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT)) >>
1525 AL_SERDES_25G_TX_DIAG_GCFSM2_DCD_TRIM_SIGN_SHIFT;
1527 info->dcd_trim = abs;
1529 info->dcd_trim = 0 - abs;
1531 rc = al_serdes_25g_gcfsm2_read(
1534 AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_ADDR,
1537 al_err("%s: al_serdes_25g_gcfsm2_read failed to read clk_delay, rc %d\n",
1541 info->clk_delay = val16 & AL_SERDES_25G_TX_DIAG_GCFSM2_CLK_DELAY_MASK;
1543 al_serdes_25g_reg_read(
1545 (enum al_serdes_reg_page)lane,
1547 SERDES_25G_CM_TOP_AFE_TXTC_CTRL2_ADDR,
1549 cal_x1 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_MASK) >>
1550 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_SHIFT;
1551 cal_x1_fixed = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_MASK) >>
1552 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL2_TXTC_CALP_X1_FIXED_SHIFT;
1553 al_serdes_25g_reg_read(
1555 (enum al_serdes_reg_page)lane,
1557 SERDES_25G_CM_TOP_AFE_TXTC_CTRL3_ADDR,
1559 cal_x2 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_MASK) >>
1560 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_X2_SHIFT;
1561 cal_xp5_fixed = (val8 &
1562 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_MASK) >>
1563 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL3_TXTC_CALP_XP5_FIXED_SHIFT;
1564 info->calp_multiplied_by_2 = 4 * cal_x2 + 2 * cal_x1 + 2 * cal_x1_fixed + cal_xp5_fixed;
1566 al_serdes_25g_reg_read(
1568 (enum al_serdes_reg_page)lane,
1570 SERDES_25G_CM_TOP_AFE_TXTC_CTRL0_ADDR,
1572 cal_x1 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_MASK) >>
1573 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_SHIFT;
1574 cal_x1_fixed = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_MASK) >>
1575 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL0_TXTC_CALN_X1_FIXED_SHIFT;
1576 al_serdes_25g_reg_read(
1578 (enum al_serdes_reg_page)lane,
1580 SERDES_25G_CM_TOP_AFE_TXTC_CTRL1_ADDR,
1582 cal_x2 = (val8 & SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_MASK) >>
1583 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_X2_SHIFT;
1584 cal_xp5_fixed = (val8 &
1585 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_MASK) >>
1586 SERDES_25G_CMU_TOP_AFE_TXTC_CTRL1_TXTC_CALN_XP5_FIXED_SHIFT;
1587 info->caln_multiplied_by_2 = 4 * cal_x2 + 2 * cal_x1 + 2 * cal_x1_fixed + cal_xp5_fixed;
1590 #define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_ABS_MASK 0x1F
1591 #define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK 0x3F
1592 #define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT 5
1593 #define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK 0xFC0
1594 #define AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT 6
1595 #define AL_SERDES_25G_RX_DIAG_LEQ_EQ_COUNT 5
1596 #define AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_EQ_ADDR 0
1597 #define AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_GAINSTAGE_ADDR 0x5
1598 #define AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_EVEN_ADDR 0x6
1599 #define AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_ODD_ADDR 0x7
1600 #define AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_EVEN_ADDR 0x8
1601 #define AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_ODD_ADDR 0x9
1602 #define AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_ADDR 0xF
1603 #define AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_MASK 0xFFF
1604 #define AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_EVEN_ADDR 0x11
1605 #define AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_ODD_ADDR 0x12
1606 #define AL_SERDES_25G_RX_DIAG_TBUS_EDGE_SLICER_ADDR 0x13
1607 #define AL_SERDES_25G_RX_DIAG_TBUS_EYE_SLICER_ADDR 0x23
1608 #define AL_SERDES_25G_RX_DIAG_TBUS_CDR_CLK_Q_ADDR 0x2
1609 #define AL_SERDES_25G_RX_DIAG_TBUS_CDR_CLK_I_ADDR 0x1
1610 #define AL_SERDES_25G_RX_DIAG_CDR_RXCLK_DLPF_L_ADDR 0x26
1611 #define AL_SERDES_25G_RX_DIAG_CDR_RXCLK_DLPF_H_ADDR 0x27
1613 static inline void al_serdes_25g_rx_diag_5bit_signed_set(uint8_t packed_val, int8_t *ptr)
1617 abs = packed_val & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_ABS_MASK;
1618 sign = (packed_val & AL_BIT(AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT)) >>
1619 AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_SIGN_SHIFT;
1626 static void al_serdes_25g_rx_diag_info_get(
1627 struct al_serdes_grp_obj *obj,
1628 enum al_serdes_lane lane,
1631 struct al_serdes_25g_rx_diag_info *info = rx_info;
1633 uint8_t val8, val8_2;
1637 al_serdes_25g_reg_read(
1639 (enum al_serdes_reg_page)lane,
1641 SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS0_ADDR,
1643 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->los_offset);
1645 al_serdes_25g_reg_read(
1647 (enum al_serdes_reg_page)lane,
1649 SERDES_25G_LANE_LOS_REFCLK_CALIBRATION_STATUS1_ADDR,
1651 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->agc_offset);
1653 rc = al_serdes_25g_gcfsm2_read(
1656 AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_GAINSTAGE_ADDR,
1659 al_err("%s: al_serdes_25g_gcfsm2_read failed to read leq_gainstage, rc %d\n",
1663 val8 = (uint8_t)val16;
1664 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_gainstage_offset);
1666 for (i = 0; i < AL_SERDES_25G_RX_DIAG_LEQ_EQ_COUNT; i++) {
1667 rc = al_serdes_25g_gcfsm2_read(
1670 AL_SERDES_25G_RX_DIAG_GCFSM2_LEQ_EQ_ADDR + i,
1673 al_err("%s: al_serdes_25g_gcfsm2_read failed to read leq_eq %d, rc %d\n",
1677 val8 = (uint8_t)val16;
1681 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq1_offset);
1684 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq2_offset);
1687 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq3_offset);
1690 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq4_offset);
1693 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->leq_eq5_offset);
1700 rc = al_serdes_25g_gcfsm2_read(
1703 AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_EVEN_ADDR,
1706 al_err("%s: al_serdes_25g_gcfsm2_read failed to read summer_even_offset, rc %d\n",
1710 val8 = (uint8_t)val16;
1711 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->summer_even_offset);
1713 rc = al_serdes_25g_gcfsm2_read(
1716 AL_SERDES_25G_RX_DIAG_GCFSM2_SUMMER_ODD_ADDR,
1719 al_err("%s: al_serdes_25g_gcfsm2_read failed to read summer_odd_offset, rc %d\n",
1723 val8 = (uint8_t)val16;
1724 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->summer_odd_offset);
1726 rc = al_serdes_25g_gcfsm2_read(
1729 AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_EVEN_ADDR,
1732 al_err("%s: al_serdes_25g_gcfsm2_read failed to read vscan_even_offset, rc %d\n",
1736 val8 = (uint8_t)val16;
1737 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->vscan_even_offset);
1739 rc = al_serdes_25g_gcfsm2_read(
1742 AL_SERDES_25G_RX_DIAG_GCFSM2_VSCAN_ODD_ADDR,
1745 al_err("%s: al_serdes_25g_gcfsm2_read failed to read vscan_odd_offset, rc %d\n",
1749 val8 = (uint8_t)val16;
1750 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->vscan_odd_offset);
1752 al_serdes_25g_tbus_read(
1755 AL_SERDES_25G_TBUS_OBJ_LANE,
1756 AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_EVEN_ADDR,
1758 val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
1759 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_even0_offset);
1760 val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
1761 AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
1762 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_even1_offset);
1764 al_serdes_25g_tbus_read(
1767 AL_SERDES_25G_TBUS_OBJ_LANE,
1768 AL_SERDES_25G_RX_DIAG_TBUS_DATA_SLICER_ODD_ADDR,
1770 val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
1771 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_odd0_offset);
1772 val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
1773 AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
1774 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->data_slicer_odd1_offset);
1776 al_serdes_25g_tbus_read(
1779 AL_SERDES_25G_TBUS_OBJ_LANE,
1780 AL_SERDES_25G_RX_DIAG_TBUS_EDGE_SLICER_ADDR,
1782 val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
1783 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->edge_slicer_even_offset);
1784 val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
1785 AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
1786 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->edge_slicer_odd_offset);
1788 al_serdes_25g_tbus_read(
1791 AL_SERDES_25G_TBUS_OBJ_LANE,
1792 AL_SERDES_25G_RX_DIAG_TBUS_EYE_SLICER_ADDR,
1794 val8 = (uint8_t)(val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_MASK);
1795 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->eye_slicer_even_offset);
1796 val8 = (uint8_t)((val16 & AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_MASK) >>
1797 AL_SERDES_25G_RX_DIAG_SIGNED_5BIT_HIGH_SHIFT);
1798 al_serdes_25g_rx_diag_5bit_signed_set(val8, &info->eye_slicer_odd_offset);
1800 al_serdes_25g_reg_masked_read(
1802 (enum al_serdes_reg_page)lane,
1803 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_ADDR,
1804 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_MASK,
1805 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL0_RXCDR_HSCAN_CLKQ_SHIFT,
1808 al_serdes_25g_reg_masked_read(
1810 (enum al_serdes_reg_page)lane,
1811 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_ADDR,
1812 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_MASK,
1813 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL1_RXCDR_HSCAN_CLKI_SHIFT,
1816 al_serdes_25g_reg_masked_read(
1818 (enum al_serdes_reg_page)lane,
1819 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_ADDR,
1820 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_MASK,
1821 SERDES_25G_LANE_CDR_REFCLK_AFE_PI_CTRL2_RXCDR_HSCAN_EYE_SHIFT,
1824 al_serdes_25g_reg_masked_read(
1826 (enum al_serdes_reg_page)lane,
1827 SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_ADDR,
1828 SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_MASK,
1829 SERDES_25G_LANE_CDR_REFCLK_AFE_VCO_CTRL2_RXCDR_DOSC_SHIFT,
1830 &info->cdr_vco_dosc);
1832 al_serdes_25g_reg_read(
1834 (enum al_serdes_reg_page)lane,
1836 SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_ADDR,
1838 al_serdes_25g_reg_read(
1840 (enum al_serdes_reg_page)lane,
1842 SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL0_ADDR,
1844 val8_2 &= SERDES_25G_LANE_CDR_RXCLK_LOAD_MODE_CTRL1_DLPF_VAL_8_MASK;
1845 info->cdr_dlpf = (uint16_t)val8_2 << 8 | val8;
1847 rc = al_serdes_25g_gcfsm2_read(
1850 AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_ADDR,
1853 al_err("%s: al_serdes_25g_gcfsm2_read failed to read cdr_vco_fr, rc %d\n",
1857 info->cdr_vco_fr = val16 & AL_SERDES_25G_RX_DIAG_GCFSM2_CDR_VCO_FR_MASK;
1859 al_serdes_25g_reg_masked_read(
1861 (enum al_serdes_reg_page)lane,
1862 SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_ADDR,
1863 SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_MASK,
1864 SERDES_25G_LANE_LEQ_REFCLK_AFE_PLE_CTRL0_RXLEQ_PLE_BLW_ZERO_SHIFT,
1865 &info->ple_resistance);
1867 al_serdes_25g_reg_read(
1869 (enum al_serdes_reg_page)lane,
1871 SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_ADDR,
1874 info->rx_term_mode = (val8 & SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_MASK) >>
1875 SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_HIZ_SHIFT;
1877 info->rx_coupling = (val8 & SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_MASK) >>
1878 SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL0_RXTERM_VCM_GND_SHIFT;
1880 al_serdes_25g_reg_masked_read(
1882 (enum al_serdes_reg_page)lane,
1883 SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_ADDR,
1884 SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_MASK,
1885 SERDES_25G_LANE_TOP_AFE_RXTERM_CTRL1_RXTERM_VAL_SHIFT,
1886 &info->rx_term_cal_code);
1888 al_serdes_25g_reg_masked_read(
1890 (enum al_serdes_reg_page)lane,
1891 SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_ADDR,
1892 SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_MASK,
1893 SERDES_25G_LANE_LEQ_REFCLK_AFE_BIAS_CTRL1_RXLEQ_BIASI_TRIM_SHIFT,
1894 &info->rx_sheet_res_cal_code);
1897 /******************************************************************************/
1898 /******************************************************************************/
1899 int al_serdes_25g_handle_init(
1900 void __iomem *serdes_regs_base,
1901 struct al_serdes_grp_obj *obj)
1909 al_memset(obj, 0, sizeof(struct al_serdes_grp_obj));
1911 obj->regs_base = (struct al_serdes_regs *)serdes_regs_base;
1912 obj->type_get = al_serdes_25g_type_get;
1913 obj->reg_read = al_serdes_25g_reg_read;
1914 obj->reg_write = al_serdes_25g_reg_write;
1915 obj->bist_overrides_enable = NULL;
1916 obj->bist_overrides_disable = NULL;
1917 obj->rx_rate_change = NULL;
1918 obj->group_pm_set = NULL;
1919 obj->lane_pm_set = NULL;
1920 obj->pma_hard_reset_group = NULL;
1921 obj->pma_hard_reset_lane = NULL;
1922 obj->loopback_control = NULL;
1923 obj->bist_pattern_select = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_pattern_select);
1924 obj->bist_tx_enable = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_tx_enable);
1925 obj->bist_tx_err_inject = NULL;
1926 obj->bist_rx_enable = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_rx_enable);
1927 obj->bist_rx_status = AL_SRDS_ADV_SRVC(al_serdes_25g_bist_rx_status);
1928 obj->tx_deemph_preset = NULL;
1929 obj->tx_deemph_inc = NULL;
1930 obj->tx_deemph_dec = NULL;
1931 obj->eye_measure_run = NULL;
1932 obj->eye_diag_sample = NULL;
1933 obj->eye_diag_run = AL_SRDS_ADV_SRVC(al_serdes_25g_eye_diag_run);
1934 obj->cdr_is_locked = AL_SRDS_ADV_SRVC(al_serdes_25g_cdr_is_locked);
1935 obj->rx_valid = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_valid);
1936 obj->signal_is_detected = AL_SRDS_ADV_SRVC(al_serdes_25g_signal_is_detected);
1937 obj->tx_advanced_params_set = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_advanced_params_set);
1938 obj->tx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_advanced_params_get);
1939 obj->rx_advanced_params_set = NULL;
1940 obj->rx_advanced_params_get = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_advanced_params_get);
1941 obj->tx_diag_info_get = AL_SRDS_ADV_SRVC(al_serdes_25g_tx_diag_info_get);
1942 obj->rx_diag_info_get = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_diag_info_get);
1943 obj->mode_set_sgmii = NULL;
1944 obj->mode_set_kr = NULL;
1945 obj->rx_equalization = AL_SRDS_ADV_SRVC(al_serdes_25g_rx_equalization);
1946 obj->calc_eye_size = AL_SRDS_ADV_SRVC(al_serdes_25g_calc_eye_size);
1947 obj->sris_config = NULL;