1 /*******************************************************************************
2 Copyright (C) 2015 Annapurna Labs Ltd.
4 This file may be licensed under the terms of the Annapurna Labs Commercial
7 Alternatively, this file can be distributed under the terms of the GNU General
8 Public License V2 as published by the Free Software Foundation and can be
9 found at http://www.gnu.org/licenses/gpl-2.0.html
11 Alternatively, redistribution and use in source and binary forms, with or
12 without modification, are permitted provided that the following conditions are
15 * Redistributions of source code must retain the above copyright notice,
16 this list of conditions and the following disclaimer.
18 * Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in
20 the documentation and/or other materials provided with the
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
24 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
27 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *******************************************************************************/
35 #ifndef __AL_SERDES_INTERNAL_REGS_H__
36 #define __AL_SERDES_INTERNAL_REGS_H__
42 /*******************************************************************************
43 * Per lane register fields
44 ******************************************************************************/
46 * RX and TX lane hard reset
47 * 0 - Hard reset is asserted
48 * 1 - Hard reset is de-asserted
50 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM 2
51 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK 0x01
52 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT 0x00
53 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT 0x01
56 * RX and TX lane hard reset control
57 * 0 - Hard reset is taken from the interface pins
58 * 1 - Hard reset is taken from registers
60 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM 2
61 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK 0x02
62 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE 0x00
63 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS 0x02
65 /* RX lane power state control */
66 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM 3
67 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK 0x1f
68 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD 0x01
69 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2 0x02
70 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1 0x04
71 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S 0x08
72 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0 0x10
74 /* TX lane power state control */
75 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM 4
76 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK 0x1f
77 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD 0x01
78 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2 0x02
79 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1 0x04
80 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S 0x08
81 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0 0x10
83 /* RX lane word width */
84 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM 5
85 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK 0x07
86 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8 0x00
87 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10 0x01
88 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16 0x02
89 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20 0x03
90 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32 0x04
91 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40 0x05
93 /* TX lane word width */
94 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM 5
95 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK 0x70
96 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8 0x00
97 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10 0x10
98 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16 0x20
99 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20 0x30
100 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32 0x40
101 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40 0x50
103 /* RX lane rate select */
104 #define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM 6
105 #define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK 0x07
106 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8 0x00
107 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4 0x01
108 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2 0x02
109 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1 0x03
111 /* TX lane rate select */
112 #define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM 6
113 #define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK 0x70
114 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8 0x00
115 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4 0x10
116 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2 0x20
117 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1 0x30
120 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
121 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
122 * partial equalized RX signal out the transmit IO pins
124 #define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM 7
125 #define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN 0x10
128 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
129 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
130 * the TX serializer output into the CDR
132 #define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM 7
133 #define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN 0x20
136 * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
137 * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
138 * lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to
141 #define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM 7
142 #define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN 0x40
145 * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
146 * receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 -
147 * Disables loopback 1 - Loops back the 20-bit receive data port to the
150 #define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM 7
151 #define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN 0x80
154 * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
155 * Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1
156 * - Selects CDR clock for transmit
158 #define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM 7
159 #define SERDES_IREG_FLD_LB_CDRCLK2TXEN 0x01
161 /* Receive lane BIST enable. Active High */
162 #define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM 8
163 #define SERDES_IREG_FLD_PCSRXBIST_EN 0x01
165 /* TX lane BIST enable. Active High */
166 #define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM 8
167 #define SERDES_IREG_FLD_PCSTXBIST_EN 0x02
170 * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
171 * the test has completed, and will remain high until a new test is initiated
173 #define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM 8
174 #define SERDES_IREG_FLD_RXBIST_DONE 0x04
177 * RX BIST error count overflow indicator. Indicates an overflow in the number
178 * of byte errors identified during the course of the test. This word is stable
179 * to sample when *_DONE_* signal has asserted
181 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM 8
182 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW 0x08
185 * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
186 * comparisons have not begun yet 1 - Indicates BIST is word locked and error
187 * comparisons have begun
189 #define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM 8
190 #define SERDES_IREG_FLD_RXBIST_RXLOCKED 0x10
193 * RX BIST error count word. Indicates the number of byte errors identified
194 * during the course of the test. This word is stable to sample when *_DONE_*
195 * signal has asserted
197 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM 9
198 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM 10
201 #define SERDES_IREG_TX_DRV_1_REG_NUM 21
202 #define SERDES_IREG_TX_DRV_1_HLEV_MASK 0x7
203 #define SERDES_IREG_TX_DRV_1_HLEV_SHIFT 0
204 #define SERDES_IREG_TX_DRV_1_LEVN_MASK 0xf8
205 #define SERDES_IREG_TX_DRV_1_LEVN_SHIFT 3
207 #define SERDES_IREG_TX_DRV_2_REG_NUM 22
208 #define SERDES_IREG_TX_DRV_2_LEVNM1_MASK 0xf
209 #define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT 0
210 #define SERDES_IREG_TX_DRV_2_LEVNM2_MASK 0x30
211 #define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT 4
213 #define SERDES_IREG_TX_DRV_3_REG_NUM 23
214 #define SERDES_IREG_TX_DRV_3_LEVNP1_MASK 0x7
215 #define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT 0
216 #define SERDES_IREG_TX_DRV_3_SLEW_MASK 0x18
217 #define SERDES_IREG_TX_DRV_3_SLEW_SHIFT 3
220 #define SERDES_IREG_RX_CALEQ_1_REG_NUM 24
221 #define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK 0x7
222 #define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT 0
223 /* DFE post-shaping tap 3dB frequency */
224 #define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK 0x38
225 #define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT 3
227 #define SERDES_IREG_RX_CALEQ_2_REG_NUM 25
228 /* DFE post-shaping tap gain */
229 #define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK 0x7
230 #define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT 0
231 /* DFE first tap gain control */
232 #define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK 0x78
233 #define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT 3
235 #define SERDES_IREG_RX_CALEQ_3_REG_NUM 26
236 #define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK 0xf
237 #define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT 0
238 #define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK 0xf0
239 #define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT 4
241 #define SERDES_IREG_RX_CALEQ_4_REG_NUM 27
242 #define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK 0xf
243 #define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT 0
244 #define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK 0x70
245 #define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT 4
247 #define SERDES_IREG_RX_CALEQ_5_REG_NUM 28
248 #define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK 0x7
249 #define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT 0
250 #define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK 0xf8
251 #define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT 3
253 /* RX lane best eye point measurement result */
254 #define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM 29
255 #define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM 30
256 #define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK 0x3F
259 * Adaptive RX Equalization enable
260 * 0 - Disables adaptive RX equalization.
261 * 1 - Enables adaptive RX equalization.
263 #define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM 31
264 #define SERDES_IREG_FLD_PCSRXEQ_START (1 << 0)
267 * Enables an eye diagram measurement
269 * 0 - Disables eye diagram measurement
270 * 1 - Enables eye diagram measurement
272 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM 31
273 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START (1 << 1)
277 * RX lane single roam eye point measurement start signal.
278 * If asserted, single measurement at fix XADJUST and YADJUST is started.
280 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM 31
281 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START (1 << 2)
285 * PHY Eye diagram measurement status
287 * 0 - Indicates eye diagram results are not
289 * 1 - Indicates eye diagram is complete and
290 * results are valid for sampling
292 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM 32
293 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE (1 << 0)
296 * Eye diagram error signal. Indicates if the
297 * measurement was invalid because the eye
298 * diagram was interrupted by the link entering
300 * 0 - Indicates eye diagram is valid
301 * 1- Indicates an error occurred, and the eye
302 * diagram measurement should be re-run
304 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM 32
305 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR (1 << 1)
308 * PHY Adaptive Equalization status
309 * 0 - Indicates Adaptive Equalization results are not valid for sampling
310 * 1 - Indicates Adaptive Equalization is complete and results are valid for
313 #define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM 32
314 #define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE (1 << 2)
318 * PHY Adaptive Equalization Status Signal
319 * 0 – Indicates adaptive equalization results
320 * are not valid for sampling
321 * 1 – Indicates adaptive equalization is
322 * complete and results are valid for sampling.
324 #define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM 32
325 #define SERDES_IREG_FLD_RXEQ_DONE (1 << 3)
329 * 7-bit eye diagram time adjust control
333 #define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM 33
335 /* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */
336 #define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM 34
339 * Eye diagram status signal. Safe for
340 * sampling when *DONE* signal has
342 * 14'h0000 - Completely Closed Eye
343 * 14'hFFFF - Completely Open Eye
345 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM 35
346 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE 0xFF
347 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT 0
349 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM 36
350 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE 0x3F
351 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT 0
354 * RX lane single roam eye point measurement result.
355 * If 0, eye is open at current XADJUST and YADJUST settings.
357 #define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM 37
358 #define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM 38
361 * Override enable for CDR lock to reference clock
362 * 0 - CDR is always locked to reference
363 * 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally
364 * depending on the incoming signal and ppm status)
366 #define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM 39
367 #define SERDES_IREG_FLD_RXLOCK2REF_OVREN (1 << 1)
370 * Selects Eye to capture based on edge
371 * 0 - Capture 1st Eye in Eye Diagram
372 * 1 - Capture 2nd Eye in Eye Diagram measurement
374 #define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM 39
375 #define SERDES_IREG_FLD_RXROAM_XORBITSEL (1 << 2)
376 #define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST 0
377 #define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND (1 << 2)
380 * RX Signal detect. 0 indicates no signal, 1 indicates signal detected.
382 #define SERDES_IREG_FLD_RXRANDET_REG_NUM 41
383 #define SERDES_IREG_FLD_RXRANDET_STAT 0x20
386 * RX data polarity inversion control:
388 * 1'b1: invert polarity
390 #define SERDES_IREG_FLD_POLARITY_RX_REG_NUM 46
391 #define SERDES_IREG_FLD_POLARITY_RX_INV (1 << 0)
394 * TX data polarity inversion control:
396 * 1'b1: invert polarity
398 #define SERDES_IREG_FLD_POLARITY_TX_REG_NUM 46
399 #define SERDES_IREG_FLD_POLARITY_TX_INV (1 << 1)
401 /* LANEPCSPSTATE* override enable (Active low) */
402 #define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM 85
403 #define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN (1 << 0)
405 /* LB* override enable (Active low) */
406 #define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM 85
407 #define SERDES_IREG_FLD_LB_LOCWREN (1 << 1)
409 /* PCSRX* override enable (Active low) */
410 #define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM 85
411 #define SERDES_IREG_FLD_PCSRX_LOCWREN (1 << 4)
413 /* PCSRXBIST* override enable (Active low) */
414 #define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM 85
415 #define SERDES_IREG_FLD_PCSRXBIST_LOCWREN (1 << 5)
417 /* PCSRXEQ* override enable (Active low) */
418 #define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM 85
419 #define SERDES_IREG_FLD_PCSRXEQ_LOCWREN (1 << 6)
421 /* PCSTX* override enable (Active low) */
422 #define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM 85
423 #define SERDES_IREG_FLD_PCSTX_LOCWREN (1 << 7)
427 * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN,
428 * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
429 * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
431 #define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM 86
433 /* PCSTXBIST* override enable (Active low) */
434 #define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM 86
435 #define SERDES_IREG_FLD_PCSTXBIST_LOCWREN (1 << 0)
437 /* Override RX_CALCEQ through the internal registers (Active low) */
438 #define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM 86
439 #define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN (1 << 3)
441 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM 86
442 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN (1 << 4)
445 /* RXCALROAMEYEMEASIN* override enable - Active Low */
446 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM 86
447 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN (1 << 6)
449 /* RXCALROAMXADJUST* override enable - Active Low */
450 #define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM 86
451 #define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN (1 << 7)
453 /* RXCALROAMYADJUST* override enable - Active Low */
454 #define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM 87
455 #define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN (1 << 0)
457 /* RXCDRCALFOSC* override enable. Active Low */
458 #define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM 87
459 #define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN (1 << 1)
461 /* Over-write enable for RXEYEDIAGFSM_INITXVAL */
462 #define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM 87
463 #define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN (1 << 2)
465 /* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */
466 #define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM 87
467 #define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN (1 << 3)
469 /* TXCALTCLKDUTY* override enable. Active Low */
470 #define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM 87
471 #define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN (1 << 4)
473 /* Override TX_DRV through the internal registers (Active low) */
474 #define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM 87
475 #define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN (1 << 5)
477 /*******************************************************************************
478 * Common lane register fields - PMA
479 ******************************************************************************/
481 * Common lane hard reset control
482 * 0 - Hard reset is taken from the interface pins
483 * 1 - Hard reset is taken from registers
485 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM 2
486 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK 0x01
487 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE 0x00
488 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS 0x01
491 * Common lane hard reset
492 * 0 - Hard reset is asserted
493 * 1 - Hard reset is de-asserted
495 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM 2
496 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK 0x02
497 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT 0x00
498 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT 0x02
500 /* Synth power state control */
501 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM 3
502 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK 0x1f
503 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD 0x01
504 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2 0x02
505 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1 0x04
506 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S 0x08
507 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0 0x10
509 /* Transmit datapath FIFO enable (Active High) */
510 #define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM 8
511 #define SERDES_IREG_FLD_CMNPCS_TXENABLE (1 << 2)
514 * RX lost of signal detector enable
518 #define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM 13
519 #define SERDES_IREG_FLD_RXLOSDET_ENABLE AL_BIT(4)
521 /* Signal Detect Threshold Level */
522 #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM 15
523 #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK AL_FIELD_MASK(2, 0)
525 /* LOS Detect Threshold Level */
526 #define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM 15
527 #define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK AL_FIELD_MASK(4, 3)
528 #define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT 3
530 #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM 30
531 #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK 0x7f
532 #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT 0
534 #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM 31
535 #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK 0x7f
536 #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT 0
538 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM 32
539 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK 0xff
540 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT 0
542 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM 33
543 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK 0x1
544 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT 0
546 #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM 33
547 #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK 0x3e
548 #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT 1
550 #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM 34
551 #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK 0xff
552 #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT 0
554 #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM 35
555 #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK 0x1
556 #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT 0
558 #define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM 35
559 #define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK 0x3e
560 #define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT 1
562 #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM 36
563 #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK 0xff
564 #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT 0
566 #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM 37
567 #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK 0x7
568 #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT 0
570 #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM 43
571 #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK 0x7
572 #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT 0
574 #define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num) (56 + (byte_num))
575 #define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES 10
578 * Selects the transmit BIST mode:
579 * 0 - Uses the 80-bit internal memory pattern (w/ OOB)
580 * 1 - Uses a 27 PRBS pattern
581 * 2 - Uses a 223 PRBS pattern
582 * 3 - Uses a 231 PRBS pattern
583 * 4 - Uses a 1010 clock pattern
584 * 5 and above - Reserved
586 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM 80
587 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK 0x07
588 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER 0x00
589 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7 0x01
590 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23 0x02
591 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31 0x03
592 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010 0x04
594 /* Single-Bit error injection enable (on posedge) */
595 #define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM 80
596 #define SERDES_IREG_FLD_TXBIST_BITERROR_EN 0x20
598 /* CMNPCIEGEN3* override enable (Active Low) */
599 #define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM 95
600 #define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN (1 << 2)
602 /* CMNPCS* override enable (Active Low) */
603 #define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM 95
604 #define SERDES_IREG_FLD_CMNPCS_LOCWREN (1 << 3)
606 /* CMNPCSBIST* override enable (Active Low) */
607 #define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM 95
608 #define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN (1 << 4)
610 /* CMNPCSPSTATE* override enable (Active Low) */
611 #define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM 95
612 #define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN (1 << 5)
614 /* PCS_EN* override enable (Active Low) */
615 #define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM 96
616 #define SERDES_IREG_FLD_PCS_LOCWREN (1 << 3)
618 /* Eye diagram sample count */
619 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM 150
620 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK 0xff
621 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT 0
623 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM 151
624 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK 0xff
625 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT 0
627 /* override control */
628 #define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM 230
629 #define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN 1 << 0
631 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM 623
632 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK 0xff
633 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT 0
635 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM 624
636 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK 0xff
637 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT 0
639 /* X and Y coefficient return value */
640 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM 626
641 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK 0x0F
642 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT 0
643 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK 0xF0
644 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT 4
646 /* X coarse scan step */
647 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM 627
648 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK 0x7F
649 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT 0
651 /* X fine scan step */
652 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM 628
653 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK 0x7F
654 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT 0
656 /* Y coarse scan step */
657 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM 629
658 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK 0x0F
659 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT 0
661 /* Y fine scan step */
662 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM 630
663 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK 0x0F
664 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT 0
666 #define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM 157
668 #define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM 158
670 #define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM 159
672 #define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM 160
674 #define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM 163
676 #define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM 164
678 /*******************************************************************************
679 * Common lane register fields - PCS
680 ******************************************************************************/
681 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM 3
682 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK AL_FIELD_MASK(5, 4)
683 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT 4
685 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM 6
686 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA AL_BIT(2)
688 #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM 18
689 #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK 0x1F
690 #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT 0
692 #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM 19
693 #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK 0x7C
694 #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT 2
696 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM 20
697 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK 0x1F
698 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT 0
700 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM 21
701 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK 0x7C
702 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT 2
704 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM 22
705 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK 0x7f
706 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT 0
708 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM 34
709 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK 0x7f
710 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT 0
712 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM 23
713 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK 0xff
714 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT 0
716 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM 22
717 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK 0x80
718 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT 7
720 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM 24
721 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK 0x3e
722 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT 1
724 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM 35
725 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK 0xff
726 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT 0
728 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM 34
729 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK 0x80
730 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT 7
732 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM 36
733 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK 0x1f
734 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT 0
736 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM 37
737 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK 0xff
738 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT 0
740 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM 36
741 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK 0xe0
742 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT 5
748 #endif /* __AL_serdes_REG_H */