2 *******************************************************************************
3 Copyright (C) 2015 Annapurna Labs Ltd.
5 This file may be licensed under the terms of the Annapurna Labs Commercial
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
12 Alternatively, redistribution and use in source and binary forms, with or
13 without modification, are permitted provided that the following conditions are
16 * Redistributions of source code must retain the above copyright notice,
17 this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in
21 the documentation and/or other materials provided with the
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *******************************************************************************/
36 #ifndef __AL_SERDES_INTERNAL_REGS_H__
37 #define __AL_SERDES_INTERNAL_REGS_H__
43 /*******************************************************************************
44 * Per lane register fields
45 ******************************************************************************/
47 * RX and TX lane hard reset
48 * 0 - Hard reset is asserted
49 * 1 - Hard reset is de-asserted
51 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM 2
52 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK 0x01
53 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT 0x00
54 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT 0x01
57 * RX and TX lane hard reset control
58 * 0 - Hard reset is taken from the interface pins
59 * 1 - Hard reset is taken from registers
61 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM 2
62 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK 0x02
63 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE 0x00
64 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS 0x02
66 /* RX lane power state control */
67 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM 3
68 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK 0x1f
69 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD 0x01
70 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2 0x02
71 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1 0x04
72 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S 0x08
73 #define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0 0x10
75 /* TX lane power state control */
76 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM 4
77 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK 0x1f
78 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD 0x01
79 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2 0x02
80 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1 0x04
81 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S 0x08
82 #define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0 0x10
84 /* RX lane word width */
85 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM 5
86 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK 0x07
87 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8 0x00
88 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10 0x01
89 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16 0x02
90 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20 0x03
91 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32 0x04
92 #define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40 0x05
94 /* TX lane word width */
95 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM 5
96 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK 0x70
97 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8 0x00
98 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10 0x10
99 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16 0x20
100 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20 0x30
101 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32 0x40
102 #define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40 0x50
104 /* RX lane rate select */
105 #define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM 6
106 #define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK 0x07
107 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8 0x00
108 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4 0x01
109 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2 0x02
110 #define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1 0x03
112 /* TX lane rate select */
113 #define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM 6
114 #define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK 0x70
115 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8 0x00
116 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4 0x10
117 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2 0x20
118 #define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1 0x30
121 * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
122 * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
123 * partial equalized RX signal out the transmit IO pins
125 #define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM 7
126 #define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN 0x10
129 * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
130 * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
131 * the TX serializer output into the CDR
133 #define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM 7
134 #define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN 0x20
137 * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
138 * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
139 * lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to
142 #define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM 7
143 #define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN 0x40
146 * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
147 * receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 -
148 * Disables loopback 1 - Loops back the 20-bit receive data port to the
151 #define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM 7
152 #define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN 0x80
155 * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
156 * Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1
157 * - Selects CDR clock for transmit
159 #define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM 7
160 #define SERDES_IREG_FLD_LB_CDRCLK2TXEN 0x01
162 /* Receive lane BIST enable. Active High */
163 #define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM 8
164 #define SERDES_IREG_FLD_PCSRXBIST_EN 0x01
166 /* TX lane BIST enable. Active High */
167 #define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM 8
168 #define SERDES_IREG_FLD_PCSTXBIST_EN 0x02
171 * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
172 * the test has completed, and will remain high until a new test is initiated
174 #define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM 8
175 #define SERDES_IREG_FLD_RXBIST_DONE 0x04
178 * RX BIST error count overflow indicator. Indicates an overflow in the number
179 * of byte errors identified during the course of the test. This word is stable
180 * to sample when *_DONE_* signal has asserted
182 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM 8
183 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW 0x08
186 * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
187 * comparisons have not begun yet 1 - Indicates BIST is word locked and error
188 * comparisons have begun
190 #define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM 8
191 #define SERDES_IREG_FLD_RXBIST_RXLOCKED 0x10
194 * RX BIST error count word. Indicates the number of byte errors identified
195 * during the course of the test. This word is stable to sample when *_DONE_*
196 * signal has asserted
198 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM 9
199 #define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM 10
202 #define SERDES_IREG_TX_DRV_1_REG_NUM 21
203 #define SERDES_IREG_TX_DRV_1_HLEV_MASK 0x7
204 #define SERDES_IREG_TX_DRV_1_HLEV_SHIFT 0
205 #define SERDES_IREG_TX_DRV_1_LEVN_MASK 0xf8
206 #define SERDES_IREG_TX_DRV_1_LEVN_SHIFT 3
208 #define SERDES_IREG_TX_DRV_2_REG_NUM 22
209 #define SERDES_IREG_TX_DRV_2_LEVNM1_MASK 0xf
210 #define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT 0
211 #define SERDES_IREG_TX_DRV_2_LEVNM2_MASK 0x30
212 #define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT 4
214 #define SERDES_IREG_TX_DRV_3_REG_NUM 23
215 #define SERDES_IREG_TX_DRV_3_LEVNP1_MASK 0x7
216 #define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT 0
217 #define SERDES_IREG_TX_DRV_3_SLEW_MASK 0x18
218 #define SERDES_IREG_TX_DRV_3_SLEW_SHIFT 3
221 #define SERDES_IREG_RX_CALEQ_1_REG_NUM 24
222 #define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK 0x7
223 #define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT 0
224 /* DFE post-shaping tap 3dB frequency */
225 #define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK 0x38
226 #define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT 3
228 #define SERDES_IREG_RX_CALEQ_2_REG_NUM 25
229 /* DFE post-shaping tap gain */
230 #define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK 0x7
231 #define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT 0
232 /* DFE first tap gain control */
233 #define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK 0x78
234 #define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT 3
236 #define SERDES_IREG_RX_CALEQ_3_REG_NUM 26
237 #define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK 0xf
238 #define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT 0
239 #define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK 0xf0
240 #define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT 4
242 #define SERDES_IREG_RX_CALEQ_4_REG_NUM 27
243 #define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK 0xf
244 #define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT 0
245 #define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK 0x70
246 #define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT 4
248 #define SERDES_IREG_RX_CALEQ_5_REG_NUM 28
249 #define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK 0x7
250 #define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT 0
251 #define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK 0xf8
252 #define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT 3
254 /* RX lane best eye point measurement result */
255 #define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM 29
256 #define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM 30
257 #define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK 0x3F
260 * Adaptive RX Equalization enable
261 * 0 - Disables adaptive RX equalization.
262 * 1 - Enables adaptive RX equalization.
264 #define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM 31
265 #define SERDES_IREG_FLD_PCSRXEQ_START (1 << 0)
268 * Enables an eye diagram measurement
270 * 0 - Disables eye diagram measurement
271 * 1 - Enables eye diagram measurement
273 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM 31
274 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START (1 << 1)
278 * RX lane single roam eye point measurement start signal.
279 * If asserted, single measurement at fix XADJUST and YADJUST is started.
281 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM 31
282 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START (1 << 2)
286 * PHY Eye diagram measurement status
288 * 0 - Indicates eye diagram results are not
290 * 1 - Indicates eye diagram is complete and
291 * results are valid for sampling
293 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM 32
294 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE (1 << 0)
297 * Eye diagram error signal. Indicates if the
298 * measurement was invalid because the eye
299 * diagram was interrupted by the link entering
301 * 0 - Indicates eye diagram is valid
302 * 1- Indicates an error occurred, and the eye
303 * diagram measurement should be re-run
305 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM 32
306 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR (1 << 1)
309 * PHY Adaptive Equalization status
310 * 0 - Indicates Adaptive Equalization results are not valid for sampling
311 * 1 - Indicates Adaptive Equalization is complete and results are valid for
314 #define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM 32
315 #define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE (1 << 2)
319 * PHY Adaptive Equalization Status Signal
320 * 0 – Indicates adaptive equalization results
321 * are not valid for sampling
322 * 1 – Indicates adaptive equalization is
323 * complete and results are valid for sampling.
325 #define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM 32
326 #define SERDES_IREG_FLD_RXEQ_DONE (1 << 3)
330 * 7-bit eye diagram time adjust control
334 #define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM 33
336 /* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */
337 #define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM 34
340 * Eye diagram status signal. Safe for
341 * sampling when *DONE* signal has
343 * 14'h0000 - Completely Closed Eye
344 * 14'hFFFF - Completely Open Eye
346 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM 35
347 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE 0xFF
348 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT 0
350 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM 36
351 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE 0x3F
352 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT 0
355 * RX lane single roam eye point measurement result.
356 * If 0, eye is open at current XADJUST and YADJUST settings.
358 #define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM 37
359 #define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM 38
362 * Override enable for CDR lock to reference clock
363 * 0 - CDR is always locked to reference
364 * 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally
365 * depending on the incoming signal and ppm status)
367 #define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM 39
368 #define SERDES_IREG_FLD_RXLOCK2REF_OVREN (1 << 1)
371 * Selects Eye to capture based on edge
372 * 0 - Capture 1st Eye in Eye Diagram
373 * 1 - Capture 2nd Eye in Eye Diagram measurement
375 #define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM 39
376 #define SERDES_IREG_FLD_RXROAM_XORBITSEL (1 << 2)
377 #define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST 0
378 #define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND (1 << 2)
381 * RX Signal detect. 0 indicates no signal, 1 indicates signal detected.
383 #define SERDES_IREG_FLD_RXRANDET_REG_NUM 41
384 #define SERDES_IREG_FLD_RXRANDET_STAT 0x20
387 * RX data polarity inversion control:
389 * 1'b1: invert polarity
391 #define SERDES_IREG_FLD_POLARITY_RX_REG_NUM 46
392 #define SERDES_IREG_FLD_POLARITY_RX_INV (1 << 0)
395 * TX data polarity inversion control:
397 * 1'b1: invert polarity
399 #define SERDES_IREG_FLD_POLARITY_TX_REG_NUM 46
400 #define SERDES_IREG_FLD_POLARITY_TX_INV (1 << 1)
402 /* LANEPCSPSTATE* override enable (Active low) */
403 #define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM 85
404 #define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN (1 << 0)
406 /* LB* override enable (Active low) */
407 #define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM 85
408 #define SERDES_IREG_FLD_LB_LOCWREN (1 << 1)
410 /* PCSRX* override enable (Active low) */
411 #define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM 85
412 #define SERDES_IREG_FLD_PCSRX_LOCWREN (1 << 4)
414 /* PCSRXBIST* override enable (Active low) */
415 #define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM 85
416 #define SERDES_IREG_FLD_PCSRXBIST_LOCWREN (1 << 5)
418 /* PCSRXEQ* override enable (Active low) */
419 #define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM 85
420 #define SERDES_IREG_FLD_PCSRXEQ_LOCWREN (1 << 6)
422 /* PCSTX* override enable (Active low) */
423 #define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM 85
424 #define SERDES_IREG_FLD_PCSTX_LOCWREN (1 << 7)
428 * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN,
429 * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
430 * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
432 #define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM 86
434 /* PCSTXBIST* override enable (Active low) */
435 #define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM 86
436 #define SERDES_IREG_FLD_PCSTXBIST_LOCWREN (1 << 0)
438 /* Override RX_CALCEQ through the internal registers (Active low) */
439 #define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM 86
440 #define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN (1 << 3)
442 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM 86
443 #define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN (1 << 4)
446 /* RXCALROAMEYEMEASIN* override enable - Active Low */
447 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM 86
448 #define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN (1 << 6)
450 /* RXCALROAMXADJUST* override enable - Active Low */
451 #define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM 86
452 #define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN (1 << 7)
454 /* RXCALROAMYADJUST* override enable - Active Low */
455 #define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM 87
456 #define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN (1 << 0)
458 /* RXCDRCALFOSC* override enable. Active Low */
459 #define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM 87
460 #define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN (1 << 1)
462 /* Over-write enable for RXEYEDIAGFSM_INITXVAL */
463 #define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM 87
464 #define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN (1 << 2)
466 /* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */
467 #define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM 87
468 #define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN (1 << 3)
470 /* TXCALTCLKDUTY* override enable. Active Low */
471 #define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM 87
472 #define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN (1 << 4)
474 /* Override TX_DRV through the internal registers (Active low) */
475 #define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM 87
476 #define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN (1 << 5)
478 /*******************************************************************************
479 * Common lane register fields - PMA
480 ******************************************************************************/
482 * Common lane hard reset control
483 * 0 - Hard reset is taken from the interface pins
484 * 1 - Hard reset is taken from registers
486 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM 2
487 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK 0x01
488 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE 0x00
489 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS 0x01
492 * Common lane hard reset
493 * 0 - Hard reset is asserted
494 * 1 - Hard reset is de-asserted
496 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM 2
497 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK 0x02
498 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT 0x00
499 #define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT 0x02
501 /* Synth power state control */
502 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM 3
503 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK 0x1f
504 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD 0x01
505 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2 0x02
506 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1 0x04
507 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S 0x08
508 #define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0 0x10
510 /* Transmit datapath FIFO enable (Active High) */
511 #define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM 8
512 #define SERDES_IREG_FLD_CMNPCS_TXENABLE (1 << 2)
515 * RX lost of signal detector enable
519 #define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM 13
520 #define SERDES_IREG_FLD_RXLOSDET_ENABLE AL_BIT(4)
522 /* Signal Detect Threshold Level */
523 #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM 15
524 #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK AL_FIELD_MASK(2, 0)
526 /* LOS Detect Threshold Level */
527 #define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM 15
528 #define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK AL_FIELD_MASK(4, 3)
529 #define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT 3
531 #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM 30
532 #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK 0x7f
533 #define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT 0
535 #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM 31
536 #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK 0x7f
537 #define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT 0
539 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM 32
540 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK 0xff
541 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT 0
543 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM 33
544 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK 0x1
545 #define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT 0
547 #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM 33
548 #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK 0x3e
549 #define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT 1
551 #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM 34
552 #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK 0xff
553 #define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT 0
555 #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM 35
556 #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK 0x1
557 #define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT 0
559 #define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM 35
560 #define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK 0x3e
561 #define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT 1
563 #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM 36
564 #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK 0xff
565 #define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT 0
567 #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM 37
568 #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK 0x7
569 #define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT 0
571 #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM 43
572 #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK 0x7
573 #define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT 0
575 #define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num) (56 + (byte_num))
576 #define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES 10
579 * Selects the transmit BIST mode:
580 * 0 - Uses the 80-bit internal memory pattern (w/ OOB)
581 * 1 - Uses a 27 PRBS pattern
582 * 2 - Uses a 223 PRBS pattern
583 * 3 - Uses a 231 PRBS pattern
584 * 4 - Uses a 1010 clock pattern
585 * 5 and above - Reserved
587 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM 80
588 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK 0x07
589 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER 0x00
590 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7 0x01
591 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23 0x02
592 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31 0x03
593 #define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010 0x04
595 /* Single-Bit error injection enable (on posedge) */
596 #define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM 80
597 #define SERDES_IREG_FLD_TXBIST_BITERROR_EN 0x20
599 /* CMNPCIEGEN3* override enable (Active Low) */
600 #define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM 95
601 #define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN (1 << 2)
603 /* CMNPCS* override enable (Active Low) */
604 #define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM 95
605 #define SERDES_IREG_FLD_CMNPCS_LOCWREN (1 << 3)
607 /* CMNPCSBIST* override enable (Active Low) */
608 #define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM 95
609 #define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN (1 << 4)
611 /* CMNPCSPSTATE* override enable (Active Low) */
612 #define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM 95
613 #define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN (1 << 5)
615 /* PCS_EN* override enable (Active Low) */
616 #define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM 96
617 #define SERDES_IREG_FLD_PCS_LOCWREN (1 << 3)
619 /* Eye diagram sample count */
620 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM 150
621 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK 0xff
622 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT 0
624 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM 151
625 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK 0xff
626 #define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT 0
628 /* override control */
629 #define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM 230
630 #define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN 1 << 0
632 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM 623
633 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK 0xff
634 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT 0
636 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM 624
637 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK 0xff
638 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT 0
640 /* X and Y coefficient return value */
641 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM 626
642 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK 0x0F
643 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT 0
644 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK 0xF0
645 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT 4
647 /* X coarse scan step */
648 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM 627
649 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK 0x7F
650 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT 0
652 /* X fine scan step */
653 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM 628
654 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK 0x7F
655 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT 0
657 /* Y coarse scan step */
658 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM 629
659 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK 0x0F
660 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT 0
662 /* Y fine scan step */
663 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM 630
664 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK 0x0F
665 #define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT 0
667 #define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM 157
669 #define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM 158
671 #define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM 159
673 #define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM 160
675 #define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM 163
677 #define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM 164
679 /*******************************************************************************
680 * Common lane register fields - PCS
681 ******************************************************************************/
682 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM 3
683 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK AL_FIELD_MASK(5, 4)
684 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT 4
686 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM 6
687 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA AL_BIT(2)
689 #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM 18
690 #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK 0x1F
691 #define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT 0
693 #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM 19
694 #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK 0x7C
695 #define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT 2
697 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM 20
698 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK 0x1F
699 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT 0
701 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM 21
702 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK 0x7C
703 #define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT 2
705 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM 22
706 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK 0x7f
707 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT 0
709 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM 34
710 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK 0x7f
711 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT 0
713 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM 23
714 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK 0xff
715 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT 0
717 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM 22
718 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK 0x80
719 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT 7
721 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM 24
722 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK 0x3e
723 #define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT 1
725 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM 35
726 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK 0xff
727 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT 0
729 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM 34
730 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK 0x80
731 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT 7
733 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM 36
734 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK 0x1f
735 #define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT 0
737 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM 37
738 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK 0xff
739 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT 0
741 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM 36
742 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK 0xe0
743 #define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT 5
749 #endif /* __AL_serdes_REG_H */