2 *******************************************************************************
3 Copyright (C) 2015 Annapurna Labs Ltd.
5 This file may be licensed under the terms of the Annapurna Labs Commercial
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
12 Alternatively, redistribution and use in source and binary forms, with or
13 without modification, are permitted provided that the following conditions are
16 * Redistributions of source code must retain the above copyright notice,
17 this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in
21 the documentation and/or other materials provided with the
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *******************************************************************************/
39 * @file al_hal_serdes_regs.h
41 * @brief ... registers
45 #ifndef __AL_HAL_SERDES_REGS_H__
46 #define __AL_HAL_SERDES_REGS_H__
48 #include "al_hal_plat_types.h"
58 /* [0x0] SerDes Registers Version */
61 /* [0x10] SerDes register file address */
63 /* [0x14] SerDes register file data */
66 /* [0x20] SerDes control */
67 uint32_t ictl_multi_bist;
68 /* [0x24] SerDes control */
70 /* [0x28] SerDes control */
73 /* [0x30] SerDes control */
74 uint32_t ipd_multi_synth;
75 /* [0x34] SerDes control */
77 /* [0x38] SerDes control */
78 uint32_t octl_multi_synthready;
79 /* [0x3c] SerDes control */
80 uint32_t octl_multi_synthstatus;
81 /* [0x40] SerDes control */
87 /* [0x10] SerDes status */
89 /* [0x14] SerDes control */
90 uint32_t ictl_multi_andme;
91 /* [0x18] SerDes control */
92 uint32_t ictl_multi_lb;
93 /* [0x1c] SerDes control */
94 uint32_t ictl_multi_rxbist;
95 /* [0x20] SerDes control */
96 uint32_t ictl_multi_txbist;
97 /* [0x24] SerDes control */
99 /* [0x28] SerDes control */
100 uint32_t ictl_multi_rxeq;
101 /* [0x2c] SerDes control */
102 uint32_t ictl_multi_rxeq_l_low;
103 /* [0x30] SerDes control */
104 uint32_t ictl_multi_rxeq_l_high;
105 /* [0x34] SerDes control */
106 uint32_t ictl_multi_rxeyediag;
107 /* [0x38] SerDes control */
108 uint32_t ictl_multi_txdeemph;
109 /* [0x3c] SerDes control */
110 uint32_t ictl_multi_txmargin;
111 /* [0x40] SerDes control */
112 uint32_t ictl_multi_txswing;
113 /* [0x44] SerDes control */
115 /* [0x48] SerDes control */
117 /* [0x4c] SerDes control */
118 uint32_t octl_multi_rxbist;
119 /* [0x50] SerDes control */
121 /* [0x54] SerDes control */
122 uint32_t octl_multi_rxeyediag;
123 /* [0x58] SerDes control */
124 uint32_t odat_multi_rxbist;
125 /* [0x5c] SerDes control */
126 uint32_t odat_multi_rxeq;
127 /* [0x60] SerDes control */
128 uint32_t multi_rx_dvalid;
129 /* [0x64] SerDes control */
134 struct al_serdes_regs {
135 uint32_t rsrvd_0[64];
136 struct serdes_gen gen; /* [0x100] */
137 struct serdes_lane lane[4]; /* [0x200] */
146 /**** version register ****/
147 /* Revision number (Minor) */
148 #define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
149 #define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
150 /* Revision number (Major) */
151 #define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
152 #define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
153 /* Date of release */
154 #define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000
155 #define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16
156 /* Month of release */
157 #define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
158 #define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21
159 /* Year of release (starting from 2000) */
160 #define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
161 #define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25
163 #define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000
164 #define SERDES_GEN_VERSION_RESERVED_SHIFT 30
166 /**** reg_addr register ****/
168 #define SERDES_GEN_REG_ADDR_VAL_MASK 0x0000FFFF
169 #define SERDES_GEN_REG_ADDR_VAL_SHIFT 0
171 /**** reg_data register ****/
173 #define SERDES_GEN_REG_DATA_VAL_MASK 0x000000FF
174 #define SERDES_GEN_REG_DATA_VAL_SHIFT 0
176 /**** ICTL_MULTI_BIST register ****/
178 #define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007
179 #define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0
181 /**** ICTL_PCS register ****/
183 #define SERDES_GEN_ICTL_PCS_EN_NT (1 << 0)
185 /**** ICTL_PMA register ****/
187 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007
188 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0
190 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \
191 (0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
192 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \
193 (3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
194 #define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \
195 (4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
197 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070
198 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4
200 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \
201 (0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
202 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \
203 (2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
204 #define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \
205 (3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
207 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700
208 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8
210 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \
211 (0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
212 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \
213 (2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
214 #define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \
215 (3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
217 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC (1 << 11)
218 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS (0 << 11)
219 #define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER (1 << 11)
221 #define SERDES_GEN_ICTL_PMA_TXENABLE_A (1 << 12)
223 #define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13)
225 /**** IPD_MULTI_SYNTH register ****/
227 #define SERDES_GEN_IPD_MULTI_SYNTH_B (1 << 0)
229 /**** IRST register ****/
231 #define SERDES_GEN_IRST_PIPE_RST_L3_B_A (1 << 0)
233 #define SERDES_GEN_IRST_PIPE_RST_L2_B_A (1 << 1)
235 #define SERDES_GEN_IRST_PIPE_RST_L1_B_A (1 << 2)
237 #define SERDES_GEN_IRST_PIPE_RST_L0_B_A (1 << 3)
239 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4)
241 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5)
243 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6)
245 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7)
247 #define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8)
249 #define SERDES_GEN_IRST_POR_B_A (1 << 12)
251 #define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16)
253 #define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17)
255 #define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18)
257 #define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19)
259 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20)
261 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21)
263 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22)
265 #define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23)
267 /**** OCTL_MULTI_SYNTHREADY register ****/
269 #define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0)
271 /**** OCTL_MULTI_SYNTHSTATUS register ****/
273 #define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0)
275 /**** clk_out register ****/
277 #define SERDES_GEN_CLK_OUT_SEL_MASK 0x0000003F
278 #define SERDES_GEN_CLK_OUT_SEL_SHIFT 0
280 /**** OCTL_PMA register ****/
282 #define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0)
284 /**** ICTL_MULTI_ANDME register ****/
286 #define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0)
288 #define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1)
290 /**** ICTL_MULTI_LB register ****/
292 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0)
294 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1)
296 #define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2)
298 #define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3)
300 #define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4)
302 #define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8)
304 #define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9)
306 /**** ICTL_MULTI_RXBIST register ****/
308 #define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0)
310 /**** ICTL_MULTI_TXBIST register ****/
312 #define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0)
314 /**** ICTL_MULTI register ****/
316 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003
317 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0
319 #define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2)
321 #define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070
322 #define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4
324 #define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8)
326 #define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9)
328 #define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12)
330 #define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13)
332 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000
333 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16
335 #define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19)
337 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000
338 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20
340 #define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23)
342 #define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000
343 #define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24
345 #define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27)
347 #define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000
348 #define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28
350 /**** ICTL_MULTI_RXEQ register ****/
352 #define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0)
354 #define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1)
356 #define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070
357 #define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4
359 /**** ICTL_MULTI_RXEQ_L_high register ****/
361 #define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0)
363 /**** ICTL_MULTI_RXEYEDIAG register ****/
365 #define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0)
367 /**** ICTL_MULTI_TXDEEMPH register ****/
369 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF
370 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0
372 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK 0x7c0
373 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT 6
374 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK 0xf000
375 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT 12
376 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK 0x7
377 #define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT 0
379 /**** ICTL_MULTI_TXMARGIN register ****/
381 #define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007
382 #define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0
384 /**** ICTL_MULTI_TXSWING register ****/
386 #define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0)
388 /**** IDAT_MULTI register ****/
390 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F
391 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0
393 #define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4)
395 /**** IPD_MULTI register ****/
397 #define SERDES_LANE_IPD_MULTI_TX_L_B (1 << 0)
399 #define SERDES_LANE_IPD_MULTI_RX_L_B (1 << 1)
401 /**** OCTL_MULTI_RXBIST register ****/
403 #define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0)
405 #define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1)
407 /**** OCTL_MULTI register ****/
409 #define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0)
411 #define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1)
413 #define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2)
415 #define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3)
417 #define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4)
419 #define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5)
421 #define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6)
423 #define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7)
425 /**** OCTL_MULTI_RXEYEDIAG register ****/
427 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF
428 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0
430 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16)
432 #define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17)
434 /**** ODAT_MULTI_RXBIST register ****/
436 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF
437 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0
439 #define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16)
441 /**** ODAT_MULTI_RXEQ register ****/
443 #define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF
444 #define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0
446 /**** MULTI_RX_DVALID register ****/
448 #define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0)
450 #define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1)
452 #define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2)
454 #define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3)
456 #define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4)
458 #define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5)
460 #define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000
461 #define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16
463 #define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24)
465 #define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25)
467 #define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26)
469 #define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27)
471 #define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28)
473 #define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29)
475 #define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30)
477 #define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31)
479 /**** reserved register ****/
481 #define SERDES_LANE_RESERVED_OUT_MASK 0x000000FF
482 #define SERDES_LANE_RESERVED_OUT_SHIFT 0
484 #define SERDES_LANE_RESERVED_IN_MASK 0x00FF0000
485 #define SERDES_LANE_RESERVED_IN_SHIFT 16
491 #endif /* __AL_HAL_serdes_REGS_H__ */
493 /** @} end of ... group */