2 *******************************************************************************
3 Copyright (C) 2015 Annapurna Labs Ltd.
5 This file may be licensed under the terms of the Annapurna Labs Commercial
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
12 Alternatively, redistribution and use in source and binary forms, with or
13 without modification, are permitted provided that the following conditions are
16 * Redistributions of source code must retain the above copyright notice,
17 this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in
21 the documentation and/or other materials provided with the
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *******************************************************************************/
38 * @file al_hal_udma_regs_m2s.h
40 * @brief C Header file for the UDMA M2S registers
44 #ifndef __AL_HAL_UDMA_M2S_REG_H
45 #define __AL_HAL_UDMA_M2S_REG_H
47 #include "al_hal_plat_types.h"
59 /* [0x0] Completion write master configuration */
60 uint32_t comp_wr_cfg_1;
61 /* [0x4] Completion write master configuration */
62 uint32_t comp_wr_cfg_2;
63 /* [0x8] Data read master configuration */
64 uint32_t data_rd_cfg_1;
65 /* [0xc] Data read master configuration */
66 uint32_t data_rd_cfg_2;
67 /* [0x10] Descriptor read master configuration */
68 uint32_t desc_rd_cfg_1;
69 /* [0x14] Descriptor read master configuration */
70 uint32_t desc_rd_cfg_2;
71 /* [0x18] Data read master configuration */
73 /* [0x1c] Descriptors read master configuration */
74 uint32_t desc_rd_cfg_3;
75 /* [0x20] Descriptors write master configuration (completion) */
76 uint32_t desc_wr_cfg_1;
77 /* [0x24] AXI outstanding configuration */
84 * 00 - No pending tasks
85 * 01 – Normal (active)
86 * 10 – Abort (error condition)
90 /* [0x4] CPU request to change DMA state */
91 uint32_t change_state;
94 * [0xc] M2S DMA error log mask.
95 * Each error has an interrupt controller cause bit.
96 * This register determines if these errors cause the M2S DMA to log the
101 uint32_t err_log_mask;
104 * [0x14] DMA header log.
105 * Sample the packet header that caused the error.
109 * [0x18] DMA header log.
110 * Sample the packet header that caused the error.
114 * [0x1c] DMA header log.
115 * Sample the packet header that caused the error.
119 * [0x20] DMA header log.
120 * Sample the packet header that caused the error.
123 /* [0x24] DMA clear error log */
124 uint32_t clear_err_log;
125 /* [0x28] M2S data FIFO status */
126 uint32_t data_fifo_status;
127 /* [0x2c] M2S header FIFO status */
128 uint32_t header_fifo_status;
129 /* [0x30] M2S unack FIFO status */
130 uint32_t unack_fifo_status;
131 /* [0x34] Select queue for debug */
132 uint32_t indirect_ctrl;
134 * [0x38] M2S prefetch FIFO status.
135 * Status of the selected queue in M2S_indirect_ctrl
137 uint32_t sel_pref_fifo_status;
139 * [0x3c] M2S completion FIFO status.
140 * Status of the selected queue in M2S_indirect_ctrl
142 uint32_t sel_comp_fifo_status;
144 * [0x40] M2S rate limit status.
145 * Status of the selected queue in M2S_indirect_ctrl
147 uint32_t sel_rate_limit_status;
149 * [0x44] M2S DWRR scheduler status.
150 * Status of the selected queue in M2S_indirect_ctrl
152 uint32_t sel_dwrr_status;
153 /* [0x48] M2S state machine and FIFO clear control */
155 /* [0x4c] Misc Check enable */
157 /* [0x50] M2S FIFO enable control, internal */
159 /* [0x54] M2S packet length configuration */
161 /* [0x58] Stream interface configuration */
166 /* [0x0] M2S descriptor prefetch configuration */
167 uint32_t desc_pref_cfg_1;
168 /* [0x4] M2S descriptor prefetch configuration */
169 uint32_t desc_pref_cfg_2;
170 /* [0x8] M2S descriptor prefetch configuration */
171 uint32_t desc_pref_cfg_3;
173 /* [0x10] Data burst read configuration */
177 struct udma_m2s_dwrr {
178 /* [0x0] Tx DMA DWRR scheduler configuration */
180 /* [0x4] Token bucket rate limit control */
181 uint32_t ctrl_deficit_cnt;
184 struct udma_m2s_rate_limiter {
185 /* [0x0] Token bucket rate limit configuration */
188 * [0x4] Token bucket rate limit control.
189 * Controls the cycle counters.
191 uint32_t ctrl_cycle_cnt;
193 * [0x8] Token bucket rate limit control.
194 * Controls the token bucket counter.
200 struct udma_rlimit_common {
201 /* [0x0] Token bucket configuration */
203 /* [0x4] Token bucket rate limit configuration */
205 /* [0x8] Token bucket rate limit configuration */
206 uint32_t cfg_token_size_1;
207 /* [0xc] Token bucket rate limit configuration */
208 uint32_t cfg_token_size_2;
209 /* [0x10] Token bucket rate limit configuration */
212 * [0x14] Mask the different types of rate limiter.
213 * 0 - Rate limit is active.
214 * 1 - Rate limit is masked.
219 struct udma_m2s_stream_rate_limiter {
220 struct udma_rlimit_common rlimit;
223 struct udma_m2s_comp {
224 /* [0x0] Completion controller configuration */
226 /* [0x4] Completion controller coalescing configuration */
228 /* [0x8] Completion controller application acknowledge configuration */
229 uint32_t cfg_application_ack;
232 struct udma_m2s_stat {
233 /* [0x0] Statistics counters configuration */
235 /* [0x4] Counting number of descriptors with First-bit set. */
238 * [0x8] Counting the net length of the data buffers [64-bit]
239 * Should be read before tx_bytes_high
241 uint32_t tx_bytes_low;
243 * [0xc] Counting the net length of the data buffers [64-bit],
244 * Should be read after tx_bytes_low (value is sampled when reading
245 * Should be read before tx_bytes_low
247 uint32_t tx_bytes_high;
248 /* [0x10] Total number of descriptors read from the host memory */
249 uint32_t prefed_desc;
250 /* [0x14] Number of packets read from the unack FIFO */
252 /* [0x18] Number of descriptors written into the completion ring */
255 * [0x1c] Number of acknowledged packets.
256 * (acknowledge received from the stream interface)
261 struct udma_m2s_feature {
263 * [0x0] M2S Feature register.
264 * M2S instantiation parameters
267 /* [0x4] Reserved M2S feature register */
270 * [0x8] M2S Feature register.
271 * M2S instantiation parameters
275 * [0xc] M2S Feature register.
276 * M2S instantiation parameters
280 * [0x10] M2S Feature register.
281 * M2S instantiation parameters
288 /* [0x20] M2S descriptor ring configuration */
290 /* [0x24] M2S descriptor ring status and information */
292 /* [0x28] TX Descriptor Ring Base Pointer [31:4] */
294 /* [0x2c] TX Descriptor Ring Base Pointer [63:32] */
297 * [0x30] TX Descriptor Ring Length[23:2]
300 /* [0x34] TX Descriptor Ring Head Pointer */
302 /* [0x38] Tx Descriptor Tail Pointer increment */
304 /* [0x3c] Tx Descriptor Tail Pointer */
306 /* [0x40] TX Descriptor Current Pointer */
308 /* [0x44] Tx Completion Ring Base Pointer [31:4] */
310 /* [0x48] TX Completion Ring Base Pointer [63:32] */
312 /* [0x4c] TX Completion Ring Head Pointer */
315 * [0x50] Tx Completion Ring Head Pointer internal (Before the
318 uint32_t tcrhp_internal;
320 /* [0x60] Rate limit configuration */
321 struct udma_rlimit_common rlimit;
323 /* [0x80] DWRR scheduler configuration */
325 /* [0x84] DWRR scheduler configuration */
327 /* [0x88] DWRR scheduler configuration */
329 /* [0x8c] DWRR scheduler software control */
330 uint32_t dwrr_sw_ctrl;
332 /* [0xa0] Completion controller configuration */
335 /* [0xb0] SW control */
338 /* [0xc0] Number of M2S Tx packets after the scheduler */
343 struct udma_m2s_regs {
344 uint32_t rsrvd_0[64];
345 struct udma_axi_m2s axi_m2s; /* [0x100] */
346 struct udma_m2s m2s; /* [0x200] */
347 struct udma_m2s_rd m2s_rd; /* [0x300] */
348 struct udma_m2s_dwrr m2s_dwrr; /* [0x340] */
349 struct udma_m2s_rate_limiter m2s_rate_limiter; /* [0x380] */
350 struct udma_m2s_stream_rate_limiter m2s_stream_rate_limiter; /* [0x3c0] */
351 struct udma_m2s_comp m2s_comp; /* [0x400] */
352 struct udma_m2s_stat m2s_stat; /* [0x500] */
353 struct udma_m2s_feature m2s_feature; /* [0x600] */
354 uint32_t rsrvd_1[576];
355 struct udma_m2s_q m2s_q[4]; /* [0x1000] */
364 /**** comp_wr_cfg_1 register ****/
365 /* AXI write ID (AWID) */
366 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK 0x000000FF
367 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_SHIFT 0
369 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK 0x000F0000
370 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_SHIFT 16
372 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK 0x03000000
373 #define UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_SHIFT 24
375 /**** comp_wr_cfg_2 register ****/
377 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK 0x000FFFFF
378 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_SHIFT 0
379 /* Bus size, 128-bit */
380 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK 0x00700000
381 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_SHIFT 20
384 * Used for arbitration between AXI masters
386 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK 0x07000000
387 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_SHIFT 24
388 /* Protection Type */
389 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK 0x70000000
390 #define UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_SHIFT 28
392 /**** data_rd_cfg_1 register ****/
393 /* AXI read ID (ARID) */
394 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_MASK 0x000000FF
395 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_SHIFT 0
397 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARCACHE_MASK 0x000F0000
398 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARCACHE_SHIFT 16
400 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARBURST_MASK 0x03000000
401 #define UDMA_AXI_M2S_DATA_RD_CFG_1_ARBURST_SHIFT 24
403 /**** data_rd_cfg_2 register ****/
405 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_MASK 0x000FFFFF
406 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_SHIFT 0
407 /* Bus size, 128-bit */
408 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARSIZE_MASK 0x00700000
409 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARSIZE_SHIFT 20
412 * Used for arbitration between AXI masters
414 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARQOS_MASK 0x07000000
415 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARQOS_SHIFT 24
416 /* Protection Type */
417 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARPROT_MASK 0x70000000
418 #define UDMA_AXI_M2S_DATA_RD_CFG_2_ARPROT_SHIFT 28
420 /**** desc_rd_cfg_1 register ****/
421 /* AXI read ID (ARID) */
422 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_MASK 0x000000FF
423 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_SHIFT 0
425 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARCACHE_MASK 0x000F0000
426 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARCACHE_SHIFT 16
428 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARBURST_MASK 0x03000000
429 #define UDMA_AXI_M2S_DESC_RD_CFG_1_ARBURST_SHIFT 24
431 /**** desc_rd_cfg_2 register ****/
433 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_MASK 0x000FFFFF
434 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_SHIFT 0
435 /* Bus size, 128-bit */
436 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARSIZE_MASK 0x00700000
437 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARSIZE_SHIFT 20
440 * Used for arbitration between AXI masters
442 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARQOS_MASK 0x07000000
443 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARQOS_SHIFT 24
444 /* Protection Type */
445 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARPROT_MASK 0x70000000
446 #define UDMA_AXI_M2S_DESC_RD_CFG_2_ARPROT_SHIFT 28
448 /**** data_rd_cfg register ****/
450 * Defines the maximum number of AXI beats for a single AXI burst.
451 * This value is used for a burst split decision.
453 #define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_MASK 0x000000FF
454 #define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_SHIFT 0
456 * Enable breaking data read request.
457 * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats
459 #define UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
461 /**** desc_rd_cfg_3 register ****/
463 * Defines the maximum number of AXI beats for a single AXI burst.
464 * This value is used for a burst split decision.
465 * Maximum burst size for reading data( in AXI beats, 128-bits)
466 * (default – 16 beats, 256 bytes)
468 #define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_MASK 0x000000FF
469 #define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_SHIFT 0
471 * Enable breaking descriptor read request.
472 * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats.
474 #define UDMA_AXI_M2S_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
476 /**** desc_wr_cfg_1 register ****/
478 * Defines the maximum number of AXI beats for a single AXI burst.
479 * This value is used for a burst split decision.
481 #define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK 0x000000FF
482 #define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT 0
484 * Minimum burst for writing completion descriptors.
485 * Defined in AXI beats
486 * 4 Descriptors per beat.
487 * Value must be aligned to cache lines (64 bytes).
488 * Default value is 2 cache lines, 32 descriptors, 8 beats.
490 #define UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK 0x00FF0000
491 #define UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT 16
493 /**** ostand_cfg register ****/
494 /* Maximum number of outstanding data reads to the AXI (AXI transactions) */
495 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK 0x0000003F
496 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_SHIFT 0
498 * Maximum number of outstanding descriptor reads to the AXI (AXI transactions)
500 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK 0x00003F00
501 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_SHIFT 8
503 * Maximum number of outstanding descriptor writes to the AXI (AXI transactions)
505 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK 0x003F0000
506 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_SHIFT 16
508 * Maximum number of outstanding data beats for descriptor write to AXI (AXI
511 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK 0xFF000000
512 #define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_SHIFT 24
514 /**** state register ****/
515 /* Completion control */
516 #define UDMA_M2S_STATE_COMP_CTRL_MASK 0x00000003
517 #define UDMA_M2S_STATE_COMP_CTRL_SHIFT 0
518 /* Stream interface */
519 #define UDMA_M2S_STATE_STREAM_IF_MASK 0x00000030
520 #define UDMA_M2S_STATE_STREAM_IF_SHIFT 4
521 /* Data read control */
522 #define UDMA_M2S_STATE_DATA_RD_CTRL_MASK 0x00000300
523 #define UDMA_M2S_STATE_DATA_RD_CTRL_SHIFT 8
524 /* Descriptor prefetch */
525 #define UDMA_M2S_STATE_DESC_PREF_MASK 0x00003000
526 #define UDMA_M2S_STATE_DESC_PREF_SHIFT 12
528 /**** change_state register ****/
529 /* Start normal operation */
530 #define UDMA_M2S_CHANGE_STATE_NORMAL (1 << 0)
531 /* Stop normal operation */
532 #define UDMA_M2S_CHANGE_STATE_DIS (1 << 1)
535 * (Prefetch, scheduling, completion and stream interface)
537 #define UDMA_M2S_CHANGE_STATE_ABORT (1 << 2)
539 /**** err_log_mask register ****/
541 * Mismatch of packet serial number.
542 * (between first packet in the unacknowledged FIFO and received ack from the
545 #define UDMA_M2S_ERR_LOG_MASK_COMP_PKT_MISMATCH (1 << 0)
547 #define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_PARITY (1 << 1)
548 /* AXI response error */
549 #define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_RESPONSE (1 << 2)
550 /* AXI timeout (ack not received) */
551 #define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_TOUT (1 << 3)
553 #define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_PARITY (1 << 4)
554 /* AXI response error */
555 #define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_RESPONSE (1 << 5)
557 #define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_TOUT (1 << 6)
559 #define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_PARITY (1 << 7)
560 /* AXI response error */
561 #define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_RESPONSE (1 << 8)
563 #define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_TOUT (1 << 9)
565 #define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_PARITY (1 << 10)
566 /* AXI response error */
567 #define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_RESPONSE (1 << 11)
569 #define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_TOUT (1 << 12)
570 /* Packet length error */
571 #define UDMA_M2S_ERR_LOG_MASK_PREF_PKT_LEN_OVERFLOW (1 << 13)
572 /* Maximum number of descriptors per packet error */
573 #define UDMA_M2S_ERR_LOG_MASK_PREF_MAX_DESC_CNT (1 << 14)
574 /* Error in first bit indication of the descriptor */
575 #define UDMA_M2S_ERR_LOG_MASK_PREF_FIRST (1 << 15)
576 /* Error in last bit indication of the descriptor */
577 #define UDMA_M2S_ERR_LOG_MASK_PREF_LAST (1 << 16)
579 #define UDMA_M2S_ERR_LOG_MASK_PREF_RING_ID (1 << 17)
580 /* Data buffer parity error */
581 #define UDMA_M2S_ERR_LOG_MASK_DATA_BUFF_PARITY (1 << 18)
583 #define UDMA_M2S_ERR_LOG_MASK_INTERNAL_MASK 0xFFF80000
584 #define UDMA_M2S_ERR_LOG_MASK_INTERNAL_SHIFT 19
586 /**** clear_err_log register ****/
587 /* Clear error log */
588 #define UDMA_M2S_CLEAR_ERR_LOG_CLEAR (1 << 0)
590 /**** data_fifo_status register ****/
591 /* FIFO used indication */
592 #define UDMA_M2S_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
593 #define UDMA_M2S_DATA_FIFO_STATUS_USED_SHIFT 0
594 /* FIFO empty indication */
595 #define UDMA_M2S_DATA_FIFO_STATUS_EMPTY (1 << 24)
596 /* FIFO full indication */
597 #define UDMA_M2S_DATA_FIFO_STATUS_FULL (1 << 28)
599 /**** header_fifo_status register ****/
600 /* FIFO used indication */
601 #define UDMA_M2S_HEADER_FIFO_STATUS_USED_MASK 0x0000FFFF
602 #define UDMA_M2S_HEADER_FIFO_STATUS_USED_SHIFT 0
603 /* FIFO empty indication */
604 #define UDMA_M2S_HEADER_FIFO_STATUS_EMPTY (1 << 24)
605 /* FIFO full indication */
606 #define UDMA_M2S_HEADER_FIFO_STATUS_FULL (1 << 28)
608 /**** unack_fifo_status register ****/
609 /* FIFO used indication */
610 #define UDMA_M2S_UNACK_FIFO_STATUS_USED_MASK 0x0000FFFF
611 #define UDMA_M2S_UNACK_FIFO_STATUS_USED_SHIFT 0
612 /* FIFO empty indication */
613 #define UDMA_M2S_UNACK_FIFO_STATUS_EMPTY (1 << 24)
614 /* FIFO full indication */
615 #define UDMA_M2S_UNACK_FIFO_STATUS_FULL (1 << 28)
617 /**** indirect_ctrl register ****/
618 /* Selected queue for status read */
619 #define UDMA_M2S_INDIRECT_CTRL_Q_NUM_MASK 0x00000FFF
620 #define UDMA_M2S_INDIRECT_CTRL_Q_NUM_SHIFT 0
622 /**** sel_pref_fifo_status register ****/
623 /* FIFO used indication */
624 #define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_MASK 0x0000FFFF
625 #define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_SHIFT 0
626 /* FIFO empty indication */
627 #define UDMA_M2S_SEL_PREF_FIFO_STATUS_EMPTY (1 << 24)
628 /* FIFO full indication */
629 #define UDMA_M2S_SEL_PREF_FIFO_STATUS_FULL (1 << 28)
631 /**** sel_comp_fifo_status register ****/
632 /* FIFO used indication */
633 #define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_MASK 0x0000FFFF
634 #define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_SHIFT 0
635 /* FIFO empty indication */
636 #define UDMA_M2S_SEL_COMP_FIFO_STATUS_EMPTY (1 << 24)
637 /* FIFO full indication */
638 #define UDMA_M2S_SEL_COMP_FIFO_STATUS_FULL (1 << 28)
640 /**** sel_rate_limit_status register ****/
642 #define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_MASK 0x00FFFFFF
643 #define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_SHIFT 0
645 /**** sel_dwrr_status register ****/
646 /* Deficit counter */
647 #define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_MASK 0x00FFFFFF
648 #define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_SHIFT 0
650 /**** cfg_len register ****/
651 /* Maximum packet size for the M2S */
652 #define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK 0x000FFFFF
653 #define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_SHIFT 0
655 * Length encoding for 64K.
656 * 0 - length 0x0000 = 0
657 * 1 - length 0x0000 = 64k
659 #define UDMA_M2S_CFG_LEN_ENCODE_64K (1 << 24)
661 /**** stream_cfg register ****/
663 * Disables the stream interface operation.
664 * Changing to 1 stops at the end of packet transmission.
666 #define UDMA_M2S_STREAM_CFG_DISABLE (1 << 0)
668 * Configuration of the stream FIFO read control.
670 * 1 - Threshold based
672 #define UDMA_M2S_STREAM_CFG_RD_MODE (1 << 1)
673 /* Minimum number of beats to start packet transmission. */
674 #define UDMA_M2S_STREAM_CFG_RD_TH_MASK 0x0003FF00
675 #define UDMA_M2S_STREAM_CFG_RD_TH_SHIFT 8
677 /**** desc_pref_cfg_1 register ****/
678 /* Size of the descriptor prefetch FIFO (in descriptors) */
679 #define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK 0x000000FF
680 #define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT 0
682 /**** desc_pref_cfg_2 register ****/
683 /* Maximum number of descriptors per packet */
684 #define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK 0x0000001F
685 #define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT 0
687 * Force RR arbitration in the prefetch arbiter.
688 * 0 -Standard arbitration based on queue QoS
689 * 1 - Force Round Robin arbitration
691 #define UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR (1 << 16)
693 /**** desc_pref_cfg_3 register ****/
695 * Minimum descriptor burst size when prefetch FIFO level is below the
696 * descriptor prefetch threshold
699 #define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK 0x0000000F
700 #define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT 0
702 * Minimum descriptor burst size when prefetch FIFO level is above the
703 * descriptor prefetch threshold
705 #define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK 0x000000F0
706 #define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT 4
708 * Descriptor fetch threshold.
709 * Used as a threshold to determine the allowed minimum descriptor burst size.
710 * (Must be at least max_desc_per_pkt)
712 #define UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK 0x0000FF00
713 #define UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT 8
715 /**** data_cfg register ****/
717 * Maximum number of data beats in the data read FIFO.
718 * Defined based on data FIFO size
719 * (default FIFO size 2KB → 128 beats)
721 #define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK 0x000003FF
722 #define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_SHIFT 0
724 * Maximum number of packets in the data read FIFO.
725 * Defined based on header FIFO size
727 #define UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK 0x00FF0000
728 #define UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_SHIFT 16
730 /**** cfg_sched register ****/
732 * Enable the DWRR scheduler.
733 * If this bit is 0, queues with same QoS will be served with RR scheduler.
735 #define UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR (1 << 0)
737 * Scheduler operation mode.
741 #define UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN (1 << 4)
743 * Enable incrementing the weight factor between DWRR iterations.
744 * 00 - Don't increase the increment factor.
745 * 01 - Increment once
746 * 10 - Increment exponential
749 #define UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK 0x00000300
750 #define UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_SHIFT 8
752 * Increment factor power of 2.
754 * This is the factor used to multiply the weight.
756 #define UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK 0x000F0000
757 #define UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_SHIFT 16
759 /**** ctrl_deficit_cnt register ****/
761 * Init value for the deficit counter.
762 * Initializes the deficit counters of all queues to this value any time this
763 * register is written.
765 #define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK 0x00FFFFFF
766 #define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_SHIFT 0
768 /**** gen_cfg register ****/
769 /* Size of the basic token fill cycle, system clock cycles */
770 #define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK 0x0000FFFF
771 #define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_SHIFT 0
773 * Rate limiter operation mode.
777 #define UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN (1 << 24)
779 /**** ctrl_cycle_cnt register ****/
780 /* Reset the short and long cycle counters. */
781 #define UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST (1 << 0)
783 /**** ctrl_token register ****/
785 * Init value for the token counter.
786 * Initializes the token counters of all queues to this value any time this
787 * register is written.
789 #define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK 0x00FFFFFF
790 #define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_SHIFT 0
792 /**** cfg_1s register ****/
793 /* Maximum number of accumulated bytes in the token counter */
794 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK 0x00FFFFFF
795 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_SHIFT 0
796 /* Enable the rate limiter. */
797 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN (1 << 24)
798 /* Stop token fill. */
799 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE (1 << 25)
801 /**** cfg_cycle register ****/
802 /* Number of short cycles between token fills */
803 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
804 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
806 /**** cfg_token_size_1 register ****/
807 /* Number of bits to add in each long cycle */
808 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
809 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
811 /**** cfg_token_size_2 register ****/
812 /* Number of bits to add in each short cycle */
813 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
814 #define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
816 /**** sw_ctrl register ****/
817 /* Reset the token bucket counter. */
818 #define UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT (1 << 0)
820 /**** mask register ****/
821 /* Mask the external rate limiter. */
822 #define UDMA_M2S_STREAM_RATE_LIMITER_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
823 /* Mask the internal rate limiter. */
824 #define UDMA_M2S_STREAM_RATE_LIMITER_MASK_INTERNAL_RATE_LIMITER (1 << 1)
825 /* Mask the external application pause interface. */
826 #define UDMA_M2S_STREAM_RATE_LIMITER_MASK_EXTERNAL_PAUSE (1 << 3)
828 /**** cfg_1c register ****/
830 * Completion FIFO size
831 * (descriptors per queue)
833 #define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK 0x000000FF
834 #define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT 0
836 * Unacknowledged FIFO size.
839 #define UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK 0x0001FF00
840 #define UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_SHIFT 8
843 * Enable the promotion of the current queue in progress for the completion
846 #define UDMA_M2S_COMP_CFG_1C_Q_PROMOTION (1 << 24)
847 /* Force RR arbitration in the completion arbiter */
848 #define UDMA_M2S_COMP_CFG_1C_FORCE_RR (1 << 25)
849 /* Minimum number of free completion entries to qualify for promotion */
850 #define UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN_MASK 0xF0000000
851 #define UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN_SHIFT 28
853 /**** cfg_application_ack register ****/
855 * Acknowledge timeout timer.
856 * ACK from the application through the stream interface)
858 #define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK 0x00FFFFFF
859 #define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT 0
861 /**** cfg_st register ****/
862 /* Use additional length value for all statistics counters. */
863 #define UDMA_M2S_STAT_CFG_ST_USE_EXTRA_LEN (1 << 0)
865 /**** reg_1 register ****/
867 * Read the size of the descriptor prefetch FIFO
870 #define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_MASK 0x000000FF
871 #define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_SHIFT 0
873 /**** reg_3 register ****/
875 * Maximum number of data beats in the data read FIFO.
876 * Defined based on data FIFO size
877 * (default FIFO size 2KB → 128 beats)
879 #define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_MASK 0x000003FF
880 #define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_SHIFT 0
882 * Maximum number of packets in the data read FIFO.
883 * Defined based on header FIFO size
885 #define UDMA_M2S_FEATURE_REG_3_DATA_RD_MAX_PKT_LIMIT_MASK 0x00FF0000
886 #define UDMA_M2S_FEATURE_REG_3_DATA_RD_MAX_PKT_LIMIT_SHIFT 16
888 /**** reg_4 register ****/
890 * Size of the completion FIFO of each queue
893 #define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_MASK 0x000000FF
894 #define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_SHIFT 0
895 /* Size of the unacknowledged FIFO (descriptors) */
896 #define UDMA_M2S_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_MASK 0x0001FF00
897 #define UDMA_M2S_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_SHIFT 8
899 /**** reg_5 register ****/
900 /* Maximum number of outstanding data reads to AXI */
901 #define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_MASK 0x0000003F
902 #define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_SHIFT 0
903 /* Maximum number of outstanding descriptor reads to AXI */
904 #define UDMA_M2S_FEATURE_REG_5_MAX_DESC_RD_OSTAND_MASK 0x00003F00
905 #define UDMA_M2S_FEATURE_REG_5_MAX_DESC_RD_OSTAND_SHIFT 8
907 * Maximum number of outstanding descriptor writes to AXI.
910 #define UDMA_M2S_FEATURE_REG_5_MAX_COMP_REQ_MASK 0x003F0000
911 #define UDMA_M2S_FEATURE_REG_5_MAX_COMP_REQ_SHIFT 16
913 * Maximum number of outstanding data beats for descriptor write to AXI.
916 #define UDMA_M2S_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
917 #define UDMA_M2S_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_SHIFT 24
919 /**** cfg register ****/
921 * Length offset to be used for each packet from this queue.
922 * (length offset is used for the scheduler and rate limiter).
924 #define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_MASK 0x0000FFFF
925 #define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_SHIFT 0
927 * Enable operation of this queue.
930 #define UDMA_M2S_Q_CFG_EN_PREF (1 << 16)
932 * Enable operation of this queue.
935 #define UDMA_M2S_Q_CFG_EN_SCHEDULING (1 << 17)
936 /* Allow prefetch of less than minimum prefetch burst size. */
937 #define UDMA_M2S_Q_CFG_ALLOW_LT_MIN_PREF (1 << 20)
938 /* Configure the AXI AWCACHE for completion write. */
939 #define UDMA_M2S_Q_CFG_AXI_AWCACHE_COMP_MASK 0x0F000000
940 #define UDMA_M2S_Q_CFG_AXI_AWCACHE_COMP_SHIFT 24
942 * AXI QoS for the selected queue.
943 * This value is used in AXI transactions associated with this queue and the
944 * prefetch and completion arbiters.
946 #define UDMA_M2S_Q_CFG_AXI_QOS_MASK 0x70000000
947 #define UDMA_M2S_Q_CFG_AXI_QOS_SHIFT 28
949 /**** status register ****/
950 /* Indicates how many entries are used in the queue */
951 #define UDMA_M2S_Q_STATUS_Q_USED_MASK 0x01FFFFFF
952 #define UDMA_M2S_Q_STATUS_Q_USED_SHIFT 0
955 * 0 – prefetch operation is stopped
956 * 1 – prefetch is operational
958 #define UDMA_M2S_Q_STATUS_PREFETCH (1 << 28)
960 * Queue scheduler status
961 * 0 – queue is not active and not participating in scheduling
962 * 1 – queue is active and participating in the scheduling process
964 #define UDMA_M2S_Q_STATUS_SCHEDULER (1 << 29)
965 /* Queue is suspended due to DMB */
966 #define UDMA_M2S_Q_STATUS_Q_DMB (1 << 30)
968 * Queue full indication.
969 * (used by the host when head pointer equals tail pointer).
971 #define UDMA_M2S_Q_STATUS_Q_FULL (1 << 31)
973 * M2S Descriptor Ring Base address [31:4].
974 * Value of the base address of the M2S descriptor ring
975 * [3:0] - 0 - 16B alignment is enforced
976 * ([11:4] should be 0 for 4KB alignment)
978 #define UDMA_M2S_Q_TDRBP_LOW_ADDR_MASK 0xFFFFFFF0
979 #define UDMA_M2S_Q_TDRBP_LOW_ADDR_SHIFT 4
981 /**** TDRL register ****/
983 * Length of the descriptor ring.
985 * Associated with the ring base address, ends at maximum burst size alignment.
987 #define UDMA_M2S_Q_TDRL_OFFSET_MASK 0x00FFFFFF
988 #define UDMA_M2S_Q_TDRL_OFFSET_SHIFT 0
990 /**** TDRHP register ****/
992 * Relative offset of the next descriptor that needs to be read into the
994 * Incremented when the DMA reads valid descriptors from the host memory to the
996 * Note that this is the offset in # of descriptors and not in byte address.
998 #define UDMA_M2S_Q_TDRHP_OFFSET_MASK 0x00FFFFFF
999 #define UDMA_M2S_Q_TDRHP_OFFSET_SHIFT 0
1001 #define UDMA_M2S_Q_TDRHP_RING_ID_MASK 0xC0000000
1002 #define UDMA_M2S_Q_TDRHP_RING_ID_SHIFT 30
1004 /**** TDRTP_inc register ****/
1005 /* Increments the value in Q_TDRTP (descriptors) */
1006 #define UDMA_M2S_Q_TDRTP_INC_VAL_MASK 0x00FFFFFF
1007 #define UDMA_M2S_Q_TDRTP_INC_VAL_SHIFT 0
1009 /**** TDRTP register ****/
1011 * Relative offset of the next free descriptor in the host memory.
1012 * Note that this is the offset in # of descriptors and not in byte address.
1014 #define UDMA_M2S_Q_TDRTP_OFFSET_MASK 0x00FFFFFF
1015 #define UDMA_M2S_Q_TDRTP_OFFSET_SHIFT 0
1017 #define UDMA_M2S_Q_TDRTP_RING_ID_MASK 0xC0000000
1018 #define UDMA_M2S_Q_TDRTP_RING_ID_SHIFT 30
1020 /**** TDCP register ****/
1022 * Relative offset of the first descriptor in the prefetch FIFO.
1023 * This is the next descriptor that will be read by the scheduler.
1025 #define UDMA_M2S_Q_TDCP_OFFSET_MASK 0x00FFFFFF
1026 #define UDMA_M2S_Q_TDCP_OFFSET_SHIFT 0
1028 #define UDMA_M2S_Q_TDCP_RING_ID_MASK 0xC0000000
1029 #define UDMA_M2S_Q_TDCP_RING_ID_SHIFT 30
1031 * M2S Descriptor Ring Base address [31:4].
1032 * Value of the base address of the M2S descriptor ring
1033 * [3:0] - 0 - 16B alignment is enforced
1034 * ([11:4] should be 0 for 4KB alignment)
1036 * Length of the descriptor ring (in descriptors) associated with the ring base
1037 * address. Ends at maximum burst size alignment.
1039 #define UDMA_M2S_Q_TCRBP_LOW_ADDR_MASK 0xFFFFFFF0
1040 #define UDMA_M2S_Q_TCRBP_LOW_ADDR_SHIFT 4
1042 /**** TCRHP register ****/
1044 * Relative offset of the next descriptor that needs to be updated by the
1045 * completion controller.
1046 * Note: This is in descriptors and not in byte address.
1048 #define UDMA_M2S_Q_TCRHP_OFFSET_MASK 0x00FFFFFF
1049 #define UDMA_M2S_Q_TCRHP_OFFSET_SHIFT 0
1051 #define UDMA_M2S_Q_TCRHP_RING_ID_MASK 0xC0000000
1052 #define UDMA_M2S_Q_TCRHP_RING_ID_SHIFT 30
1054 /**** TCRHP_internal register ****/
1056 * Relative offset of the next descriptor that needs to be updated by the
1057 * completion controller.
1058 * Note: This is in descriptors and not in byte address.
1060 #define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_MASK 0x00FFFFFF
1061 #define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_SHIFT 0
1063 #define UDMA_M2S_Q_TCRHP_INTERNAL_RING_ID_MASK 0xC0000000
1064 #define UDMA_M2S_Q_TCRHP_INTERNAL_RING_ID_SHIFT 30
1066 /**** rate_limit_cfg_1 register ****/
1067 /* Maximum number of accumulated bytes in the token counter. */
1068 #define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_MASK 0x00FFFFFF
1069 #define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_SHIFT 0
1070 /* Enable the rate limiter. */
1071 #define UDMA_M2S_Q_RATE_LIMIT_CFG_1_EN (1 << 24)
1072 /* Stop token fill. */
1073 #define UDMA_M2S_Q_RATE_LIMIT_CFG_1_PAUSE (1 << 25)
1075 /**** rate_limit_cfg_cycle register ****/
1076 /* Number of short cycles between token fills */
1077 #define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
1078 #define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
1080 /**** rate_limit_cfg_token_size_1 register ****/
1081 /* Number of bits to add in each long cycle */
1082 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
1083 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
1085 /**** rate_limit_cfg_token_size_2 register ****/
1086 /* Number of bits to add in each cycle */
1087 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
1088 #define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
1090 /**** rate_limit_sw_ctrl register ****/
1091 /* Reset the token bucket counter. */
1092 #define UDMA_M2S_Q_RATE_LIMIT_SW_CTRL_RST_TOKEN_CNT (1 << 0)
1094 /**** rate_limit_mask register ****/
1095 /* Mask the external rate limiter. */
1096 #define UDMA_M2S_Q_RATE_LIMIT_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
1097 /* Mask the internal rate limiter. */
1098 #define UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_RATE_LIMITER (1 << 1)
1100 * Mask the internal pause mechanism for DMB.
1101 * (Data Memory Barrier).
1103 #define UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_PAUSE_DMB (1 << 2)
1104 /* Mask the external application pause interface. */
1105 #define UDMA_M2S_Q_RATE_LIMIT_MASK_EXTERNAL_PAUSE (1 << 3)
1107 /**** dwrr_cfg_1 register ****/
1108 /* Maximum number of accumulated bytes in the deficit counter */
1109 #define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK 0x00FFFFFF
1110 #define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_SHIFT 0
1111 /* Bypass the DWRR. */
1112 #define UDMA_M2S_Q_DWRR_CFG_1_STRICT (1 << 24)
1113 /* Stop deficit counter increment. */
1114 #define UDMA_M2S_Q_DWRR_CFG_1_PAUSE (1 << 25)
1116 /**** dwrr_cfg_2 register ****/
1118 * Value for the queue QoS.
1119 * Queues with the same QoS value are scheduled with RR/DWRR.
1120 * Only LOG(number of queues) is used.
1122 #define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK 0x000000FF
1123 #define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT 0
1125 /**** dwrr_cfg_3 register ****/
1127 #define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK 0x000000FF
1128 #define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_SHIFT 0
1130 /**** dwrr_sw_ctrl register ****/
1131 /* Reset the DWRR deficit counter. */
1132 #define UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT (1 << 0)
1134 /**** comp_cfg register ****/
1135 /* Enable writing to the completion ring */
1136 #define UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE (1 << 0)
1137 /* Disable the completion coalescing function. */
1138 #define UDMA_M2S_Q_COMP_CFG_DIS_COMP_COAL (1 << 1)
1140 /**** q_sw_ctrl register ****/
1142 * Reset the DMB hardware barrier
1143 * (enable queue operation).
1145 #define UDMA_M2S_Q_SW_CTRL_RST_DMB (1 << 0)
1146 /* Reset the tail pointer hardware. */
1147 #define UDMA_M2S_Q_SW_CTRL_RST_TAIL_PTR (1 << 1)
1148 /* Reset the head pointer hardware. */
1149 #define UDMA_M2S_Q_SW_CTRL_RST_HEAD_PTR (1 << 2)
1150 /* Reset the current pointer hardware. */
1151 #define UDMA_M2S_Q_SW_CTRL_RST_CURRENT_PTR (1 << 3)
1152 /* Reset the queue */
1153 #define UDMA_M2S_Q_SW_CTRL_RST_Q (1 << 8)
1159 #endif /* __AL_HAL_UDMA_M2S_REG_H */