2 *******************************************************************************
3 Copyright (C) 2015 Annapurna Labs Ltd.
5 This file may be licensed under the terms of the Annapurna Labs Commercial
8 Alternatively, this file can be distributed under the terms of the GNU General
9 Public License V2 as published by the Free Software Foundation and can be
10 found at http://www.gnu.org/licenses/gpl-2.0.html
12 Alternatively, redistribution and use in source and binary forms, with or
13 without modification, are permitted provided that the following conditions are
16 * Redistributions of source code must retain the above copyright notice,
17 this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in
21 the documentation and/or other materials provided with the
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *******************************************************************************/
39 * @file al_hal_eth_mac_regs.h
41 * @brief Ethernet MAC registers
45 #ifndef __AL_HAL_ETH_MAC_REGS_H__
46 #define __AL_HAL_ETH_MAC_REGS_H__
48 #include "al_hal_plat_types.h"
57 struct al_eth_mac_1g_stats {
58 uint32_t reserved1[2];
59 uint32_t aFramesTransmittedOK; /* 0x68 */
60 uint32_t aFramesReceivedOK; /* 0x6c */
61 uint32_t aFrameCheckSequenceErrors; /* 0x70 */
62 uint32_t aAlignmentErrors; /* 0x74 */
63 uint32_t aOctetsTransmittedOK; /* 0x78 */
64 uint32_t aOctetsReceivedOK; /* 0x7c */
65 uint32_t aPAUSEMACCtrlFramesTransmitted; /* 0x80 */
66 uint32_t aPAUSEMACCtrlFramesReceived; /* 0x84 */
67 uint32_t ifInErrors ; /* 0x88 */
68 uint32_t ifOutErrors; /* 0x8c */
69 uint32_t ifInUcastPkts; /* 0x90 */
70 uint32_t ifInMulticastPkts; /* 0x94 */
71 uint32_t ifInBroadcastPkts; /* 0x98 */
73 uint32_t ifOutUcastPkts; /* 0xa0 */
74 uint32_t ifOutMulticastPkts; /* 0xa4 */
75 uint32_t ifOutBroadcastPkts; /* 0xa8 */
76 uint32_t etherStatsDropEvents; /* 0xac */
77 uint32_t etherStatsOctets; /* 0xb0 */
78 uint32_t etherStatsPkts; /* 0xb4 */
79 uint32_t etherStatsUndersizePkts; /* 0xb8 */
80 uint32_t etherStatsOversizePkts; /* 0xbc */
81 uint32_t etherStatsPkts64Octets; /* 0xc0 */
82 uint32_t etherStatsPkts65to127Octets; /* 0xc4 */
83 uint32_t etherStatsPkts128to255Octets; /* 0xc8 */
84 uint32_t etherStatsPkts256to511Octets; /* 0xcc */
85 uint32_t etherStatsPkts512to1023Octets; /* 0xd0 */
86 uint32_t etherStatsPkts1024to1518Octets; /* 0xd4 */
87 uint32_t etherStatsPkts1519toX; /* 0xd8 */
88 uint32_t etherStatsJabbers; /* 0xdc */
89 uint32_t etherStatsFragments; /* 0xe0 */
90 uint32_t reserved3[71];
93 struct al_eth_mac_1g {
102 uint32_t pause_quant;
103 uint32_t rx_section_empty;
105 uint32_t rx_section_full;
106 uint32_t tx_section_empty;
107 uint32_t tx_section_full;
108 uint32_t rx_almost_empty;
110 uint32_t rx_almost_full;
111 uint32_t tx_almost_empty;
112 uint32_t tx_almost_full;
116 uint32_t Reserved[5];
121 struct al_eth_mac_1g_stats stats;
123 uint32_t phy_regs_base;
124 uint32_t Reserved2[127];
127 struct al_eth_mac_10g_stats_v2 {
128 uint32_t aFramesTransmittedOK; /* 0x80 */
130 uint32_t aFramesReceivedOK; /* 0x88 */
132 uint32_t aFrameCheckSequenceErrors; /* 0x90 */
134 uint32_t aAlignmentErrors; /* 0x98 */
136 uint32_t aPAUSEMACCtrlFramesTransmitted; /* 0xa0 */
138 uint32_t aPAUSEMACCtrlFramesReceived; /* 0xa8 */
140 uint32_t aFrameTooLongErrors; /* 0xb0 */
142 uint32_t aInRangeLengthErrors; /* 0xb8 */
144 uint32_t VLANTransmittedOK; /* 0xc0 */
146 uint32_t VLANReceivedOK; /* 0xc8 */
148 uint32_t ifOutOctetsL; /* 0xd0 */
149 uint32_t ifOutOctetsH; /* 0xd4 */
150 uint32_t ifInOctetsL; /* 0xd8 */
151 uint32_t ifInOctetsH; /* 0xdc */
152 uint32_t ifInUcastPkts; /* 0xe0 */
154 uint32_t ifInMulticastPkts; /* 0xe8 */
156 uint32_t ifInBroadcastPkts; /* 0xf0 */
158 uint32_t ifOutErrors; /* 0xf8 */
159 uint32_t reserved14[3];
160 uint32_t ifOutUcastPkts; /* 0x108 */
162 uint32_t ifOutMulticastPkts; /* 0x110 */
164 uint32_t ifOutBroadcastPkts; /* 0x118 */
166 uint32_t etherStatsDropEvents; /* 0x120 */
168 uint32_t etherStatsOctets; /* 0x128 */
170 uint32_t etherStatsPkts; /* 0x130 */
172 uint32_t etherStatsUndersizePkts; /* 0x138 */
174 uint32_t etherStatsPkts64Octets; /* 0x140 */
176 uint32_t etherStatsPkts65to127Octets; /* 0x148 */
178 uint32_t etherStatsPkts128to255Octets; /* 0x150 */
180 uint32_t etherStatsPkts256to511Octets; /* 0x158 */
182 uint32_t etherStatsPkts512to1023Octets; /* 0x160 */
184 uint32_t etherStatsPkts1024to1518Octets; /* 0x168 */
186 uint32_t etherStatsPkts1519toX; /* 0x170 */
188 uint32_t etherStatsOversizePkts; /* 0x178 */
190 uint32_t etherStatsJabbers; /* 0x180 */
192 uint32_t etherStatsFragments; /* 0x188 */
194 uint32_t ifInErrors; /* 0x190 */
195 uint32_t reserved32[91];
198 struct al_eth_mac_10g_stats_v3_rx {
199 uint32_t etherStatsOctets; /* 0x00 */
201 uint32_t ifOctetsL; /* 0x08 */
202 uint32_t ifOctetsH; /* 0x0c */
203 uint32_t aAlignmentErrors; /* 0x10 */
205 uint32_t aPAUSEMACCtrlFrames; /* 0x18 */
207 uint32_t FramesOK; /* 0x20 */
209 uint32_t CRCErrors; /* 0x28 */
211 uint32_t VLANOK; /* 0x30 */
213 uint32_t ifInErrors; /* 0x38 */
215 uint32_t ifInUcastPkts; /* 0x40 */
217 uint32_t ifInMulticastPkts; /* 0x48 */
219 uint32_t ifInBroadcastPkts; /* 0x50 */
221 uint32_t etherStatsDropEvents; /* 0x58 */
223 uint32_t etherStatsPkts; /* 0x60 */
225 uint32_t etherStatsUndersizePkts; /* 0x68 */
227 uint32_t etherStatsPkts64Octets; /* 0x70 */
229 uint32_t etherStatsPkts65to127Octets; /* 0x78 */
231 uint32_t etherStatsPkts128to255Octets; /* 0x80 */
233 uint32_t etherStatsPkts256to511Octets; /* 0x88 */
235 uint32_t etherStatsPkts512to1023Octets; /* 0x90 */
237 uint32_t etherStatsPkts1024to1518Octets; /* 0x98 */
239 uint32_t etherStatsPkts1519toMax; /* 0xa0 */
241 uint32_t etherStatsOversizePkts; /* 0xa8 */
243 uint32_t etherStatsJabbers; /* 0xb0 */
245 uint32_t etherStatsFragments; /* 0xb8 */
247 uint32_t aMACControlFramesReceived; /* 0xc0 */
249 uint32_t aFrameTooLong; /* 0xc8 */
251 uint32_t aInRangeLengthErrors; /* 0xd0 */
253 uint32_t reserved29[10];
256 struct al_eth_mac_10g_stats_v3_tx {
257 uint32_t etherStatsOctets; /* 0x00 */
259 uint32_t ifOctetsL; /* 0x08 */
260 uint32_t ifOctetsH; /* 0x0c */
261 uint32_t aAlignmentErrors; /* 0x10 */
263 uint32_t aPAUSEMACCtrlFrames; /* 0x18 */
265 uint32_t FramesOK; /* 0x20 */
267 uint32_t CRCErrors; /* 0x28 */
269 uint32_t VLANOK; /* 0x30 */
271 uint32_t ifOutErrors; /* 0x38 */
273 uint32_t ifUcastPkts; /* 0x40 */
275 uint32_t ifMulticastPkts; /* 0x48 */
277 uint32_t ifBroadcastPkts; /* 0x50 */
279 uint32_t etherStatsDropEvents; /* 0x58 */
281 uint32_t etherStatsPkts; /* 0x60 */
283 uint32_t etherStatsUndersizePkts; /* 0x68 */
285 uint32_t etherStatsPkts64Octets; /* 0x70 */
287 uint32_t etherStatsPkts65to127Octets; /* 0x78 */
289 uint32_t etherStatsPkts128to255Octets; /* 0x80 */
291 uint32_t etherStatsPkts256to511Octets; /* 0x88 */
293 uint32_t etherStatsPkts512to1023Octets; /* 0x90 */
295 uint32_t etherStatsPkts1024to1518Octets; /* 0x98 */
297 uint32_t etherStatsPkts1519toTX_MTU; /* 0xa0 */
299 uint32_t reserved51[4];
300 uint32_t aMACControlFrames; /* 0xc0 */
301 uint32_t reserved52[15];
304 struct al_eth_mac_10g_stats_v3 {
305 uint32_t reserved1[32];
307 struct al_eth_mac_10g_stats_v3_rx rx;
309 struct al_eth_mac_10g_stats_v3_tx tx;
312 union al_eth_mac_10g_stats {
313 struct al_eth_mac_10g_stats_v2 v2;
314 struct al_eth_mac_10g_stats_v3 v3;
317 struct al_eth_mac_10g {
327 uint32_t rx_fifo_sections;
329 uint32_t tx_fifo_sections;
330 uint32_t rx_fifo_almost_f_e;
331 uint32_t tx_fifo_almost_f_e;
332 uint32_t hashtable_load;
334 uint32_t mdio_cfg_status;
339 uint16_t mdio_regaddr;
344 uint32_t Reserved1[3];
346 uint32_t cl01_pause_quanta;
347 uint32_t cl23_pause_quanta;
348 uint32_t cl45_pause_quanta;
350 uint32_t cl67_pause_quanta;
351 uint32_t cl01_quanta_thresh;
352 uint32_t cl23_quanta_thresh;
353 uint32_t cl45_quanta_thresh;
355 uint32_t cl67_quanta_thresh;
356 uint32_t rx_pause_status;
358 uint32_t ts_timestamp;
360 union al_eth_mac_10g_stats stats;
367 uint32_t dev_ability;
368 uint32_t partner_ability;
369 uint32_t an_expansion;
373 uint32_t Reserved4[9];
376 uint32_t link_timer_lo;
377 uint32_t link_timer_hi;
381 uint32_t Reserved5[43];
384 struct al_eth_mac_gen {
385 /* [0x0] Ethernet Controller Version */
388 /* [0xc] MAC selection configuration */
390 /* [0x10] 10/100/1000 MAC external configuration */
392 /* [0x14] 10/100/1000 MAC status */
393 uint32_t mac_1g_stat;
394 /* [0x18] RGMII external configuration */
396 /* [0x1c] RGMII status */
398 /* [0x20] 1/2.5/10G MAC external configuration */
399 uint32_t mac_10g_cfg;
400 /* [0x24] 1/2.5/10G MAC status */
401 uint32_t mac_10g_stat;
402 /* [0x28] XAUI PCS configuration */
404 /* [0x2c] XAUI PCS status */
406 /* [0x30] RXAUI PCS configuration */
408 /* [0x34] RXAUI PCS status */
410 /* [0x38] Signal detect configuration */
412 /* [0x3c] MDIO control register for MDIO interface 1 */
413 uint32_t mdio_ctrl_1;
414 /* [0x40] MDIO information register for MDIO interface 1 */
416 /* [0x44] MDIO control register for MDIO interface 2 */
417 uint32_t mdio_ctrl_2;
418 /* [0x48] MDIO information register for MDIO interface 2 */
420 /* [0x4c] XGMII 32 to 64 data FIFO control */
421 uint32_t xgmii_dfifo_32_64;
422 /* [0x50] Reserved 1 out */
423 uint32_t mac_res_1_out;
424 /* [0x54] XGMII 64 to 32 data FIFO control */
425 uint32_t xgmii_dfifo_64_32;
426 /* [0x58] Reserved 1 in */
427 uint32_t mac_res_1_in;
428 /* [0x5c] SerDes TX FIFO control */
429 uint32_t sd_fifo_ctrl;
430 /* [0x60] SerDes TX FIFO status */
431 uint32_t sd_fifo_stat;
432 /* [0x64] SerDes in/out selection */
434 /* [0x68] Clock configuration */
437 /* [0x70] LOS and SD selection */
439 /* [0x74] RGMII selection configuration */
441 /* [0x78] Ethernet LED configuration */
445 struct al_eth_mac_kr {
446 /* [0x0] PCS register file address */
448 /* [0x4] PCS register file data */
450 /* [0x8] AN register file address */
452 /* [0xc] AN register file data */
454 /* [0x10] PMA register file address */
456 /* [0x14] PMA register file data */
458 /* [0x18] MTIP register file address */
460 /* [0x1c] MTIP register file data */
462 /* [0x20] KR PCS config */
464 /* [0x24] KR PCS status */
468 struct al_eth_mac_sgmii {
469 /* [0x0] PCS register file address */
471 /* [0x4] PCS register file data */
473 /* [0x8] PCS clock divider configuration */
475 /* [0xc] PCS Status */
479 struct al_eth_mac_stat {
480 /* [0x0] Receive rate matching error */
481 uint32_t match_fault;
482 /* [0x4] EEE, number of times the MAC went into low power mode */
484 /* [0x8] EEE, number of times the MAC went out of low power mode */
488 * FEC corrected error indication
490 uint32_t v3_pcs_40g_ll_cerr_0;
493 * FEC corrected error indication
495 uint32_t v3_pcs_40g_ll_cerr_1;
498 * FEC corrected error indication
500 uint32_t v3_pcs_40g_ll_cerr_2;
503 * FEC corrected error indication
505 uint32_t v3_pcs_40g_ll_cerr_3;
508 * FEC uncorrectable error indication
510 uint32_t v3_pcs_40g_ll_ncerr_0;
513 * FEC uncorrectable error indication
515 uint32_t v3_pcs_40g_ll_ncerr_1;
518 * FEC uncorrectable error indication
520 uint32_t v3_pcs_40g_ll_ncerr_2;
523 * FEC uncorrectable error indication
525 uint32_t v3_pcs_40g_ll_ncerr_3;
528 * FEC corrected error indication
530 uint32_t v3_pcs_10g_ll_cerr;
533 * FEC uncorrectable error indication
535 uint32_t v3_pcs_10g_ll_ncerr;
538 struct al_eth_mac_stat_lane {
539 /* [0x0] Character error */
541 /* [0x4] Disparity error */
543 /* [0x8] Comma detection */
547 struct al_eth_mac_gen_v3 {
548 /* [0x0] ASYNC FIFOs control */
550 /* [0x4] TX ASYNC FIFO configuration */
551 uint32_t tx_afifo_cfg_1;
552 /* [0x8] TX ASYNC FIFO configuration */
553 uint32_t tx_afifo_cfg_2;
554 /* [0xc] TX ASYNC FIFO configuration */
555 uint32_t tx_afifo_cfg_3;
556 /* [0x10] TX ASYNC FIFO configuration */
557 uint32_t tx_afifo_cfg_4;
558 /* [0x14] TX ASYNC FIFO configuration */
559 uint32_t tx_afifo_cfg_5;
560 /* [0x18] RX ASYNC FIFO configuration */
561 uint32_t rx_afifo_cfg_1;
562 /* [0x1c] RX ASYNC FIFO configuration */
563 uint32_t rx_afifo_cfg_2;
564 /* [0x20] RX ASYNC FIFO configuration */
565 uint32_t rx_afifo_cfg_3;
566 /* [0x24] RX ASYNC FIFO configuration */
567 uint32_t rx_afifo_cfg_4;
568 /* [0x28] RX ASYNC FIFO configuration */
569 uint32_t rx_afifo_cfg_5;
570 /* [0x2c] MAC selection configuration */
572 /* [0x30] 10G LL MAC configuration */
573 uint32_t mac_10g_ll_cfg;
574 /* [0x34] 10G LL MAC control */
575 uint32_t mac_10g_ll_ctrl;
576 /* [0x38] 10G LL PCS configuration */
577 uint32_t pcs_10g_ll_cfg;
578 /* [0x3c] 10G LL PCS status */
579 uint32_t pcs_10g_ll_status;
580 /* [0x40] 40G LL PCS configuration */
581 uint32_t pcs_40g_ll_cfg;
582 /* [0x44] 40G LL PCS status */
583 uint32_t pcs_40g_ll_status;
584 /* [0x48] PCS 40G register file address */
585 uint32_t pcs_40g_ll_addr;
586 /* [0x4c] PCS 40G register file data */
587 uint32_t pcs_40g_ll_data;
588 /* [0x50] 40G LL MAC configuration */
589 uint32_t mac_40g_ll_cfg;
590 /* [0x54] 40G LL MAC status */
591 uint32_t mac_40g_ll_status;
592 /* [0x58] Preamble configuration (high [55:32]) */
593 uint32_t preamble_cfg_high;
594 /* [0x5c] Preamble configuration (low [31:0]) */
595 uint32_t preamble_cfg_low;
596 /* [0x60] MAC 40G register file address */
597 uint32_t mac_40g_ll_addr;
598 /* [0x64] MAC 40G register file data */
599 uint32_t mac_40g_ll_data;
600 /* [0x68] 40G LL MAC control */
601 uint32_t mac_40g_ll_ctrl;
602 /* [0x6c] PCS 40G register file address */
603 uint32_t pcs_40g_fec_91_ll_addr;
604 /* [0x70] PCS 40G register file data */
605 uint32_t pcs_40g_fec_91_ll_data;
606 /* [0x74] 40G LL PCS EEE configuration */
607 uint32_t pcs_40g_ll_eee_cfg;
608 /* [0x78] 40G LL PCS EEE status */
609 uint32_t pcs_40g_ll_eee_status;
611 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
614 uint32_t serdes_32_tx_shift;
616 * [0x80] SERDES 32-bit interface shift configuration (when swap is
619 uint32_t serdes_32_rx_shift;
621 * [0x84] SERDES 32-bit interface bit selection
623 uint32_t serdes_32_tx_sel;
625 * [0x88] SERDES 32-bit interface bit selection
627 uint32_t serdes_32_rx_sel;
628 /* [0x8c] AN/LT wrapper control */
630 /* [0x90] AN/LT wrapper register file address */
631 uint32_t an_lt_0_addr;
632 /* [0x94] AN/LT wrapper register file data */
633 uint32_t an_lt_0_data;
634 /* [0x98] AN/LT wrapper register file address */
635 uint32_t an_lt_1_addr;
636 /* [0x9c] AN/LT wrapper register file data */
637 uint32_t an_lt_1_data;
638 /* [0xa0] AN/LT wrapper register file address */
639 uint32_t an_lt_2_addr;
640 /* [0xa4] AN/LT wrapper register file data */
641 uint32_t an_lt_2_data;
642 /* [0xa8] AN/LT wrapper register file address */
643 uint32_t an_lt_3_addr;
644 /* [0xac] AN/LT wrapper register file data */
645 uint32_t an_lt_3_data;
646 /* [0xb0] External SERDES control */
647 uint32_t ext_serdes_ctrl;
648 /* [0xb4] spare bits */
653 struct al_eth_mac_regs {
654 struct al_eth_mac_1g mac_1g; /* [0x000] */
655 struct al_eth_mac_10g mac_10g; /* [0x400] */
656 uint32_t rsrvd_0[64]; /* [0x800] */
657 struct al_eth_mac_gen gen; /* [0x900] */
658 struct al_eth_mac_kr kr; /* [0xa00] */
659 struct al_eth_mac_sgmii sgmii; /* [0xb00] */
660 struct al_eth_mac_stat stat; /* [0xc00] */
661 struct al_eth_mac_stat_lane stat_lane[4]; /* [0xd00] */
662 struct al_eth_mac_gen_v3 gen_v3; /* [0xe00] */
670 /**** 1G MAC registers ****/
672 #define ETH_1G_MAC_CMD_CFG_TX_ENA (1 << 0)
673 #define ETH_1G_MAC_CMD_CFG_RX_ENA (1 << 1)
674 /* enable Half Duplex */
675 #define ETH_1G_MAC_CMD_CFG_HD_EN (1 << 10)
676 /* enable 1G speed */
677 #define ETH_1G_MAC_CMD_CFG_1G_SPD (1 << 3)
678 /* enable 10M speed */
679 #define ETH_1G_MAC_CMD_CFG_10M_SPD (1 << 25)
681 /**** 10G MAC registers ****/
683 #define ETH_10G_MAC_CMD_CFG_TX_ENA (1 << 0)
684 #define ETH_10G_MAC_CMD_CFG_RX_ENA (1 << 1)
685 #define ETH_10G_MAC_CMD_CFG_WAN_MODE (1 << 3)
686 #define ETH_10G_MAC_CMD_CFG_PROMIS_EN (1 << 4)
687 #define ETH_10G_MAC_CMD_CFG_PAD_EN (1 << 5)
688 #define ETH_10G_MAC_CMD_CFG_CRC_FWD (1 << 6)
689 #define ETH_10G_MAC_CMD_CFG_PAUSE_FWD (1 << 7)
690 #define ETH_10G_MAC_CMD_CFG_PAUSE_IGNORE (1 << 8)
691 #define ETH_10G_MAC_CMD_CFG_TX_ADDR_INS (1 << 9)
692 #define ETH_10G_MAC_CMD_CFG_LOOP_ENA (1 << 10)
693 #define ETH_10G_MAC_CMD_CFG_TX_PAD_EN (1 << 11)
694 #define ETH_10G_MAC_CMD_CFG_SW_RESET (1 << 12)
695 #define ETH_10G_MAC_CMD_CFG_CNTL_FRM_ENA (1 << 13)
696 #define ETH_10G_MAC_CMD_CFG_RX_ERR_DISC (1 << 14)
697 #define ETH_10G_MAC_CMD_CFG_PHY_TXENA (1 << 15)
698 #define ETH_10G_MAC_CMD_CFG_FORCE_SEND_IDLE (1 << 16)
699 #define ETH_10G_MAC_CMD_CFG_NO_LGTH_CHECK (1 << 17)
700 #define ETH_10G_MAC_CMD_CFG_COL_CNT_EXT (1 << 18)
701 #define ETH_10G_MAC_CMD_CFG_PFC_MODE (1 << 19)
702 #define ETH_10G_MAC_CMD_CFG_PAUSE_PFC_COMP (1 << 20)
703 #define ETH_10G_MAC_CMD_CFG_SFD_ANY (1 << 21)
704 #define ETH_10G_MAC_CMD_CFG_TX_FLUSH (1 << 22)
705 #define ETH_10G_MAC_CMD_CFG_TX_LOWP_ENA (1 << 23)
706 #define ETH_10G_MAC_CMD_CFG_REG_LOWP_RXEMPTY (1 << 24)
707 #define ETH_10G_MAC_CMD_CFG_SHORT_DISCARD (1 << 25)
709 /* mdio_cfg_status */
710 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK 0x0000001c
711 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_SHIFT 2
713 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_1_CLK 0
714 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_3_CLK 1
715 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_5_CLK 2
716 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_7_CLK 3
717 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_9_CLK 4
718 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_11_CLK 5
719 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_13_CLK 6
720 #define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_15_CLK 7
723 #define ETH_10G_MAC_CONTROL_AN_EN_MASK 0x00001000
724 #define ETH_10G_MAC_CONTROL_AN_EN_SHIFT 12
727 #define ETH_10G_MAC_IF_MODE_SGMII_EN_MASK 0x00000001
728 #define ETH_10G_MAC_IF_MODE_SGMII_EN_SHIFT 0
729 #define ETH_10G_MAC_IF_MODE_SGMII_AN_MASK 0x00000002
730 #define ETH_10G_MAC_IF_MODE_SGMII_AN_SHIFT 1
731 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_MASK 0x0000000c
732 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_SHIFT 2
733 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_MASK 0x00000010
734 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_SHIFT 4
736 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_10M 0
737 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_100M 1
738 #define ETH_10G_MAC_IF_MODE_SGMII_SPEED_1G 2
740 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_FULL 0
741 #define ETH_10G_MAC_IF_MODE_SGMII_DUPLEX_HALF 1
743 /**** version register ****/
744 /* Revision number (Minor) */
745 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
746 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
747 /* Revision number (Major) */
748 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
749 #define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
750 /* Date of release */
751 #define ETH_MAC_GEN_VERSION_DATE_DAY_MASK 0x001F0000
752 #define ETH_MAC_GEN_VERSION_DATE_DAY_SHIFT 16
753 /* Month of release */
754 #define ETH_MAC_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
755 #define ETH_MAC_GEN_VERSION_DATA_MONTH_SHIFT 21
756 /* Year of release (starting from 2000) */
757 #define ETH_MAC_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
758 #define ETH_MAC_GEN_VERSION_DATE_YEAR_SHIFT 25
760 #define ETH_MAC_GEN_VERSION_RESERVED_MASK 0xC0000000
761 #define ETH_MAC_GEN_VERSION_RESERVED_SHIFT 30
763 /**** cfg register ****/
765 * Selects between the 10/100/1000 MAC and the 1/2.5/10G MAC:
769 #define ETH_MAC_GEN_CFG_MAC_1_10 (1 << 0)
771 * Selects the operation mode of the 1/2.5/10G MAC:
773 * 01 - 10G XAUI/RXAUI
777 #define ETH_MAC_GEN_CFG_XGMII_SGMII_MASK 0x00000006
778 #define ETH_MAC_GEN_CFG_XGMII_SGMII_SHIFT 1
780 * Selects the operation mode of the PCS:
784 #define ETH_MAC_GEN_CFG_XAUI_RXAUI (1 << 3)
785 /* Swap bits of TBI (SGMII mode) interface */
786 #define ETH_MAC_GEN_CFG_SWAP_TBI_RX (1 << 4)
788 * Determines the offset of the TBI bus on the SerDes interface:
792 #define ETH_MAC_GEN_CFG_TBI_MSB_RX (1 << 5)
794 * Selects the SGMII PCS/MAC:
795 * 0 – 10G MAC with SGMII
796 * 1 – 1G MAC with SGMII
798 #define ETH_MAC_GEN_CFG_SGMII_SEL (1 << 6)
800 * Selects between RGMII and SGMII for the 1G MAC:
804 #define ETH_MAC_GEN_CFG_RGMII_SGMII_SEL (1 << 7)
805 /* Swap bits of TBI (SGMII mode) interface */
806 #define ETH_MAC_GEN_CFG_SWAP_TBI_TX (1 << 8)
808 * Determines the offset of the TBI bus on the SerDes interface:
812 #define ETH_MAC_GEN_CFG_TBI_MSB_TX (1 << 9)
814 * Selection between the MDIO from 10/100/1000 MAC or the 1/2.5/10G MAC
818 #define ETH_MAC_GEN_CFG_MDIO_1_10 (1 << 10)
824 #define ETH_MAC_GEN_CFG_MDIO_POL (1 << 11)
825 /* Swap bits on SerDes interface */
826 #define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_MASK 0x000F0000
827 #define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_SHIFT 16
828 /* Swap bits on SerDes interface */
829 #define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_MASK 0x0F000000
830 #define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_SHIFT 24
832 /**** mac_1g_cfg register ****/
834 * Selection of the input for the "set_1000" input of the Ethernet 10/100/1000
836 * 0 - From RGMII converter (automatic speed selection)
837 * 1 - From register set_1000_def
839 #define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_SEL (1 << 0)
840 /* Default value for the 10/100/1000 MAC "set_1000" input */
841 #define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_DEF (1 << 1)
843 * Selection of the input for the "set_10" input of the Ethernet 10/100/1000
845 * 0 - From RGMII converter (automatic speed selection)
846 * 1 - From register set_10_def
848 #define ETH_MAC_GEN_MAC_1G_CFG_SET_10_SEL (1 << 4)
849 /* Default value for the 10/100/1000 MAC "set_10" input */
850 #define ETH_MAC_GEN_MAC_1G_CFG_SET_10_DEF (1 << 5)
851 /* Transmit low power enable */
852 #define ETH_MAC_GEN_MAC_1G_CFG_LOWP_ENA (1 << 8)
854 * Enable magic packet mode:
856 * 1 - Normal operation
858 #define ETH_MAC_GEN_MAC_1G_CFG_SLEEPN (1 << 9)
859 /* Swap ff_tx_crc input */
860 #define ETH_MAC_GEN_MAC_1G_CFG_SWAP_FF_TX_CRC (1 << 12)
862 /**** mac_1g_stat register ****/
863 /* Status of the en_10 output form the 10/100/1000 MAC */
864 #define ETH_MAC_GEN_MAC_1G_STAT_EN_10 (1 << 0)
865 /* Status of the eth_mode output from th 10/100/1000 MAC */
866 #define ETH_MAC_GEN_MAC_1G_STAT_ETH_MODE (1 << 1)
867 /* Status of the lowp output from the 10/100/1000 MAC */
868 #define ETH_MAC_GEN_MAC_1G_STAT_LOWP (1 << 4)
869 /* Status of the wakeup output from the 10/100/1000 MAC */
870 #define ETH_MAC_GEN_MAC_1G_STAT_WAKEUP (1 << 5)
872 /**** rgmii_cfg register ****/
874 * Selection of the input for the "set_1000" input of the RGMII converter
876 * 1 - From register set_1000_def (automatic speed selection)
878 #define ETH_MAC_GEN_RGMII_CFG_SET_1000_SEL (1 << 0)
879 /* Default value for the RGMII converter "set_1000" input */
880 #define ETH_MAC_GEN_RGMII_CFG_SET_1000_DEF (1 << 1)
882 * Selection of the input for the "set_10" input of the RGMII converter:
884 * 1 - From register set_10_def (automatic speed selection)
886 #define ETH_MAC_GEN_RGMII_CFG_SET_10_SEL (1 << 4)
887 /* Default value for the 10/100/1000 MAC "set_10" input */
888 #define ETH_MAC_GEN_RGMII_CFG_SET_10_DEF (1 << 5)
889 /* Enable automatic speed selection (based on PHY in-band status information) */
890 #define ETH_MAC_GEN_RGMII_CFG_ENA_AUTO (1 << 8)
891 /* Force full duplex, only valid when ena_auto is '1'. */
892 #define ETH_MAC_GEN_RGMII_CFG_SET_FD (1 << 9)
894 /**** rgmii_stat register ****/
896 * Status of the speed output form the RGMII converter
902 #define ETH_MAC_GEN_RGMII_STAT_SPEED_MASK 0x00000003
903 #define ETH_MAC_GEN_RGMII_STAT_SPEED_SHIFT 0
905 * Link indication from the RGMII converter (valid only if the external PHY
906 * supports in-band status signaling)
908 #define ETH_MAC_GEN_RGMII_STAT_LINK (1 << 4)
910 * Full duplex indication from the RGMII converter (valid only if the external
911 * PHY supports in-band status signaling)
913 #define ETH_MAC_GEN_RGMII_STAT_DUP (1 << 5)
915 /**** mac_10g_cfg register ****/
916 /* Instruct the XGMII to transmit local fault. */
917 #define ETH_MAC_GEN_MAC_10G_CFG_TX_LOC_FAULT (1 << 0)
918 /* Instruct the XGMII to transmit remote fault. */
919 #define ETH_MAC_GEN_MAC_10G_CFG_TX_REM_FAULT (1 << 1)
920 /* Instruct the XGMII to transmit link fault. */
921 #define ETH_MAC_GEN_MAC_10G_CFG_TX_LI_FAULT (1 << 2)
923 * Synchronous reset for the PCS layer. Can be used after SerDes lock assertion
924 * to reset the PCS state machine.
926 #define ETH_MAC_GEN_MAC_10G_CFG_SG_SRESET (1 << 3)
928 * PHY LOS indication selection
929 * 00 - Select register value from phy_los_def
930 * 01 - Select input from the SerDes
931 * 10 - Select input from GPIO
932 * 11 - Select inverted input from GPIO
934 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_MASK 0x00000030
935 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_SHIFT 4
937 * Default value for PHY LOS indication. Reflects the LOS indication from the
938 * SerDes. ('0' if not used)
940 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_DEF (1 << 6)
941 /* Reverse polarity of the LOS signal from the SerDes */
942 #define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_POL (1 << 7)
943 /* Transmit low power enable */
944 #define ETH_MAC_GEN_MAC_10G_CFG_LOWP_ENA (1 << 8)
945 /* Swap ff_tx_crc input */
946 #define ETH_MAC_GEN_MAC_10G_CFG_SWAP_FF_TX_CRC (1 << 12)
948 /**** mac_10g_stat register ****/
949 /* XGMII RS detects local fault */
950 #define ETH_MAC_GEN_MAC_10G_STAT_LOC_FAULT (1 << 0)
951 /* XGMII RS detects remote fault */
952 #define ETH_MAC_GEN_MAC_10G_STAT_REM_FAULT (1 << 1)
953 /* XGMII RS detects link fault */
954 #define ETH_MAC_GEN_MAC_10G_STAT_LI_FAULT (1 << 2)
956 #define ETH_MAC_GEN_MAC_10G_STAT_PFC_MODE (1 << 3)
958 #define ETH_MAC_GEN_MAC_10G_STAT_SG_ENA (1 << 4)
960 #define ETH_MAC_GEN_MAC_10G_STAT_SG_ANDONE (1 << 5)
962 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SYNC (1 << 6)
964 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_MASK 0x00000180
965 #define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_SHIFT 7
966 /* Status of the lowp output form the 1/2.5/10G MAC */
967 #define ETH_MAC_GEN_MAC_10G_STAT_LOWP (1 << 9)
968 /* Status of the ts_avail output from th 1/2.5/10G MAC */
969 #define ETH_MAC_GEN_MAC_10G_STAT_TS_AVAIL (1 << 10)
970 /* Transmit pause indication */
971 #define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_MASK 0xFF000000
972 #define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_SHIFT 24
974 /**** xaui_cfg register ****/
975 /* Increase rate matching FIFO threshold */
976 #define ETH_MAC_GEN_XAUI_CFG_JUMBO_EN (1 << 0)
978 /**** xaui_stat register ****/
979 /* Lane alignment status */
980 #define ETH_MAC_GEN_XAUI_STAT_ALIGN_DONE (1 << 0)
981 /* Lane synchronization */
982 #define ETH_MAC_GEN_XAUI_STAT_SYNC_MASK 0x000000F0
983 #define ETH_MAC_GEN_XAUI_STAT_SYNC_SHIFT 4
984 /* Code group alignment indication */
985 #define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_MASK 0x00000F00
986 #define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_SHIFT 8
988 /**** rxaui_cfg register ****/
989 /* Increase rate matching FIFO threshold */
990 #define ETH_MAC_GEN_RXAUI_CFG_JUMBO_EN (1 << 0)
991 /* Scrambler enable */
992 #define ETH_MAC_GEN_RXAUI_CFG_SRBL_EN (1 << 1)
993 /* Disparity calculation across lanes enabled */
994 #define ETH_MAC_GEN_RXAUI_CFG_DISP_ACROSS_LANE (1 << 2)
996 /**** rxaui_stat register ****/
997 /* Lane alignment status */
998 #define ETH_MAC_GEN_RXAUI_STAT_ALIGN_DONE (1 << 0)
999 /* Lane synchronization */
1000 #define ETH_MAC_GEN_RXAUI_STAT_SYNC_MASK 0x000000F0
1001 #define ETH_MAC_GEN_RXAUI_STAT_SYNC_SHIFT 4
1002 /* Code group alignment indication */
1003 #define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_MASK 0x00000F00
1004 #define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_SHIFT 8
1006 /**** sd_cfg register ****/
1008 * Signal detect selection
1012 #define ETH_MAC_GEN_SD_CFG_SEL_MASK 0x0000000F
1013 #define ETH_MAC_GEN_SD_CFG_SEL_SHIFT 0
1014 /* Signal detect value */
1015 #define ETH_MAC_GEN_SD_CFG_VAL_MASK 0x000000F0
1016 #define ETH_MAC_GEN_SD_CFG_VAL_SHIFT 4
1017 /* Signal detect revers polarity (reverse polarity of signal from the SerDes */
1018 #define ETH_MAC_GEN_SD_CFG_POL_MASK 0x00000F00
1019 #define ETH_MAC_GEN_SD_CFG_POL_SHIFT 8
1021 /**** mdio_ctrl_1 register ****/
1023 * Available indication
1024 * 0 - The port was available and it is captured by this Ethernet controller.
1025 * 1 - The port is used by another Ethernet controller.
1027 #define ETH_MAC_GEN_MDIO_CTRL_1_AVAIL (1 << 0)
1029 /**** mdio_1 register ****/
1030 /* Current Ethernet interface number that controls the MDIO port */
1031 #define ETH_MAC_GEN_MDIO_1_INFO_MASK 0x000000FF
1032 #define ETH_MAC_GEN_MDIO_1_INFO_SHIFT 0
1034 /**** mdio_ctrl_2 register ****/
1036 * Available indication
1037 * 0 - The port was available and it is captured by this Ethernet controller.
1038 * 1 - The port is used by another Ethernet controller.
1040 #define ETH_MAC_GEN_MDIO_CTRL_2_AVAIL (1 << 0)
1042 /**** mdio_2 register ****/
1043 /* Current Ethernet interface number that controls the MDIO port */
1044 #define ETH_MAC_GEN_MDIO_2_INFO_MASK 0x000000FF
1045 #define ETH_MAC_GEN_MDIO_2_INFO_SHIFT 0
1047 /**** xgmii_dfifo_32_64 register ****/
1049 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_ENABLE (1 << 0)
1050 /* Read Write command every 2 cycles */
1051 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_RW_2_CYCLES (1 << 1)
1052 /* Swap LSB MSB when creating wider bus */
1053 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_SWAP_LSB_MSB (1 << 2)
1054 /* Software reset */
1055 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_SW_RESET (1 << 4)
1056 /* Read threshold */
1057 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_MASK 0x0000FF00
1058 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_SHIFT 8
1060 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_MASK 0x00FF0000
1061 #define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_SHIFT 16
1063 /**** xgmii_dfifo_64_32 register ****/
1065 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_ENABLE (1 << 0)
1066 /* Read Write command every 2 cycles */
1067 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_RW_2_CYCLES (1 << 1)
1068 /* Swap LSB MSB when creating wider bus */
1069 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_SWAP_LSB_MSB (1 << 2)
1070 /* Software reset */
1071 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_SW_RESET (1 << 4)
1072 /* Read threshold */
1073 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_MASK 0x0000FF00
1074 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_SHIFT 8
1076 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_MASK 0x00FF0000
1077 #define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_SHIFT 16
1079 /**** sd_fifo_ctrl register ****/
1081 #define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_MASK 0x0000000F
1082 #define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_SHIFT 0
1083 /* Software reset */
1084 #define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_MASK 0x000000F0
1085 #define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_SHIFT 4
1086 /* Read threshold */
1087 #define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_MASK 0x0000FF00
1088 #define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_SHIFT 8
1090 /**** sd_fifo_stat register ****/
1092 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_MASK 0x000000FF
1093 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_SHIFT 0
1095 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_MASK 0x0000FF00
1096 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_SHIFT 8
1098 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_MASK 0x00FF0000
1099 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_SHIFT 16
1101 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_MASK 0xFF000000
1102 #define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_SHIFT 24
1104 /**** mux_sel register ****/
1106 * SGMII input selection selector
1112 #define ETH_MAC_GEN_MUX_SEL_SGMII_IN_MASK 0x00000003
1113 #define ETH_MAC_GEN_MUX_SEL_SGMII_IN_SHIFT 0
1115 * RXAUI Lane 0 Input
1121 #define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_MASK 0x0000000C
1122 #define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_SHIFT 2
1124 * RXAUI Lane 1 Input
1130 #define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_MASK 0x00000030
1131 #define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_SHIFT 4
1139 #define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_MASK 0x000000C0
1140 #define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_SHIFT 6
1148 #define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_MASK 0x00000300
1149 #define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_SHIFT 8
1157 #define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_MASK 0x00000C00
1158 #define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_SHIFT 10
1166 #define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_MASK 0x00003000
1167 #define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_SHIFT 12
1175 #define ETH_MAC_GEN_MUX_SEL_KR_IN_MASK 0x0000C000
1176 #define ETH_MAC_GEN_MUX_SEL_KR_IN_SHIFT 14
1178 * SerDes 0 input selection (TX)
1183 * 100 – RXAUI lane 0
1184 * 101 – RXAUI lane 1
1188 #define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_MASK 0x00070000
1189 #define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_SHIFT 16
1191 * SERDES 1 input selection (Tx)
1196 * 100 – RXAUI lane 0
1197 * 101 – RXAUI lane 1
1201 #define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_MASK 0x00380000
1202 #define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_SHIFT 19
1204 * SerDes 2 input selection (Tx)
1209 * 100 – RXAUI lane 0
1210 * 101 – RXAUI lane 1
1214 #define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_MASK 0x01C00000
1215 #define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_SHIFT 22
1217 * SerDes 3 input selection (Tx)
1222 * 100 – RXAUI lane 0
1223 * 101 – RXAUI lane 1
1227 #define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_MASK 0x0E000000
1228 #define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_SHIFT 25
1230 /**** clk_cfg register ****/
1232 * Rx/Tx lane 0 clock MUX select
1233 * must be aligned with data selector MUXs)
1234 * 0 – SerDes 0 clock
1235 * 0 – SerDes 1 clock
1236 * 2 – SerDes 2 clock
1237 * 3 – SerDes 3 clock
1239 #define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_MASK 0x00000003
1240 #define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_SHIFT 0
1242 * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs)
1243 * 0 - SerDes 0 clock
1244 * 1 - SerDes 1 clock
1245 * 2 - SerDes 2 clock
1246 * 3 - SerDes 3 clock
1248 #define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_MASK 0x00000030
1249 #define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_SHIFT 4
1251 * RX/TX lane 0 clock MUX select (should be aligned with data selector MUXs)
1252 * 0 - SERDES 0 clock
1253 * 1 - SERDES 1 clock
1254 * 2 - SERDES 2 clock
1255 * 3 - SERDES 3 clock
1257 #define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_MASK 0x00000300
1258 #define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_SHIFT 8
1260 * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs)
1261 * 0 - SerDes 0 clock
1262 * 1 - SerDes 1 clock
1263 * 2 - SerDes 2 clock
1264 * 3 - SerDes 3 clock
1266 #define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_MASK 0x00003000
1267 #define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_SHIFT 12
1269 * MAC GMII Rx clock MUX select must be aligned with data selector MUXs)
1273 #define ETH_MAC_GEN_CLK_CFG_GMII_RX_CLK_SEL (1 << 16)
1275 * MAC GMII Tx clock MUX select (should be aligned with data selector MUXs)
1279 #define ETH_MAC_GEN_CLK_CFG_GMII_TX_CLK_SEL (1 << 18)
1281 * Tx clock MUX select,
1282 * Selects the internal clock for the Tx data path
1283 * 0 – SerDes[0] TX DWORD CLK REF (for RXAUI and SGMII)
1284 * 1 – SerDes[0] TX WORD CLK REF (for XAUI and KR)
1286 #define ETH_MAC_GEN_CLK_CFG_TX_CLK_SEL (1 << 28)
1288 * Rxclock MUX select
1289 * Selects the internal clock for the Rx data path
1290 * 0 – XGMII TX CLK 32 LOCAL (for XAUI and RXAUI and KR)
1291 * 1 – SerDes[0] RX DWORD CLK GENERATED (125M)
1294 #define ETH_MAC_GEN_CLK_CFG_RX_CLK_SEL (1 << 30)
1296 /**** los_sel register ****/
1298 * Selected LOS/SD select
1304 #define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_MASK 0x00000003
1305 #define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_SHIFT 0
1307 * Selected LOS/SD select
1313 #define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_MASK 0x00000030
1314 #define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_SHIFT 4
1316 * Selected LOS/SD select
1322 #define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_MASK 0x00000300
1323 #define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_SHIFT 8
1325 * Selected LOS/SD select
1331 #define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_MASK 0x00003000
1332 #define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_SHIFT 12
1334 /**** rgmii_sel register ****/
1335 /* Swap [3:0] input with [7:4] */
1336 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_3_0 (1 << 0)
1337 /* Swap [4] input with [9] */
1338 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_4 (1 << 1)
1339 /* Swap [7:4] input with [3:0] */
1340 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_7_3 (1 << 2)
1341 /* Swap [9] input with [4] */
1342 #define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_9 (1 << 3)
1343 /* Swap [3:0] input with [7:4] */
1344 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_3_0 (1 << 4)
1345 /* Swap [4] input with [9] */
1346 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_4 (1 << 5)
1347 /* Swap [7:4] input with [3:0] */
1348 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_7_3 (1 << 6)
1349 /* Swap [9] input with [4] */
1350 #define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_9 (1 << 7)
1352 /**** led_cfg register ****/
1354 * LED source selection:
1358 * 3 – Rx | Tx activity
1361 #define ETH_MAC_GEN_LED_CFG_SEL_MASK 0x0000000F
1362 #define ETH_MAC_GEN_LED_CFG_SEL_SHIFT 0
1364 /* turn the led on/off based on default value field (ETH_MAC_GEN_LED_CFG_DEF) */
1365 #define ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG 0
1366 #define ETH_MAC_GEN_LED_CFG_SEL_RX_ACTIVITY_DEPRECIATED 1
1367 #define ETH_MAC_GEN_LED_CFG_SEL_TX_ACTIVITY_DEPRECIATED 2
1368 #define ETH_MAC_GEN_LED_CFG_SEL_RX_TX_ACTIVITY_DEPRECIATED 3
1369 #define ETH_MAC_GEN_LED_CFG_SEL_LINK_ACTIVITY 10
1371 /* LED default value */
1372 #define ETH_MAC_GEN_LED_CFG_DEF (1 << 4)
1373 /* LED signal polarity */
1374 #define ETH_MAC_GEN_LED_CFG_POL (1 << 5)
1376 * activity timer (MSB)
1377 * 32 bit timer @SB clock
1379 #define ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK 0x00FF0000
1380 #define ETH_MAC_GEN_LED_CFG_ACT_TIMER_SHIFT 16
1382 * activity timer (MSB)
1383 * 32 bit timer @SB clock
1385 #define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK 0xFF000000
1386 #define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_SHIFT 24
1388 /**** pcs_addr register ****/
1390 #define ETH_MAC_KR_PCS_ADDR_VAL_MASK 0x0000FFFF
1391 #define ETH_MAC_KR_PCS_ADDR_VAL_SHIFT 0
1393 /**** pcs_data register ****/
1395 #define ETH_MAC_KR_PCS_DATA_VAL_MASK 0x0000FFFF
1396 #define ETH_MAC_KR_PCS_DATA_VAL_SHIFT 0
1398 /**** an_addr register ****/
1400 #define ETH_MAC_KR_AN_ADDR_VAL_MASK 0x0000FFFF
1401 #define ETH_MAC_KR_AN_ADDR_VAL_SHIFT 0
1403 /**** an_data register ****/
1405 #define ETH_MAC_KR_AN_DATA_VAL_MASK 0x0000FFFF
1406 #define ETH_MAC_KR_AN_DATA_VAL_SHIFT 0
1408 /**** pma_addr register ****/
1410 #define ETH_MAC_KR_PMA_ADDR_VAL_MASK 0x0000FFFF
1411 #define ETH_MAC_KR_PMA_ADDR_VAL_SHIFT 0
1413 /**** pma_data register ****/
1415 #define ETH_MAC_KR_PMA_DATA_VAL_MASK 0x0000FFFF
1416 #define ETH_MAC_KR_PMA_DATA_VAL_SHIFT 0
1418 /**** mtip_addr register ****/
1420 #define ETH_MAC_KR_MTIP_ADDR_VAL_MASK 0x0000FFFF
1421 #define ETH_MAC_KR_MTIP_ADDR_VAL_SHIFT 0
1423 /**** mtip_data register ****/
1425 #define ETH_MAC_KR_MTIP_DATA_VAL_MASK 0x0000FFFF
1426 #define ETH_MAC_KR_MTIP_DATA_VAL_SHIFT 0
1428 /**** pcs_cfg register ****/
1429 /* Enable Auto-Negotiation after Reset */
1430 #define ETH_MAC_KR_PCS_CFG_STRAP_AN_ENA (1 << 0)
1432 * Signal detect selector for the EEE
1433 * 0 – Register default value
1436 #define ETH_MAC_KR_PCS_CFG_EEE_SD_SEL (1 << 4)
1437 /* Signal detect default value for the EEE */
1438 #define ETH_MAC_KR_PCS_CFG_EEE_DEF_VAL (1 << 5)
1439 /* Signal detect polarity reversal for the EEE */
1440 #define ETH_MAC_KR_PCS_CFG_EEE_SD_POL (1 << 6)
1441 /* EEE timer value */
1442 #define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK 0x0000FF00
1443 #define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT 8
1445 * Selects source for the enable SerDes DME signal
1446 * 0 – Register value
1449 #define ETH_MAC_KR_PCS_CFG_DME_SEL (1 << 16)
1450 /* DME default value */
1451 #define ETH_MAC_KR_PCS_CFG_DME_VAL (1 << 17)
1452 /* DME default polarity reversal when selecting PCS output */
1453 #define ETH_MAC_KR_PCS_CFG_DME_POL (1 << 18)
1455 /**** pcs_stat register ****/
1456 /* Link enable by the Auto-Negotiation */
1457 #define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_MASK 0x0000003F
1458 #define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_SHIFT 0
1460 #define ETH_MAC_KR_PCS_STAT_BLOCK_LOCK (1 << 8)
1462 #define ETH_MAC_KR_PCS_STAT_HI_BER (1 << 9)
1464 #define ETH_MAC_KR_PCS_STAT_RX_WAKE_ERR (1 << 16)
1466 #define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_ALERT (1 << 17)
1468 #define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_QUIET (1 << 18)
1470 #define ETH_MAC_KR_PCS_STAT_PMA_RXMODE_QUIET (1 << 19)
1472 #define ETH_MAC_KR_PCS_STAT_RX_LPI_ACTIVE (1 << 20)
1474 #define ETH_MAC_KR_PCS_STAT_TX_LPI_ACTIVE (1 << 21)
1476 /**** reg_addr register ****/
1478 #define ETH_MAC_SGMII_REG_ADDR_VAL_MASK 0x0000001F
1479 #define ETH_MAC_SGMII_REG_ADDR_VAL_SHIFT 0
1481 #define ETH_MAC_SGMII_REG_ADDR_CTRL_REG 0x0
1482 #define ETH_MAC_SGMII_REG_ADDR_IF_MODE_REG 0x14
1484 /**** reg_data register ****/
1486 #define ETH_MAC_SGMII_REG_DATA_VAL_MASK 0x0000FFFF
1487 #define ETH_MAC_SGMII_REG_DATA_VAL_SHIFT 0
1489 #define ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE (1 << 12)
1490 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_EN (1 << 0)
1491 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_AN (1 << 1)
1492 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_MASK 0xC
1493 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_SHIFT 2
1494 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_10 0x0
1495 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_100 0x1
1496 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_1000 0x2
1497 #define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_DUPLEX (1 << 4)
1499 /**** clk_div register ****/
1500 /* Value for 1000M selection */
1501 #define ETH_MAC_SGMII_CLK_DIV_VAL_1000_MASK 0x000000FF
1502 #define ETH_MAC_SGMII_CLK_DIV_VAL_1000_SHIFT 0
1503 /* Value for 100M selection */
1504 #define ETH_MAC_SGMII_CLK_DIV_VAL_100_MASK 0x0000FF00
1505 #define ETH_MAC_SGMII_CLK_DIV_VAL_100_SHIFT 8
1506 /* Value for 10M selection */
1507 #define ETH_MAC_SGMII_CLK_DIV_VAL_10_MASK 0x00FF0000
1508 #define ETH_MAC_SGMII_CLK_DIV_VAL_10_SHIFT 16
1509 /* Bypass PCS selection */
1510 #define ETH_MAC_SGMII_CLK_DIV_BYPASS (1 << 24)
1512 * Divider selection when bypass field is '1', one hot
1517 #define ETH_MAC_SGMII_CLK_DIV_SEL_MASK 0x0E000000
1518 #define ETH_MAC_SGMII_CLK_DIV_SEL_SHIFT 25
1520 /**** link_stat register ****/
1522 #define ETH_MAC_SGMII_LINK_STAT_SET_1000 (1 << 0)
1524 #define ETH_MAC_SGMII_LINK_STAT_SET_100 (1 << 1)
1526 #define ETH_MAC_SGMII_LINK_STAT_SET_10 (1 << 2)
1528 #define ETH_MAC_SGMII_LINK_STAT_LED_AN (1 << 3)
1530 #define ETH_MAC_SGMII_LINK_STAT_HD_ENA (1 << 4)
1532 #define ETH_MAC_SGMII_LINK_STAT_LED_LINK (1 << 5)
1534 /**** afifo_ctrl register ****/
1535 /* enable tx input operation */
1536 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_IN (1 << 0)
1537 /* enable tx output operation */
1538 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_OUT (1 << 1)
1539 /* enable rx input operation */
1540 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_IN (1 << 4)
1541 /* enable rx output operation */
1542 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_OUT (1 << 5)
1543 /* enable tx FIFO input operation */
1544 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_IN (1 << 8)
1545 /* enable tx FIFO output operation */
1546 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_OUT (1 << 9)
1547 /* enable rx FIFO input operation */
1548 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_IN (1 << 12)
1549 /* enable rx FIFO output operation */
1550 #define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_OUT (1 << 13)
1552 /**** tx_afifo_cfg_1 register ****/
1553 /* minimum packet size configuration */
1554 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF
1555 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0
1557 /**** tx_afifo_cfg_2 register ****/
1558 /* maximum packet size configuration */
1559 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF
1560 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0
1562 /**** tx_afifo_cfg_3 register ****/
1563 /* input bus width */
1564 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF
1565 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0
1566 /* input bus width divide factor */
1567 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000
1568 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16
1570 /**** tx_afifo_cfg_4 register ****/
1571 /* output bus width */
1572 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF
1573 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0
1574 /* output bus width divide factor */
1575 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000
1576 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16
1578 /**** tx_afifo_cfg_5 register ****/
1580 * determines if the input bus is valid/read or “write enable”.
1584 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0)
1586 * determines if the output bus is valid/read or “write enable”.
1590 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1)
1591 /* Swap input bus bytes */
1592 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4)
1593 /* Swap output bus bytes */
1594 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5)
1596 * output clock select
1598 * 1 – clk_mac_sys_clk
1600 #define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_CLK_SEL (1 << 8)
1602 /**** rx_afifo_cfg_1 register ****/
1603 /* minimum packet size configuration */
1604 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF
1605 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0
1607 /**** rx_afifo_cfg_2 register ****/
1608 /* maximum packet size configuration */
1609 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF
1610 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0
1612 /**** rx_afifo_cfg_3 register ****/
1613 /* input bus width */
1614 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF
1615 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0
1616 /* input bus width divide factor */
1617 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000
1618 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16
1620 /**** rx_afifo_cfg_4 register ****/
1621 /* output bus width */
1622 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF
1623 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0
1624 /* output bus width divide factor */
1625 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000
1626 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16
1628 /**** rx_afifo_cfg_5 register ****/
1630 * determines if the input bus is valid/read or “write enable”.
1634 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0)
1636 * determines if the output bus is valid/read or “write enable”.
1640 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1)
1641 /* Swap input bus bytes */
1642 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4)
1643 /* Swap output bus bytes */
1644 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5)
1646 * input clock select
1648 * 1 – clk_serdes_int_0_tx_dword_ref
1649 * 2 – clk_mac_sys_clk
1652 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_MASK 0x00000300
1653 #define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_SHIFT 8
1655 /**** mac_sel register ****/
1657 * Select the MAC that is connected to the SGMII PCS.
1661 #define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_SGMII (1 << 0)
1663 * Select between the 10G and 40G MAC
1667 #define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_40G (1 << 4)
1669 /**** mac_10g_ll_cfg register ****/
1671 * select between 10G (KR PCS) and 1G (SGMII) mode.
1675 #define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MODE_1G (1 << 0)
1676 /* enable Magic packet detection in the MAC (all other packets are dropped) */
1677 #define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MAGIC_ENA (1 << 5)
1679 /**** mac_10g_ll_ctrl register ****/
1680 /* Force the MAC to stop TX transmission after low power mode. */
1681 #define ETH_MAC_GEN_V3_MAC_10G_LL_CTRL_LPI_TXHOLD (1 << 0)
1683 /**** pcs_10g_ll_cfg register ****/
1685 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX (1 << 0)
1687 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX (1 << 1)
1689 * RX FEC error propagation enable,
1692 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_ERR_ENA (1 << 2)
1694 * Gearbox configuration:
1700 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_MASK 0x00000030
1701 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_SHIFT 4
1703 * Gearbox configuration:
1709 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_MASK 0x000000C0
1710 #define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_SHIFT 6
1712 /**** pcs_10g_ll_status register ****/
1713 /* FEC locked indication */
1714 #define ETH_MAC_GEN_V3_PCS_10G_LL_STATUS_FEC_LOCKED (1 << 0)
1716 /**** pcs_40g_ll_cfg register ****/
1718 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_MASK 0x0000000F
1719 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_SHIFT 0
1721 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_MASK 0x000000F0
1722 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_SHIFT 4
1724 * RX FEC error propagation enable,
1727 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_MASK 0x00000F00
1728 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_SHIFT 8
1730 * SERDES width, 16 bit enable
1734 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_SD_16B (1 << 12)
1736 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC91_ENA (1 << 13)
1738 * PHY LOS indication selection
1739 * 00 - Select register value from phy_los_def
1740 * 01 - Select input from the SerDes
1741 * 10 - Select input from GPIO
1742 * 11 - Select inverted input from GPIO
1744 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00030000
1745 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_SHIFT 16
1746 /* PHY LOS default value */
1747 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_DEF (1 << 18)
1748 /* PHY LOS polarity */
1749 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_POL (1 << 19)
1751 * Energy detect indication selection
1752 * 00 - Select register value from phy_los_def
1753 * 01 - Select input from the SerDes
1754 * 10 - Select input from GPIO
1755 * 11 - Select inverted input from GPIO
1757 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_MASK 0x00300000
1758 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_SHIFT 20
1759 /* Energy detect default value */
1760 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_DEF (1 << 22)
1761 /* Energy detect polarity */
1762 #define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_POL (1 << 23)
1764 /**** pcs_40g_ll_status register ****/
1766 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_MASK 0x0000000F
1767 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_SHIFT 0
1769 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_ALIGN_DONE (1 << 4)
1771 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_HIGH_BER (1 << 8)
1772 /* FEC locked indication */
1773 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_MASK 0x0000F000
1774 #define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_SHIFT 12
1776 /**** pcs_40g_ll_addr register ****/
1778 #define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_MASK 0x0001FFFF
1779 #define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_SHIFT 0
1781 /**** pcs_40g_ll_data register ****/
1783 #define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_MASK 0x0000FFFF
1784 #define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_SHIFT 0
1786 /**** mac_40g_ll_cfg register ****/
1787 /* change TX CRC polarity */
1788 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_SWAP_FF_TX_CRC (1 << 0)
1789 /* force TX remote fault */
1790 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_REM_FAULT (1 << 4)
1791 /* force TX local fault */
1792 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LOC_FAULT (1 << 5)
1793 /* force TX Link fault */
1794 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LI_FAULT (1 << 6)
1796 * PHY LOS indication selection
1797 * 00 - Select register value from phy_los_def
1798 * 01 - Select input from the SerDes
1799 * 10 - Select input from GPIO
1800 * 11 - Select inverted input from GPIO
1802 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00000300
1803 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_SHIFT 8
1804 /* PHY LOS default value */
1805 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_DEF (1 << 10)
1806 /* PHY LOS polarity */
1807 #define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_POL (1 << 11)
1809 /**** mac_40g_ll_status register ****/
1810 /* pause on indication */
1811 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_MASK 0x000000FF
1812 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_SHIFT 0
1813 /* local fault indication received */
1814 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT (1 << 8)
1815 /* remote fault indication received */
1816 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT (1 << 9)
1817 /* Link fault indication */
1818 #define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LI_FAULT (1 << 10)
1820 /**** preamble_cfg_high register ****/
1821 /* preamble value */
1822 #define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_MASK 0x00FFFFFF
1823 #define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_SHIFT 0
1825 /**** mac_40g_ll_addr register ****/
1827 #define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_MASK 0x000003FF
1828 #define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_SHIFT 0
1830 /**** mac_40g_ll_ctrl register ****/
1831 /* Force the MAC to stop TX transmission after low power mode. */
1832 #define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_LPI_TXHOLD (1 << 0)
1834 #define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_REG_LOWP_ENA (1 << 1)
1836 /**** pcs_40g_fec_91_ll_addr register ****/
1838 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_MASK 0x000001FF
1839 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_SHIFT 0
1841 /**** pcs_40g_fec_91_ll_data register ****/
1843 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_MASK 0x0000FFFF
1844 #define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_SHIFT 0
1846 /**** pcs_40g_ll_eee_cfg register ****/
1847 /* Low power timer configuration */
1848 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK 0x000000FF
1849 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT 0
1850 /* Low power Fast wake */
1851 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_LPI_FW (1 << 8)
1853 /**** pcs_40g_ll_eee_status register ****/
1855 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_MASK 0x00000003
1856 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_SHIFT 0
1858 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_MASK 0x00000070
1859 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_SHIFT 4
1861 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_MODE (1 << 8)
1863 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_MASK 0x00007000
1864 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_SHIFT 12
1866 #define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_ACTIVE (1 << 15)
1868 /**** serdes_32_tx_shift register ****/
1870 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_MASK 0x0000001F
1871 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_SHIFT 0
1873 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_MASK 0x000003E0
1874 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_SHIFT 5
1876 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_MASK 0x00007C00
1877 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_SHIFT 10
1879 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_MASK 0x000F8000
1880 #define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_SHIFT 15
1882 /**** serdes_32_rx_shift register ****/
1884 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_MASK 0x0000001F
1885 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_SHIFT 0
1887 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_MASK 0x000003E0
1888 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_SHIFT 5
1890 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_MASK 0x00007C00
1891 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_SHIFT 10
1893 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_MASK 0x000F8000
1894 #define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_SHIFT 15
1896 /**** serdes_32_tx_sel register ****/
1898 * 0 – directly from serdes
1900 * 2 – swapped with shift
1901 * 3 - legacy (based on gen cfg register)
1903 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_MASK 0x00000003
1904 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_SHIFT 0
1906 * 0 – directly from serdes
1908 * 2 – swapped with shift
1909 * 3 - legacy (based on gen cfg register)
1911 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_MASK 0x00000030
1912 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_SHIFT 4
1914 * 0 – directly from serdes
1916 * 2 – swapped with shift
1917 * 3 - legacy (based on gen cfg register)
1919 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_MASK 0x00000300
1920 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_SHIFT 8
1922 * 0 – directly from serdes
1924 * 2 – swapped with shift
1925 * 3 - legacy (based on gen cfg register)
1927 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_MASK 0x00003000
1928 #define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_SHIFT 12
1930 /**** serdes_32_rx_sel register ****/
1932 * 0 – directly from serdes
1934 * 2 – swapped with shift
1935 * 3 - legacy (based on gen cfg register)
1937 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_MASK 0x00000003
1938 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_SHIFT 0
1940 * 0 – directly from serdes
1942 * 2 – swapped with shift
1943 * 3 - legacy (based on gen cfg register)
1945 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_MASK 0x00000030
1946 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_SHIFT 4
1948 * 0 – directly from serdes
1950 * 2 – swapped with shift
1951 * 3 - legacy (based on gen cfg register)
1953 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_MASK 0x00000300
1954 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_SHIFT 8
1956 * 0 – directly from serdes
1958 * 2 – swapped with shift
1959 * 3 - legacy (based on gen cfg register)
1961 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_MASK 0x00003000
1962 #define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_SHIFT 12
1964 /**** an_lt_ctrl register ****/
1965 /* reset lane [3:0] */
1966 #define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_MASK 0x0000000F
1967 #define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_SHIFT 0
1969 /* PHY LOS indication input selection
1973 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_0 (1 << 8)
1974 /* PHY LOS indication input selection
1978 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_1 (1 << 9)
1979 /* PHY LOS indication input selection
1983 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_2 (1 << 10)
1984 /* PHY LOS indication input selection
1988 #define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_3 (1 << 11)
1990 /**** an_lt_0_addr register ****/
1992 #define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_MASK 0x0000FFFF
1993 #define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_SHIFT 0
1995 /**** an_lt_1_addr register ****/
1997 #define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_MASK 0x0000FFFF
1998 #define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_SHIFT 0
2000 /**** an_lt_2_addr register ****/
2002 #define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_MASK 0x0000FFFF
2003 #define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_SHIFT 0
2005 /**** an_lt_3_addr register ****/
2007 #define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_MASK 0x0000FFFF
2008 #define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_SHIFT 0
2010 /**** ext_serdes_ctrl register ****/
2012 * Lane 0, SERDES selection:
2013 * 0 – 10G SERDES, lane 0
2014 * 1 – 25G SERDES, lane 0
2016 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_SEL_25_10 (1 << 0)
2018 * Lane 1, SERDES selection:
2019 * 0 – 10G SERDES, lane 1
2020 * 1 – 25G SERDES, lane 1
2022 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_SEL_25_10 (1 << 1)
2024 * Lane 2, SERDES selection:
2025 * 0 – 10G SERDES, lane 2
2026 * 1 – 25G SERDES, lane 0
2028 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_2_SEL_25_10 (1 << 2)
2030 * Lane 3, SERDES selection:
2031 * 0 – 10G SERDES, lane 3
2032 * 1 – 25G SERDES, lane 1
2034 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_3_SEL_25_10 (1 << 3)
2036 /* Lane 0 Rx, 25G 40bit-32bit gearshitf sw reset */
2037 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_RX_25_GS_SW_RESET (1 << 4)
2038 /* Lane 0 Tx, 25G 40bit-32bit gearshitf sw reset */
2039 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_TX_25_GS_SW_RESET (1 << 5)
2040 /* Lane 1 Rx, 25G 40bit-32bit gearshitf sw reset */
2041 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_RX_25_GS_SW_RESET (1 << 6)
2042 /* Lane 1 Tx, 25G 40bit-32bit gearshitf sw reset */
2043 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_TX_25_GS_SW_RESET (1 << 7)
2044 /* SerDes 25G gear shift Tx lane selector */
2045 #define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_SRDS25_GS_TX_LANE_CLK_SEL (1 << 8)
2047 /*** MAC Core registers addresses ***/
2048 /* command config */
2049 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR 0x00000008
2050 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA (1 << 0)
2051 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA (1 << 1)
2052 #define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_PFC_MODE (1 << 19)
2055 #define ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR 0x00000014
2057 #define ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR 0x00000054
2058 #define ETH_MAC_GEN_V3_MAC_40G_CL23_PAUSE_QUANTA_ADDR 0x00000058
2059 #define ETH_MAC_GEN_V3_MAC_40G_CL45_PAUSE_QUANTA_ADDR 0x0000005C
2060 #define ETH_MAC_GEN_V3_MAC_40G_CL67_PAUSE_QUANTA_ADDR 0x00000060
2061 #define ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR 0x00000064
2062 #define ETH_MAC_GEN_V3_MAC_40G_CL23_QUANTA_THRESH_ADDR 0x00000068
2063 #define ETH_MAC_GEN_V3_MAC_40G_CL45_QUANTA_THRESH_ADDR 0x0000006C
2064 #define ETH_MAC_GEN_V3_MAC_40G_CL67_QUANTA_THRESH_ADDR 0x00000070
2067 #define ETH_MAC_GEN_V3_SPARE_CHICKEN_DISABLE_TIMESTAMP_STRETCH (1 << 0)
2069 /*** PCS Core registers addresses ***/
2070 /* 40g control/status */
2071 #define ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR 0x00000000
2072 /* 40g EEE control and capability */
2073 #define ETH_MAC_GEN_V3_PCS_40G_EEE_CONTROL_ADDR 0x00000028
2075 #define ETH_MAC_KR_PCS_CONTROL_1_ADDR 0x00000000
2077 #define ETH_MAC_KR_PCS_BASE_R_STATUS2 0x00000021
2079 #define ETH_MAC_KR_AN_MILLISECONDS_COUNTER_ADDR 0x00008000
2080 #define ETH_MAC_AN_LT_MILLISECONDS_COUNTER_ADDR 0x00000020
2086 #endif /* __AL_HAL_ETH_MAC_REGS_H__ */
2088 /** @} end of Ethernet group */