1 /******************************************************************************
3 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
5 *****************************************************************************/
7 /******************************************************************************
11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp.
12 * All rights reserved.
16 * 2.1. This is your license from Intel Corp. under its intellectual property
17 * rights. You may have additional license terms from the party that provided
18 * you this software, covering your right to use that party's intellectual
21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
22 * copy of the source code appearing in this file ("Covered Code") an
23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the
24 * base code distributed originally by Intel ("Original Intel Code") to copy,
25 * make derivatives, distribute, use and display any portion of the Covered
26 * Code in any form, with the right to sublicense such rights; and
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
29 * license (with the right to sublicense), under only those claims of Intel
30 * patents that are infringed by the Original Intel Code, to make, use, sell,
31 * offer to sell, and import the Covered Code and derivative works thereof
32 * solely to the minimum extent necessary to exercise the above copyright
33 * license, and in no event shall the patent license extend to any additions
34 * to or modifications of the Original Intel Code. No other license or right
35 * is granted directly or by implication, estoppel or otherwise;
37 * The above copyright and patent license is granted only if the following
42 * 3.1. Redistribution of Source with Rights to Further Distribute Source.
43 * Redistribution of source code of any substantial portion of the Covered
44 * Code or modification with rights to further distribute source must include
45 * the above Copyright Notice, the above License, this list of Conditions,
46 * and the following Disclaimer and Export Compliance provision. In addition,
47 * Licensee must cause all Covered Code to which Licensee contributes to
48 * contain a file documenting the changes Licensee made to create that Covered
49 * Code and the date of any change. Licensee must include in that file the
50 * documentation of any changes made by any predecessor Licensee. Licensee
51 * must include a prominent statement that the modification is derived,
52 * directly or indirectly, from Original Intel Code.
54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source.
55 * Redistribution of source code of any substantial portion of the Covered
56 * Code or modification without rights to further distribute source must
57 * include the following Disclaimer and Export Compliance provision in the
58 * documentation and/or other materials provided with distribution. In
59 * addition, Licensee may not authorize further sublicense of source of any
60 * portion of the Covered Code, and must include terms to the effect that the
61 * license from Licensee to its licensee is limited to the intellectual
62 * property embodied in the software Licensee provides to its licensee, and
63 * not to intellectual property embodied in modifications its licensee may
66 * 3.3. Redistribution of Executable. Redistribution in executable form of any
67 * substantial portion of the Covered Code or modification must reproduce the
68 * above Copyright Notice, and the following Disclaimer and Export Compliance
69 * provision in the documentation and/or other materials provided with the
72 * 3.4. Intel retains all right, title, and interest in and to the Original
75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by
76 * Intel shall be used in advertising or otherwise to promote the sale, use or
77 * other dealings in products derived from or relating to the Covered Code
78 * without prior written authorization from Intel.
80 * 4. Disclaimer and Export Compliance
82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
99 * 4.3. Licensee shall not export, either directly or indirectly, any of this
100 * software or system incorporating such software without first obtaining any
101 * required license or other approval from the U. S. Department of Commerce or
102 * any other agency or department of the United States Government. In the
103 * event Licensee exports any such software from the United States or
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
106 * compliance with all laws, regulations, orders, or other restrictions of the
107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor
108 * any of its subsidiaries will export/re-export any technical data, process,
109 * software, or service, directly or indirectly, to any country for which the
110 * United States government or any agency thereof requires an export license,
111 * other governmental approval, or letter of assurance, without first obtaining
112 * such license, approval or letter.
114 *****************************************************************************
116 * Alternatively, you may choose to be licensed under the terms of the
119 * Redistribution and use in source and binary forms, with or without
120 * modification, are permitted provided that the following conditions
122 * 1. Redistributions of source code must retain the above copyright
123 * notice, this list of conditions, and the following disclaimer,
124 * without modification.
125 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
126 * substantially similar to the "NO WARRANTY" disclaimer below
127 * ("Disclaimer") and any redistribution must be conditioned upon
128 * including a substantially similar Disclaimer requirement for further
129 * binary redistribution.
130 * 3. Neither the names of the above-listed copyright holders nor the names
131 * of any contributors may be used to endorse or promote products derived
132 * from this software without specific prior written permission.
134 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
135 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
136 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
137 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
138 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
139 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
140 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
141 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
142 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
143 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
144 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
146 * Alternatively, you may choose to be licensed under the terms of the
147 * GNU General Public License ("GPL") version 2 as published by the Free
148 * Software Foundation.
150 *****************************************************************************/
156 /*******************************************************************************
158 * Additional ACPI Tables (2)
160 * These tables are not consumed directly by the ACPICA subsystem, but are
161 * included here to support device drivers and the AML disassembler.
163 ******************************************************************************/
167 * Values for description table header signatures for tables defined in this
168 * file. Useful because they make it more difficult to inadvertently type in
169 * the wrong signature.
171 #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */
172 #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */
173 #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */
174 #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */
175 #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */
176 #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */
177 #define ACPI_SIG_MPST "MPST" /* Memory Power State Table */
178 #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */
179 #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */
180 #define ACPI_SIG_MTMR "MTMR" /* MID Timer table */
181 #define ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */
182 #define ACPI_SIG_PCCT "PCCT" /* Platform Communications Channel Table */
183 #define ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */
184 #define ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */
185 #define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */
186 #define ACPI_SIG_RASF "RASF" /* RAS Feature table */
187 #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */
188 #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */
189 #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */
193 * All tables must be byte-packed to match the ACPI specification, since
194 * the tables are provided by the system BIOS.
199 * Note: C bitfields are not used for this reason:
201 * "Bitfields are great and easy to read, but unfortunately the C language
202 * does not specify the layout of bitfields in memory, which means they are
203 * essentially useless for dealing with packed data in on-disk formats or
204 * binary wire protocols." (Or ACPI tables and buffers.) "If you ask me,
205 * this decision was a design error in C. Ritchie could have picked an order
206 * and stuck with it." Norman Ramsey.
207 * See http://stackoverflow.com/a/1053662/41661
211 /*******************************************************************************
213 * IORT - IO Remapping Table
215 * Conforms to "IO Remapping Table System Software on ARM Platforms",
216 * Document number: ARM DEN 0049D, March 2018
218 ******************************************************************************/
220 typedef struct acpi_table_iort
222 ACPI_TABLE_HEADER Header;
233 typedef struct acpi_iort_node
240 UINT32 MappingOffset;
245 /* Values for subtable Type above */
247 enum AcpiIortNodeType
249 ACPI_IORT_NODE_ITS_GROUP = 0x00,
250 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
251 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
252 ACPI_IORT_NODE_SMMU = 0x03,
253 ACPI_IORT_NODE_SMMU_V3 = 0x04,
254 ACPI_IORT_NODE_PMCG = 0x05
258 typedef struct acpi_iort_id_mapping
260 UINT32 InputBase; /* Lowest value in input range */
261 UINT32 IdCount; /* Number of IDs */
262 UINT32 OutputBase; /* Lowest value in output range */
263 UINT32 OutputReference; /* A reference to the output node */
266 } ACPI_IORT_ID_MAPPING;
268 /* Masks for Flags field above for IORT subtable */
270 #define ACPI_IORT_ID_SINGLE_MAPPING (1)
273 typedef struct acpi_iort_memory_access
275 UINT32 CacheCoherency;
280 } ACPI_IORT_MEMORY_ACCESS;
282 /* Values for CacheCoherency field above */
284 #define ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */
285 #define ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */
287 /* Masks for Hints field above */
289 #define ACPI_IORT_HT_TRANSIENT (1)
290 #define ACPI_IORT_HT_WRITE (1<<1)
291 #define ACPI_IORT_HT_READ (1<<2)
292 #define ACPI_IORT_HT_OVERRIDE (1<<3)
294 /* Masks for MemoryFlags field above */
296 #define ACPI_IORT_MF_COHERENCY (1)
297 #define ACPI_IORT_MF_ATTRIBUTES (1<<1)
301 * IORT node specific subtables
303 typedef struct acpi_iort_its_group
306 UINT32 Identifiers[1]; /* GIC ITS identifier arrary */
308 } ACPI_IORT_ITS_GROUP;
311 typedef struct acpi_iort_named_component
314 UINT64 MemoryProperties; /* Memory access properties */
315 UINT8 MemoryAddressLimit; /* Memory address size limit */
316 char DeviceName[1]; /* Path of namespace object */
318 } ACPI_IORT_NAMED_COMPONENT;
320 /* Masks for Flags field above */
322 #define ACPI_IORT_NC_STALL_SUPPORTED (1)
323 #define ACPI_IORT_NC_PASID_BITS (31<<1)
325 typedef struct acpi_iort_root_complex
327 UINT64 MemoryProperties; /* Memory access properties */
329 UINT32 PciSegmentNumber;
330 UINT8 MemoryAddressLimit; /* Memory address size limit */
331 UINT8 Reserved[3]; /* Reserved, must be zero */
333 } ACPI_IORT_ROOT_COMPLEX;
335 /* Values for AtsAttribute field above */
337 #define ACPI_IORT_ATS_SUPPORTED 0x00000001 /* The root complex supports ATS */
338 #define ACPI_IORT_ATS_UNSUPPORTED 0x00000000 /* The root complex doesn't support ATS */
341 typedef struct acpi_iort_smmu
343 UINT64 BaseAddress; /* SMMU base address */
344 UINT64 Span; /* Length of memory range */
347 UINT32 GlobalInterruptOffset;
348 UINT32 ContextInterruptCount;
349 UINT32 ContextInterruptOffset;
350 UINT32 PmuInterruptCount;
351 UINT32 PmuInterruptOffset;
352 UINT64 Interrupts[1]; /* Interrupt array */
356 /* Values for Model field above */
358 #define ACPI_IORT_SMMU_V1 0x00000000 /* Generic SMMUv1 */
359 #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */
360 #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */
361 #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */
362 #define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */
363 #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium ThunderX SMMUv2 */
365 /* Masks for Flags field above */
367 #define ACPI_IORT_SMMU_DVM_SUPPORTED (1)
368 #define ACPI_IORT_SMMU_COHERENT_WALK (1<<1)
370 /* Global interrupt format */
372 typedef struct acpi_iort_smmu_gsi
377 UINT32 NSgCfgIrptFlags;
379 } ACPI_IORT_SMMU_GSI;
382 typedef struct acpi_iort_smmu_v3
384 UINT64 BaseAddress; /* SMMUv3 base address */
394 UINT32 IdMappingIndex;
398 /* Values for Model field above */
400 #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */
401 #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* HiSilicon Hi161x SMMUv3 */
402 #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */
404 /* Masks for Flags field above */
406 #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
407 #define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1)
408 #define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3)
410 typedef struct acpi_iort_pmcg
412 UINT64 Page0BaseAddress;
414 UINT32 NodeReference;
415 UINT64 Page1BaseAddress;
420 /*******************************************************************************
422 * IVRS - I/O Virtualization Reporting Structure
425 * Conforms to "AMD I/O Virtualization Technology (IOMMU) Specification",
426 * Revision 1.26, February 2009.
428 ******************************************************************************/
430 typedef struct acpi_table_ivrs
432 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
433 UINT32 Info; /* Common virtualization info */
438 /* Values for Info field above */
440 #define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */
441 #define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */
442 #define ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */
445 /* IVRS subtable header */
447 typedef struct acpi_ivrs_header
449 UINT8 Type; /* Subtable type */
451 UINT16 Length; /* Subtable length */
452 UINT16 DeviceId; /* ID of IOMMU */
456 /* Values for subtable Type above */
460 ACPI_IVRS_TYPE_HARDWARE = 0x10,
461 ACPI_IVRS_TYPE_MEMORY1 = 0x20,
462 ACPI_IVRS_TYPE_MEMORY2 = 0x21,
463 ACPI_IVRS_TYPE_MEMORY3 = 0x22
466 /* Masks for Flags field above for IVHD subtable */
468 #define ACPI_IVHD_TT_ENABLE (1)
469 #define ACPI_IVHD_PASS_PW (1<<1)
470 #define ACPI_IVHD_RES_PASS_PW (1<<2)
471 #define ACPI_IVHD_ISOC (1<<3)
472 #define ACPI_IVHD_IOTLB (1<<4)
474 /* Masks for Flags field above for IVMD subtable */
476 #define ACPI_IVMD_UNITY (1)
477 #define ACPI_IVMD_READ (1<<1)
478 #define ACPI_IVMD_WRITE (1<<2)
479 #define ACPI_IVMD_EXCLUSION_RANGE (1<<3)
483 * IVRS subtables, correspond to Type in ACPI_IVRS_HEADER
486 /* 0x10: I/O Virtualization Hardware Definition Block (IVHD) */
488 typedef struct acpi_ivrs_hardware
490 ACPI_IVRS_HEADER Header;
491 UINT16 CapabilityOffset; /* Offset for IOMMU control fields */
492 UINT64 BaseAddress; /* IOMMU control registers */
493 UINT16 PciSegmentGroup;
494 UINT16 Info; /* MSI number and unit ID */
497 } ACPI_IVRS_HARDWARE;
499 /* Masks for Info field above */
501 #define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */
502 #define ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, UnitID */
506 * Device Entries for IVHD subtable, appear after ACPI_IVRS_HARDWARE structure.
507 * Upper two bits of the Type field are the (encoded) length of the structure.
508 * Currently, only 4 and 8 byte entries are defined. 16 and 32 byte entries
509 * are reserved for future use but not defined.
511 typedef struct acpi_ivrs_de_header
517 } ACPI_IVRS_DE_HEADER;
519 /* Length of device entry is in the top two bits of Type field above */
521 #define ACPI_IVHD_ENTRY_LENGTH 0xC0
523 /* Values for device entry Type field above */
525 enum AcpiIvrsDeviceEntryType
527 /* 4-byte device entries, all use ACPI_IVRS_DEVICE4 */
529 ACPI_IVRS_TYPE_PAD4 = 0,
530 ACPI_IVRS_TYPE_ALL = 1,
531 ACPI_IVRS_TYPE_SELECT = 2,
532 ACPI_IVRS_TYPE_START = 3,
533 ACPI_IVRS_TYPE_END = 4,
535 /* 8-byte device entries */
537 ACPI_IVRS_TYPE_PAD8 = 64,
538 ACPI_IVRS_TYPE_NOT_USED = 65,
539 ACPI_IVRS_TYPE_ALIAS_SELECT = 66, /* Uses ACPI_IVRS_DEVICE8A */
540 ACPI_IVRS_TYPE_ALIAS_START = 67, /* Uses ACPI_IVRS_DEVICE8A */
541 ACPI_IVRS_TYPE_EXT_SELECT = 70, /* Uses ACPI_IVRS_DEVICE8B */
542 ACPI_IVRS_TYPE_EXT_START = 71, /* Uses ACPI_IVRS_DEVICE8B */
543 ACPI_IVRS_TYPE_SPECIAL = 72 /* Uses ACPI_IVRS_DEVICE8C */
546 /* Values for Data field above */
548 #define ACPI_IVHD_INIT_PASS (1)
549 #define ACPI_IVHD_EINT_PASS (1<<1)
550 #define ACPI_IVHD_NMI_PASS (1<<2)
551 #define ACPI_IVHD_SYSTEM_MGMT (3<<4)
552 #define ACPI_IVHD_LINT0_PASS (1<<6)
553 #define ACPI_IVHD_LINT1_PASS (1<<7)
556 /* Types 0-4: 4-byte device entry */
558 typedef struct acpi_ivrs_device4
560 ACPI_IVRS_DE_HEADER Header;
564 /* Types 66-67: 8-byte device entry */
566 typedef struct acpi_ivrs_device8a
568 ACPI_IVRS_DE_HEADER Header;
573 } ACPI_IVRS_DEVICE8A;
575 /* Types 70-71: 8-byte device entry */
577 typedef struct acpi_ivrs_device8b
579 ACPI_IVRS_DE_HEADER Header;
582 } ACPI_IVRS_DEVICE8B;
584 /* Values for ExtendedData above */
586 #define ACPI_IVHD_ATS_DISABLED (1<<31)
588 /* Type 72: 8-byte device entry */
590 typedef struct acpi_ivrs_device8c
592 ACPI_IVRS_DE_HEADER Header;
597 } ACPI_IVRS_DEVICE8C;
599 /* Values for Variety field above */
601 #define ACPI_IVHD_IOAPIC 1
602 #define ACPI_IVHD_HPET 2
605 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition Block (IVMD) */
607 typedef struct acpi_ivrs_memory
609 ACPI_IVRS_HEADER Header;
618 /*******************************************************************************
620 * LPIT - Low Power Idle Table
622 * Conforms to "ACPI Low Power Idle Table (LPIT)" July 2014.
624 ******************************************************************************/
626 typedef struct acpi_table_lpit
628 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
633 /* LPIT subtable header */
635 typedef struct acpi_lpit_header
637 UINT32 Type; /* Subtable type */
638 UINT32 Length; /* Subtable length */
645 /* Values for subtable Type above */
649 ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00,
650 ACPI_LPIT_TYPE_RESERVED = 0x01 /* 1 and above are reserved */
653 /* Masks for Flags field above */
655 #define ACPI_LPIT_STATE_DISABLED (1)
656 #define ACPI_LPIT_NO_COUNTER (1<<1)
659 * LPIT subtables, correspond to Type in ACPI_LPIT_HEADER
662 /* 0x00: Native C-state instruction based LPI structure */
664 typedef struct acpi_lpit_native
666 ACPI_LPIT_HEADER Header;
667 ACPI_GENERIC_ADDRESS EntryTrigger;
670 ACPI_GENERIC_ADDRESS ResidencyCounter;
671 UINT64 CounterFrequency;
676 /*******************************************************************************
678 * MADT - Multiple APIC Description Table
681 ******************************************************************************/
683 typedef struct acpi_table_madt
685 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
686 UINT32 Address; /* Physical address of local APIC */
691 /* Masks for Flags field above */
693 #define ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */
695 /* Values for PCATCompat flag */
697 #define ACPI_MADT_DUAL_PIC 1
698 #define ACPI_MADT_MULTIPLE_APIC 0
701 /* Values for MADT subtable type in ACPI_SUBTABLE_HEADER */
705 ACPI_MADT_TYPE_LOCAL_APIC = 0,
706 ACPI_MADT_TYPE_IO_APIC = 1,
707 ACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,
708 ACPI_MADT_TYPE_NMI_SOURCE = 3,
709 ACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,
710 ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,
711 ACPI_MADT_TYPE_IO_SAPIC = 6,
712 ACPI_MADT_TYPE_LOCAL_SAPIC = 7,
713 ACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,
714 ACPI_MADT_TYPE_LOCAL_X2APIC = 9,
715 ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,
716 ACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,
717 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,
718 ACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,
719 ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
720 ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
721 ACPI_MADT_TYPE_RESERVED = 16 /* 16 and greater are reserved */
726 * MADT Subtables, correspond to Type in ACPI_SUBTABLE_HEADER
729 /* 0: Processor Local APIC */
731 typedef struct acpi_madt_local_apic
733 ACPI_SUBTABLE_HEADER Header;
734 UINT8 ProcessorId; /* ACPI processor id */
735 UINT8 Id; /* Processor's local APIC id */
738 } ACPI_MADT_LOCAL_APIC;
743 typedef struct acpi_madt_io_apic
745 ACPI_SUBTABLE_HEADER Header;
746 UINT8 Id; /* I/O APIC ID */
747 UINT8 Reserved; /* Reserved - must be zero */
748 UINT32 Address; /* APIC physical address */
749 UINT32 GlobalIrqBase; /* Global system interrupt where INTI lines start */
754 /* 2: Interrupt Override */
756 typedef struct acpi_madt_interrupt_override
758 ACPI_SUBTABLE_HEADER Header;
759 UINT8 Bus; /* 0 - ISA */
760 UINT8 SourceIrq; /* Interrupt source (IRQ) */
761 UINT32 GlobalIrq; /* Global system interrupt */
764 } ACPI_MADT_INTERRUPT_OVERRIDE;
769 typedef struct acpi_madt_nmi_source
771 ACPI_SUBTABLE_HEADER Header;
773 UINT32 GlobalIrq; /* Global system interrupt */
775 } ACPI_MADT_NMI_SOURCE;
778 /* 4: Local APIC NMI */
780 typedef struct acpi_madt_local_apic_nmi
782 ACPI_SUBTABLE_HEADER Header;
783 UINT8 ProcessorId; /* ACPI processor id */
785 UINT8 Lint; /* LINTn to which NMI is connected */
787 } ACPI_MADT_LOCAL_APIC_NMI;
790 /* 5: Address Override */
792 typedef struct acpi_madt_local_apic_override
794 ACPI_SUBTABLE_HEADER Header;
795 UINT16 Reserved; /* Reserved, must be zero */
796 UINT64 Address; /* APIC physical address */
798 } ACPI_MADT_LOCAL_APIC_OVERRIDE;
803 typedef struct acpi_madt_io_sapic
805 ACPI_SUBTABLE_HEADER Header;
806 UINT8 Id; /* I/O SAPIC ID */
807 UINT8 Reserved; /* Reserved, must be zero */
808 UINT32 GlobalIrqBase; /* Global interrupt for SAPIC start */
809 UINT64 Address; /* SAPIC physical address */
811 } ACPI_MADT_IO_SAPIC;
816 typedef struct acpi_madt_local_sapic
818 ACPI_SUBTABLE_HEADER Header;
819 UINT8 ProcessorId; /* ACPI processor id */
820 UINT8 Id; /* SAPIC ID */
821 UINT8 Eid; /* SAPIC EID */
822 UINT8 Reserved[3]; /* Reserved, must be zero */
824 UINT32 Uid; /* Numeric UID - ACPI 3.0 */
825 char UidString[1]; /* String UID - ACPI 3.0 */
827 } ACPI_MADT_LOCAL_SAPIC;
830 /* 8: Platform Interrupt Source */
832 typedef struct acpi_madt_interrupt_source
834 ACPI_SUBTABLE_HEADER Header;
836 UINT8 Type; /* 1=PMI, 2=INIT, 3=corrected */
837 UINT8 Id; /* Processor ID */
838 UINT8 Eid; /* Processor EID */
839 UINT8 IoSapicVector; /* Vector value for PMI interrupts */
840 UINT32 GlobalIrq; /* Global system interrupt */
841 UINT32 Flags; /* Interrupt Source Flags */
843 } ACPI_MADT_INTERRUPT_SOURCE;
845 /* Masks for Flags field above */
847 #define ACPI_MADT_CPEI_OVERRIDE (1)
850 /* 9: Processor Local X2APIC (ACPI 4.0) */
852 typedef struct acpi_madt_local_x2apic
854 ACPI_SUBTABLE_HEADER Header;
855 UINT16 Reserved; /* Reserved - must be zero */
856 UINT32 LocalApicId; /* Processor x2APIC ID */
858 UINT32 Uid; /* ACPI processor UID */
860 } ACPI_MADT_LOCAL_X2APIC;
863 /* 10: Local X2APIC NMI (ACPI 4.0) */
865 typedef struct acpi_madt_local_x2apic_nmi
867 ACPI_SUBTABLE_HEADER Header;
869 UINT32 Uid; /* ACPI processor UID */
870 UINT8 Lint; /* LINTn to which NMI is connected */
871 UINT8 Reserved[3]; /* Reserved - must be zero */
873 } ACPI_MADT_LOCAL_X2APIC_NMI;
876 /* 11: Generic Interrupt (ACPI 5.0 + ACPI 6.0 changes) */
878 typedef struct acpi_madt_generic_interrupt
880 ACPI_SUBTABLE_HEADER Header;
881 UINT16 Reserved; /* Reserved - must be zero */
882 UINT32 CpuInterfaceNumber;
885 UINT32 ParkingVersion;
886 UINT32 PerformanceInterrupt;
887 UINT64 ParkedAddress;
889 UINT64 GicvBaseAddress;
890 UINT64 GichBaseAddress;
891 UINT32 VgicInterrupt;
892 UINT64 GicrBaseAddress;
894 UINT8 EfficiencyClass;
897 } ACPI_MADT_GENERIC_INTERRUPT;
899 /* Masks for Flags field above */
901 /* ACPI_MADT_ENABLED (1) Processor is usable if set */
902 #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */
903 #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */
906 /* 12: Generic Distributor (ACPI 5.0 + ACPI 6.0 changes) */
908 typedef struct acpi_madt_generic_distributor
910 ACPI_SUBTABLE_HEADER Header;
911 UINT16 Reserved; /* Reserved - must be zero */
914 UINT32 GlobalIrqBase;
916 UINT8 Reserved2[3]; /* Reserved - must be zero */
918 } ACPI_MADT_GENERIC_DISTRIBUTOR;
920 /* Values for Version field above */
922 enum AcpiMadtGicVersion
924 ACPI_MADT_GIC_VERSION_NONE = 0,
925 ACPI_MADT_GIC_VERSION_V1 = 1,
926 ACPI_MADT_GIC_VERSION_V2 = 2,
927 ACPI_MADT_GIC_VERSION_V3 = 3,
928 ACPI_MADT_GIC_VERSION_V4 = 4,
929 ACPI_MADT_GIC_VERSION_RESERVED = 5 /* 5 and greater are reserved */
933 /* 13: Generic MSI Frame (ACPI 5.1) */
935 typedef struct acpi_madt_generic_msi_frame
937 ACPI_SUBTABLE_HEADER Header;
938 UINT16 Reserved; /* Reserved - must be zero */
945 } ACPI_MADT_GENERIC_MSI_FRAME;
947 /* Masks for Flags field above */
949 #define ACPI_MADT_OVERRIDE_SPI_VALUES (1)
952 /* 14: Generic Redistributor (ACPI 5.1) */
954 typedef struct acpi_madt_generic_redistributor
956 ACPI_SUBTABLE_HEADER Header;
957 UINT16 Reserved; /* reserved - must be zero */
961 } ACPI_MADT_GENERIC_REDISTRIBUTOR;
964 /* 15: Generic Translator (ACPI 6.0) */
966 typedef struct acpi_madt_generic_translator
968 ACPI_SUBTABLE_HEADER Header;
969 UINT16 Reserved; /* reserved - must be zero */
970 UINT32 TranslationId;
974 } ACPI_MADT_GENERIC_TRANSLATOR;
978 * Common flags fields for MADT subtables
981 /* MADT Local APIC flags */
983 #define ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */
985 /* MADT MPS INTI flags (IntiFlags) */
987 #define ACPI_MADT_POLARITY_MASK (3) /* 00-01: Polarity of APIC I/O input signals */
988 #define ACPI_MADT_TRIGGER_MASK (3<<2) /* 02-03: Trigger mode of APIC input signals */
990 /* Values for MPS INTI flags */
992 #define ACPI_MADT_POLARITY_CONFORMS 0
993 #define ACPI_MADT_POLARITY_ACTIVE_HIGH 1
994 #define ACPI_MADT_POLARITY_RESERVED 2
995 #define ACPI_MADT_POLARITY_ACTIVE_LOW 3
997 #define ACPI_MADT_TRIGGER_CONFORMS (0)
998 #define ACPI_MADT_TRIGGER_EDGE (1<<2)
999 #define ACPI_MADT_TRIGGER_RESERVED (2<<2)
1000 #define ACPI_MADT_TRIGGER_LEVEL (3<<2)
1003 /*******************************************************************************
1005 * MCFG - PCI Memory Mapped Configuration table and subtable
1008 * Conforms to "PCI Firmware Specification", Revision 3.0, June 20, 2005
1010 ******************************************************************************/
1012 typedef struct acpi_table_mcfg
1014 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1022 typedef struct acpi_mcfg_allocation
1024 UINT64 Address; /* Base address, processor-relative */
1025 UINT16 PciSegment; /* PCI segment group number */
1026 UINT8 StartBusNumber; /* Starting PCI Bus number */
1027 UINT8 EndBusNumber; /* Final PCI Bus number */
1030 } ACPI_MCFG_ALLOCATION;
1033 /*******************************************************************************
1035 * MCHI - Management Controller Host Interface Table
1038 * Conforms to "Management Component Transport Protocol (MCTP) Host
1039 * Interface Specification", Revision 1.0.0a, October 13, 2009
1041 ******************************************************************************/
1043 typedef struct acpi_table_mchi
1045 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1046 UINT8 InterfaceType;
1048 UINT64 ProtocolData;
1049 UINT8 InterruptType;
1051 UINT8 PciDeviceFlag;
1052 UINT32 GlobalInterrupt;
1053 ACPI_GENERIC_ADDRESS ControlRegister;
1062 /*******************************************************************************
1064 * MPST - Memory Power State Table (ACPI 5.0)
1067 ******************************************************************************/
1069 #define ACPI_MPST_CHANNEL_INFO \
1071 UINT8 Reserved1[3]; \
1072 UINT16 PowerNodeCount; \
1077 typedef struct acpi_table_mpst
1079 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1080 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */
1085 /* Memory Platform Communication Channel Info */
1087 typedef struct acpi_mpst_channel
1089 ACPI_MPST_CHANNEL_INFO /* Platform Communication Channel */
1091 } ACPI_MPST_CHANNEL;
1094 /* Memory Power Node Structure */
1096 typedef struct acpi_mpst_power_node
1102 UINT64 RangeAddress;
1104 UINT32 NumPowerStates;
1105 UINT32 NumPhysicalComponents;
1107 } ACPI_MPST_POWER_NODE;
1109 /* Values for Flags field above */
1111 #define ACPI_MPST_ENABLED 1
1112 #define ACPI_MPST_POWER_MANAGED 2
1113 #define ACPI_MPST_HOT_PLUG_CAPABLE 4
1116 /* Memory Power State Structure (follows POWER_NODE above) */
1118 typedef struct acpi_mpst_power_state
1123 } ACPI_MPST_POWER_STATE;
1126 /* Physical Component ID Structure (follows POWER_STATE above) */
1128 typedef struct acpi_mpst_component
1132 } ACPI_MPST_COMPONENT;
1135 /* Memory Power State Characteristics Structure (follows all POWER_NODEs) */
1137 typedef struct acpi_mpst_data_hdr
1139 UINT16 CharacteristicsCount;
1142 } ACPI_MPST_DATA_HDR;
1144 typedef struct acpi_mpst_power_data
1149 UINT32 AveragePower;
1154 } ACPI_MPST_POWER_DATA;
1156 /* Values for Flags field above */
1158 #define ACPI_MPST_PRESERVE 1
1159 #define ACPI_MPST_AUTOENTRY 2
1160 #define ACPI_MPST_AUTOEXIT 4
1163 /* Shared Memory Region (not part of an ACPI table) */
1165 typedef struct acpi_mpst_shared
1170 UINT32 CommandRegister;
1171 UINT32 StatusRegister;
1172 UINT32 PowerStateId;
1174 UINT64 EnergyConsumed;
1175 UINT64 AveragePower;
1180 /*******************************************************************************
1182 * MSCT - Maximum System Characteristics Table (ACPI 4.0)
1185 ******************************************************************************/
1187 typedef struct acpi_table_msct
1189 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1190 UINT32 ProximityOffset; /* Location of proximity info struct(s) */
1191 UINT32 MaxProximityDomains;/* Max number of proximity domains */
1192 UINT32 MaxClockDomains; /* Max number of clock domains */
1193 UINT64 MaxAddress; /* Max physical address in system */
1198 /* Subtable - Maximum Proximity Domain Information. Version 1 */
1200 typedef struct acpi_msct_proximity
1204 UINT32 RangeStart; /* Start of domain range */
1205 UINT32 RangeEnd; /* End of domain range */
1206 UINT32 ProcessorCapacity;
1207 UINT64 MemoryCapacity; /* In bytes */
1209 } ACPI_MSCT_PROXIMITY;
1212 /*******************************************************************************
1214 * MSDM - Microsoft Data Management table
1216 * Conforms to "Microsoft Software Licensing Tables (SLIC and MSDM)",
1217 * November 29, 2011. Copyright 2011 Microsoft
1219 ******************************************************************************/
1221 /* Basic MSDM table is only the common ACPI header */
1223 typedef struct acpi_table_msdm
1225 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1230 /*******************************************************************************
1232 * MTMR - MID Timer Table
1235 * Conforms to "Simple Firmware Interface Specification",
1236 * Draft 0.8.2, Oct 19, 2010
1237 * NOTE: The ACPI MTMR is equivalent to the SFI MTMR table.
1239 ******************************************************************************/
1241 typedef struct acpi_table_mtmr
1243 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1249 typedef struct acpi_mtmr_entry
1251 ACPI_GENERIC_ADDRESS PhysicalAddress;
1258 /*******************************************************************************
1260 * NFIT - NVDIMM Interface Table (ACPI 6.0+)
1263 ******************************************************************************/
1265 typedef struct acpi_table_nfit
1267 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1268 UINT32 Reserved; /* Reserved, must be zero */
1272 /* Subtable header for NFIT */
1274 typedef struct acpi_nfit_header
1282 /* Values for subtable type in ACPI_NFIT_HEADER */
1286 ACPI_NFIT_TYPE_SYSTEM_ADDRESS = 0,
1287 ACPI_NFIT_TYPE_MEMORY_MAP = 1,
1288 ACPI_NFIT_TYPE_INTERLEAVE = 2,
1289 ACPI_NFIT_TYPE_SMBIOS = 3,
1290 ACPI_NFIT_TYPE_CONTROL_REGION = 4,
1291 ACPI_NFIT_TYPE_DATA_REGION = 5,
1292 ACPI_NFIT_TYPE_FLUSH_ADDRESS = 6,
1293 ACPI_NFIT_TYPE_CAPABILITIES = 7,
1294 ACPI_NFIT_TYPE_RESERVED = 8 /* 8 and greater are reserved */
1301 /* 0: System Physical Address Range Structure */
1303 typedef struct acpi_nfit_system_address
1305 ACPI_NFIT_HEADER Header;
1308 UINT32 Reserved; /* Reserved, must be zero */
1309 UINT32 ProximityDomain;
1310 UINT8 RangeGuid[16];
1313 UINT64 MemoryMapping;
1315 } ACPI_NFIT_SYSTEM_ADDRESS;
1319 #define ACPI_NFIT_ADD_ONLINE_ONLY (1) /* 00: Add/Online Operation Only */
1320 #define ACPI_NFIT_PROXIMITY_VALID (1<<1) /* 01: Proximity Domain Valid */
1322 /* Range Type GUIDs appear in the include/acuuid.h file */
1325 /* 1: Memory Device to System Address Range Map Structure */
1327 typedef struct acpi_nfit_memory_map
1329 ACPI_NFIT_HEADER Header;
1330 UINT32 DeviceHandle;
1336 UINT64 RegionOffset;
1338 UINT16 InterleaveIndex;
1339 UINT16 InterleaveWays;
1341 UINT16 Reserved; /* Reserved, must be zero */
1343 } ACPI_NFIT_MEMORY_MAP;
1347 #define ACPI_NFIT_MEM_SAVE_FAILED (1) /* 00: Last SAVE to Memory Device failed */
1348 #define ACPI_NFIT_MEM_RESTORE_FAILED (1<<1) /* 01: Last RESTORE from Memory Device failed */
1349 #define ACPI_NFIT_MEM_FLUSH_FAILED (1<<2) /* 02: Platform flush failed */
1350 #define ACPI_NFIT_MEM_NOT_ARMED (1<<3) /* 03: Memory Device is not armed */
1351 #define ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4) /* 04: Memory Device observed SMART/health events */
1352 #define ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5) /* 05: SMART/health events enabled */
1353 #define ACPI_NFIT_MEM_MAP_FAILED (1<<6) /* 06: Mapping to SPA failed */
1356 /* 2: Interleave Structure */
1358 typedef struct acpi_nfit_interleave
1360 ACPI_NFIT_HEADER Header;
1361 UINT16 InterleaveIndex;
1362 UINT16 Reserved; /* Reserved, must be zero */
1365 UINT32 LineOffset[1]; /* Variable length */
1367 } ACPI_NFIT_INTERLEAVE;
1370 /* 3: SMBIOS Management Information Structure */
1372 typedef struct acpi_nfit_smbios
1374 ACPI_NFIT_HEADER Header;
1375 UINT32 Reserved; /* Reserved, must be zero */
1376 UINT8 Data[1]; /* Variable length */
1381 /* 4: NVDIMM Control Region Structure */
1383 typedef struct acpi_nfit_control_region
1385 ACPI_NFIT_HEADER Header;
1390 UINT16 SubsystemVendorId;
1391 UINT16 SubsystemDeviceId;
1392 UINT16 SubsystemRevisionId;
1394 UINT8 ManufacturingLocation;
1395 UINT16 ManufacturingDate;
1396 UINT8 Reserved[2]; /* Reserved, must be zero */
1397 UINT32 SerialNumber;
1401 UINT64 CommandOffset;
1403 UINT64 StatusOffset;
1406 UINT8 Reserved1[6]; /* Reserved, must be zero */
1408 } ACPI_NFIT_CONTROL_REGION;
1412 #define ACPI_NFIT_CONTROL_BUFFERED (1) /* Block Data Windows implementation is buffered */
1414 /* ValidFields bits */
1416 #define ACPI_NFIT_CONTROL_MFG_INFO_VALID (1) /* Manufacturing fields are valid */
1419 /* 5: NVDIMM Block Data Window Region Structure */
1421 typedef struct acpi_nfit_data_region
1423 ACPI_NFIT_HEADER Header;
1429 UINT64 StartAddress;
1431 } ACPI_NFIT_DATA_REGION;
1434 /* 6: Flush Hint Address Structure */
1436 typedef struct acpi_nfit_flush_address
1438 ACPI_NFIT_HEADER Header;
1439 UINT32 DeviceHandle;
1441 UINT8 Reserved[6]; /* Reserved, must be zero */
1442 UINT64 HintAddress[1]; /* Variable length */
1444 } ACPI_NFIT_FLUSH_ADDRESS;
1447 /* 7: Platform Capabilities Structure */
1449 typedef struct acpi_nfit_capabilities
1451 ACPI_NFIT_HEADER Header;
1452 UINT8 HighestCapability;
1453 UINT8 Reserved[3]; /* Reserved, must be zero */
1454 UINT32 Capabilities;
1457 } ACPI_NFIT_CAPABILITIES;
1459 /* Capabilities Flags */
1461 #define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */
1462 #define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */
1463 #define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */
1467 * NFIT/DVDIMM device handle support - used as the _ADR for each NVDIMM
1469 typedef struct nfit_device_handle
1473 } NFIT_DEVICE_HANDLE;
1475 /* Device handle construction and extraction macros */
1477 #define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F
1478 #define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0
1479 #define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00
1480 #define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000
1481 #define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000
1483 #define ACPI_NFIT_DIMM_NUMBER_OFFSET 0
1484 #define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4
1485 #define ACPI_NFIT_MEMORY_ID_OFFSET 8
1486 #define ACPI_NFIT_SOCKET_ID_OFFSET 12
1487 #define ACPI_NFIT_NODE_ID_OFFSET 16
1489 /* Macro to construct a NFIT/NVDIMM device handle */
1491 #define ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) \
1493 ((channel) << ACPI_NFIT_CHANNEL_NUMBER_OFFSET) | \
1494 ((memory) << ACPI_NFIT_MEMORY_ID_OFFSET) | \
1495 ((socket) << ACPI_NFIT_SOCKET_ID_OFFSET) | \
1496 ((node) << ACPI_NFIT_NODE_ID_OFFSET))
1498 /* Macros to extract individual fields from a NFIT/NVDIMM device handle */
1500 #define ACPI_NFIT_GET_DIMM_NUMBER(handle) \
1501 ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK)
1503 #define ACPI_NFIT_GET_CHANNEL_NUMBER(handle) \
1504 (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET)
1506 #define ACPI_NFIT_GET_MEMORY_ID(handle) \
1507 (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET)
1509 #define ACPI_NFIT_GET_SOCKET_ID(handle) \
1510 (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET)
1512 #define ACPI_NFIT_GET_NODE_ID(handle) \
1513 (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET)
1516 /*******************************************************************************
1518 * PCCT - Platform Communications Channel Table (ACPI 5.0)
1519 * Version 2 (ACPI 6.2)
1521 ******************************************************************************/
1523 typedef struct acpi_table_pcct
1525 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1531 /* Values for Flags field above */
1533 #define ACPI_PCCT_DOORBELL 1
1535 /* Values for subtable type in ACPI_SUBTABLE_HEADER */
1539 ACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,
1540 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,
1541 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2, /* ACPI 6.1 */
1542 ACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3, /* ACPI 6.2 */
1543 ACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4, /* ACPI 6.2 */
1544 ACPI_PCCT_TYPE_RESERVED = 5 /* 5 and greater are reserved */
1548 * PCCT Subtables, correspond to Type in ACPI_SUBTABLE_HEADER
1551 /* 0: Generic Communications Subspace */
1553 typedef struct acpi_pcct_subspace
1555 ACPI_SUBTABLE_HEADER Header;
1559 ACPI_GENERIC_ADDRESS DoorbellRegister;
1560 UINT64 PreserveMask;
1563 UINT32 MaxAccessRate;
1564 UINT16 MinTurnaroundTime;
1566 } ACPI_PCCT_SUBSPACE;
1569 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */
1571 typedef struct acpi_pcct_hw_reduced
1573 ACPI_SUBTABLE_HEADER Header;
1574 UINT32 PlatformInterrupt;
1579 ACPI_GENERIC_ADDRESS DoorbellRegister;
1580 UINT64 PreserveMask;
1583 UINT32 MaxAccessRate;
1584 UINT16 MinTurnaroundTime;
1586 } ACPI_PCCT_HW_REDUCED;
1589 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */
1591 typedef struct acpi_pcct_hw_reduced_type2
1593 ACPI_SUBTABLE_HEADER Header;
1594 UINT32 PlatformInterrupt;
1599 ACPI_GENERIC_ADDRESS DoorbellRegister;
1600 UINT64 PreserveMask;
1603 UINT32 MaxAccessRate;
1604 UINT16 MinTurnaroundTime;
1605 ACPI_GENERIC_ADDRESS PlatformAckRegister;
1606 UINT64 AckPreserveMask;
1607 UINT64 AckWriteMask;
1609 } ACPI_PCCT_HW_REDUCED_TYPE2;
1612 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */
1614 typedef struct acpi_pcct_ext_pcc_master
1616 ACPI_SUBTABLE_HEADER Header;
1617 UINT32 PlatformInterrupt;
1622 ACPI_GENERIC_ADDRESS DoorbellRegister;
1623 UINT64 PreserveMask;
1626 UINT32 MaxAccessRate;
1627 UINT32 MinTurnaroundTime;
1628 ACPI_GENERIC_ADDRESS PlatformAckRegister;
1629 UINT64 AckPreserveMask;
1632 ACPI_GENERIC_ADDRESS CmdCompleteRegister;
1633 UINT64 CmdCompleteMask;
1634 ACPI_GENERIC_ADDRESS CmdUpdateRegister;
1635 UINT64 CmdUpdatePreserveMask;
1636 UINT64 CmdUpdateSetMask;
1637 ACPI_GENERIC_ADDRESS ErrorStatusRegister;
1638 UINT64 ErrorStatusMask;
1640 } ACPI_PCCT_EXT_PCC_MASTER;
1643 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */
1645 typedef struct acpi_pcct_ext_pcc_slave
1647 ACPI_SUBTABLE_HEADER Header;
1648 UINT32 PlatformInterrupt;
1653 ACPI_GENERIC_ADDRESS DoorbellRegister;
1654 UINT64 PreserveMask;
1657 UINT32 MaxAccessRate;
1658 UINT32 MinTurnaroundTime;
1659 ACPI_GENERIC_ADDRESS PlatformAckRegister;
1660 UINT64 AckPreserveMask;
1663 ACPI_GENERIC_ADDRESS CmdCompleteRegister;
1664 UINT64 CmdCompleteMask;
1665 ACPI_GENERIC_ADDRESS CmdUpdateRegister;
1666 UINT64 CmdUpdatePreserveMask;
1667 UINT64 CmdUpdateSetMask;
1668 ACPI_GENERIC_ADDRESS ErrorStatusRegister;
1669 UINT64 ErrorStatusMask;
1671 } ACPI_PCCT_EXT_PCC_SLAVE;
1674 /* Values for doorbell flags above */
1676 #define ACPI_PCCT_INTERRUPT_POLARITY (1)
1677 #define ACPI_PCCT_INTERRUPT_MODE (1<<1)
1681 * PCC memory structures (not part of the ACPI table)
1684 /* Shared Memory Region */
1686 typedef struct acpi_pcct_shared_memory
1692 } ACPI_PCCT_SHARED_MEMORY;
1695 /* Extended PCC Subspace Shared Memory Region (ACPI 6.2) */
1697 typedef struct acpi_pcct_ext_pcc_shared_memory
1704 } ACPI_PCCT_EXT_PCC_SHARED_MEMORY;
1707 /*******************************************************************************
1709 * PDTT - Platform Debug Trigger Table (ACPI 6.2)
1712 ******************************************************************************/
1714 typedef struct acpi_table_pdtt
1716 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1725 * PDTT Communication Channel Identifier Structure.
1726 * The number of these structures is defined by TriggerCount above,
1727 * starting at ArrayOffset.
1729 typedef struct acpi_pdtt_channel
1734 } ACPI_PDTT_CHANNEL;
1736 /* Flags for above */
1738 #define ACPI_PDTT_RUNTIME_TRIGGER (1)
1739 #define ACPI_PDTT_WAIT_COMPLETION (1<<1)
1742 /*******************************************************************************
1744 * PMTT - Platform Memory Topology Table (ACPI 5.0)
1747 ******************************************************************************/
1749 typedef struct acpi_table_pmtt
1751 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1757 /* Common header for PMTT subtables that follow main table */
1759 typedef struct acpi_pmtt_header
1769 /* Values for Type field above */
1771 #define ACPI_PMTT_TYPE_SOCKET 0
1772 #define ACPI_PMTT_TYPE_CONTROLLER 1
1773 #define ACPI_PMTT_TYPE_DIMM 2
1774 #define ACPI_PMTT_TYPE_RESERVED 3 /* 0x03-0xFF are reserved */
1776 /* Values for Flags field above */
1778 #define ACPI_PMTT_TOP_LEVEL 0x0001
1779 #define ACPI_PMTT_PHYSICAL 0x0002
1780 #define ACPI_PMTT_MEMORY_TYPE 0x000C
1784 * PMTT subtables, correspond to Type in acpi_pmtt_header
1788 /* 0: Socket Structure */
1790 typedef struct acpi_pmtt_socket
1792 ACPI_PMTT_HEADER Header;
1799 /* 1: Memory Controller subtable */
1801 typedef struct acpi_pmtt_controller
1803 ACPI_PMTT_HEADER Header;
1805 UINT32 WriteLatency;
1806 UINT32 ReadBandwidth;
1807 UINT32 WriteBandwidth;
1813 } ACPI_PMTT_CONTROLLER;
1815 /* 1a: Proximity Domain substructure */
1817 typedef struct acpi_pmtt_domain
1819 UINT32 ProximityDomain;
1824 /* 2: Physical Component Identifier (DIMM) */
1826 typedef struct acpi_pmtt_physical_component
1828 ACPI_PMTT_HEADER Header;
1834 } ACPI_PMTT_PHYSICAL_COMPONENT;
1837 /*******************************************************************************
1839 * PPTT - Processor Properties Topology Table (ACPI 6.2)
1842 ******************************************************************************/
1844 typedef struct acpi_table_pptt
1846 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1850 /* Values for Type field above */
1854 ACPI_PPTT_TYPE_PROCESSOR = 0,
1855 ACPI_PPTT_TYPE_CACHE = 1,
1856 ACPI_PPTT_TYPE_ID = 2,
1857 ACPI_PPTT_TYPE_RESERVED = 3
1861 /* 0: Processor Hierarchy Node Structure */
1863 typedef struct acpi_pptt_processor
1865 ACPI_SUBTABLE_HEADER Header;
1869 UINT32 AcpiProcessorId;
1870 UINT32 NumberOfPrivResources;
1872 } ACPI_PPTT_PROCESSOR;
1876 #define ACPI_PPTT_PHYSICAL_PACKAGE (1) /* Physical package */
1877 #define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (2) /* ACPI Processor ID valid */
1880 /* 1: Cache Type Structure */
1882 typedef struct acpi_pptt_cache
1884 ACPI_SUBTABLE_HEADER Header;
1887 UINT32 NextLevelOfCache;
1889 UINT32 NumberOfSets;
1890 UINT8 Associativity;
1898 #define ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */
1899 #define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */
1900 #define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */
1901 #define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */
1902 #define ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */
1903 #define ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */
1904 #define ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */
1906 /* Masks for Attributes */
1908 #define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */
1909 #define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */
1910 #define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */
1912 /* Attributes describing cache */
1913 #define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */
1914 #define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */
1915 #define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */
1916 #define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */
1918 #define ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */
1919 #define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */
1920 #define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */
1921 #define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */
1923 #define ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */
1924 #define ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */
1926 /* 2: ID Structure */
1928 typedef struct acpi_pptt_id
1930 ACPI_SUBTABLE_HEADER Header;
1942 /*******************************************************************************
1944 * RASF - RAS Feature Table (ACPI 5.0)
1947 ******************************************************************************/
1949 typedef struct acpi_table_rasf
1951 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
1952 UINT8 ChannelId[12];
1956 /* RASF Platform Communication Channel Shared Memory Region */
1958 typedef struct acpi_rasf_shared_memory
1964 UINT8 Capabilities[16];
1965 UINT8 SetCapabilities[16];
1966 UINT16 NumParameterBlocks;
1967 UINT32 SetCapabilitiesStatus;
1969 } ACPI_RASF_SHARED_MEMORY;
1971 /* RASF Parameter Block Structure Header */
1973 typedef struct acpi_rasf_parameter_block
1979 } ACPI_RASF_PARAMETER_BLOCK;
1981 /* RASF Parameter Block Structure for PATROL_SCRUB */
1983 typedef struct acpi_rasf_patrol_scrub_parameter
1985 ACPI_RASF_PARAMETER_BLOCK Header;
1986 UINT16 PatrolScrubCommand;
1987 UINT64 RequestedAddressRange[2];
1988 UINT64 ActualAddressRange[2];
1990 UINT8 RequestedSpeed;
1992 } ACPI_RASF_PATROL_SCRUB_PARAMETER;
1994 /* Masks for Flags and Speed fields above */
1996 #define ACPI_RASF_SCRUBBER_RUNNING 1
1997 #define ACPI_RASF_SPEED (7<<1)
1998 #define ACPI_RASF_SPEED_SLOW (0<<1)
1999 #define ACPI_RASF_SPEED_MEDIUM (4<<1)
2000 #define ACPI_RASF_SPEED_FAST (7<<1)
2002 /* Channel Commands */
2004 enum AcpiRasfCommands
2006 ACPI_RASF_EXECUTE_RASF_COMMAND = 1
2009 /* Platform RAS Capabilities */
2011 enum AcpiRasfCapabiliities
2013 ACPI_HW_PATROL_SCRUB_SUPPORTED = 0,
2014 ACPI_SW_PATROL_SCRUB_EXPOSED = 1
2017 /* Patrol Scrub Commands */
2019 enum AcpiRasfPatrolScrubCommands
2021 ACPI_RASF_GET_PATROL_PARAMETERS = 1,
2022 ACPI_RASF_START_PATROL_SCRUBBER = 2,
2023 ACPI_RASF_STOP_PATROL_SCRUBBER = 3
2026 /* Channel Command flags */
2028 #define ACPI_RASF_GENERATE_SCI (1<<15)
2034 ACPI_RASF_SUCCESS = 0,
2035 ACPI_RASF_NOT_VALID = 1,
2036 ACPI_RASF_NOT_SUPPORTED = 2,
2038 ACPI_RASF_FAILED = 4,
2039 ACPI_RASF_ABORTED = 5,
2040 ACPI_RASF_INVALID_DATA = 6
2045 #define ACPI_RASF_COMMAND_COMPLETE (1)
2046 #define ACPI_RASF_SCI_DOORBELL (1<<1)
2047 #define ACPI_RASF_ERROR (1<<2)
2048 #define ACPI_RASF_STATUS (0x1F<<3)
2051 /*******************************************************************************
2053 * SBST - Smart Battery Specification Table
2056 ******************************************************************************/
2058 typedef struct acpi_table_sbst
2060 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
2061 UINT32 WarningLevel;
2063 UINT32 CriticalLevel;
2068 /*******************************************************************************
2070 * SDEI - Software Delegated Exception Interface Descriptor Table
2072 * Conforms to "Software Delegated Exception Interface (SDEI)" ARM DEN0054A,
2073 * May 8th, 2017. Copyright 2017 ARM Ltd.
2075 ******************************************************************************/
2077 typedef struct acpi_table_sdei
2079 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
2084 /*******************************************************************************
2086 * SDEV - Secure Devices Table (ACPI 6.2)
2089 ******************************************************************************/
2091 typedef struct acpi_table_sdev
2093 ACPI_TABLE_HEADER Header; /* Common ACPI table header */
2098 typedef struct acpi_sdev_header
2107 /* Values for subtable type above */
2111 ACPI_SDEV_TYPE_NAMESPACE_DEVICE = 0,
2112 ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE = 1,
2113 ACPI_SDEV_TYPE_RESERVED = 2 /* 2 and greater are reserved */
2116 /* Values for flags above */
2118 #define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1)
2124 /* 0: Namespace Device Based Secure Device Structure */
2126 typedef struct acpi_sdev_namespace
2128 ACPI_SDEV_HEADER Header;
2129 UINT16 DeviceIdOffset;
2130 UINT16 DeviceIdLength;
2131 UINT16 VendorDataOffset;
2132 UINT16 VendorDataLength;
2134 } ACPI_SDEV_NAMESPACE;
2136 /* 1: PCIe Endpoint Device Based Device Structure */
2138 typedef struct acpi_sdev_pcie
2140 ACPI_SDEV_HEADER Header;
2145 UINT16 VendorDataOffset;
2146 UINT16 VendorDataLength;
2150 /* 1a: PCIe Endpoint path entry */
2152 typedef struct acpi_sdev_pcie_path
2157 } ACPI_SDEV_PCIE_PATH;
2160 /* Reset to default packing */
2164 #endif /* __ACTBL2_H__ */