2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
3 * Communications, Inc. All rights reserved.
5 * Redistribution and use in source and binary forms are permitted
6 * provided that the following conditions are met:
7 * 1. The materials contained herein are unmodified and are used
9 * 2. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following NO
11 * ''WARRANTY'' disclaimer below (''Disclaimer''), without
13 * 3. Redistributions in binary form must reproduce at minimum a
14 * disclaimer similar to the Disclaimer below and any redistribution
15 * must be conditioned upon including a substantially similar
16 * Disclaimer requirement for further binary redistribution.
17 * 4. Neither the names of the above-listed copyright holders nor the
18 * names of any contributors may be used to endorse or promote
19 * product derived from this software without specific prior written
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24 * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
26 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
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29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * $Id: //depot/sw/branches/sam_hal/ah.h#19 $
42 * Atheros Hardware Access Layer
44 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal
45 * structure for use with the device. Hardware-related operations that
46 * follow must call back into the HAL through interface, supplying the
47 * reference as the first parameter.
51 * Bus i/o type definitions. We define a platform-independent
52 * set of types that are mapped to platform-dependent data for
53 * register read/write operations. We use types that are large
54 * enough to hold a pointer; smaller data should fit and only
55 * require type coercion to work. Larger data can be stored
56 * elsewhere and a reference passed for the bus tag and/or handle.
58 typedef void* HAL_SOFTC; /* pointer to driver/OS state */
59 typedef void* HAL_BUS_TAG; /* opaque bus i/o id tag */
60 typedef void* HAL_BUS_HANDLE; /* opaque bus i/o handle */
65 * __ahdecl is analogous to _cdecl; it defines the calling
66 * convention used within the HAL. For most systems this
67 * can just default to be empty and the compiler will (should)
68 * use _cdecl. For systems where _cdecl is not compatible this
69 * must be defined. See linux/ah_osdep.h for an example.
76 * Status codes that may be returned by the HAL. Note that
77 * interfaces that return a status code set it only when an
78 * error occurs--i.e. you cannot check it for success.
81 HAL_OK = 0, /* No error */
82 HAL_ENXIO = 1, /* No hardware present */
83 HAL_ENOMEM = 2, /* Memory allocation failed */
84 HAL_EIO = 3, /* Hardware didn't respond as expected */
85 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */
86 HAL_EEVERSION = 5, /* EEPROM version invalid */
87 HAL_EELOCKED = 6, /* EEPROM unreadable */
88 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */
89 HAL_EEREAD = 8, /* EEPROM read problem */
90 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */
91 HAL_EESIZE = 10, /* EEPROM size not supported */
92 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */
93 HAL_EINVAL = 12, /* Invalid parameter to function */
94 HAL_ENOTSUPP = 13, /* Hardware revision not supported */
95 HAL_ESELFTEST = 14, /* Hardware self-test failed */
96 HAL_EINPROGRESS = 15, /* Operation incomplete */
100 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
105 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
106 HAL_CAP_CIPHER = 1, /* hardware supports cipher */
107 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */
108 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */
109 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */
110 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */
111 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */
112 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */
113 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */
114 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */
115 HAL_CAP_DIAG = 11, /* hardware diagnostic support */
116 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */
117 HAL_CAP_BURST = 13, /* hardware supports packet bursting */
118 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */
119 HAL_CAP_TXPOW = 15, /* global tx power limit */
120 HAL_CAP_TPC = 16, /* per-packet tx power control */
121 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */
122 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */
123 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */
124 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */
125 HAL_CAP_XR = 21, /* hardware has XR support */
126 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */
127 HAL_CAP_CHAN_HALFRATE = 23, /* hardware can support half rate channels */
128 HAL_CAP_CHAN_QUARTERRATE = 24, /* hardware can support quarter rate channels */
129 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */
130 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */
131 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */
132 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */
133 HAL_CAP_INTMIT = 29, /* interference mitigation */
134 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
135 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
136 } HAL_CAPABILITY_TYPE;
139 * "States" for setting the LED. These correspond to
140 * the possible 802.11 operational states and there may
141 * be a many-to-one mapping between these states and the
142 * actual hardware state for the LED's (i.e. the hardware
143 * may have fewer states).
154 * Transmit queue types/numbers. These are used to tag
155 * each transmit queue in the hardware and to identify a set
156 * of transmit queues for operations such as start/stop dma.
159 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
160 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */
161 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */
162 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */
163 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */
166 #define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */
169 * Transmit queue subtype. These map directly to
170 * WME Access Categories (except for UPSD). Refer
171 * to Table 5 of the WME spec.
174 HAL_WME_AC_BK = 0, /* background access category */
175 HAL_WME_AC_BE = 1, /* best effort access category*/
176 HAL_WME_AC_VI = 2, /* video access category */
177 HAL_WME_AC_VO = 3, /* voice access category */
178 HAL_WME_UPSD = 4, /* uplink power save */
179 HAL_XR_DATA = 5, /* uplink power save */
180 } HAL_TX_QUEUE_SUBTYPE;
183 * Transmit queue flags that control various
184 * operational parameters.
188 * Per queue interrupt enables. When set the associated
189 * interrupt may be delivered for packets sent through
190 * the queue. Without these enabled no interrupts will
191 * be delivered for transmits through the queue.
193 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
194 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
195 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
196 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
197 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
199 * Enable hardware compression for packets sent through
200 * the queue. The compression buffer must be setup and
201 * packets must have a key entry marked in the tx descriptor.
203 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
205 * Disable queue when veol is hit or ready time expires.
206 * By default the queue is disabled only on reaching the
207 * physical end of queue (i.e. a null link ptr in the
210 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
212 * Schedule frames on delivery of a DBA (DMA Beacon Alert)
213 * event. Frames will be transmitted only when this timer
214 * fires, e.g to transmit a beacon in ap or adhoc modes.
216 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
218 * Each transmit queue has a counter that is incremented
219 * each time the queue is enabled and decremented when
220 * the list of frames to transmit is traversed (or when
221 * the ready time for the queue expires). This counter
222 * must be non-zero for frames to be scheduled for
223 * transmission. The following controls disable bumping
224 * this counter under certain conditions. Typically this
225 * is used to gate frames based on the contents of another
226 * queue (e.g. CAB traffic may only follow a beacon frame).
227 * These are meaningful only when frames are scheduled
228 * with a non-ASAP policy (e.g. DBA-gated).
230 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
231 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
234 * Fragment burst backoff policy. Normally the no backoff
235 * is done after a successful transmission, the next fragment
236 * is sent at SIFS. If this flag is set backoff is done
237 * after each fragment, regardless whether it was ack'd or
238 * not, after the backoff count reaches zero a normal channel
239 * access procedure is done before the next transmit (i.e.
240 * wait AIFS instead of SIFS).
242 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
244 * Disable post-tx backoff following each frame.
246 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
248 * DCU arbiter lockout control. This controls how
249 * lower priority tx queues are handled with respect to
250 * to a specific queue when multiple queues have frames
251 * to send. No lockout means lower priority queues arbitrate
252 * concurrently with this queue. Intra-frame lockout
253 * means lower priority queues are locked out until the
254 * current frame transmits (e.g. including backoffs and bursting).
255 * Global lockout means nothing lower can arbitrary so
256 * long as there is traffic activity on this queue (frames,
259 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
260 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
262 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
263 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
264 } HAL_TX_QUEUE_FLAGS;
267 u_int32_t tqi_ver; /* hal TXQ version */
268 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */
269 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */
270 u_int32_t tqi_priority; /* (not used) */
271 u_int32_t tqi_aifs; /* aifs */
272 u_int32_t tqi_cwmin; /* cwMin */
273 u_int32_t tqi_cwmax; /* cwMax */
274 u_int16_t tqi_shretry; /* rts retry limit */
275 u_int16_t tqi_lgretry; /* long retry limit (not used)*/
276 u_int32_t tqi_cbrPeriod; /* CBR period (us) */
277 u_int32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */
278 u_int32_t tqi_burstTime; /* max burst duration (us) */
279 u_int32_t tqi_readyTime; /* frame schedule time (us) */
280 u_int32_t tqi_compBuf; /* comp buffer phys addr */
283 #define HAL_TQI_NONVAL 0xffff
285 /* token to use for aifs, cwmin, cwmax */
286 #define HAL_TXQ_USEDEFAULT ((u_int32_t) -1)
288 /* compression definitions */
289 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */
290 #define HAL_COMP_BUF_ALIGN_SIZE 512
293 * Transmit packet types. This belongs in ah_desc.h, but
294 * is here so we can give a proper type to various parameters
295 * (and not require everyone include the file).
297 * NB: These values are intentionally assigned for
298 * direct use when setting up h/w descriptors.
301 HAL_PKT_TYPE_NORMAL = 0,
302 HAL_PKT_TYPE_ATIM = 1,
303 HAL_PKT_TYPE_PSPOLL = 2,
304 HAL_PKT_TYPE_BEACON = 3,
305 HAL_PKT_TYPE_PROBE_RESP = 4,
306 HAL_PKT_TYPE_CHIRP = 5,
307 HAL_PKT_TYPE_GRP_POLL = 6,
310 /* Rx Filter Frame Types */
312 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
313 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
314 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
315 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
316 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
317 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
318 HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */
319 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
320 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
321 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors*/
326 HAL_PM_FULL_SLEEP = 1,
327 HAL_PM_NETWORK_SLEEP = 2,
333 * These are mapped to take advantage of the common locations for many of
334 * the bits on all of the currently supported MAC chips. This is to make
335 * the ISR as efficient as possible, while still abstracting HW differences.
336 * When new hardware breaks this commonality this enumerated type, as well
337 * as the HAL functions using it, must be modified. All values are directly
338 * mapped unless commented otherwise.
341 HAL_INT_RX = 0x00000001, /* Non-common mapping */
342 HAL_INT_RXDESC = 0x00000002,
343 HAL_INT_RXNOFRM = 0x00000008,
344 HAL_INT_RXEOL = 0x00000010,
345 HAL_INT_RXORN = 0x00000020,
346 HAL_INT_TX = 0x00000040, /* Non-common mapping */
347 HAL_INT_TXDESC = 0x00000080,
348 HAL_INT_TXURN = 0x00000800,
349 HAL_INT_MIB = 0x00001000,
350 HAL_INT_RXPHY = 0x00004000,
351 HAL_INT_RXKCM = 0x00008000,
352 HAL_INT_SWBA = 0x00010000,
353 HAL_INT_BMISS = 0x00040000,
354 HAL_INT_BNR = 0x00100000, /* Non-common mapping */
355 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
356 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
357 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
358 HAL_INT_GPIO = 0x01000000,
359 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
360 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
361 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
362 HAL_INT_BMISC = HAL_INT_TIM
367 /* Interrupt bits that map directly to ISR/IMR bits */
368 HAL_INT_COMMON = HAL_INT_RXNOFRM
383 HAL_RFGAIN_INACTIVE = 0,
384 HAL_RFGAIN_READ_REQUESTED = 1,
385 HAL_RFGAIN_NEED_CHANGE = 2
389 * Channels are specified by frequency.
392 u_int16_t channel; /* setting in Mhz */
393 u_int16_t channelFlags; /* see below */
395 int8_t maxRegTxPower; /* max regulatory tx power in dBm */
396 int8_t maxTxPower; /* max true tx power in 0.5 dBm */
397 int8_t minTxPower; /* min true tx power in 0.5 dBm */
401 #define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */
402 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
403 #define CHANNEL_CCK 0x0020 /* CCK channel */
404 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
405 #define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */
406 #define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */
407 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */
408 #define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */
409 #define CHANNEL_XR 0x0800 /* XR channel */
410 #define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */
411 #define CHANNEL_HALF 0x4000 /* Half rate channel */
412 #define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */
415 #define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference
416 used for as AR as well as RADAR
417 interference detection */
418 #define CHANNEL_DFS 0x02 /* DFS required on channel */
419 #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */
420 #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */
422 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
423 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
424 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
426 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN)
428 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
430 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
431 #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO)
432 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
433 #define CHANNEL_108A CHANNEL_T
434 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
435 #define CHANNEL_ALL \
436 (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | CHANNEL_TURBO)
437 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO)
439 #define HAL_ANTENNA_MIN_MODE 0
440 #define HAL_ANTENNA_FIXED_A 1
441 #define HAL_ANTENNA_FIXED_B 2
442 #define HAL_ANTENNA_MAX_MODE 3
445 u_int32_t ackrcv_bad;
452 typedef u_int16_t HAL_CTRY_CODE; /* country code */
453 typedef u_int16_t HAL_REG_DOMAIN; /* regulatory domain code */
456 CTRY_DEBUG = 0x1ff, /* debug country code */
457 CTRY_DEFAULT = 0 /* default country code */
461 HAL_MODE_11A = 0x001, /* 11a channels */
462 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
463 HAL_MODE_11B = 0x004, /* 11b channels */
464 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
466 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
468 HAL_MODE_11G = 0x008, /* XXX historical */
470 HAL_MODE_108G = 0x020, /* 11a+Turbo channels */
471 HAL_MODE_108A = 0x040, /* 11g+Turbo channels */
472 HAL_MODE_XR = 0x100, /* XR channels */
473 HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */
474 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */
479 int rateCount; /* NB: for proper padding */
480 u_int8_t rateCodeToIndex[32]; /* back mapping */
482 u_int8_t valid; /* valid for rate control use */
483 u_int8_t phy; /* CCK/OFDM/XR */
484 u_int16_t rateKbps; /* transfer rate in kbs */
485 u_int8_t rateCode; /* rate for h/w descriptors */
486 u_int8_t shortPreamble; /* mask for enabling short
487 * preamble in CCK rate code */
488 u_int8_t dot11Rate; /* value for supported rates
489 * info element of MLME */
490 u_int8_t controlRate; /* index of next lower basic
491 * rate; used for dur. calcs */
492 u_int16_t lpAckDuration; /* long preamble ACK duration */
493 u_int16_t spAckDuration; /* short preamble ACK duration*/
498 u_int rs_count; /* number of valid entries */
499 u_int8_t rs_rates[32]; /* rates */
503 * Antenna switch control. By default antenna selection
504 * enables multiple (2) antenna use. To force use of the
505 * A or B antenna only specify a fixed setting. Fixing
506 * the antenna will also disable any diversity support.
509 HAL_ANT_VARIABLE = 0, /* variable by programming */
510 HAL_ANT_FIXED_A = 1, /* fixed antenna A */
511 HAL_ANT_FIXED_B = 2, /* fixed antenna B */
515 HAL_M_STA = 1, /* infrastructure station */
516 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
517 HAL_M_HOSTAP = 6, /* Software Access Point */
518 HAL_M_MONITOR = 8 /* Monitor mode */
522 u_int8_t kv_type; /* one of HAL_CIPHER */
524 u_int16_t kv_len; /* length in bits */
525 u_int8_t kv_val[16]; /* enough for 128-bit keys */
526 u_int8_t kv_mic[8]; /* TKIP MIC key */
527 u_int8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */
532 HAL_CIPHER_AES_OCB = 1,
533 HAL_CIPHER_AES_CCM = 2,
536 HAL_CIPHER_CLR = 5, /* no encryption */
538 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */
542 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */
544 HAL_SLOT_TIME_20 = 20,
548 * Per-station beacon timer state. Note that the specified
549 * beacon interval (given in TU's) can also include flags
550 * to force a TSF reset and to enable the beacon xmit logic.
551 * If bs_cfpmaxduration is non-zero the hardware is setup to
552 * coexist with a PCF-capable AP.
555 u_int32_t bs_nexttbtt; /* next beacon in TU */
556 u_int32_t bs_nextdtim; /* next DTIM in TU */
557 u_int32_t bs_intval; /* beacon interval+flags */
558 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
559 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
560 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
561 u_int32_t bs_dtimperiod;
562 u_int16_t bs_cfpperiod; /* CFP period in TU */
563 u_int16_t bs_cfpmaxduration; /* max CFP duration in TU */
564 u_int32_t bs_cfpnext; /* next CFP in TU */
565 u_int16_t bs_timoffset; /* byte offset to TIM bitmap */
566 u_int16_t bs_bmissthreshold; /* beacon miss threshold */
567 u_int32_t bs_sleepduration; /* max sleep duration */
571 * Like HAL_BEACON_STATE but for non-station mode setup.
572 * NB: see above flag definitions
575 u_int32_t bt_intval; /* beacon interval+flags */
576 u_int32_t bt_nexttbtt; /* next beacon in TU */
577 u_int32_t bt_nextatim; /* next ATIM in TU */
578 u_int32_t bt_nextdba; /* next DBA in 1/8th TU */
579 u_int32_t bt_nextswba; /* next SWBA in 1/8th TU */
583 * Per-node statistics maintained by the driver for use in
584 * optimizing signal quality and other operational aspects.
587 u_int32_t ns_avgbrssi; /* average beacon rssi */
588 u_int32_t ns_avgrssi; /* average data rssi */
589 u_int32_t ns_avgtxrssi; /* average tx rssi */
592 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
595 struct ath_tx_status;
596 struct ath_rx_status;
599 * Hardware Access Layer (HAL) API.
601 * Clients of the HAL call ath_hal_attach to obtain a reference to an
602 * ath_hal structure for use with the device. Hardware-related operations
603 * that follow must call back into the HAL through interface, supplying
604 * the reference as the first parameter. Note that before using the
605 * reference returned by ath_hal_attach the caller should verify the
606 * ABI version number.
609 u_int32_t ah_magic; /* consistency check magic number */
610 u_int32_t ah_abi; /* HAL ABI version */
611 #define HAL_ABI_VERSION 0x06102600 /* YYMMDDnn */
612 u_int16_t ah_devid; /* PCI device ID */
613 u_int16_t ah_subvendorid; /* PCI subvendor ID */
614 HAL_SOFTC ah_sc; /* back pointer to driver/os state */
615 HAL_BUS_TAG ah_st; /* params for register r+w */
616 HAL_BUS_HANDLE ah_sh;
617 HAL_CTRY_CODE ah_countryCode;
619 u_int32_t ah_macVersion; /* MAC version id */
620 u_int16_t ah_macRev; /* MAC revision */
621 u_int16_t ah_phyRev; /* PHY revision */
622 /* NB: when only one radio is present the rev is in 5Ghz */
623 u_int16_t ah_analog5GhzRev;/* 5GHz radio revision */
624 u_int16_t ah_analog2GhzRev;/* 2GHz radio revision */
626 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *,
628 void __ahdecl(*ah_detach)(struct ath_hal*);
630 /* Reset functions */
631 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE,
632 HAL_CHANNEL *, HAL_BOOL bChannelChange,
634 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *);
635 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *);
636 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *);
637 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, HAL_BOOL *);
638 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t);
641 HAL_BOOL __ahdecl(*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *);
643 /* Transmit functions */
644 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*,
645 HAL_BOOL incTrigLevel);
646 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE,
647 const HAL_TXQ_INFO *qInfo);
648 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q,
649 const HAL_TXQ_INFO *qInfo);
650 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q,
651 HAL_TXQ_INFO *qInfo);
652 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q);
653 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q);
654 u_int32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int);
655 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp);
656 u_int32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q);
657 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int);
658 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int);
659 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *,
660 u_int pktLen, u_int hdrLen,
661 HAL_PKT_TYPE type, u_int txPower,
662 u_int txRate0, u_int txTries0,
663 u_int keyIx, u_int antMode, u_int flags,
664 u_int rtsctsRate, u_int rtsctsDuration,
665 u_int compicvLen, u_int compivLen,
667 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*,
668 u_int txRate1, u_int txTries1,
669 u_int txRate2, u_int txTries2,
670 u_int txRate3, u_int txTries3);
671 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *,
672 u_int segLen, HAL_BOOL firstSeg,
673 HAL_BOOL lastSeg, const struct ath_desc *);
674 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *,
675 struct ath_desc *, struct ath_tx_status *);
676 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *);
677 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*);
679 /* Receive Functions */
680 u_int32_t __ahdecl(*ah_getRxDP)(struct ath_hal*);
681 void __ahdecl(*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp);
682 void __ahdecl(*ah_enableReceive)(struct ath_hal*);
683 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*);
684 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*);
685 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*);
686 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*,
687 u_int32_t filter0, u_int32_t filter1);
688 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*,
690 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*,
692 u_int32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*);
693 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, u_int32_t);
694 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *,
695 u_int32_t size, u_int flags);
696 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *,
697 struct ath_desc *, u_int32_t phyAddr,
698 struct ath_desc *next, u_int64_t tsf,
699 struct ath_rx_status *);
700 void __ahdecl(*ah_rxMonitor)(struct ath_hal *,
701 const HAL_NODE_STATS *, HAL_CHANNEL *);
702 void __ahdecl(*ah_procMibEvent)(struct ath_hal *,
703 const HAL_NODE_STATS *);
706 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *,
707 HAL_CAPABILITY_TYPE, u_int32_t capability,
709 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *,
710 HAL_CAPABILITY_TYPE, u_int32_t capability,
711 u_int32_t setting, HAL_STATUS *);
712 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request,
713 const void *args, u_int32_t argsize,
714 void **result, u_int32_t *resultsize);
715 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, u_int8_t *);
716 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const u_int8_t*);
717 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, u_int8_t *);
718 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const u_int8_t*);
719 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*,
720 u_int16_t, HAL_STATUS *);
721 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE);
722 void __ahdecl(*ah_writeAssocid)(struct ath_hal*,
723 const u_int8_t *bssid, u_int16_t assocId);
724 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, u_int32_t gpio);
725 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, u_int32_t gpio);
726 u_int32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, u_int32_t gpio);
727 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *,
728 u_int32_t gpio, u_int32_t val);
729 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t);
730 u_int32_t __ahdecl(*ah_getTsf32)(struct ath_hal*);
731 u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*);
732 void __ahdecl(*ah_resetTsf)(struct ath_hal*);
733 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*);
734 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*,
736 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*);
737 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*);
738 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int);
739 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*);
740 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*,
742 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int);
743 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*);
744 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int);
745 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*);
746 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int);
747 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*);
748 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int);
749 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*);
750 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, u_int16_t, int);
751 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, u_int8_t, int);
753 /* Key Cache Functions */
754 u_int32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*);
755 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, u_int16_t);
756 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *,
758 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*,
759 u_int16_t, const HAL_KEYVAL *,
760 const u_int8_t *, int);
761 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*,
762 u_int16_t, const u_int8_t *);
764 /* Power Management Functions */
765 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*,
766 HAL_POWER_MODE mode, int setChip);
767 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*);
768 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *);
771 /* Beacon Management Functions */
772 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*,
773 const HAL_BEACON_TIMERS *);
774 /* NB: deprecated, use ah_setBeaconTimers instead */
775 void __ahdecl(*ah_beaconInit)(struct ath_hal *,
776 u_int32_t nexttbtt, u_int32_t intval);
777 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*,
778 const HAL_BEACON_STATE *);
779 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*);
781 /* Interrupt functions */
782 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*);
783 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*);
784 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*);
785 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT);
789 * Check the PCI vendor ID and device ID against Atheros' values
790 * and return a printable description for any Atheros hardware.
791 * AH_NULL is returned if the ID's do not describe Atheros hardware.
793 extern const char *__ahdecl ath_hal_probe(u_int16_t vendorid, u_int16_t devid);
796 * Attach the HAL for use with the specified device. The device is
797 * defined by the PCI device ID. The caller provides an opaque pointer
798 * to an upper-layer data structure (HAL_SOFTC) that is stored in the
799 * HAL state block for later use. Hardware register accesses are done
800 * using the specified bus tag and handle. On successful return a
801 * reference to a state block is returned that must be supplied in all
802 * subsequent HAL calls. Storage associated with this reference is
803 * dynamically allocated and must be freed by calling the ah_detach
804 * method when the client is done. If the attach operation fails a
805 * null (AH_NULL) reference will be returned and a status code will
806 * be returned if the status parameter is non-zero.
808 extern struct ath_hal * __ahdecl ath_hal_attach(u_int16_t devid, HAL_SOFTC,
809 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status);
812 * Set the Vendor ID for Vendor SKU's which can modify the
813 * channel properties returned by ath_hal_init_channels.
814 * Return AH_TRUE if set succeeds
817 extern HAL_BOOL __ahdecl ath_hal_setvendor(struct ath_hal *, u_int32_t );
820 * Return a list of channels available for use with the hardware.
821 * The list is based on what the hardware is capable of, the specified
822 * country code, the modeSelect mask, and whether or not outdoor
823 * channels are to be permitted.
825 * The channel list is returned in the supplied array. maxchans
826 * defines the maximum size of this array. nchans contains the actual
827 * number of channels returned. If a problem occurred or there were
828 * no channels that met the criteria then AH_FALSE is returned.
830 extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *,
831 HAL_CHANNEL *chans, u_int maxchans, u_int *nchans,
832 u_int8_t *regclassids, u_int maxregids, u_int *nregids,
833 HAL_CTRY_CODE cc, u_int16_t modeSelect,
834 HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels);
837 * Calibrate noise floor data following a channel scan or similar.
838 * This must be called prior retrieving noise floor data.
840 extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah);
843 * Return bit mask of wireless modes supported by the hardware.
845 extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE);
848 * Return rate table for specified mode (11a, 11b, 11g, etc).
850 extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *,
854 * Calculate the transmit duration of a frame.
856 extern u_int16_t __ahdecl ath_hal_computetxtime(struct ath_hal *,
857 const HAL_RATE_TABLE *rates, u_int32_t frameLen,
858 u_int16_t rateix, HAL_BOOL shortPreamble);
861 * Return if device is public safety.
863 extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *);
866 * Convert between IEEE channel number and channel frequency
867 * using the specified channel flags; e.g. CHANNEL_2GHZ.
869 extern int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags);
872 * Return a version string for the HAL release.
874 extern char ath_hal_version[];
876 * Return a NULL-terminated array of build/configuration options.
878 extern const char* ath_hal_buildopts[];
879 #endif /* _ATH_AH_H_ */