2 * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
3 * Communications, Inc. All rights reserved.
5 * Redistribution and use in source and binary forms are permitted
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36 * $Id: //depot/sw/branches/sam_hal/ah_desc.h#2 $
39 #ifndef _DEV_ATH_DESC_H
40 #define _DEV_ATH_DESC_H
43 * Transmit descriptor status. This structure is filled
44 * in only after the tx descriptor process method finds a
45 * ``done'' descriptor; at which point it returns something
46 * other than HAL_EINPROGRESS.
48 * Note that ts_antenna may not be valid for all h/w. It
49 * should be used only if non-zero.
51 struct ath_tx_status {
52 u_int16_t ts_seqnum; /* h/w assigned sequence number */
53 u_int16_t ts_tstamp; /* h/w assigned timestamp */
54 u_int8_t ts_status; /* frame status, 0 => xmit ok */
55 u_int8_t ts_rate; /* h/w transmit rate index */
56 #define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
57 int8_t ts_rssi; /* tx ack RSSI */
58 u_int8_t ts_shortretry; /* # short retries */
59 u_int8_t ts_longretry; /* # long retries */
60 u_int8_t ts_virtcol; /* virtual collision count */
61 u_int8_t ts_antenna; /* antenna information */
64 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */
65 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
66 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */
69 * Receive descriptor status. This structure is filled
70 * in only after the rx descriptor process method finds a
71 * ``done'' descriptor; at which point it returns something
72 * other than HAL_EINPROGRESS.
74 * If rx_status is zero, then the frame was received ok;
75 * otherwise the error information is indicated and rs_phyerr
76 * contains a phy error code if HAL_RXERR_PHY is set. In general
77 * the frame contents is undefined when an error occurred thought
78 * for some errors (e.g. a decryption error), it may be meaningful.
80 * Note that the receive timestamp is expanded using the TSF to
81 * 15 bits (regardless of what the h/w provides directly).
83 * rx_rssi is in units of dbm above the noise floor. This value
84 * is measured during the preamble and PLCP; i.e. with the initial
85 * 4us of detection. The noise floor is typically a consistent
86 * -96dBm absolute power in a 20MHz channel.
88 struct ath_rx_status {
89 u_int16_t rs_datalen; /* rx frame length */
90 u_int16_t rs_tstamp; /* h/w assigned timestamp */
91 u_int8_t rs_status; /* rx status, 0 => recv ok */
92 u_int8_t rs_phyerr; /* phy error code */
93 int8_t rs_rssi; /* rx frame RSSI */
94 u_int8_t rs_keyix; /* key cache index */
95 u_int8_t rs_rate; /* h/w receive rate index */
96 u_int8_t rs_antenna; /* antenna information */
97 u_int8_t rs_more; /* more descriptors follow */
100 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */
101 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
102 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */
103 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
104 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
107 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
108 HAL_PHYERR_TIMING = 1, /* Timing error */
109 HAL_PHYERR_PARITY = 2, /* Illegal parity */
110 HAL_PHYERR_RATE = 3, /* Illegal rate */
111 HAL_PHYERR_LENGTH = 4, /* Illegal length */
112 HAL_PHYERR_RADAR = 5, /* Radar detect */
113 HAL_PHYERR_SERVICE = 6, /* Illegal service */
114 HAL_PHYERR_TOR = 7, /* Transmit override receive */
115 /* NB: these are specific to the 5212 */
116 HAL_PHYERR_OFDM_TIMING = 17, /* */
117 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
118 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
119 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */
120 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
121 HAL_PHYERR_OFDM_SERVICE = 22, /* */
122 HAL_PHYERR_OFDM_RESTART = 23, /* */
123 HAL_PHYERR_CCK_TIMING = 25, /* */
124 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
125 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */
126 HAL_PHYERR_CCK_SERVICE = 30, /* */
127 HAL_PHYERR_CCK_RESTART = 31, /* */
130 /* value found in rs_keyix to mark invalid entries */
131 #define HAL_RXKEYIX_INVALID ((u_int8_t) -1)
132 /* value used to specify no encryption key for xmit */
133 #define HAL_TXKEYIX_INVALID ((u_int) -1)
135 /* XXX rs_antenna definitions */
138 * Definitions for the software frame/packet descriptors used by
139 * the Atheros HAL. This definition obscures hardware-specific
140 * details from the driver. Drivers are expected to fillin the
141 * portions of a descriptor that are not opaque then use HAL calls
142 * to complete the work. Status for completed frames is returned
143 * in a device-independent format.
147 * The following definitions are passed directly
148 * the hardware and managed by the HAL. Drivers
149 * should not touch those elements marked opaque.
151 u_int32_t ds_link; /* phys address of next descriptor */
152 u_int32_t ds_data; /* phys address of data buffer */
153 u_int32_t ds_ctl0; /* opaque DMA control 0 */
154 u_int32_t ds_ctl1; /* opaque DMA control 1 */
155 u_int32_t ds_hw[4]; /* opaque h/w region */
157 * The remaining definitions are managed by software;
158 * these are valid only after the rx/tx process descriptor
159 * methods return a non-EINPROGRESS code.
162 struct ath_tx_status tx;/* xmit status */
163 struct ath_rx_status rx;/* recv status */
165 void *ds_vdata; /* virtual addr of data buffer */
168 #define ds_txstat ds_us.tx
169 #define ds_rxstat ds_us.rx
171 /* flags passed to tx descriptor setup methods */
172 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
173 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
174 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
175 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
176 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
177 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
178 /* NB: this only affects frame, not any RTS/CTS */
179 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
181 /* flags passed to rx descriptor setup methods */
182 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
183 #endif /* _DEV_ATH_AR521XDMA_H */