2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
17 #ifndef _ATH_AR9300_H_
18 #define _ATH_AR9300_H_
20 #include "ar9300_freebsd_inc.h"
22 #define AH_BIG_ENDIAN 4321
23 #define AH_LITTLE_ENDIAN 1234
25 #if _BYTE_ORDER == _BIG_ENDIAN
26 #define AH_BYTE_ORDER AH_BIG_ENDIAN
28 #define AH_BYTE_ORDER AH_LITTLE_ENDIAN
31 /* XXX doesn't belong here */
32 #define AR_EEPROM_MODAL_SPURS 5
35 * (a) this should be N(a),
36 * (b) FreeBSD does define nitems,
37 * (c) it doesn't have an AH_ prefix, sigh.
39 #define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0]))
41 #include "ah_internal.h"
42 #include "ah_eeprom.h"
44 #include "ar9300eep.h" /* For Eeprom definitions */
47 #define AR9300_MAGIC 0x19741014
50 /* MAC register values */
52 #define INIT_CONFIG_STATUS 0x00000000
53 #define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
54 #define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */
57 * Various fifo fill before Tx start, in 64-byte units
58 * i.e. put the frame in the air while still DMAing
60 #define MIN_TX_FIFO_THRESHOLD 0x1
61 #define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1)
62 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
64 #define CHANSEL_DIV 15
67 #define COEFF ((FCLK * 5) / 2)
68 #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV)
69 #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV)
70 #define CHANSEL_5G_DOT5MHZ 2188
73 * Receive Queue Fifo depth.
76 HAL_HP_RXFIFO_DEPTH = 16,
77 HAL_LP_RXFIFO_DEPTH = 128,
83 #define NUM_CORNER_FIX_BITS_2133 7
84 #define CCK_OFDM_GAIN_DELTA 15
93 enum GAIN_PARAMS_2133 {
109 typedef struct _gain_opt_step {
110 int16_t paramVal[NUM_CORNER_FIX_BITS_2133];
113 } GAIN_OPTIMIZATION_STEP;
116 u_int32_t numStepsInLadder;
117 u_int32_t defaultStepNum;
118 GAIN_OPTIMIZATION_STEP optStep[10];
119 } GAIN_OPTIMIZATION_LADDER;
122 u_int32_t currStepNum;
124 u_int32_t targetGain;
127 u_int32_t gainFCorrection;
129 GAIN_OPTIMIZATION_STEP *curr_step;
133 u_int16_t synth_center;
134 u_int16_t ctl_center;
135 u_int16_t ext_center;
138 /* RF HAL structures */
139 typedef struct rf_hal_funcs {
140 HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *);
141 HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah,
142 struct ieee80211_channel *chan);
145 struct ar9300_ani_default {
146 u_int16_t m1_thresh_low;
147 u_int16_t m2_thresh_low;
150 u_int16_t m2_count_thr;
151 u_int16_t m2_count_thr_low;
152 u_int16_t m1_thresh_low_ext;
153 u_int16_t m2_thresh_low_ext;
154 u_int16_t m1_thresh_ext;
155 u_int16_t m2_thresh_ext;
157 u_int16_t firstep_low;
158 u_int16_t cycpwr_thr1;
159 u_int16_t cycpwr_thr1_ext;
163 * Per-channel ANI state private to the driver.
165 struct ar9300_ani_state {
166 struct ieee80211_channel c; /* XXX ew? */
167 HAL_BOOL must_restore;
169 u_int8_t ofdm_noise_immunity_level;
170 u_int8_t cck_noise_immunity_level;
171 u_int8_t spur_immunity_level;
172 u_int8_t firstep_level;
173 u_int8_t ofdm_weak_sig_detect_off;
174 u_int8_t mrc_cck_off;
177 u_int32_t listen_time;
178 u_int32_t ofdm_trig_high;
179 u_int32_t ofdm_trig_low;
180 int32_t cck_trig_high;
181 int32_t cck_trig_low;
182 int32_t rssi_thr_low;
183 int32_t rssi_thr_high;
185 int32_t rssi; /* The current RSSI */
186 u_int32_t tx_frame_count; /* Last tx_frame_count */
187 u_int32_t rx_frame_count; /* Last rx Frame count */
188 u_int32_t rx_busy_count; /* Last rx busy count */
189 u_int32_t rx_ext_busy_count; /* Last rx busy count; extension channel */
190 u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */
191 u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */
192 u_int32_t cck_phy_err_count; /* CCK err count since last reset */
194 struct ar9300_ani_default ini_def; /* INI default values for ANI registers */
195 HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */
198 #define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */
200 #define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */
202 #define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */
203 #define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */
204 #define HAL_AR_EN 0x40000000 /* AR detect is capable */
207 ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI))
209 struct ar9300_stats {
210 u_int32_t ast_ani_niup; /* ANI increased noise immunity */
211 u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */
212 u_int32_t ast_ani_spurup; /* ANI increased spur immunity */
213 u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */
214 u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
215 u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
216 u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
217 u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
218 u_int32_t ast_ani_stepup; /* ANI increased first step level */
219 u_int32_t ast_ani_stepdown;/* ANI decreased first step level */
220 u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
221 u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
222 u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
223 u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */
224 u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
225 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
226 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
229 struct ar9300_rad_reader {
232 u_int32_t rd_resetVal;
236 struct ar9300_rad_writer {
241 struct ar9300_radar_event {
242 u_int32_t re_ts; /* 32 bit time stamp */
243 u_int8_t re_rssi; /* rssi of radar event */
244 u_int8_t re_dur; /* duration of radar pulse */
245 u_int8_t re_chanIndex; /* Channel of event */
248 struct ar9300_radar_q_elem {
250 u_int32_t rq_busy; /* 32 bit to insure atomic read/write */
251 struct ar9300_radar_event rq_event; /* Radar event */
254 struct ar9300_radar_q_info {
255 u_int16_t ri_qsize; /* q size */
256 u_int16_t ri_seqSize; /* Size of sequence ring */
257 struct ar9300_rad_reader ri_reader; /* State for the q reader */
258 struct ar9300_rad_writer ri_writer; /* state for the q writer */
261 #define HAL_MAX_ACK_RADAR_DUR 511
262 #define HAL_MAX_NUM_PEAKS 3
263 #define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */
264 #define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */
265 #define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */
266 #define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */
267 #define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */
269 struct ar9300_ar_state {
270 u_int16_t ar_prev_time_stamp;
271 u_int32_t ar_prev_width;
272 u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR];
273 u_int32_t ar_ack_sum;
274 u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS];
275 u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */
276 u_int32_t ar_par_threshold; /* Thresh to determine peak */
277 u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */
280 struct ar9300_radar_state {
281 struct ieee80211_channel *rs_chan; /* Channel info */
282 u_int8_t rs_chan_index; /* Channel index in radar structure */
283 u_int32_t rs_num_radar_events; /* Number of radar events */
284 int32_t rs_firpwr; /* Thresh to check radar sig is gone */
285 u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */
286 u_int32_t rs_height; /* Thresh for pulse height (dB)*/
287 u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */
288 u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */
291 u_int8_t uc_receiver_errors;
292 u_int8_t uc_bad_tlp_errors;
293 u_int8_t uc_bad_dllp_errors;
294 u_int8_t uc_replay_timeout_errors;
295 u_int8_t uc_replay_number_rollover_errors;
296 } ar_pcie_error_moniter_counters;
298 #define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */
299 #define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */
300 #define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */
301 #define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */
302 #define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */
303 #define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */
306 * For Kite and later chipsets, the following bits are not being programmed in EEPROM
307 * and so need to be enabled always.
308 * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40
309 * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40
311 #define AR9300_RDEXT_DEFAULT 0x1F
313 #define AR9300_MAX_CHAINS 3
314 #define AR9300_NUM_CHAINS(chainmask) \
315 (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1))
316 #define AR9300_CHAIN0_MASK 0x1
317 #define AR9300_CHAIN1_MASK 0x2
318 #define AR9300_CHAIN2_MASK 0x4
320 /* Support for multiple INIs */
321 struct ar9300_ini_array {
322 const u_int32_t *ia_array;
324 u_int32_t ia_columns;
326 #define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
327 (iniarray)->ia_array = (const u_int32_t *)(array); \
328 (iniarray)->ia_rows = (rows); \
329 (iniarray)->ia_columns = (columns); \
331 #define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
333 #define INIT_CAL(_perCal) \
334 (_perCal)->cal_state = CAL_WAITING; \
335 (_perCal)->cal_next = AH_NULL;
337 #define INSERT_CAL(_ahp, _perCal) \
339 if ((_ahp)->ah_cal_list_last == AH_NULL) { \
340 (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \
341 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \
343 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \
344 (_ahp)->ah_cal_list_last = (_perCal); \
345 (_perCal)->cal_next = (_ahp)->ah_cal_list; \
349 typedef enum cal_types {
350 IQ_MISMATCH_CAL = 0x1,
354 typedef enum cal_state {
359 } HAL_CAL_STATE; /* Calibrate state */
361 #define MIN_CAL_SAMPLES 1
362 #define MAX_CAL_SAMPLES 64
363 #define INIT_LOG_COUNT 5
364 #define PER_MIN_LOG_COUNT 2
365 #define PER_MAX_LOG_COUNT 10
367 #define AR9300_NUM_BT_WEIGHTS 4
368 #define AR9300_NUM_WLAN_WEIGHTS 4
370 /* Per Calibration data structure */
371 typedef struct per_cal_data {
372 HAL_CAL_TYPES cal_type; // Type of calibration
373 u_int32_t cal_num_samples; // Number of SW samples to collect
374 u_int32_t cal_count_max; // Number of HW samples to collect
375 void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func
376 void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func
379 /* List structure for calibration data */
380 typedef struct cal_list {
381 const HAL_PERCAL_DATA *cal_data;
382 HAL_CAL_STATE cal_state;
383 struct cal_list *cal_next;
386 #define AR9300_NUM_CAL_TYPES 2
387 #define AR9300_PAPRD_TABLE_SZ 24
388 #define AR9300_PAPRD_GAIN_TABLE_SZ 32
389 #define AR9382_MAX_GPIO_PIN_NUM (16)
390 #define AR9382_GPIO_PIN_8_RESERVED (8)
391 #define AR9382_GPIO_9_INPUT_ONLY (9)
392 #define AR9382_MAX_GPIO_INPUT_PIN_NUM (13)
393 #define AR9382_GPIO_PIN_11_RESERVED (11)
394 #define AR9382_MAX_JTAG_GPIO_PIN_NUM (3)
396 /* Paprd tx power adjust data structure */
397 struct ar9300_paprd_pwr_adjust {
398 u_int32_t target_rate; // rate index
399 u_int32_t reg_addr; // register offset
400 u_int32_t reg_mask; // mask of register
401 u_int32_t reg_mask_offset; // mask offset of register
402 u_int32_t sub_db; // offset value unit of dB
405 struct ar9300NfLimits {
411 #define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/
412 struct ath_hal_9300 {
413 struct ath_hal_private ah_priv; /* base class */
416 * Information retrieved from EEPROM.
418 ar9300_eeprom_t ah_eeprom;
420 GAIN_VALUES ah_gain_values;
422 u_int8_t ah_macaddr[IEEE80211_ADDR_LEN];
423 u_int8_t ah_bssid[IEEE80211_ADDR_LEN];
424 u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN];
425 u_int16_t ah_assoc_id;
430 u_int32_t ah_mask_reg; /* copy of AR_IMR */
431 u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */
432 u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */
433 os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */
434 struct ar9300_stats ah_stats; /* various statistics */
435 RF_HAL_FUNCS ah_rf_hal;
436 u_int32_t ah_tx_desc_mask; /* mask for TXDESC */
437 u_int32_t ah_tx_ok_interrupt_mask;
438 u_int32_t ah_tx_err_interrupt_mask;
439 u_int32_t ah_tx_desc_interrupt_mask;
440 u_int32_t ah_tx_eol_interrupt_mask;
441 u_int32_t ah_tx_urn_interrupt_mask;
442 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
443 HAL_SMPS_MODE ah_sm_power_mode;
444 HAL_BOOL ah_chip_full_sleep;
445 u_int32_t ah_atim_window;
446 HAL_ANT_SETTING ah_diversity_control; /* antenna setting */
447 u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */
448 u_int8_t ah_tx_chainmask_cfg; /* chain mask config */
449 u_int8_t ah_rx_chainmask_cfg;
450 u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */
451 /* Calibration related fields */
452 HAL_CAL_TYPES ah_supp_cals;
453 HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */
454 HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */
455 HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */
456 HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */
457 HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */
459 #define ah_total_power_meas_i ah_meas0.unsign
460 #define ah_total_power_meas_q ah_meas1.unsign
461 #define ah_total_iq_corr_meas ah_meas2.sign
463 u_int32_t unsign[AR9300_MAX_CHAINS];
464 int32_t sign[AR9300_MAX_CHAINS];
467 u_int32_t unsign[AR9300_MAX_CHAINS];
468 int32_t sign[AR9300_MAX_CHAINS];
471 u_int32_t unsign[AR9300_MAX_CHAINS];
472 int32_t sign[AR9300_MAX_CHAINS];
475 u_int32_t unsign[AR9300_MAX_CHAINS];
476 int32_t sign[AR9300_MAX_CHAINS];
478 u_int16_t ah_cal_samples;
479 /* end - Calibration related fields */
480 u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */
481 u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */
482 u_int32_t ah_misc_mode; /* MISC_MODE settings */
483 HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */
485 AUTO_32KHZ, /* use it if 32kHz crystal present */
486 USE_32KHZ, /* do it regardless */
487 DONT_USE_32KHZ, /* don't use it regardless */
488 } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */
490 u_int32_t ah_ofdm_tx_power;
491 int16_t ah_tx_power_index_offset;
493 u_int ah_slot_time; /* user-specified slot time */
494 u_int ah_ack_timeout; /* user-specified ack timeout */
497 * 11g-specific stuff; belongs in the driver.
499 u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */
500 u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */
501 u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */
503 * RF Silent handling; setup according to the EEPROM.
505 u_int32_t ah_gpio_select; /* GPIO pin to use */
506 u_int32_t ah_polarity; /* polarity to disable RF */
507 u_int32_t ah_gpio_bit; /* after init, prev value */
508 HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */
512 * Bluetooth coexistence static setup according to the registry
514 HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */
515 u_int8_t ah_bt_coex_config_type; /* BT coex configuration */
516 u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */
517 u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */
518 u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */
519 u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */
520 HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */
521 u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */
523 * Bluetooth coexistence runtime settings
525 HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */
526 u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */
527 u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */
528 u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */
529 u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */
530 u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */
534 * Generic timer support
536 u_int32_t ah_avail_gen_timers; /* mask of available timers */
537 u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */
538 u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */
539 HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */
542 * ANI & Radar support.
544 u_int32_t ah_proc_phy_err; /* Process Phy errs */
545 u_int32_t ah_ani_period; /* ani update list period */
546 struct ar9300_ani_state *ah_curani; /* cached last reference */
547 struct ar9300_ani_state ah_ani[255]; /* per-channel state */
548 struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */
549 struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */
550 struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */
551 struct ar9300_ar_state ah_ar; /* AR detector state */
552 struct ar9300_radar_q_elem *ah_arq; /* AR event queue */
553 struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */
556 * Transmit power state. Note these are maintained
557 * here so they can be retrieved by diagnostic tools.
559 u_int16_t ah_rates_array[16];
562 * Tx queue interrupt state.
564 u_int32_t ah_intr_txqs;
566 HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */
567 HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */
570 * Extension Channel Rx Clear State
572 u_int32_t ah_cycle_count;
573 u_int32_t ah_ctl_busy;
574 u_int32_t ah_ext_busy;
577 HAL_HT_EXTPROTSPACING ah_ext_prot_spacing;
578 u_int8_t ah_tx_chainmask; /* tx chain mask */
579 u_int8_t ah_rx_chainmask; /* rx chain mask */
581 /* optional tx chainmask */
582 u_int8_t ah_tx_chainmaskopt;
584 u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */
585 u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */
589 HAL_BOOL ah_emu_eeprom;
591 HAL_ANI_CMD ah_ani_function;
592 HAL_BOOL ah_rifs_enabled;
593 u_int32_t ah_rifs_reg[11];
594 u_int32_t ah_rifs_sec_cnt;
596 /* open-loop power control */
597 u_int32_t original_gain[22];
601 /* cycle counts for beacon stuck diagnostics */
603 u_int32_t ah_rx_clear;
604 u_int32_t ah_rx_frame;
605 u_int32_t ah_tx_frame;
607 #define BB_HANG_SIG1 0
608 #define BB_HANG_SIG2 1
609 #define BB_HANG_SIG3 2
610 #define BB_HANG_SIG4 3
611 #define MAC_HANG_SIG1 4
612 #define MAC_HANG_SIG2 5
613 /* bb hang detection */
615 hal_hw_hangs_t ah_hang_wars;
618 * Keytable type table
620 #define AR_KEYTABLE_SIZE 128 /* XXX! */
621 uint8_t ah_keytype[AR_KEYTABLE_SIZE];
622 #undef AR_KEYTABLE_SIZE
624 * Support for ar9300 multiple INIs
626 struct ar9300_ini_array ah_ini_pcie_serdes;
627 struct ar9300_ini_array ah_ini_pcie_serdes_low_power;
628 struct ar9300_ini_array ah_ini_modes_additional;
629 struct ar9300_ini_array ah_ini_modes_additional_40mhz;
630 struct ar9300_ini_array ah_ini_modes_rxgain;
631 struct ar9300_ini_array ah_ini_modes_rxgain_bounds;
632 struct ar9300_ini_array ah_ini_modes_txgain;
633 struct ar9300_ini_array ah_ini_japan2484;
634 struct ar9300_ini_array ah_ini_radio_post_sys2ant;
635 struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR;
637 * New INI format starting with Osprey 2.0 INI.
638 * Pre, core, post arrays for each sub-system (mac, bb, radio, soc)
640 #define ATH_INI_PRE 0
641 #define ATH_INI_CORE 1
642 #define ATH_INI_POST 2
643 #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1)
644 struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */
645 struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */
646 struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */
647 struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */
650 * Added to support DFS postamble array in INI that we need to apply
654 struct ar9300_ini_array ah_ini_dfs;
657 struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */
660 /* To indicate EEPROM mapping used */
661 u_int32_t ah_immunity_vals[6];
662 HAL_BOOL ah_immunity_on;
664 * snap shot of counter register for debug purposes
672 HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */
673 u_int32_t nf_tsf32; /* timestamp for NF calibration duration */
675 u_int32_t reg_dmn; /* Regulatory Domain */
676 int16_t twice_antenna_gain; /* Antenna Gain */
677 u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */
680 * Upper limit after factoring in the regulatory max, antenna gain and
681 * multichain factor. No TxBF, CDD or STBC gain factored
683 int16_t upper_limit[AR9300_MAX_CHAINS];
685 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */
686 int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS];
688 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/
689 int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS];
691 /* Transmit Status ring support */
692 struct ar9300_txs *ts_ring;
695 u_int32_t ts_paddr_start;
696 u_int32_t ts_paddr_end;
698 /* Receive Buffer size */
699 #define HAL_RXBUFSIZE_DEFAULT 0xfff
700 u_int16_t rx_buf_size;
702 u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states).
704 /* Indicate the PLL source clock rate is 25Mhz or not.
705 * clk_25mhz = 0 by default.
709 u_int16_t small_signal_gain[AH_MAX_CHAINS];
710 u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ];
711 u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ];
712 u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ];
713 u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */
714 u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */
715 u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */
716 u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */
717 u_int32_t paprd_training_power;
718 /* For GreenTx use to store the default tx power */
719 u_int8_t ah_default_tx_power[ar9300_rate_size];
720 HAL_BOOL ah_paprd_broken;
722 /* To store offsets of host interface registers */
726 u_int32_t AR_PM_STATE;
727 u_int32_t AR_H_INFOL;
728 u_int32_t AR_H_INFOH;
729 u_int32_t AR_PCIE_PM_CTRL;
730 u_int32_t AR_HOST_TIMEOUT;
733 u_int32_t AR_INTR_SYNC_CAUSE;
734 u_int32_t AR_INTR_SYNC_CAUSE_CLR;
735 u_int32_t AR_INTR_SYNC_ENABLE;
736 u_int32_t AR_INTR_ASYNC_MASK;
737 u_int32_t AR_INTR_SYNC_MASK;
738 u_int32_t AR_INTR_ASYNC_CAUSE_CLR;
739 u_int32_t AR_INTR_ASYNC_CAUSE;
740 u_int32_t AR_INTR_ASYNC_ENABLE;
741 u_int32_t AR_PCIE_SERDES;
742 u_int32_t AR_PCIE_SERDES2;
743 u_int32_t AR_GPIO_OUT;
744 u_int32_t AR_GPIO_IN;
745 u_int32_t AR_GPIO_OE_OUT;
746 u_int32_t AR_GPIO_OE1_OUT;
747 u_int32_t AR_GPIO_INTR_POL;
748 u_int32_t AR_GPIO_INPUT_EN_VAL;
749 u_int32_t AR_GPIO_INPUT_MUX1;
750 u_int32_t AR_GPIO_INPUT_MUX2;
751 u_int32_t AR_GPIO_OUTPUT_MUX1;
752 u_int32_t AR_GPIO_OUTPUT_MUX2;
753 u_int32_t AR_GPIO_OUTPUT_MUX3;
754 u_int32_t AR_INPUT_STATE;
756 u_int32_t AR_PCIE_CORE_RESET_EN;
758 u_int32_t AR_EEPROM_STATUS_DATA;
760 u_int32_t AR_RFSILENT;
761 u_int32_t AR_GPIO_PDPU;
762 u_int32_t AR_GPIO_DS;
764 u_int32_t AR_PCIE_MSI;
765 u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE;
766 u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY;
767 u_int32_t AR_TSF_SNAPSHOT_BT_CNTL;
768 u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ;
769 u_int32_t AR_TDMA_CCA_CNTL;
770 u_int32_t AR_TXAPSYNC;
771 u_int32_t AR_TXSYNC_INIT_SYNC_TMR;
772 u_int32_t AR_INTR_PRIO_SYNC_CAUSE;
773 u_int32_t AR_INTR_PRIO_SYNC_ENABLE;
774 u_int32_t AR_INTR_PRIO_ASYNC_MASK;
775 u_int32_t AR_INTR_PRIO_SYNC_MASK;
776 u_int32_t AR_INTR_PRIO_ASYNC_CAUSE;
777 u_int32_t AR_INTR_PRIO_ASYNC_ENABLE;
780 u_int32_t ah_enterprise_mode;
782 u_int32_t ah_dc_offset;
783 HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */
784 HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */
785 u_int32_t ah_disable_cck;
786 HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */
790 * Different types of memory where the calibration data might be stored.
791 * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp.
792 * To disable searching a type, set its parameter to 0.
798 #ifdef ATH_CAL_NAND_FLASH
802 * This is where we found the calibration data.
804 int calibration_data_source;
805 int calibration_data_source_address;
807 * This is where we look for the calibration data. must be set before ath_attach() is called
809 int calibration_data_try;
810 int calibration_data_try_address;
812 tx_iq_cal_enable : 1,
813 tx_iq_cal_during_agc_cal : 1,
814 tx_cl_cal_enable : 1;
818 HAL_BOOL ah_mci_ready;
819 u_int32_t ah_mci_int_raw;
820 u_int32_t ah_mci_int_rx_msg;
821 u_int32_t ah_mci_rx_status;
822 u_int32_t ah_mci_cont_status;
823 u_int8_t ah_mci_bt_state;
824 u_int32_t ah_mci_gpm_addr;
825 u_int8_t *ah_mci_gpm_buf;
826 u_int32_t ah_mci_gpm_len;
827 u_int32_t ah_mci_gpm_idx;
828 u_int32_t ah_mci_sched_addr;
829 u_int8_t *ah_mci_sched_buf;
830 u_int8_t ah_mci_coex_major_version_wlan;
831 u_int8_t ah_mci_coex_minor_version_wlan;
832 u_int8_t ah_mci_coex_major_version_bt;
833 u_int8_t ah_mci_coex_minor_version_bt;
834 HAL_BOOL ah_mci_coex_bt_version_known;
835 HAL_BOOL ah_mci_coex_wlan_channels_update;
836 u_int32_t ah_mci_coex_wlan_channels[4];
837 HAL_BOOL ah_mci_coex_2g5g_update;
838 HAL_BOOL ah_mci_coex_is_2g;
839 HAL_BOOL ah_mci_query_bt;
840 HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */
841 HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */
842 HAL_BOOL ah_mci_need_flush_btinfo;
843 HAL_BOOL ah_mci_concur_tx_en;
844 u_int8_t ah_mci_stomp_low_tx_pri;
845 u_int8_t ah_mci_stomp_all_tx_pri;
846 u_int8_t ah_mci_stomp_none_tx_pri;
847 u_int32_t ah_mci_wlan_cal_seq;
848 u_int32_t ah_mci_wlan_cal_done;
850 HAL_BOOL ah_aic_enabled;
851 u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL];
854 #endif /* ATH_SUPPORT_MCI */
855 u_int8_t ah_cac_quiet_enabled;
857 u_int32_t ah_mcast_filter_l32_set;
858 u_int32_t ah_mcast_filter_u32_set;
860 HAL_BOOL ah_reduced_self_gen_mask;
861 HAL_BOOL ah_chip_reset_done;
862 HAL_BOOL ah_abort_txdma_norx;
863 /* store previous passive RX Cal info */
864 HAL_BOOL ah_skip_rx_iq_cal;
865 HAL_BOOL ah_rx_cal_complete; /* previous rx cal completed or not */
866 u_int32_t ah_rx_cal_chan; /* chan on which rx cal is done */
867 u_int32_t ah_rx_cal_chan_flag;
868 u_int32_t ah_rx_cal_corr[AR9300_MAX_CHAINS];
870 /* Local additions for FreeBSD */
872 * These fields are in the top level HAL in the atheros
873 * codebase; here we place them in the AR9300 HAL and
874 * access them via accessor methods if the driver requires them.
876 u_int32_t ah_ob_db1[3];
878 u_int32_t ah_bb_panic_timeout_ms;
879 u_int32_t ah_bb_panic_last_status;
880 u_int32_t ah_tx_trig_level;
881 u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2];
882 int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */
883 int ah_phyrestart_disabled;
884 HAL_RSSI_TX_POWER green_tx_status;
886 int ah_enable_keysearch_always;
891 struct ar9300NfLimits nf_2GHz;
892 struct ar9300NfLimits nf_5GHz;
893 struct ar9300NfLimits *nfp;
896 #define AH9300(_ah) ((struct ath_hal_9300 *)(_ah))
898 #define IS_9300_EMU(ah) \
899 (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE)
901 #define ar9300_eep_data_in_flash(_ah) \
902 (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM))
905 // Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents.
907 ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \
908 (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G))))
912 * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows
913 * other cards' DMA reads to complete in the middle of our reset.
915 #define WAR_6773(x) do { \
916 if ((++(x) % 64) == 0) \
920 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
922 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
923 OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\
928 #define UPPER_5G_SUB_BANDSTART 5700
929 #define MID_5G_SUB_BANDSTART 5400
930 #define TRAINPOWER_DB_OFFSET 6
932 #define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \
934 if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \
935 else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \
936 { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \
937 else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0)
940 #define ar9300FeatureNotSupported(feature, ah, func) \
941 ath_hal_printf(ah, # feature \
942 " not supported but called from %s\n", (func)), \
945 #define ar9300FeatureNotSupported(feature, ah, func) \
946 ath_hal_printf(ah, # feature \
947 " not supported but called from %s\n", (func))
948 #endif /* AH_ASSERT */
951 * Green Tx, Based on different RSSI of Received Beacon thresholds,
952 * using different tx power by modified register tx power related values.
953 * The thresholds are decided by system team.
955 #define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */
956 #define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */
957 #define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta
958 Calibration Offset */
959 #define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value
961 #define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value
962 in middle distance */
963 #define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value
965 #define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx
969 #define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx
975 /* Tx power for short distacnce in SwGreenTx.*/
976 static const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = {
977 6, /*ALL_TARGET_LEGACY_6_24*/
978 6, /*ALL_TARGET_LEGACY_36*/
979 6, /*ALL_TARGET_LEGACY_48*/
980 4, /*ALL_TARGET_LEGACY_54*/
981 6, /*ALL_TARGET_LEGACY_1L_5L*/
982 6, /*ALL_TARGET_LEGACY_5S*/
983 6, /*ALL_TARGET_LEGACY_11L*/
984 6, /*ALL_TARGET_LEGACY_11S*/
985 6, /*ALL_TARGET_HT20_0_8_16*/
986 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
987 4, /*ALL_TARGET_HT20_4*/
988 4, /*ALL_TARGET_HT20_5*/
989 4, /*ALL_TARGET_HT20_6*/
990 2, /*ALL_TARGET_HT20_7*/
991 0, /*ALL_TARGET_HT20_12*/
992 0, /*ALL_TARGET_HT20_13*/
993 0, /*ALL_TARGET_HT20_14*/
994 0, /*ALL_TARGET_HT20_15*/
995 0, /*ALL_TARGET_HT20_20*/
996 0, /*ALL_TARGET_HT20_21*/
997 0, /*ALL_TARGET_HT20_22*/
998 0, /*ALL_TARGET_HT20_23*/
999 6, /*ALL_TARGET_HT40_0_8_16*/
1000 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
1001 4, /*ALL_TARGET_HT40_4*/
1002 4, /*ALL_TARGET_HT40_5*/
1003 4, /*ALL_TARGET_HT40_6*/
1004 2, /*ALL_TARGET_HT40_7*/
1005 0, /*ALL_TARGET_HT40_12*/
1006 0, /*ALL_TARGET_HT40_13*/
1007 0, /*ALL_TARGET_HT40_14*/
1008 0, /*ALL_TARGET_HT40_15*/
1009 0, /*ALL_TARGET_HT40_20*/
1010 0, /*ALL_TARGET_HT40_21*/
1011 0, /*ALL_TARGET_HT40_22*/
1012 0 /*ALL_TARGET_HT40_23*/
1015 /* Tx power for middle distacnce in SwGreenTx.*/
1016 static const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = {
1017 14, /*ALL_TARGET_LEGACY_6_24*/
1018 14, /*ALL_TARGET_LEGACY_36*/
1019 14, /*ALL_TARGET_LEGACY_48*/
1020 12, /*ALL_TARGET_LEGACY_54*/
1021 14, /*ALL_TARGET_LEGACY_1L_5L*/
1022 14, /*ALL_TARGET_LEGACY_5S*/
1023 14, /*ALL_TARGET_LEGACY_11L*/
1024 14, /*ALL_TARGET_LEGACY_11S*/
1025 14, /*ALL_TARGET_HT20_0_8_16*/
1026 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
1027 14, /*ALL_TARGET_HT20_4*/
1028 14, /*ALL_TARGET_HT20_5*/
1029 12, /*ALL_TARGET_HT20_6*/
1030 10, /*ALL_TARGET_HT20_7*/
1031 0, /*ALL_TARGET_HT20_12*/
1032 0, /*ALL_TARGET_HT20_13*/
1033 0, /*ALL_TARGET_HT20_14*/
1034 0, /*ALL_TARGET_HT20_15*/
1035 0, /*ALL_TARGET_HT20_20*/
1036 0, /*ALL_TARGET_HT20_21*/
1037 0, /*ALL_TARGET_HT20_22*/
1038 0, /*ALL_TARGET_HT20_23*/
1039 14, /*ALL_TARGET_HT40_0_8_16*/
1040 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
1041 14, /*ALL_TARGET_HT40_4*/
1042 14, /*ALL_TARGET_HT40_5*/
1043 12, /*ALL_TARGET_HT40_6*/
1044 10, /*ALL_TARGET_HT40_7*/
1045 0, /*ALL_TARGET_HT40_12*/
1046 0, /*ALL_TARGET_HT40_13*/
1047 0, /*ALL_TARGET_HT40_14*/
1048 0, /*ALL_TARGET_HT40_15*/
1049 0, /*ALL_TARGET_HT40_20*/
1050 0, /*ALL_TARGET_HT40_21*/
1051 0, /*ALL_TARGET_HT40_22*/
1052 0 /*ALL_TARGET_HT40_23*/
1055 /* OLPC DeltaCalibration Offset unit in half dB.*/
1056 static const u_int8_t wb225_gtx_olpc_cal_offset[6] = {
1066 * Definitions for HwGreenTx
1068 #define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */
1069 #define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */
1070 #define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx
1071 BB_powertx_rate9 reg
1074 #define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx
1075 BB_powertx_rate9 reg
1079 /* Tx power for short distacnce in HwGreenTx.*/
1080 static const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = {
1081 14, /*ALL_TARGET_LEGACY_6_24*/
1082 14, /*ALL_TARGET_LEGACY_36*/
1083 8, /*ALL_TARGET_LEGACY_48*/
1084 2, /*ALL_TARGET_LEGACY_54*/
1085 14, /*ALL_TARGET_LEGACY_1L_5L*/
1086 14, /*ALL_TARGET_LEGACY_5S*/
1087 14, /*ALL_TARGET_LEGACY_11L*/
1088 14, /*ALL_TARGET_LEGACY_11S*/
1089 12, /*ALL_TARGET_HT20_0_8_16*/
1090 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
1091 12, /*ALL_TARGET_HT20_4*/
1092 12, /*ALL_TARGET_HT20_5*/
1093 8, /*ALL_TARGET_HT20_6*/
1094 2, /*ALL_TARGET_HT20_7*/
1095 0, /*ALL_TARGET_HT20_12*/
1096 0, /*ALL_TARGET_HT20_13*/
1097 0, /*ALL_TARGET_HT20_14*/
1098 0, /*ALL_TARGET_HT20_15*/
1099 0, /*ALL_TARGET_HT20_20*/
1100 0, /*ALL_TARGET_HT20_21*/
1101 0, /*ALL_TARGET_HT20_22*/
1102 0, /*ALL_TARGET_HT20_23*/
1103 10, /*ALL_TARGET_HT40_0_8_16*/
1104 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
1105 10, /*ALL_TARGET_HT40_4*/
1106 10, /*ALL_TARGET_HT40_5*/
1107 6, /*ALL_TARGET_HT40_6*/
1108 2, /*ALL_TARGET_HT40_7*/
1109 0, /*ALL_TARGET_HT40_12*/
1110 0, /*ALL_TARGET_HT40_13*/
1111 0, /*ALL_TARGET_HT40_14*/
1112 0, /*ALL_TARGET_HT40_15*/
1113 0, /*ALL_TARGET_HT40_20*/
1114 0, /*ALL_TARGET_HT40_21*/
1115 0, /*ALL_TARGET_HT40_22*/
1116 0 /*ALL_TARGET_HT40_23*/
1119 /* Tx power for middle distacnce in HwGreenTx.*/
1120 static const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = {
1121 18, /*ALL_TARGET_LEGACY_6_24*/
1122 18, /*ALL_TARGET_LEGACY_36*/
1123 14, /*ALL_TARGET_LEGACY_48*/
1124 12, /*ALL_TARGET_LEGACY_54*/
1125 18, /*ALL_TARGET_LEGACY_1L_5L*/
1126 18, /*ALL_TARGET_LEGACY_5S*/
1127 18, /*ALL_TARGET_LEGACY_11L*/
1128 18, /*ALL_TARGET_LEGACY_11S*/
1129 16, /*ALL_TARGET_HT20_0_8_16*/
1130 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/
1131 16, /*ALL_TARGET_HT20_4*/
1132 16, /*ALL_TARGET_HT20_5*/
1133 14, /*ALL_TARGET_HT20_6*/
1134 12, /*ALL_TARGET_HT20_7*/
1135 0, /*ALL_TARGET_HT20_12*/
1136 0, /*ALL_TARGET_HT20_13*/
1137 0, /*ALL_TARGET_HT20_14*/
1138 0, /*ALL_TARGET_HT20_15*/
1139 0, /*ALL_TARGET_HT20_20*/
1140 0, /*ALL_TARGET_HT20_21*/
1141 0, /*ALL_TARGET_HT20_22*/
1142 0, /*ALL_TARGET_HT20_23*/
1143 14, /*ALL_TARGET_HT40_0_8_16*/
1144 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/
1145 14, /*ALL_TARGET_HT40_4*/
1146 14, /*ALL_TARGET_HT40_5*/
1147 14, /*ALL_TARGET_HT40_6*/
1148 12, /*ALL_TARGET_HT40_7*/
1149 0, /*ALL_TARGET_HT40_12*/
1150 0, /*ALL_TARGET_HT40_13*/
1151 0, /*ALL_TARGET_HT40_14*/
1152 0, /*ALL_TARGET_HT40_15*/
1153 0, /*ALL_TARGET_HT40_20*/
1154 0, /*ALL_TARGET_HT40_21*/
1155 0, /*ALL_TARGET_HT40_22*/
1156 0 /*ALL_TARGET_HT40_23*/
1159 /* MIMO Modes used in TPC calculations */
1161 AR9300_DEF_MODE = 0, /* Could be CDD or Direct */
1166 POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */
1167 POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */
1168 POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in
1169 * BB_powertx_rate9 reg
1171 POSEIDON_STORED_REG_SZ /* Can not add anymore */
1172 } POSEIDON_STORED_REGS;
1175 POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */
1176 POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */
1177 } POSEIDON_STORED_REGS_G2;
1179 #if AH_NEED_TX_DATA_SWAP
1180 #if AH_NEED_RX_DATA_SWAP
1181 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0)
1183 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0)
1185 #elif AH_NEED_RX_DATA_SWAP
1186 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0)
1188 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0)
1191 extern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *);
1195 extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid,
1196 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
1197 HAL_OPS_CONFIG *ah_config,
1198 HAL_STATUS *status);
1199 extern struct ath_hal * ar9300_attach(u_int16_t devid,
1200 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
1201 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status);
1202 extern void ar9300_detach(struct ath_hal *ah);
1203 extern void ar9300_read_revisions(struct ath_hal *ah);
1204 extern HAL_BOOL ar9300_chip_test(struct ath_hal *ah);
1205 extern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah,
1206 u_int16_t flags, u_int16_t *low, u_int16_t *high);
1207 extern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah);
1209 extern void ar9300_beacon_init(struct ath_hal *ah,
1210 u_int32_t next_beacon, u_int32_t beacon_period,
1211 u_int32_t beacon_period_fraction, HAL_OPMODE opmode);
1212 extern void ar9300_set_sta_beacon_timers(struct ath_hal *ah,
1213 const HAL_BEACON_STATE *);
1215 extern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah);
1216 extern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL);
1217 extern HAL_INT ar9300_get_interrupts(struct ath_hal *ah);
1218 extern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL);
1219 extern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah,
1220 HAL_INT_MITIGATION reg, u_int32_t value);
1221 extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah,
1222 HAL_INT_MITIGATION reg);
1223 extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *);
1224 extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry);
1225 extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry);
1226 extern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah,
1227 const struct ieee80211_channel *chan);
1229 extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *,
1230 u_int16_t entry, const u_int8_t *mac);
1231 extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
1232 const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key);
1233 extern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah);
1234 #if ATH_SUPPORT_KEYPLUMB_WAR
1235 extern HAL_BOOL ar9300_check_key_cache_entry(struct ath_hal *ah, u_int16_t entry,
1236 const HAL_KEYVAL *k, int xorKey);
1239 extern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac);
1240 extern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *);
1241 extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac);
1242 extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *);
1243 extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg);
1245 extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
1247 extern HAL_BOOL ar9300_ant_swcom_sel(struct ath_hal *ah, u_int8_t ops,
1248 u_int32_t *common_tbl1, u_int32_t *common_tbl2);
1249 extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah,
1250 u_int16_t reg_domain, HAL_STATUS *stats);
1251 extern u_int ar9300_get_wireless_modes(struct ath_hal *ah);
1252 extern void ar9300_enable_rf_kill(struct ath_hal *);
1253 extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType);
1254 extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType);
1255 extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio);
1256 extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val);
1257 extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio);
1258 extern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah);
1259 extern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel);
1260 extern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah);
1261 extern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t);
1262 extern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah);
1263 extern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map);
1264 extern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state);
1265 extern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable);
1266 extern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable);
1267 extern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
1268 u_int16_t assoc_id);
1269 extern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *);
1270 extern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *);
1271 extern int ar9300_ppm_get_trigger(struct ath_hal *);
1272 extern u_int32_t ar9300_ppm_force(struct ath_hal *);
1273 extern void ar9300_ppm_un_force(struct ath_hal *);
1274 extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *);
1275 extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t);
1276 extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah);
1277 extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah);
1278 extern u_int64_t ar9300_get_tsf64(struct ath_hal *ah);
1279 extern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah);
1280 extern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf);
1281 extern void ar9300_reset_tsf(struct ath_hal *ah);
1282 extern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet);
1283 extern u_int32_t ar9300_get_random_seed(struct ath_hal *ah);
1284 extern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah);
1285 extern void ar9300_update_mib_mac_stats(struct ath_hal *ah);
1286 extern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats);
1287 extern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah);
1288 extern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah);
1289 extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah);
1290 extern u_int ar9300_get_def_antenna(struct ath_hal *ah);
1291 extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna);
1292 extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah,
1293 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan,
1294 u_int8_t *, u_int8_t *, u_int8_t *);
1295 extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah);
1296 extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int);
1297 extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int);
1298 extern u_int ar9300_get_ack_timeout(struct ath_hal *);
1299 extern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration,
1300 u_int32_t next_start, HAL_QUIET_FLAG flag);
1301 extern void ar9300_set_pcu_config(struct ath_hal *);
1302 extern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE,
1303 u_int32_t, u_int32_t *);
1304 extern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE,
1305 u_int32_t, u_int32_t, HAL_STATUS *);
1306 extern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request,
1307 const void *args, u_int32_t argsize,
1308 void **result, u_int32_t *resultsize);
1309 extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info);
1310 extern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah);
1311 extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode);
1312 extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah);
1313 extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear);
1314 extern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode,
1316 extern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah);
1317 extern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip);
1318 extern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode);
1320 extern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off);
1322 extern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid,
1323 u_int16_t assoc_id);
1327 extern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern,
1328 u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len);
1329 //extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes);
1330 extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable);
1331 extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid,
1332 HAL_BOOL offloadEnable);
1335 #define WOW_OFFLOAD_ARP_INFO_MAX 2
1337 struct hal_wow_offload_arp_info {
1345 } RemoteIPv4Address;
1357 #define WOW_OFFLOAD_NS_INFO_MAX 2
1359 struct hal_wow_offload_ns_info {
1367 } RemoteIPv6Address;
1371 } SolicitedNodeIPv6Address;
1379 } TargetIPv6Addresses[2];
1382 extern void ar9300_wowoffload_prep(struct ath_hal *ah);
1383 extern void ar9300_wowoffload_post(struct ath_hal *ah);
1384 extern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size);
1385 extern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param);
1386 extern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes);
1387 extern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap);
1388 extern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data);
1389 extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data);
1390 #endif /* ATH_WOW_OFFLOAD */
1393 extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode,
1394 struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask,
1395 u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing,
1396 HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan);
1397 extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan,
1398 HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask);
1399 extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type);
1400 extern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan);
1401 extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask);
1402 extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah);
1403 extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode);
1404 extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah);
1405 extern HAL_BOOL ar9300_disable(struct ath_hal *ah);
1406 extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *);
1407 extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan,
1408 u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals);
1409 extern void ar9300_reset_cal_valid(struct ath_hal *ah,
1410 const struct ieee80211_channel *chan,
1411 HAL_BOOL *isIQdone, u_int32_t cal_type);
1412 extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains);
1413 extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains);
1414 extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah);
1415 extern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains);
1416 extern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah);
1417 extern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]);
1419 extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit,
1420 u_int16_t extra_txpow, u_int16_t tpc_in_db);
1421 extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf,
1422 struct ieee80211_channel *chan, int is_scan);
1423 extern int16_t ar9300_get_nf_from_reg(struct ath_hal *ah, struct ieee80211_channel *chan, int wait_time);
1424 extern int ar9300_get_rx_nf_offset(struct ath_hal *ah, struct ieee80211_channel *chan, int8_t *nf_pwr, int8_t *nf_cal);
1425 extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]);
1427 extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah);
1428 extern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode);
1429 extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode,
1430 u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode);
1431 extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode,
1432 const struct ieee80211_channel *chan,
1433 u_int8_t powerPerRate[],
1434 u_int8_t chainmask);
1435 extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah,
1436 u_int8_t powerPerRate[]);
1437 extern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah,
1438 u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power);
1440 extern void ar9300_reset_tx_status_ring(struct ath_hal *ah);
1441 extern void ar9300_enable_mib_counters(struct ath_hal *);
1442 extern void ar9300_disable_mib_counters(struct ath_hal *);
1443 extern void ar9300_ani_attach(struct ath_hal *);
1444 extern void ar9300_ani_detach(struct ath_hal *);
1445 extern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *);
1446 extern struct ar9300_stats *ar9300_ani_get_current_stats(struct ath_hal *);
1447 extern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param);
1448 struct ath_rx_status;
1450 extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *);
1451 extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *,
1452 const struct ieee80211_channel *, HAL_ANISTATS *);
1453 extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning);
1454 extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode);
1455 extern void ar9300_enable_tpc(struct ath_hal *);
1457 extern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz);
1458 extern void ar9300_rx_gain_table_apply(struct ath_hal *ah);
1459 extern void ar9300_tx_gain_table_apply(struct ath_hal *ah);
1460 extern void ar9300_mat_enable(struct ath_hal *ah, int enable);
1461 extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry);
1462 extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan);
1464 /* BB Panic Watchdog declarations */
1465 #define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */
1466 #define HAL_BB_PANIC_WD_TMO_HORNET 85
1467 extern void ar9300_config_bb_panic_watchdog(struct ath_hal *);
1468 extern void ar9300_handle_bb_panic(struct ath_hal *);
1469 extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic);
1470 extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah);
1471 extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason);
1473 /* DFS declarations */
1474 extern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan);
1475 extern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan,
1477 extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
1478 extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
1479 extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan);
1480 extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah,
1481 u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses,
1482 int *numb5radars, HAL_PHYERR_PARAM *pe);
1483 extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val);
1484 extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable);
1485 extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable);
1486 extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start);
1488 extern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah);
1489 extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah);
1492 extern void ar9300_mark_phy_inactive(struct ath_hal *ah);
1494 /* Spectral scan declarations */
1495 extern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss);
1496 extern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62);
1497 extern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss);
1498 extern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah);
1499 extern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah);
1500 extern void ar9300_start_spectral_scan(struct ath_hal *ah);
1501 extern void ar9300_stop_spectral_scan(struct ath_hal *ah);
1502 extern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah);
1503 extern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval);
1504 int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah);
1505 int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah);
1506 /* End spectral scan declarations */
1508 /* Raw ADC capture functions */
1509 extern void ar9300_enable_test_addac_mode(struct ath_hal *ah);
1510 extern void ar9300_disable_test_addac_mode(struct ath_hal *ah);
1511 extern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain);
1512 extern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples);
1513 extern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr);
1514 extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain);
1516 extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode,
1517 struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status);
1518 extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now);
1520 extern void ar9300_get_channel_centers(struct ath_hal *ah,
1521 const struct ieee80211_channel *chan,
1522 CHAN_CENTERS *centers);
1523 extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah,
1524 const struct ieee80211_channel *chan);
1525 extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah,
1526 const struct ieee80211_channel *chan);
1527 extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*);
1529 extern void ar9300_dma_reg_dump(struct ath_hal *);
1530 extern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable);
1531 extern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable);
1532 extern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable);
1533 extern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah);
1534 extern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah);
1537 extern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo);
1538 extern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf);
1539 extern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum);
1540 extern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type);
1541 extern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh);
1542 extern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value);
1543 extern void ar9300_bt_coex_disable(struct ath_hal *ah);
1544 extern int ar9300_bt_coex_enable(struct ath_hal *ah);
1545 extern void ar9300_init_bt_coex(struct ath_hal *ah);
1546 extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg);
1547 extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn);
1549 extern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf);
1550 extern void ar9300_free_generic_timer(struct ath_hal *ah, int index);
1551 extern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next,
1552 u_int32_t timer_period);
1553 extern void ar9300_stop_generic_timer(struct ath_hal *ah, int index);
1554 extern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger,
1556 extern void ar9300_start_tsf2(struct ath_hal *ah);
1558 extern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi);
1559 extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah);
1560 extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah);
1561 extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value);
1562 extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah);
1563 extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah);
1564 extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah);
1565 extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah,
1566 u_int32_t rssi_threshold);
1567 extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah);
1568 extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on);
1569 extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats,
1572 extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq);
1573 extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq);
1574 extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah);
1575 extern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *);
1576 extern void ar9300_clear_mib_counters(struct ath_hal *ah);
1578 /* EEPROM interface functions */
1579 /* Common Interface functions */
1580 extern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *);
1581 extern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param);
1583 extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah,
1584 ar9300_eeprom_t *p_eep_data,
1588 extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah,
1589 ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan,
1590 u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction,
1591 u_int16_t twice_max_regulatory_power, u_int16_t power_limit);
1592 extern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *);
1593 extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value);
1594 extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *);
1595 extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data);
1596 extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
1597 extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi);
1599 extern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data);
1600 extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data);
1601 extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e);
1602 extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band);
1603 extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan,
1604 u_int8_t index, u_int16_t *config);
1605 extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp);
1606 extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz);
1607 extern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah);
1608 extern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah);
1609 extern void ar9300_disp_tpc_tables(struct ath_hal *ah);
1610 extern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah);
1611 extern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max);
1612 extern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel);
1614 /* Common EEPROM Help function */
1615 extern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable);
1616 extern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs);
1618 extern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks);
1620 /* tx_bf interface */
1621 #define ar9300_init_txbf(ah)
1622 #define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt)
1623 #define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt)
1624 #define ar9300_txbf_save_cv_from_compress( \
1625 ah, key_idx, mimo_control, compress_rpt) \
1627 #define ar9300_txbf_save_cv_from_non_compress( \
1628 ah, key_idx, mimo_control, non_compress_rpt) \
1630 #define ar9300_txbf_rc_update( \
1631 ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \
1633 #define ar9300_fill_csi_frame( \
1634 ah, rx_status, bandwidth, local_h, csi_frame_body) \
1636 #define ar9300_fill_txbf_capabilities(ah)
1637 #define ar9300_get_txbf_capabilities(ah) NULL
1638 #define ar9300_txbf_set_key( \
1639 ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss)
1640 #define ar9300_read_key_cache_mac(ah, entry, mac) false
1641 #define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr)
1642 #define ar9300_set_selfgenrate_limit(ah, ts_ratecode)
1643 #define ar9300_reset_lowest_txrate(ah)
1644 #define ar9300_txbf_set_basic_set(ah)
1646 extern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs);
1647 extern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah);
1652 extern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type);
1653 extern void ar9300_mci_bt_coex_disable(struct ath_hal *ah);
1654 extern int ar9300_mci_bt_coex_enable(struct ath_hal *ah);
1655 extern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr,
1656 void *gpm_buf, u_int16_t len,
1657 u_int32_t sched_addr);
1658 extern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done);
1659 extern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done);
1660 extern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done);
1661 extern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header,
1662 u_int32_t flag, u_int32_t *payload, u_int8_t len,
1663 HAL_BOOL wait_done, HAL_BOOL check_bt);
1664 extern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah,
1666 u_int32_t *mci_int_rx_msg);
1667 extern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data);
1668 extern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep);
1669 extern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done);
1670 extern void ar9300_mci_mute_bt(struct ath_hal *ah);
1671 extern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out);
1672 extern void ar9300_mci_enable_interrupt(struct ath_hal *ah);
1673 extern void ar9300_mci_disable_interrupt(struct ath_hal *ah);
1674 extern void ar9300_mci_detach (struct ath_hal *ah);
1675 extern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints);
1676 extern void ar9300_mci_sync_bt_state (struct ath_hal *ah);
1677 extern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g);
1678 extern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done);
1680 extern u_int32_t ar9300_aic_calibration (struct ath_hal *ah);
1681 extern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah);
1685 extern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable);
1687 extern HAL_BOOL ar9300_regulatory_domain_override(
1688 struct ath_hal *ah, u_int16_t regdmn);
1689 #if ATH_ANT_DIV_COMB
1690 extern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf);
1691 extern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf);
1692 #endif /* ATH_ANT_DIV_COMB */
1693 extern void ar9300_disable_phy_restart(struct ath_hal *ah,
1694 int disable_phy_restart);
1695 extern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable);
1696 extern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah);
1697 extern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val);
1698 extern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah);
1700 #ifdef ATH_TX99_DIAG
1701 #ifndef ATH_SUPPORT_HTC
1702 extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower);
1703 extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask);
1704 extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype);
1705 extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data);
1706 extern void ar9300_tx99_stop(struct ath_hal *ah);
1707 #endif /* ATH_SUPPORT_HTC */
1708 #endif /* ATH_TX99_DIAG */
1709 extern HAL_BOOL ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array);
1710 extern void ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask);
1713 AR9300_COEFF_TX_TYPE = 0,
1714 AR9300_COEFF_RX_TYPE
1717 #endif /* _ATH_AR9300_H_ */