2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
20 * Values defined in this file may only be changed under exceptional circumstances.
22 * Please ask Fiona Cain before making any changes.
25 #ifndef __ar9300templateAP121_h__
26 #define __ar9300templateAP121_h__
28 static ar9300_eeprom_t ar9300_template_ap121=
33 ar9300_eeprom_template_ap121, // template_version;
35 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6];
37 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]=
40 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
42 //static OSPREY_BASE_EEP_HEADER base_eep_header=
45 {0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
46 0x11, // txrx_mask; //4 bits tx and 4 bits rx
47 {AR9300_OPFLAGS_11G , 0}, // op_cap_flags;
49 0, // blue_tooth_options;
51 4, // device_type; // takes lower byte in eeprom location
52 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
53 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
54 0x0d, //feature_enable; //bit0 - enable tx temp comp
55 //bit1 - enable tx volt comp
56 //bit2 - enable fastClock - default to 1
57 //bit3 - enable doubling - default to 1
58 //bit4 - enable internal regulator - default to 0
59 //bit5 - enable paprd -- default to 0
60 0, //misc_configuration: bit0 - turn down drivestrength
61 6, // eeprom_write_enable_gpio
62 0, // wlan_disable_gpio
64 0xff, // rx_band_select_gpio
70 //static OSPREY_MODAL_EEP_HEADER modal_header_2g=
73 0x110, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting)
74 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
75 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
76 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
77 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
80 {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
81 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
82 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
84 0, // xpa_bias_lvl; // 1
85 0x0e, // tx_frame_to_data_start; // 1
86 0x0e, // tx_frame_to_pa_on; // 1
87 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
88 0, // antenna_gain; // 1
89 0x2c, // switchSettling; // 1
90 -30, // adcDesiredSize; // 1
91 0, // txEndToXpaOff; // 1
92 0x2, // txEndToRxOn; // 1
93 0xe, // tx_frame_to_xpa_on; // 1
95 0x80c0e0, // paprd_rate_mask_ht20 // 4
96 0x1ffffff, // paprd_rate_mask_ht40
97 0, // switchcomspdt; // 2
98 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
101 {0,0,0,0,0} //futureModal[5];
105 6, // ant_div_control
108 {0,0,0,0,0,0,0,0}, // temp slop extension
110 0, // quick drop high
112 //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]=
119 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]=
121 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
122 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
123 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
126 //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
133 //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS]
140 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]
147 //static OSP_CAL_TARGET_POWER_HT cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]
154 //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]=
161 //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]=
169 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]=
171 //0_8_16,1-3_9-11_17-19,
172 // 4,5,6,7,12,13,14,15,20,21,22,23
173 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}},
174 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}},
175 {{32,32,32,32,32,30,32,32,30,28,28,28,28,24}},
178 //static OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]=
180 //0_8_16,1-3_9-11_17-19,
181 // 4,5,6,7,12,13,14,15,20,21,22,23
182 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}},
183 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}},
184 {{30,30,30,30,30,28,30,30,28,26,26,26,26,22}},
187 //static A_UINT8 ctl_index_2g[OSPREY_NUM_CTLS_2G]=
206 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
229 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
230 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
231 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
232 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)},
234 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
235 /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
236 /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
239 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
240 /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
244 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1),
245 /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1),
246 /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1),
247 /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)},
249 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
250 /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
251 /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
254 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
255 /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
256 /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
259 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
260 /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
261 /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
264 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1),
265 /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1),
266 /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1),
267 /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}
271 //OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G];
273 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
276 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
277 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
278 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}},
280 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}},
281 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
282 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
284 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}},
285 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
286 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
288 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
289 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
294 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
295 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
296 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
298 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}},
299 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
300 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
302 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
304 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
306 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
307 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
311 //static OSPREY_MODAL_EEP_HEADER modal_header_5g=
315 0x220, // ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting)
316 0x44444, // ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
317 {0x150,0x150,0x150}, // ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
318 {0,0,0}, // xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
319 {0,0,0}, // xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
322 {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
323 {-1,0,0}, // noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
324 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
326 0, // xpa_bias_lvl; // 1
327 0x0e, // tx_frame_to_data_start; // 1
328 0x0e, // tx_frame_to_pa_on; // 1
329 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
330 0, // antenna_gain; // 1
331 0x2d, // switchSettling; // 1
332 -30, // adcDesiredSize; // 1
333 0, // txEndToXpaOff; // 1
334 0x2, // txEndToRxOn; // 1
335 0xe, // tx_frame_to_xpa_on; // 1
336 28, // thresh62; // 1
337 0xf0e0e0, // paprd_rate_mask_ht20 // 4
338 0xf0e0e0, // paprd_rate_mask_ht40 // 4
339 0, // switchcomspdt; // 2
340 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
343 {0,0,0,0,0} //futureModal[5];
347 40, // temp_slope_low
348 50, // temp_slope_high
355 //static A_UINT8 cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]=
375 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]=
378 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
379 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
380 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
384 //static CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]=
397 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]=
410 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]=
424 //static CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]=
439 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]=
442 //0_8_16,1-3_9-11_17-19,
443 // 4,5,6,7,12,13,14,15,20,21,22,23
444 {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}},
445 {{30,30,30,28,24,20,30,28,24,20,20,20,20,16}},
446 {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}},
447 {{30,30,30,26,22,18,30,26,22,18,18,18,18,16}},
448 {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}},
449 {{30,30,30,24,20,16,30,24,20,16,16,16,16,14}},
450 {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}},
451 {{30,30,30,22,18,14,30,22,18,14,14,14,14,12}},
454 //static OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]=
456 //0_8_16,1-3_9-11_17-19,
457 // 4,5,6,7,12,13,14,15,20,21,22,23
458 {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}},
459 {{28,28,28,26,22,18,28,26,22,18,18,18,18,14}},
460 {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}},
461 {{28,28,28,24,20,16,28,24,20,16,16,16,16,12}},
462 {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}},
463 {{28,28,28,22,18,14,28,22,18,14,14,14,14,10}},
464 {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}},
465 {{28,28,28,20,16,12,28,20,16,12,12,12,12,8}},
468 //static A_UINT8 ctl_index_5g[OSPREY_NUM_CTLS_5G]=
491 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
494 {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
495 /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
496 /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0),
497 /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
498 /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0),
499 /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
500 /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0),
501 /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)},
503 {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
504 /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
505 /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0),
506 /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
507 /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0),
508 /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
509 /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0),
510 /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)},
512 {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0),
513 /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0),
514 /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0),
515 /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0),
516 /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0),
517 /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0),
518 /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0),
519 /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)},
521 {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
522 /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0),
523 /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0),
524 /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0),
525 /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
526 /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
527 /* Data[3].ctl_edges[6].bChannel*/0xFF,
528 /* Data[3].ctl_edges[7].bChannel*/0xFF},
530 {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
531 /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
532 /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
533 /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0),
534 /* Data[4].ctl_edges[4].bChannel*/0xFF,
535 /* Data[4].ctl_edges[5].bChannel*/0xFF,
536 /* Data[4].ctl_edges[6].bChannel*/0xFF,
537 /* Data[4].ctl_edges[7].bChannel*/0xFF},
539 {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0),
540 /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0),
541 /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0),
542 /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0),
543 /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0),
544 /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0),
545 /* Data[5].ctl_edges[6].bChannel*/0xFF,
546 /* Data[5].ctl_edges[7].bChannel*/0xFF},
548 {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
549 /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0),
550 /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0),
551 /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0),
552 /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
553 /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0),
554 /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0),
555 /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)},
557 {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
558 /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
559 /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0),
560 /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
561 /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0),
562 /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
563 /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0),
564 /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)},
566 {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0),
567 /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0),
568 /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0),
569 /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0),
570 /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0),
571 /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0),
572 /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0),
573 /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)}
576 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]=
578 #if AH_BYTE_ORDER == AH_BIG_ENDIAN