2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
20 * Values defined in this file may only be changed under exceptional circumstances.
22 * Please ask Fiona Cain before making any changes.
25 #ifndef __ar9300template_cus157_h__
26 #define __ar9300template_cus157_h__
28 static ar9300_eeprom_t Ar9300Template_cus157=
33 ar9300_eeprom_template_cus157, // templateVersion;
35 {0x00,0x03,0x7f,0x0,0x0,0x0}, //macAddr[6];
37 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]=
40 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
42 //static OSPREY_BASE_EEP_HEADER baseEepHeader=
45 {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
46 0x77, // txrxMask; //4 bits tx and 4 bits rx
47 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags;
49 0, // blueToothOptions;
51 5, // deviceType; // takes lower byte in eeprom location
52 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
53 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
54 0x0d, //featureEnable; //bit0 - enable tx temp comp
55 //bit1 - enable tx volt comp
56 //bit2 - enable fastClock - default to 1
57 //bit3 - enable doubling - default to 1
58 //bit4 - enable internal regulator - default to 0
59 //bit5 - enable paprd -- default to 0
60 0, //miscConfiguration: bit0 - turn down drivestrength
61 6, // eepromWriteEnableGpio
64 0xff, // rxBandSelectGpio
70 //static OSPREY_MODAL_EEP_HEADER modalHeader2G=
73 0x110, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting)
74 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
75 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
76 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
77 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
80 {FREQ2FBIN(2464, 1),0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
81 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
82 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
84 0, // xpaBiasLvl; // 1
85 0x0e, // txFrameToDataStart; // 1
86 0x0e, // txFrameToPaOn; // 1
87 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
88 0, // antennaGain; // 1
89 0x2c, // switchSettling; // 1
90 -30, // adcDesiredSize; // 1
91 0, // txEndToXpaOff; // 1
92 0x2, // txEndToRxOn; // 1
93 0xe, // txFrameToXpaOn; // 1
95 0x80C080, // paprdRateMaskHt20 // 4
96 0x80C080, // paprdRateMaskHt40
98 {0,0,0,0,0,0,0,0,0} //futureModal[9];
101 {{0,0,0,0,0,0,0,0,0,0,0,0,0,0}}, // base_ext1
103 //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]=
110 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]=
112 { {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
113 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
114 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
117 //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
124 //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS]
131 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]
138 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]
145 //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]=
152 //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]=
160 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]=
162 //0_8_16,1-3_9-11_17-19,
163 // 4,5,6,7,12,13,14,15,20,21,22,23
164 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}},
165 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}},
166 {{32,32,32,32,30,30,32,32,30,30,32,32,30,30}},
169 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]=
171 //0_8_16,1-3_9-11_17-19,
172 // 4,5,6,7,12,13,14,15,20,21,22,23
173 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}},
174 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}},
175 {{30,30,30,30,30,28,30,30,28,28,30,30,28,26}},
178 //static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]=
197 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
220 {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
221 /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
222 /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
223 /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)},
225 {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
226 /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
227 /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
230 {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
231 /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
235 {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
236 /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
237 /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
238 /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)},
240 {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
241 /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
242 /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
245 {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
246 /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
247 /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
250 {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
251 /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
252 /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
255 {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
256 /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
257 /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
258 /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}
262 //OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G];
264 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
267 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
268 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
269 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}},
271 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}},
272 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
273 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
275 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}},
276 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
277 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
279 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
280 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
281 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
286 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
287 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
288 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
290 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}},
291 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
292 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
294 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
295 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
296 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
298 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
299 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
300 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
304 //static OSPREY_MODAL_EEP_HEADER modalHeader5G=
308 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting)
309 0x44444, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
310 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
311 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
312 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
315 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
316 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
317 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
319 0, // xpaBiasLvl; // 1
320 0x0e, // txFrameToDataStart; // 1
321 0x0e, // txFrameToPaOn; // 1
322 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
323 0, // antennaGain; // 1
324 0x2d, // switchSettling; // 1
325 -30, // adcDesiredSize; // 1
326 0, // txEndToXpaOff; // 1
327 0x2, // txEndToRxOn; // 1
328 0xe, // txFrameToXpaOn; // 1
329 28, // thresh62; // 1
330 0xf0e0e0, // paprdRateMaskHt20 // 4
331 0xf0e0e0, // paprdRateMaskHt40 // 4
332 {0,0,0,0,0,0,0,0,0,0} //futureModal[10];
344 //static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]=
364 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]=
367 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
368 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
369 {{0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}, {0,0,0,0,0,0}},
373 //static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
386 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
399 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
413 //static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
428 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
431 //0_8_16,1-3_9-11_17-19,
432 // 4,5,6,7,12,13,14,15,20,21,22,23
433 {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}},
434 {{30,30,30,28,24,20,30,28,24,18,30,26,22,16}},
435 {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}},
436 {{30,30,30,26,22,18,30,26,22,16,30,24,20,14}},
437 {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}},
438 {{30,30,30,24,20,16,30,24,20,14,30,22,18,12}},
439 {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}},
440 {{28,28,28,22,18,14,28,22,18,12,28,20,16,10}},
443 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
445 //0_8_16,1-3_9-11_17-19,
446 // 4,5,6,7,12,13,14,15,20,21,22,23
447 {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}},
448 {{28,28,28,26,22,18,28,24,20,16,20,16,16,16}},
449 {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}},
450 {{28,28,28,28,24,20,28,28,24,20,22,20,20,20}},
451 {{28,28,28,24,20,16,28,24,20,16,18,16,16,16}},
452 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}},
453 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}},
454 {{28,28,28,22,18,14,22,20,16,12,14,12,12,10}},
457 //static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]=
480 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
483 {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
484 /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
485 /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
486 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
487 /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0),
488 /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
489 /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
490 /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
492 {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
493 /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
494 /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
495 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
496 /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0),
497 /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
498 /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
499 /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
501 {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
502 /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
503 /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
504 /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0),
505 /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0),
506 /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0),
507 /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0),
508 /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)},
510 {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
511 /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
512 /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0),
513 /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0),
514 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
515 /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
516 /* Data[3].ctlEdges[6].bChannel*/0xFF,
517 /* Data[3].ctlEdges[7].bChannel*/0xFF},
519 {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
520 /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
521 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
522 /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0),
523 /* Data[4].ctlEdges[4].bChannel*/0xFF,
524 /* Data[4].ctlEdges[5].bChannel*/0xFF,
525 /* Data[4].ctlEdges[6].bChannel*/0xFF,
526 /* Data[4].ctlEdges[7].bChannel*/0xFF},
528 {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
529 /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0),
530 /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0),
531 /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
532 /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0),
533 /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
534 /* Data[5].ctlEdges[6].bChannel*/0xFF,
535 /* Data[5].ctlEdges[7].bChannel*/0xFF},
537 {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
538 /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
539 /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0),
540 /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0),
541 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
542 /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0),
543 /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0),
544 /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)},
546 {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
547 /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
548 /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0),
549 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
550 /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0),
551 /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
552 /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
553 /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
555 {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
556 /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
557 /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
558 /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
559 /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0),
560 /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
561 /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0),
562 /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)}
565 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]=
567 #if AH_BYTE_ORDER == AH_BIG_ENDIAN