2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
20 * Values defined in this file may only be changed under exceptional circumstances.
22 * Please ask Fiona Cain before making any changes.
25 #ifndef __ar9300templateOsprey_k31_h__
26 #define __ar9300templateOsprey_k31_h__
28 static ar9300_eeprom_t ar9300_template_osprey_k31=
33 ar9300_eeprom_template_osprey_k31, // templateVersion;
35 //NC, Mac Address Colon from HB116
36 {0,3,0x7f,41,22,0xb4}, //macAddr[6];
38 //static A_UINT8 custData[OSPREY_CUSTOMER_DATA_SIZE]=
40 //NC, No Serial Number
41 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
43 //static OSPREY_BASE_EEP_HEADER baseEepHeader=
46 {0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
47 0x33, // txrxMask; //4 bits tx and 4 bits rx
48 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags;
50 0, // blueToothOptions;
52 5, // deviceType; // takes lower byte in eeprom location
53 OSPREY_PWR_TABLE_OFFSET, // pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
54 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
55 0x1d, //featureEnable; //bit0 - enable tx temp comp
56 //bit1 - enable tx volt comp
57 //bit2 - enable fastClock - default to 1
58 //bit3 - enable doubling - default to 1
59 //bit4 - enable internal regulator - default to 0
60 0, //miscConfiguration: bit0 - turn down drivestrength
61 6, // eepromWriteEnableGpio
64 0xff, // rxBandSelectGpio
70 //static OSPREY_MODAL_EEP_HEADER modalHeader2G=
73 0x110, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting)
74 0xeeeee, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
75 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
76 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
77 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
80 {0xa4,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
81 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
82 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
84 0xf, // xpaBiasLvl; // 1
85 0x0e, // txFrameToDataStart; // 1
86 0x0e, // txFrameToPaOn; // 1
87 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
88 0, // antennaGain; // 1
89 0x2c, // switchSettling; // 1
90 -30, // adcDesiredSize; // 1
91 0, // txEndToXpaOff; // 1
92 0x2, // txEndToRxOn; // 1
93 0xe, // txFrameToXpaOn; // 1
95 0x0c80C080, // papdRateMaskHt20 // 4
96 0x0080C080, // papdRateMaskHt40
97 0, // switchcomspdt; // 2
98 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
101 {0,0,0,0,0} //futureModal[5];
105 0, // ant_div_control
108 {0,0,0,0,0,0,0,0}, // temp slop extension
110 0, // quick drop high
114 //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]=
121 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]=
123 { {{235,0,148,150,162,0}, {235,0,147,150,163,0}, {235,0,147,150,163,0}},
124 {{232,0,147,148,162,0}, {233,0,147,148,163,0}, {234,0,147,148,163,0}},
125 {{0,0,0,136,162,0}, {0,0,0,136,163,0}, {0,0,0,136,163,0}},
128 //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
135 //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS]
142 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]
149 //static OSP_CAL_TARGET_POWER_HT calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]
156 //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]=
163 //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]=
171 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]=
173 //0_8_16,1-3_9-11_17-19,
174 // 4,5,6,7,12,13,14,15,20,21,22,23
175 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}},
176 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}},
177 {{32,32,32,32,32,30,32,32,30,28,0,0,0,0}},
180 //static OSP_CAL_TARGET_POWER_HT calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]=
182 //0_8_16,1-3_9-11_17-19,
183 // 4,5,6,7,12,13,14,15,20,21,22,23
184 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}},
185 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}},
186 {{30,30,30,30,30,28,30,30,28,26,0,0,0,0}},
189 //static A_UINT8 ctlIndex_2G[OSPREY_NUM_CTLS_2G]=
208 //A_UINT8 ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
231 {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
232 /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
233 /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
234 /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)},
236 {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
237 /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
238 /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
241 {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
242 /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
246 {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
247 /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
248 /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
249 /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)},
251 {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
252 /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
253 /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
256 {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
257 /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
258 /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
261 {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
262 /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
263 /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
266 {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
267 /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
268 /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
269 /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}
273 //OSP_CAL_CTL_DATA_2G ctlPowerData_2G[OSPREY_NUM_CTLS_2G];
275 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
278 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
279 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
280 {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}},
282 {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}},
283 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
284 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
286 {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}},
287 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
288 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
290 {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
291 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
292 {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
297 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
298 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
299 {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
301 {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}},
302 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
303 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
305 {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
306 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
307 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
309 {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
310 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
311 {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
315 //static OSPREY_MODAL_EEP_HEADER modalHeader5G=
319 0x220, // antCtrlCommon; // 4 idle, t1, t2, b (4 bits per setting)
320 0x11111, // antCtrlCommon2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
321 {0x150,0x150,0x150}, // antCtrlChain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
322 {0,0,0}, // xatten1DB[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
323 {0,0,0}, // xatten1Margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
326 {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
327 {-1,0,0}, // noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3 //Check if the register is per chain
328 {0, 0, 0, 0, 0, 0,0,0,0,0,0}, // reserved
330 0, // xpaBiasLvl; // 1
331 0x0e, // txFrameToDataStart; // 1
332 0x0e, // txFrameToPaOn; // 1
333 3, // txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
334 0, // antennaGain; // 1
335 0x2d, // switchSettling; // 1
336 -30, // adcDesiredSize; // 1
337 0, // txEndToXpaOff; // 1
338 0x2, // txEndToRxOn; // 1
339 0xe, // txFrameToXpaOn; // 1
340 28, // thresh62; // 1
341 0x0cf0e0e0, // papdRateMaskHt20 // 4
342 0x6cf0e0e0, // papdRateMaskHt40 // 4
343 0, // switchcomspdt; // 2
344 0, // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
347 {0,0,0,0,0} //futureModal[5];
359 //static A_UINT8 calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]=
379 //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]=
382 {{170,0,149,0,0,0},{170,0,149,147,167,0},{170,0,149,0,0,0},{170,0,147,0,0,0}, {170,0,146,148,164,0}, {170,0,146,0,0,0}, {170,0,147,145,163,0}, {170,0,146,143,162,0}},
383 {{170,0,149,0,0,0},{170,0,149,147,167,0},{170,0,149,0,0,0},{170,0,147,0,0,0}, {170,0,146,148,164,0}, {170,0,146,0,0,0}, {170,0,147,145,163,0}, {170,0,146,143,162,0}},
384 {{0,0,0,0,0,0}, {0,0,0,136,167,0},{0,0,0,0,0}, {0,0,0,0,0}, {0 ,0,0 ,137,164,0}, {0,0,0,0,0}, {0 ,0,0 ,136,163,0}, {0 ,0,0 ,136,162,0}},
388 //static CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
401 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
414 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
428 //static CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
443 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
446 //0_8_16,1-3_9-11_17-19,
447 // 4,5,6,7,12,13,14,15,20,21,22,23
448 {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}},
449 {{30,30,30,28,24,20,30,28,24,20,0,0,0,0}},
450 {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}},
451 {{30,30,30,26,22,18,30,26,22,18,0,0,0,0}},
452 {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}},
453 {{30,30,30,24,20,16,30,24,20,16,0,0,0,0}},
454 {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}},
455 {{30,30,30,22,18,14,30,22,18,14,0,0,0,0}},
458 //static OSP_CAL_TARGET_POWER_HT calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
460 //0_8_16,1-3_9-11_17-19,
461 // 4,5,6,7,12,13,14,15,20,21,22,23
462 {{28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0}},
463 {{28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0}},
464 {{28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0}},
465 {{28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0}},
466 {{28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0}},
467 {{28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0}},
468 {{28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0}},
469 {{28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0}},
472 //static A_UINT8 ctlIndex_5G[OSPREY_NUM_CTLS_5G]=
495 // A_UINT8 ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
498 {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
499 /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
500 /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
501 /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
502 /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0),
503 /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
504 /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
505 /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
507 {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
508 /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
509 /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
510 /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
511 /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0),
512 /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
513 /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
514 /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
516 {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
517 /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
518 /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
519 /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0),
520 /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0),
521 /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0),
522 /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0),
523 /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)},
525 {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
526 /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
527 /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0),
528 /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0),
529 /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
530 /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
531 /* Data[3].ctlEdges[6].bChannel*/0xFF,
532 /* Data[3].ctlEdges[7].bChannel*/0xFF},
534 {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
535 /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
536 /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
537 /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0),
538 /* Data[4].ctlEdges[4].bChannel*/0xFF,
539 /* Data[4].ctlEdges[5].bChannel*/0xFF,
540 /* Data[4].ctlEdges[6].bChannel*/0xFF,
541 /* Data[4].ctlEdges[7].bChannel*/0xFF},
543 {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
544 /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0),
545 /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0),
546 /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
547 /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0),
548 /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
549 /* Data[5].ctlEdges[6].bChannel*/0xFF,
550 /* Data[5].ctlEdges[7].bChannel*/0xFF},
552 {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
553 /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
554 /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0),
555 /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0),
556 /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
557 /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0),
558 /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0),
559 /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)},
561 {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
562 /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
563 /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0),
564 /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
565 /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0),
566 /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
567 /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
568 /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
570 {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
571 /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
572 /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
573 /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
574 /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0),
575 /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
576 /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0),
577 /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)}
580 //static OSP_CAL_CTL_DATA_5G ctlData_5G[OSPREY_NUM_CTLS_5G]=
582 #if AH_BYTE_ORDER == AH_BIG_ENDIAN