sys/contrib/dev/ath/ath_hal/ar9300/ar9300template_wasp_2.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
   9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
  11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  14  * PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 /*
  18  * READ THIS NOTICE!
  19  *
  20  * Values defined in this file may only be changed under exceptional circumstances.
  21  *
  22  * Please ask Fiona Cain before making any changes.
  23  */
  24
  25 #ifndef __ar9300template_wasp_2_h__
  26 #define __ar9300template_wasp_2_h__
  27
  28 /* Ensure that AH_BYTE_ORDER is defined */
  29 #ifndef AH_BYTE_ORDER
  30 #error AH_BYTE_ORDER needs to be defined!
  31 #endif
  32
  33 static ar9300_eeprom_t ar9300_template_wasp_2=
  34 {
  35
  36         2, //  eepromVersion;
  37
  38     ar9300_eeprom_template_wasp_2, //  templateVersion;
  39
  40         {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6];
  41
  42     //static  A_UINT8   custData[OSPREY_CUSTOMER_DATA_SIZE]=
  43
  44         {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
  45
  46     //static OSPREY_BASE_EEP_HEADER baseEepHeader=
  47
  48         {
  49                     {0,0x1f},   //   regDmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
  50                     0x33,       //   txrxMask;  //4 bits tx and 4 bits rx
  51                     {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 3},       //   opCapFlags;
  52                     0,          //   rfSilent;
  53                     0,          //   blueToothOptions;
  54                     0,          //   deviceCap;
  55                     4,          //   deviceType; // takes lower byte in eeprom location
  56                     OSPREY_PWR_TABLE_OFFSET,    //    pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
  57                         {0,0},  //   params_for_tuning_caps[2];  //placeholder, get more details from Don
  58             0x0c,     //featureEnable; //bit0 - enable tx temp comp
  59                              //bit1 - enable tx volt comp
  60                              //bit2 - enable fastClock - default to 1
  61                              //bit3 - enable doubling - default to 1
  62                                                          //bit4 - enable internal regulator - default to 0
  63                 0,       //miscConfiguration: bit0 - turn down drivestrength
  64                         3,              // eepromWriteEnableGpio
  65                         0,              // wlanDisableGpio
  66                         8,              // wlanLedGpio
  67                         0xff,           // rxBandSelectGpio
  68                         0,                      // txrxgain
  69             0,          //   swreg
  70         },
  71
  72
  73         //static OSPREY_MODAL_EEP_HEADER modalHeader2G=
  74         {
  75
  76                     0x220,                      //  antCtrlCommon;                         // 4   idle, t1, t2, b (4 bits per setting)
  77                     0x88888,            //  antCtrlCommon2;                        // 4    ra1l1, ra2l1, ra1l2, ra2l2, ra12
  78                     {0x150,0x150,0x150},        //  antCtrlChain[OSPREY_MAX_CHAINS];       // 6   idle, t, r, rx1, rx12, b (2 bits each)
  79                     {0,0,0},                    //   xatten1DB[OSPREY_MAX_CHAINS];           // 3  //xatten1_db for merlin (0xa20c/b20c 5:0)
  80                     {0,0,0},                    //   xatten1Margin[OSPREY_MAX_CHAINS];          // 3  //xatten1_margin for merlin (0xa20c/b20c 16:12
  81                         36,                             //    tempSlope;
  82                         0,                              //    voltSlope;
  83                     {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS];  // spur channels in usual fbin coding format
  84                     {-1,0,0},                   //    noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3    //Check if the register is per chain
  85             {0, 0, 0, 0, 0, 0,0,0,0,0,0},               // reserved
  86             0,                                          // quick drop
  87                     0,                          //   xpaBiasLvl;                            // 1
  88                     0x0e,                       //   txFrameToDataStart;                    // 1
  89                     0x0e,                       //   txFrameToPaOn;                         // 1
  90                     3,                          //   txClip;                                     // 4 bits tx_clip, 4 bits dac_scale_cck
  91                     0,                          //    antennaGain;                           // 1
  92                     0x2c,                       //   switchSettling;                        // 1
  93                     -30,                        //    adcDesiredSize;                        // 1
  94                     0,                          //   txEndToXpaOff;                         // 1
  95                     0x2,                        //   txEndToRxOn;                           // 1
  96                     0xe,                        //   txFrameToXpaOn;                        // 1
  97                     28,                         //   thresh62;                              // 1
  98                         0x0c80C080,             //       papdRateMaskHt20                                               // 4
  99                         0x0080C080,             //       papdRateMaskHt40
 100                     0,                          //   switchcomspdt;                         // 2
 101                         0,                              // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
 102                         0,                              //  rf_gain_cap
 103                         0,                              //  tx_gain_cap
 104                         {0,0,0,0,0}    //futureModal[5];
 105         },
 106
 107         {
 108                 0,                                                                      //   ant_div_control
 109                         {0,0},                                  // base_ext1
 110                         0,                                              // misc_enable
 111                         {0,0,0,0,0,0,0,0},              // temp slop extension
 112                 0,                                                                      // quick drop low
 113                 0,                                                                      // quick drop high
 114         },
 115
 116         //static A_UINT8 calFreqPier2G[OSPREY_NUM_2G_CAL_PIERS]=
 117         {
 118                 FREQ2FBIN(2412, 1),
 119                 FREQ2FBIN(2437, 1),
 120                 FREQ2FBIN(2472, 1)
 121         },
 122
 123         //static OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData2G[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]=
 124
 125         {       {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 126                 {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 127                 {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 128         },
 129
 130         //A_UINT8 calTarget_freqbin_Cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
 131
 132         {
 133                 FREQ2FBIN(2412, 1),
 134                 FREQ2FBIN(2484, 1)
 135         },
 136
 137         //static CAL_TARGET_POWER_LEG calTarget_freqbin_2G[OSPREY_NUM_2G_20_TARGET_POWERS]
 138         {
 139                 FREQ2FBIN(2412, 1),
 140                 FREQ2FBIN(2437, 1),
 141                 FREQ2FBIN(2472, 1)
 142         },
 143
 144         //static   OSP_CAL_TARGET_POWER_HT  calTarget_freqbin_2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]
 145         {
 146                 FREQ2FBIN(2412, 1),
 147                 FREQ2FBIN(2437, 1),
 148                 FREQ2FBIN(2472, 1)
 149         },
 150
 151         //static   OSP_CAL_TARGET_POWER_HT  calTarget_freqbin_2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]
 152         {
 153                 FREQ2FBIN(2412, 1),
 154                 FREQ2FBIN(2437, 1),
 155                 FREQ2FBIN(2472, 1)
 156         },
 157
 158         //static CAL_TARGET_POWER_LEG calTargetPowerCck[OSPREY_NUM_2G_CCK_TARGET_POWERS]=
 159         {
 160                 //1L-5L,5S,11L,11S
 161         {{36,36,36,36}},
 162                 {{36,36,36,36}}
 163          },
 164
 165         //static CAL_TARGET_POWER_LEG calTargetPower2G[OSPREY_NUM_2G_20_TARGET_POWERS]=
 166         {
 167         //6-24,36,48,54
 168                 {{32,32,28,24}},
 169                 {{32,32,28,24}},
 170                 {{32,32,28,24}},
 171         },
 172
 173         //static   OSP_CAL_TARGET_POWER_HT  calTargetPower2GHT20[OSPREY_NUM_2G_20_TARGET_POWERS]=
 174         {
 175         //0_8_16,1-3_9-11_17-19,
 176         //      4,5,6,7,12,13,14,15,20,21,22,23
 177                 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
 178                 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
 179                 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
 180         },
 181
 182         //static    OSP_CAL_TARGET_POWER_HT  calTargetPower2GHT40[OSPREY_NUM_2G_40_TARGET_POWERS]=
 183         {
 184         //0_8_16,1-3_9-11_17-19,
 185         //      4,5,6,7,12,13,14,15,20,21,22,23
 186                 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
 187                 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
 188                 {{32,32,32,32,28,20,32,32,28,20,32,32,28,20}},
 189         },
 190
 191 //static    A_UINT8            ctlIndex_2G[OSPREY_NUM_CTLS_2G]=
 192
 193         {
 194
 195                     0x11,
 196                 0x12,
 197                 0x15,
 198                 0x17,
 199                 0x41,
 200                 0x42,
 201                         0x45,
 202                 0x47,
 203                         0x31,
 204                 0x32,
 205                 0x35,
 206                 0x37
 207
 208     },
 209
 210 //A_UINT8   ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
 211
 212         {
 213                 {FREQ2FBIN(2412, 1),
 214                  FREQ2FBIN(2417, 1),
 215                  FREQ2FBIN(2457, 1),
 216                  FREQ2FBIN(2462, 1)},
 217
 218                 {FREQ2FBIN(2412, 1),
 219                  FREQ2FBIN(2417, 1),
 220                  FREQ2FBIN(2462, 1),
 221                  0xFF},
 222
 223                 {FREQ2FBIN(2412, 1),
 224                  FREQ2FBIN(2417, 1),
 225                  FREQ2FBIN(2462, 1),
 226                  0xFF},
 227
 228                 {FREQ2FBIN(2422, 1),
 229                  FREQ2FBIN(2427, 1),
 230                  FREQ2FBIN(2447, 1),
 231                  FREQ2FBIN(2452, 1)},
 232
 233                 {/*Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
 234                 /*Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
 235                 /*Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
 236                 /*Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(2484, 1)},
 237
 238                 {/*Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
 239                  /*Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
 240                  /*Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
 241                  0},
 242
 243                 {/*Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
 244                  /*Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
 245                  FREQ2FBIN(2472, 1),
 246                  0},
 247
 248                 {/*Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
 249                  /*Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
 250                  /*Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
 251                  /*Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)},
 252
 253                 {/*Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
 254                  /*Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
 255                  /*Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
 256                  0},
 257
 258                 {/*Data[9].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
 259                  /*Data[9].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
 260                  /*Data[9].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
 261                  0},
 262
 263                 {/*Data[10].ctlEdges[0].bChannel*/FREQ2FBIN(2412, 1),
 264                  /*Data[10].ctlEdges[1].bChannel*/FREQ2FBIN(2417, 1),
 265                  /*Data[10].ctlEdges[2].bChannel*/FREQ2FBIN(2472, 1),
 266                  0},
 267
 268                 {/*Data[11].ctlEdges[0].bChannel*/FREQ2FBIN(2422, 1),
 269                  /*Data[11].ctlEdges[1].bChannel*/FREQ2FBIN(2427, 1),
 270                  /*Data[11].ctlEdges[2].bChannel*/FREQ2FBIN(2447, 1),
 271                  /*Data[11].ctlEdges[3].bChannel*/FREQ2FBIN(2462, 1)}
 272         },
 273
 274
 275 //OSP_CAL_CTL_DATA_2G   ctlPowerData_2G[OSPREY_NUM_CTLS_2G];
 276
 277 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 278     {
 279
 280             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 281             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 282             {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}},
 283
 284             {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}},
 285             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 286             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 287
 288             {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}},
 289             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 290             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 291
 292             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 293             {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
 294             {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
 295
 296     },
 297 #else
 298         {
 299             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 300             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 301             {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
 302
 303             {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}},
 304             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 305             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 306
 307             {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
 308             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 309             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 310
 311             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 312             {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
 313             {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
 314         },
 315 #endif
 316
 317 //static    OSPREY_MODAL_EEP_HEADER   modalHeader5G=
 318
 319         {
 320
 321                     0x440,                      //  antCtrlCommon;                         // 4   idle, t1, t2, b (4 bits per setting)
 322                     0x11111,            //  antCtrlCommon2;                        // 4    ra1l1, ra2l1, ra1l2, ra2l2, ra12
 323                     {0x000,0x000,0x000},        //  antCtrlChain[OSPREY_MAX_CHAINS];       // 6   idle, t, r, rx1, rx12, b (2 bits each)
 324                     {0,0,0},                    //   xatten1DB[OSPREY_MAX_CHAINS];           // 3  //xatten1_db for merlin (0xa20c/b20c 5:0)
 325                     {0,0,0},                    //   xatten1Margin[OSPREY_MAX_CHAINS];          // 3  //xatten1_margin for merlin (0xa20c/b20c 16:12
 326                         68,                             //    tempSlope;
 327                         0,                              //    voltSlope;
 328                     {0,0,0,0,0}, // spurChans[OSPREY_EEPROM_MODAL_SPURS];  // spur channels in usual fbin coding format
 329                     {-1,0,0},                   //    noiseFloorThreshCh[OSPREY_MAX_CHAINS]; // 3    //Check if the register is per chain
 330                         {0, 0, 0, 0, 0, 0,0,0,0,0,0},                           // reserved
 331                         0,                                                                                      // quick drop
 332                     0,                          //   xpaBiasLvl;                            // 1
 333                     0x0e,                       //   txFrameToDataStart;                    // 1
 334                     0x0e,                       //   txFrameToPaOn;                         // 1
 335                     3,                          //   txClip;                                     // 4 bits tx_clip, 4 bits dac_scale_cck
 336                     0,                          //    antennaGain;                           // 1
 337                     0x2d,                       //   switchSettling;                        // 1
 338                     -30,                        //    adcDesiredSize;                        // 1
 339                     0,                          //   txEndToXpaOff;                         // 1
 340                     0x2,                        //   txEndToRxOn;                           // 1
 341                     0xe,                        //   txFrameToXpaOn;                        // 1
 342                     28,                         //   thresh62;                              // 1
 343                         0x0cf0e0e0,             //       papdRateMaskHt20                                               // 4
 344                         0x6cf0e0e0,             //       papdRateMaskHt40                                               // 4
 345                     0,                          //   switchcomspdt;                         // 2
 346                         0,                              // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
 347                         0,                              //  rf_gain_cap
 348                         0,                              //  tx_gain_cap
 349                         {0,0,0,0,0}    //futureModal[5];
 350         },
 351
 352         {                       // base_ext2
 353                 0,
 354                 0,
 355                 {0,0,0},
 356                 {0,0,0},
 357                 {0,0,0},
 358                 {0,0,0}
 359         },
 360
 361 //static    A_UINT8            calFreqPier5G[OSPREY_NUM_5G_CAL_PIERS]=
 362         {
 363                     //pPiers[0] =
 364                     FREQ2FBIN(5180, 0),
 365                     //pPiers[1] =
 366                     FREQ2FBIN(5220, 0),
 367                     //pPiers[2] =
 368                     FREQ2FBIN(5320, 0),
 369                     //pPiers[3] =
 370                     FREQ2FBIN(5400, 0),
 371                     //pPiers[4] =
 372                     FREQ2FBIN(5500, 0),
 373                     //pPiers[5] =
 374                     FREQ2FBIN(5600, 0),
 375                     //pPiers[6] =
 376                     FREQ2FBIN(5725, 0),
 377                 //pPiers[7] =
 378                 FREQ2FBIN(5825, 0)
 379         },
 380
 381 //static    OSP_CAL_DATA_PER_FREQ_OP_LOOP calPierData5G[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]=
 382
 383         {
 384                 {{0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},    {0,0,0,0,0},  {0,0,0,0,0}},
 385                 {{0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},    {0,0,0,0,0},  {0,0,0,0,0}},
 386                 {{0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},  {0,0,0,0,0},    {0,0,0,0,0},  {0,0,0,0,0}},
 387
 388         },
 389
 390 //static    CAL_TARGET_POWER_LEG calTarget_freqbin_5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
 391
 392         {
 393                         FREQ2FBIN(5180, 0),
 394                         FREQ2FBIN(5220, 0),
 395                         FREQ2FBIN(5320, 0),
 396                         FREQ2FBIN(5400, 0),
 397                         FREQ2FBIN(5500, 0),
 398                         FREQ2FBIN(5600, 0),
 399                         FREQ2FBIN(5725, 0),
 400                         FREQ2FBIN(5825, 0)
 401         },
 402
 403 //static    OSP_CAL_TARGET_POWER_HT  calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
 404
 405         {
 406                         FREQ2FBIN(5180, 0),
 407                         FREQ2FBIN(5240, 0),
 408                         FREQ2FBIN(5320, 0),
 409                         FREQ2FBIN(5500, 0),
 410                         FREQ2FBIN(5700, 0),
 411                         FREQ2FBIN(5745, 0),
 412                         FREQ2FBIN(5725, 0),
 413                         FREQ2FBIN(5825, 0)
 414         },
 415
 416 //static    OSP_CAL_TARGET_POWER_HT  calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
 417
 418         {
 419                         FREQ2FBIN(5180, 0),
 420                         FREQ2FBIN(5240, 0),
 421                         FREQ2FBIN(5320, 0),
 422                         FREQ2FBIN(5500, 0),
 423                         FREQ2FBIN(5700, 0),
 424                         FREQ2FBIN(5745, 0),
 425                         FREQ2FBIN(5725, 0),
 426                         FREQ2FBIN(5825, 0)
 427         },
 428
 429
 430 //static    CAL_TARGET_POWER_LEG calTargetPower5G[OSPREY_NUM_5G_20_TARGET_POWERS]=
 431
 432
 433         {
 434         //6-24,36,48,54
 435             {{20,20,20,10}},
 436             {{20,20,20,10}},
 437             {{20,20,20,10}},
 438             {{20,20,20,10}},
 439             {{20,20,20,10}},
 440             {{20,20,20,10}},
 441             {{20,20,20,10}},
 442             {{20,20,20,10}},
 443         },
 444
 445 //static    OSP_CAL_TARGET_POWER_HT  calTargetPower5GHT20[OSPREY_NUM_5G_20_TARGET_POWERS]=
 446
 447         {
 448         //0_8_16,1-3_9-11_17-19,
 449         //      4,5,6,7,12,13,14,15,20,21,22,23
 450             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 451             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 452             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 453             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 454             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 455             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 456             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 457             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 458         },
 459
 460 //static    OSP_CAL_TARGET_POWER_HT  calTargetPower5GHT40[OSPREY_NUM_5G_40_TARGET_POWERS]=
 461         {
 462         //0_8_16,1-3_9-11_17-19,
 463         //      4,5,6,7,12,13,14,15,20,21,22,23
 464             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 465             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 466             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 467             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 468             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 469             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 470             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 471             {{20,20,10,10,0,0,10,10,0,0,10,10,0,0}},
 472         },
 473
 474 //static    A_UINT8            ctlIndex_5G[OSPREY_NUM_CTLS_5G]=
 475
 476         {
 477                     //pCtlIndex[0] =
 478                     0x10,
 479                     //pCtlIndex[1] =
 480                     0x16,
 481                     //pCtlIndex[2] =
 482                     0x18,
 483                     //pCtlIndex[3] =
 484                     0x40,
 485                     //pCtlIndex[4] =
 486                     0x46,
 487                     //pCtlIndex[5] =
 488                     0x48,
 489                     //pCtlIndex[6] =
 490                     0x30,
 491                     //pCtlIndex[7] =
 492                     0x36,
 493                 //pCtlIndex[8] =
 494                 0x38
 495         },
 496
 497 //    A_UINT8   ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
 498
 499         {
 500             {/* Data[0].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
 501             /* Data[0].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
 502             /* Data[0].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
 503             /* Data[0].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
 504             /* Data[0].ctlEdges[4].bChannel*/FREQ2FBIN(5600, 0),
 505             /* Data[0].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
 506             /* Data[0].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
 507             /* Data[0].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
 508
 509             {/* Data[1].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
 510             /* Data[1].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
 511             /* Data[1].ctlEdges[2].bChannel*/FREQ2FBIN(5280, 0),
 512             /* Data[1].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
 513             /* Data[1].ctlEdges[4].bChannel*/FREQ2FBIN(5520, 0),
 514             /* Data[1].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
 515             /* Data[1].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
 516             /* Data[1].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
 517
 518             {/* Data[2].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
 519             /* Data[2].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
 520             /* Data[2].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
 521             /* Data[2].ctlEdges[3].bChannel*/FREQ2FBIN(5310, 0),
 522             /* Data[2].ctlEdges[4].bChannel*/FREQ2FBIN(5510, 0),
 523             /* Data[2].ctlEdges[5].bChannel*/FREQ2FBIN(5550, 0),
 524             /* Data[2].ctlEdges[6].bChannel*/FREQ2FBIN(5670, 0),
 525             /* Data[2].ctlEdges[7].bChannel*/FREQ2FBIN(5755, 0)},
 526
 527             {/* Data[3].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
 528             /* Data[3].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
 529             /* Data[3].ctlEdges[2].bChannel*/FREQ2FBIN(5260, 0),
 530             /* Data[3].ctlEdges[3].bChannel*/FREQ2FBIN(5320, 0),
 531             /* Data[3].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
 532             /* Data[3].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
 533             /* Data[3].ctlEdges[6].bChannel*/0xFF,
 534             /* Data[3].ctlEdges[7].bChannel*/0xFF},
 535
 536             {/* Data[4].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
 537             /* Data[4].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
 538             /* Data[4].ctlEdges[2].bChannel*/FREQ2FBIN(5500, 0),
 539             /* Data[4].ctlEdges[3].bChannel*/FREQ2FBIN(5700, 0),
 540             /* Data[4].ctlEdges[4].bChannel*/0xFF,
 541             /* Data[4].ctlEdges[5].bChannel*/0xFF,
 542             /* Data[4].ctlEdges[6].bChannel*/0xFF,
 543             /* Data[4].ctlEdges[7].bChannel*/0xFF},
 544
 545             {/* Data[5].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
 546             /* Data[5].ctlEdges[1].bChannel*/FREQ2FBIN(5270, 0),
 547             /* Data[5].ctlEdges[2].bChannel*/FREQ2FBIN(5310, 0),
 548             /* Data[5].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
 549             /* Data[5].ctlEdges[4].bChannel*/FREQ2FBIN(5590, 0),
 550             /* Data[5].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
 551             /* Data[5].ctlEdges[6].bChannel*/0xFF,
 552             /* Data[5].ctlEdges[7].bChannel*/0xFF},
 553
 554             {/* Data[6].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
 555             /* Data[6].ctlEdges[1].bChannel*/FREQ2FBIN(5200, 0),
 556             /* Data[6].ctlEdges[2].bChannel*/FREQ2FBIN(5220, 0),
 557             /* Data[6].ctlEdges[3].bChannel*/FREQ2FBIN(5260, 0),
 558             /* Data[6].ctlEdges[4].bChannel*/FREQ2FBIN(5500, 0),
 559             /* Data[6].ctlEdges[5].bChannel*/FREQ2FBIN(5600, 0),
 560             /* Data[6].ctlEdges[6].bChannel*/FREQ2FBIN(5700, 0),
 561             /* Data[6].ctlEdges[7].bChannel*/FREQ2FBIN(5745, 0)},
 562
 563             {/* Data[7].ctlEdges[0].bChannel*/FREQ2FBIN(5180, 0),
 564             /* Data[7].ctlEdges[1].bChannel*/FREQ2FBIN(5260, 0),
 565             /* Data[7].ctlEdges[2].bChannel*/FREQ2FBIN(5320, 0),
 566             /* Data[7].ctlEdges[3].bChannel*/FREQ2FBIN(5500, 0),
 567             /* Data[7].ctlEdges[4].bChannel*/FREQ2FBIN(5560, 0),
 568             /* Data[7].ctlEdges[5].bChannel*/FREQ2FBIN(5700, 0),
 569             /* Data[7].ctlEdges[6].bChannel*/FREQ2FBIN(5745, 0),
 570             /* Data[7].ctlEdges[7].bChannel*/FREQ2FBIN(5825, 0)},
 571
 572             {/* Data[8].ctlEdges[0].bChannel*/FREQ2FBIN(5190, 0),
 573             /* Data[8].ctlEdges[1].bChannel*/FREQ2FBIN(5230, 0),
 574             /* Data[8].ctlEdges[2].bChannel*/FREQ2FBIN(5270, 0),
 575             /* Data[8].ctlEdges[3].bChannel*/FREQ2FBIN(5510, 0),
 576             /* Data[8].ctlEdges[4].bChannel*/FREQ2FBIN(5550, 0),
 577             /* Data[8].ctlEdges[5].bChannel*/FREQ2FBIN(5670, 0),
 578             /* Data[8].ctlEdges[6].bChannel*/FREQ2FBIN(5755, 0),
 579             /* Data[8].ctlEdges[7].bChannel*/FREQ2FBIN(5795, 0)}
 580         },
 581
 582 //static    OSP_CAL_CTL_DATA_5G   ctlData_5G[OSPREY_NUM_CTLS_5G]=
 583
 584 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 585         {
 586             {{{1, 60},
 587               {1, 60},
 588               {1, 60},
 589               {1, 60},
 590               {1, 60},
 591               {1, 60},
 592               {1, 60},
 593               {0, 60}}},
 594
 595             {{{1, 60},
 596               {1, 60},
 597               {1, 60},
 598               {1, 60},
 599               {1, 60},
 600               {1, 60},
 601               {1, 60},
 602               {0, 60}}},
 603
 604             {{{0, 60},
 605               {1, 60},
 606               {0, 60},
 607               {1, 60},
 608               {1, 60},
 609               {1, 60},
 610               {1, 60},
 611               {1, 60}}},
 612
 613             {{{0, 60},
 614               {1, 60},
 615               {1, 60},
 616               {0, 60},
 617               {1, 60},
 618               {0, 60},
 619               {0, 60},
 620               {0, 60}}},
 621
 622             {{{1, 60},
 623               {1, 60},
 624               {1, 60},
 625               {0, 60},
 626               {0, 60},
 627               {0, 60},
 628               {0, 60},
 629               {0, 60}}},
 630
 631             {{{1, 60},
 632               {1, 60},
 633               {1, 60},
 634               {1, 60},
 635               {1, 60},
 636               {0, 60},
 637               {0, 60},
 638               {0, 60}}},
 639
 640             {{{1, 60},
 641               {1, 60},
 642               {1, 60},
 643               {1, 60},
 644               {1, 60},
 645               {1, 60},
 646               {1, 60},
 647               {1, 60}}},
 648
 649             {{{1, 60},
 650               {1, 60},
 651               {0, 60},
 652               {1, 60},
 653               {1, 60},
 654               {1, 60},
 655               {1, 60},
 656               {0, 60}}},
 657
 658             {{{1, 60},
 659               {0, 60},
 660               {1, 60},
 661               {1, 60},
 662               {1, 60},
 663               {1, 60},
 664               {0, 60},
 665               {1, 60}}},
 666         }
 667 #else
 668         {
 669             {{{60, 1},
 670               {60, 1},
 671               {60, 1},
 672               {60, 1},
 673               {60, 1},
 674               {60, 1},
 675               {60, 1},
 676               {60, 0}}},
 677
 678             {{{60, 1},
 679               {60, 1},
 680               {60, 1},
 681               {60, 1},
 682               {60, 1},
 683               {60, 1},
 684               {60, 1},
 685               {60, 0}}},
 686
 687             {{{60, 0},
 688               {60, 1},
 689               {60, 0},
 690               {60, 1},
 691               {60, 1},
 692               {60, 1},
 693               {60, 1},
 694               {60, 1}}},
 695
 696             {{{60, 0},
 697               {60, 1},
 698               {60, 1},
 699               {60, 0},
 700               {60, 1},
 701               {60, 0},
 702               {60, 0},
 703               {60, 0}}},
 704
 705             {{{60, 1},
 706               {60, 1},
 707               {60, 1},
 708               {60, 0},
 709               {60, 0},
 710               {60, 0},
 711               {60, 0},
 712               {60, 0}}},
 713
 714             {{{60, 1},
 715               {60, 1},
 716               {60, 1},
 717               {60, 1},
 718               {60, 1},
 719               {60, 0},
 720               {60, 0},
 721               {60, 0}}},
 722
 723             {{{60, 1},
 724               {60, 1},
 725               {60, 1},
 726               {60, 1},
 727               {60, 1},
 728               {60, 1},
 729               {60, 1},
 730               {60, 1}}},
 731
 732             {{{60, 1},
 733               {60, 1},
 734               {60, 0},
 735               {60, 1},
 736               {60, 1},
 737               {60, 1},
 738               {60, 1},
 739               {60, 0}}},
 740
 741             {{{60, 1},
 742               {60, 0},
 743               {60, 1},
 744               {60, 1},
 745               {60, 1},
 746               {60, 1},
 747               {60, 0},
 748               {60, 1}}},
 749         }
 750 #endif
 751 };
 752
 753 #endif