sys/contrib/dev/ath/ath_hal/ar9300/ar9300template_xb112.h

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
   9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
  11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  14  * PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 /*
  18  * READ THIS NOTICE!
  19  *
  20  * Values defined in this file may only be changed under exceptional circumstances.
  21  *
  22  * Please ask Fiona Cain before making any changes.
  23  */
  24
  25 #ifndef __ar9300templateXB112_h__
  26 #define __ar9300templateXB112_h__
  27
  28 /* Ensure that AH_BYTE_ORDER is defined */
  29 #ifndef AH_BYTE_ORDER
  30 #error AH_BYTE_ORDER needs to be defined!
  31 #endif
  32
  33 static ar9300_eeprom_t ar9300_template_xb112=
  34 {
  35
  36         2, //  eeprom_version;
  37
  38     ar9300_eeprom_template_xb112, //  template_version;
  39
  40         {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6];
  41
  42     //static  A_UINT8   custData[OSPREY_CUSTOMER_DATA_SIZE]=
  43
  44         {"xb112-041-f0000"},
  45 //      {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
  46
  47     //static OSPREY_BASE_EEP_HEADER base_eep_header=
  48
  49         {
  50                     {0,0x1f},   //   reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
  51                     0x77,       //   txrx_mask;  //4 bits tx and 4 bits rx
  52                     {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0},       //   op_cap_flags;
  53                     0,          //   rf_silent;
  54                     0,          //   blue_tooth_options;
  55                     0,          //   device_cap;
  56                     5,          //   device_type; // takes lower byte in eeprom location
  57                     OSPREY_PWR_TABLE_OFFSET,    //    pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
  58                         {0,0},  //   params_for_tuning_caps[2];  //placeholder, get more details from Don
  59             0x0d,     //feature_enable; //bit0 - enable tx temp comp
  60                              //bit1 - enable tx volt comp
  61                              //bit2 - enable fastClock - default to 1
  62                              //bit3 - enable doubling - default to 1
  63                                                          //bit4 - enable internal regulator - default to 0
  64                                                          //bit5 - enable paprd -- default to 0
  65                 0,       //misc_configuration: bit0 - turn down drivestrength
  66                         6,              // eeprom_write_enable_gpio
  67                         0,              // wlan_disable_gpio
  68                         8,              // wlan_led_gpio
  69                         0xff,           // rx_band_select_gpio
  70                         0,                      // txrxgain
  71             0,          //   swreg
  72         },
  73
  74
  75         //static OSPREY_MODAL_EEP_HEADER modal_header_2g=
  76         {
  77
  78                     0x110,                      //  ant_ctrl_common;                         // 4   idle, t1, t2, b (4 bits per setting)
  79                     0x22222,            //  ant_ctrl_common2;                        // 4    ra1l1, ra2l1, ra1l2, ra2l2, ra12
  80                     {0x10,0x10,0x10},   //  ant_ctrl_chain[OSPREY_MAX_CHAINS];       // 6   idle, t, r, rx1, rx12, b (2 bits each)
  81                     {0x1b,0x1b,0x1b},           //   xatten1_db[OSPREY_MAX_CHAINS];           // 3  //xatten1_db for merlin (0xa20c/b20c 5:0)
  82                     {0x15,0x15,0x15},                   //   xatten1_margin[OSPREY_MAX_CHAINS];          // 3  //xatten1_margin for merlin (0xa20c/b20c 16:12
  83                         50,                             //    temp_slope;
  84                         0,                              //    voltSlope;
  85                     {FREQ2FBIN(2464, 1),0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS];  // spur channels in usual fbin coding format
  86                     {-1,0,0},                   //    noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3    //Check if the register is per chain
  87                         {0, 0, 0, 0, 0, 0,0,0,0,0,0},                           // reserved
  88                         0,                                                                                      // quick drop
  89                     0,                          //   xpa_bias_lvl;                            // 1
  90                     0x0e,                       //   tx_frame_to_data_start;                    // 1
  91                     0x0e,                       //   tx_frame_to_pa_on;                         // 1
  92                     3,                          //   txClip;                                     // 4 bits tx_clip, 4 bits dac_scale_cck
  93                     0,                          //    antenna_gain;                           // 1
  94                     0x2c,                       //   switchSettling;                        // 1
  95                     -30,                        //    adcDesiredSize;                        // 1
  96                     0,                          //   txEndToXpaOff;                         // 1
  97                     0x2,                        //   txEndToRxOn;                           // 1
  98                     0xe,                        //   tx_frame_to_xpa_on;                        // 1
  99                     28,                         //   thresh62;                              // 1
 100                         0x0c80C080,             //       paprd_rate_mask_ht20                                           // 4
 101                         0x0080C080,             //       paprd_rate_mask_ht40
 102                     0,                          //   switchcomspdt;                         // 2
 103                         0,                              // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
 104                         0,                              //  rf_gain_cap
 105                         0,                              //  tx_gain_cap
 106                         {0,0,0,0,0}    //futureModal[5];
 107         },
 108
 109         {
 110                 0,                                                          //   ant_div_control
 111                         {0,0},                                  // base_ext1
 112                         0,                                              // misc_enable
 113                         {0,0,0,0,0,0,0,0},              // temp slop extension
 114                 0,                                                                      // quick drop low
 115                 0,                                                                      // quick drop high
 116         },
 117
 118         //static A_UINT8 cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS]=
 119         {
 120                 FREQ2FBIN(2412, 1),
 121                 FREQ2FBIN(2437, 1),
 122                 FREQ2FBIN(2462, 1)
 123         },
 124
 125         //static OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS]=
 126
 127         {       {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 128                 {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 129                 {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 130         },
 131
 132         //A_UINT8 cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
 133
 134         {
 135                 FREQ2FBIN(2412, 1),
 136                 FREQ2FBIN(2472, 1)
 137         },
 138
 139         //static CAL_TARGET_POWER_LEG cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS]
 140         {
 141                 FREQ2FBIN(2412, 1),
 142                 FREQ2FBIN(2437, 1),
 143                 FREQ2FBIN(2472, 1)
 144         },
 145
 146         //static   OSP_CAL_TARGET_POWER_HT  cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]
 147         {
 148                 FREQ2FBIN(2412, 1),
 149                 FREQ2FBIN(2437, 1),
 150                 FREQ2FBIN(2472, 1)
 151         },
 152
 153         //static   OSP_CAL_TARGET_POWER_HT  cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]
 154         {
 155                 FREQ2FBIN(2412, 1),
 156                 FREQ2FBIN(2437, 1),
 157                 FREQ2FBIN(2472, 1)
 158         },
 159
 160         //static CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS]=
 161         {
 162                 //1L-5L,5S,11L,11S
 163         {{38,38,38,38}},
 164                 {{38,38,38,38}}
 165          },
 166
 167         //static CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS]=
 168         {
 169         //6-24,36,48,54
 170                 {{38,38,36,34}},
 171                 {{38,38,36,34}},
 172                 {{38,38,34,32}},
 173         },
 174
 175         //static   OSP_CAL_TARGET_POWER_HT  cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS]=
 176         {
 177         //0_8_16,1-3_9-11_17-19,
 178         //      4,5,6,7,12,13,14,15,20,21,22,23
 179                 {{36,36,36,36,36,34,34,32,30,28,28,28,28,26}},
 180                 {{36,36,36,36,36,34,36,34,32,30,30,30,28,26}},
 181                 {{36,36,36,36,36,34,34,32,30,28,28,28,28,26}},
 182         },
 183
 184         //static    OSP_CAL_TARGET_POWER_HT  cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS]=
 185         {
 186         //0_8_16,1-3_9-11_17-19,
 187         //      4,5,6,7,12,13,14,15,20,21,22,23
 188                 {{36,36,36,36,34,32,32,30,28,26,26,26,26,24}},
 189                 {{36,36,36,36,34,32,34,32,30,28,28,28,28,24}},
 190                 {{36,36,36,36,34,32,32,30,28,26,26,26,26,24}},
 191         },
 192
 193 //static    A_UINT8            ctl_index_2g[OSPREY_NUM_CTLS_2G]=
 194
 195         {
 196
 197                     0x11,
 198                 0x12,
 199                 0x15,
 200                 0x17,
 201                 0x41,
 202                 0x42,
 203                         0x45,
 204                 0x47,
 205                         0x31,
 206                 0x32,
 207                 0x35,
 208                 0x37
 209
 210     },
 211
 212 //A_UINT8   ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
 213
 214         {
 215                 {FREQ2FBIN(2412, 1),
 216                  FREQ2FBIN(2417, 1),
 217                  FREQ2FBIN(2457, 1),
 218                  FREQ2FBIN(2462, 1)},
 219
 220                 {FREQ2FBIN(2412, 1),
 221                  FREQ2FBIN(2417, 1),
 222                  FREQ2FBIN(2462, 1),
 223                  0xFF},
 224
 225                 {FREQ2FBIN(2412, 1),
 226                  FREQ2FBIN(2417, 1),
 227                  FREQ2FBIN(2462, 1),
 228                  0xFF},
 229
 230                 {FREQ2FBIN(2422, 1),
 231                  FREQ2FBIN(2427, 1),
 232                  FREQ2FBIN(2447, 1),
 233                  FREQ2FBIN(2452, 1)},
 234
 235                 {/*Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
 236                 /*Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
 237                 /*Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
 238                 /*Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(2484, 1)},
 239
 240                 {/*Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
 241                  /*Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
 242                  /*Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
 243                  0},
 244
 245                 {/*Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
 246                  /*Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
 247                  FREQ2FBIN(2472, 1),
 248                  0},
 249
 250                 {/*Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1),
 251                  /*Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1),
 252                  /*Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1),
 253                  /*Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)},
 254
 255                 {/*Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
 256                  /*Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
 257                  /*Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
 258                  0},
 259
 260                 {/*Data[9].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
 261                  /*Data[9].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
 262                  /*Data[9].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
 263                  0},
 264
 265                 {/*Data[10].ctl_edges[0].bChannel*/FREQ2FBIN(2412, 1),
 266                  /*Data[10].ctl_edges[1].bChannel*/FREQ2FBIN(2417, 1),
 267                  /*Data[10].ctl_edges[2].bChannel*/FREQ2FBIN(2472, 1),
 268                  0},
 269
 270                 {/*Data[11].ctl_edges[0].bChannel*/FREQ2FBIN(2422, 1),
 271                  /*Data[11].ctl_edges[1].bChannel*/FREQ2FBIN(2427, 1),
 272                  /*Data[11].ctl_edges[2].bChannel*/FREQ2FBIN(2447, 1),
 273                  /*Data[11].ctl_edges[3].bChannel*/FREQ2FBIN(2462, 1)}
 274         },
 275
 276
 277 //OSP_CAL_CTL_DATA_2G   ctl_power_data_2g[OSPREY_NUM_CTLS_2G];
 278
 279 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 280     {
 281
 282             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 283             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 284             {{{1, 60}, {0, 60}, {0, 60}, {1, 60}}},
 285
 286             {{{1, 60}, {0, 60}, {0, 60}, {0, 60}}},
 287             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 288             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 289
 290             {{{0, 60}, {1, 60}, {1, 60}, {0, 60}}},
 291             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 292             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 293
 294             {{{0, 60}, {1, 60}, {0, 60}, {0, 60}}},
 295             {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
 296             {{{0, 60}, {1, 60}, {1, 60}, {1, 60}}},
 297
 298     },
 299 #else
 300         {
 301             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 302             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 303             {{{60, 1}, {60, 0}, {60, 0}, {60, 1}}},
 304
 305             {{{60, 1}, {60, 0}, {60, 0}, {60, 0}}},
 306             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 307             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 308
 309             {{{60, 0}, {60, 1}, {60, 1}, {60, 0}}},
 310             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 311             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 312
 313             {{{60, 0}, {60, 1}, {60, 0}, {60, 0}}},
 314             {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
 315             {{{60, 0}, {60, 1}, {60, 1}, {60, 1}}},
 316         },
 317 #endif
 318
 319 //static    OSPREY_MODAL_EEP_HEADER   modal_header_5g=
 320
 321         {
 322
 323                     0x110,                      //  ant_ctrl_common;                         // 4   idle, t1, t2, b (4 bits per setting)
 324                     0x22222,            //  ant_ctrl_common2;                        // 4    ra1l1, ra2l1, ra1l2, ra2l2, ra12
 325                     {0x000,0x000,0x000},        //  ant_ctrl_chain[OSPREY_MAX_CHAINS];       // 6   idle, t, r, rx1, rx12, b (2 bits each)
 326                     {0x13,0x19,0x17},                   //   xatten1_db[OSPREY_MAX_CHAINS];           // 3  //xatten1_db for merlin (0xa20c/b20c 5:0)
 327                     {0x19,0x19,0x19},                   //   xatten1_margin[OSPREY_MAX_CHAINS];          // 3  //xatten1_margin for merlin (0xa20c/b20c 16:12
 328                         70,                             //    temp_slope;
 329                         15,                             //    voltSlope;
 330                     {0,0,0,0,0}, // spur_chans[OSPREY_EEPROM_MODAL_SPURS];  // spur channels in usual fbin coding format
 331                     {-1,0,0},                   //    noise_floor_thresh_ch[OSPREY_MAX_CHAINS]; // 3    //Check if the register is per chain
 332                         {0, 0, 0, 0, 0, 0,0,0,0,0,0},                           // reserved
 333                         0,                                                                                      // quick drop
 334                     0,                          //   xpa_bias_lvl;                            // 1
 335                     0x0e,                       //   tx_frame_to_data_start;                    // 1
 336                     0x0e,                       //   tx_frame_to_pa_on;                         // 1
 337                     3,                          //   txClip;                                     // 4 bits tx_clip, 4 bits dac_scale_cck
 338                     0,                          //    antenna_gain;                           // 1
 339                     0x2d,                       //   switchSettling;                        // 1
 340                     -30,                        //    adcDesiredSize;                        // 1
 341                     0,                          //   txEndToXpaOff;                         // 1
 342                     0x2,                        //   txEndToRxOn;                           // 1
 343                     0xe,                        //   tx_frame_to_xpa_on;                        // 1
 344                     28,                         //   thresh62;                              // 1
 345                         0x0cf0e0e0,             //       paprd_rate_mask_ht20                                           // 4
 346                         0x6cf0e0e0,             //       paprd_rate_mask_ht40                                           // 4
 347                     0,                          //   switchcomspdt;                         // 2
 348                         0,                              // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
 349                         0,                              //  rf_gain_cap
 350                         0,                              //  tx_gain_cap
 351                         {0,0,0,0,0}    //futureModal[5];
 352         },
 353
 354         {                               // base_ext2
 355                 72,                             //    tempSlopeL;
 356                 105,                    //    tempSlopeH;
 357                 {0x10,0x14,0x10},       // xatten1_db_low
 358                 {0x19,0x19,0x19},       // xatten1_margin_low
 359                 {0x1d,0x20,0x24},       // xatten1_db_high
 360                 {0x10,0x10,0x10}        // xatten1_margin_high
 361         },
 362
 363 //static    A_UINT8            cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS]=
 364         {
 365                     //pPiers[0] =
 366                     FREQ2FBIN(5180, 0),
 367                     //pPiers[1] =
 368                     FREQ2FBIN(5220, 0),
 369                     //pPiers[2] =
 370                     FREQ2FBIN(5320, 0),
 371                     //pPiers[3] =
 372                     FREQ2FBIN(5400, 0),
 373                     //pPiers[4] =
 374                     FREQ2FBIN(5500, 0),
 375                     //pPiers[5] =
 376                     FREQ2FBIN(5600, 0),
 377                     //pPiers[6] =
 378                     FREQ2FBIN(5700, 0),
 379                 //pPiers[7] =
 380                 FREQ2FBIN(5785, 0)
 381         },
 382
 383 //static    OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS]=
 384
 385         {
 386                 {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},    {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 387                 {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},    {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 388                 {{0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},  {0,0,0,0,0,0},    {0,0,0,0,0,0},  {0,0,0,0,0,0}},
 389
 390         },
 391
 392 //static    CAL_TARGET_POWER_LEG cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS]=
 393
 394         {
 395                         FREQ2FBIN(5180, 0),
 396                         FREQ2FBIN(5220, 0),
 397                         FREQ2FBIN(5320, 0),
 398                         FREQ2FBIN(5400, 0),
 399                         FREQ2FBIN(5500, 0),
 400                         FREQ2FBIN(5600, 0),
 401                         FREQ2FBIN(5725, 0),
 402                         FREQ2FBIN(5825, 0)
 403         },
 404
 405 //static    OSP_CAL_TARGET_POWER_HT  cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]=
 406
 407         {
 408                         FREQ2FBIN(5180, 0),
 409                         FREQ2FBIN(5220, 0),
 410                         FREQ2FBIN(5320, 0),
 411                         FREQ2FBIN(5400, 0),
 412                         FREQ2FBIN(5500, 0),
 413                         FREQ2FBIN(5600, 0),
 414                         FREQ2FBIN(5725, 0),
 415                         FREQ2FBIN(5825, 0)
 416         },
 417
 418 //static    OSP_CAL_TARGET_POWER_HT  cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]=
 419
 420         {
 421                         FREQ2FBIN(5180, 0),
 422                         FREQ2FBIN(5220, 0),
 423                         FREQ2FBIN(5320, 0),
 424                         FREQ2FBIN(5400, 0),
 425                         FREQ2FBIN(5500, 0),
 426                         FREQ2FBIN(5600, 0),
 427                         FREQ2FBIN(5725, 0),
 428                         FREQ2FBIN(5825, 0)
 429         },
 430
 431
 432 //static    CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS]=
 433
 434
 435         {
 436         //6-24,36,48,54
 437             {{32,32,28,26}},
 438             {{32,32,28,26}},
 439             {{32,32,28,26}},
 440             {{32,32,26,24}},
 441             {{32,32,26,24}},
 442             {{32,32,24,22}},
 443             {{30,30,24,22}},
 444             {{30,30,24,22}},
 445         },
 446
 447 //static    OSP_CAL_TARGET_POWER_HT  cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS]=
 448
 449         {
 450         //0_8_16,1-3_9-11_17-19,
 451         //      4,5,6,7,12,13,14,15,20,21,22,23
 452             {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}},
 453             {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}},
 454             {{32,32,32,32,28,26,32,28,26,24,24,24,22,22}},
 455             {{32,32,32,32,28,26,32,26,24,22,22,22,20,20}},
 456             {{32,32,32,32,28,26,32,26,24,22,20,18,16,16}},
 457             {{32,32,32,32,28,26,32,24,20,16,18,16,14,14}},
 458             {{30,30,30,30,28,26,30,24,20,16,18,16,14,14}},
 459             {{30,30,30,30,28,26,30,24,20,16,18,16,14,14}},
 460         },
 461
 462 //static    OSP_CAL_TARGET_POWER_HT  cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS]=
 463         {
 464         //0_8_16,1-3_9-11_17-19,
 465         //      4,5,6,7,12,13,14,15,20,21,22,23
 466             {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}},
 467             {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}},
 468             {{32,32,32,30,28,26,30,28,26,24,24,24,22,22}},
 469             {{32,32,32,30,28,26,30,26,24,22,22,22,20,20}},
 470             {{32,32,32,30,28,26,30,26,24,22,20,18,16,16}},
 471             {{32,32,32,30,28,26,30,22,20,16,18,16,14,14}},
 472             {{30,30,30,30,28,26,30,22,20,16,18,16,14,14}},
 473             {{30,30,30,30,28,26,30,22,20,16,18,16,14,14}},
 474         },
 475
 476 //static    A_UINT8            ctl_index_5g[OSPREY_NUM_CTLS_5G]=
 477
 478         {
 479                     //pCtlIndex[0] =
 480                     0x10,
 481                     //pCtlIndex[1] =
 482                     0x16,
 483                     //pCtlIndex[2] =
 484                     0x18,
 485                     //pCtlIndex[3] =
 486                     0x40,
 487                     //pCtlIndex[4] =
 488                     0x46,
 489                     //pCtlIndex[5] =
 490                     0x48,
 491                     //pCtlIndex[6] =
 492                     0x30,
 493                     //pCtlIndex[7] =
 494                     0x36,
 495                 //pCtlIndex[8] =
 496                 0x38
 497         },
 498
 499 //    A_UINT8   ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
 500
 501         {
 502             {/* Data[0].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
 503             /* Data[0].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
 504             /* Data[0].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0),
 505             /* Data[0].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
 506             /* Data[0].ctl_edges[4].bChannel*/FREQ2FBIN(5600, 0),
 507             /* Data[0].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
 508             /* Data[0].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0),
 509             /* Data[0].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)},
 510
 511             {/* Data[1].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
 512             /* Data[1].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
 513             /* Data[1].ctl_edges[2].bChannel*/FREQ2FBIN(5280, 0),
 514             /* Data[1].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
 515             /* Data[1].ctl_edges[4].bChannel*/FREQ2FBIN(5520, 0),
 516             /* Data[1].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
 517             /* Data[1].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0),
 518             /* Data[1].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)},
 519
 520             {/* Data[2].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0),
 521             /* Data[2].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0),
 522             /* Data[2].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0),
 523             /* Data[2].ctl_edges[3].bChannel*/FREQ2FBIN(5310, 0),
 524             /* Data[2].ctl_edges[4].bChannel*/FREQ2FBIN(5510, 0),
 525             /* Data[2].ctl_edges[5].bChannel*/FREQ2FBIN(5550, 0),
 526             /* Data[2].ctl_edges[6].bChannel*/FREQ2FBIN(5670, 0),
 527             /* Data[2].ctl_edges[7].bChannel*/FREQ2FBIN(5755, 0)},
 528
 529             {/* Data[3].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
 530             /* Data[3].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0),
 531             /* Data[3].ctl_edges[2].bChannel*/FREQ2FBIN(5260, 0),
 532             /* Data[3].ctl_edges[3].bChannel*/FREQ2FBIN(5320, 0),
 533             /* Data[3].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
 534             /* Data[3].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
 535             /* Data[3].ctl_edges[6].bChannel*/0xFF,
 536             /* Data[3].ctl_edges[7].bChannel*/0xFF},
 537
 538             {/* Data[4].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
 539             /* Data[4].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
 540             /* Data[4].ctl_edges[2].bChannel*/FREQ2FBIN(5500, 0),
 541             /* Data[4].ctl_edges[3].bChannel*/FREQ2FBIN(5700, 0),
 542             /* Data[4].ctl_edges[4].bChannel*/0xFF,
 543             /* Data[4].ctl_edges[5].bChannel*/0xFF,
 544             /* Data[4].ctl_edges[6].bChannel*/0xFF,
 545             /* Data[4].ctl_edges[7].bChannel*/0xFF},
 546
 547             {/* Data[5].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0),
 548             /* Data[5].ctl_edges[1].bChannel*/FREQ2FBIN(5270, 0),
 549             /* Data[5].ctl_edges[2].bChannel*/FREQ2FBIN(5310, 0),
 550             /* Data[5].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0),
 551             /* Data[5].ctl_edges[4].bChannel*/FREQ2FBIN(5590, 0),
 552             /* Data[5].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0),
 553             /* Data[5].ctl_edges[6].bChannel*/0xFF,
 554             /* Data[5].ctl_edges[7].bChannel*/0xFF},
 555
 556             {/* Data[6].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
 557             /* Data[6].ctl_edges[1].bChannel*/FREQ2FBIN(5200, 0),
 558             /* Data[6].ctl_edges[2].bChannel*/FREQ2FBIN(5220, 0),
 559             /* Data[6].ctl_edges[3].bChannel*/FREQ2FBIN(5260, 0),
 560             /* Data[6].ctl_edges[4].bChannel*/FREQ2FBIN(5500, 0),
 561             /* Data[6].ctl_edges[5].bChannel*/FREQ2FBIN(5600, 0),
 562             /* Data[6].ctl_edges[6].bChannel*/FREQ2FBIN(5700, 0),
 563             /* Data[6].ctl_edges[7].bChannel*/FREQ2FBIN(5745, 0)},
 564
 565             {/* Data[7].ctl_edges[0].bChannel*/FREQ2FBIN(5180, 0),
 566             /* Data[7].ctl_edges[1].bChannel*/FREQ2FBIN(5260, 0),
 567             /* Data[7].ctl_edges[2].bChannel*/FREQ2FBIN(5320, 0),
 568             /* Data[7].ctl_edges[3].bChannel*/FREQ2FBIN(5500, 0),
 569             /* Data[7].ctl_edges[4].bChannel*/FREQ2FBIN(5560, 0),
 570             /* Data[7].ctl_edges[5].bChannel*/FREQ2FBIN(5700, 0),
 571             /* Data[7].ctl_edges[6].bChannel*/FREQ2FBIN(5745, 0),
 572             /* Data[7].ctl_edges[7].bChannel*/FREQ2FBIN(5825, 0)},
 573
 574             {/* Data[8].ctl_edges[0].bChannel*/FREQ2FBIN(5190, 0),
 575             /* Data[8].ctl_edges[1].bChannel*/FREQ2FBIN(5230, 0),
 576             /* Data[8].ctl_edges[2].bChannel*/FREQ2FBIN(5270, 0),
 577             /* Data[8].ctl_edges[3].bChannel*/FREQ2FBIN(5510, 0),
 578             /* Data[8].ctl_edges[4].bChannel*/FREQ2FBIN(5550, 0),
 579             /* Data[8].ctl_edges[5].bChannel*/FREQ2FBIN(5670, 0),
 580             /* Data[8].ctl_edges[6].bChannel*/FREQ2FBIN(5755, 0),
 581             /* Data[8].ctl_edges[7].bChannel*/FREQ2FBIN(5795, 0)}
 582         },
 583
 584 //static    OSP_CAL_CTL_DATA_5G   ctlData_5G[OSPREY_NUM_CTLS_5G]=
 585
 586 #if AH_BYTE_ORDER == AH_BIG_ENDIAN
 587         {
 588             {{{1, 60},
 589               {1, 60},
 590               {1, 60},
 591               {1, 60},
 592               {1, 60},
 593               {1, 60},
 594               {1, 60},
 595               {0, 60}}},
 596
 597             {{{1, 60},
 598               {1, 60},
 599               {1, 60},
 600               {1, 60},
 601               {1, 60},
 602               {1, 60},
 603               {1, 60},
 604               {0, 60}}},
 605
 606             {{{0, 60},
 607               {1, 60},
 608               {0, 60},
 609               {1, 60},
 610               {1, 60},
 611               {1, 60},
 612               {1, 60},
 613               {1, 60}}},
 614
 615             {{{0, 60},
 616               {1, 60},
 617               {1, 60},
 618               {0, 60},
 619               {1, 60},
 620               {0, 60},
 621               {0, 60},
 622               {0, 60}}},
 623
 624             {{{1, 60},
 625               {1, 60},
 626               {1, 60},
 627               {0, 60},
 628               {0, 60},
 629               {0, 60},
 630               {0, 60},
 631               {0, 60}}},
 632
 633             {{{1, 60},
 634               {1, 60},
 635               {1, 60},
 636               {1, 60},
 637               {1, 60},
 638               {0, 60},
 639               {0, 60},
 640               {0, 60}}},
 641
 642             {{{1, 60},
 643               {1, 60},
 644               {1, 60},
 645               {1, 60},
 646               {1, 60},
 647               {1, 60},
 648               {1, 60},
 649               {1, 60}}},
 650
 651             {{{1, 60},
 652               {1, 60},
 653               {0, 60},
 654               {1, 60},
 655               {1, 60},
 656               {1, 60},
 657               {1, 60},
 658               {0, 60}}},
 659
 660             {{{1, 60},
 661               {0, 60},
 662               {1, 60},
 663               {1, 60},
 664               {1, 60},
 665               {1, 60},
 666               {0, 60},
 667               {1, 60}}},
 668         }
 669 #else
 670         {
 671             {{{60, 1},
 672               {60, 1},
 673               {60, 1},
 674               {60, 1},
 675               {60, 1},
 676               {60, 1},
 677               {60, 1},
 678               {60, 0}}},
 679
 680             {{{60, 1},
 681               {60, 1},
 682               {60, 1},
 683               {60, 1},
 684               {60, 1},
 685               {60, 1},
 686               {60, 1},
 687               {60, 0}}},
 688
 689             {{{60, 0},
 690               {60, 1},
 691               {60, 0},
 692               {60, 1},
 693               {60, 1},
 694               {60, 1},
 695               {60, 1},
 696               {60, 1}}},
 697
 698             {{{60, 0},
 699               {60, 1},
 700               {60, 1},
 701               {60, 0},
 702               {60, 1},
 703               {60, 0},
 704               {60, 0},
 705               {60, 0}}},
 706
 707             {{{60, 1},
 708               {60, 1},
 709               {60, 1},
 710               {60, 0},
 711               {60, 0},
 712               {60, 0},
 713               {60, 0},
 714               {60, 0}}},
 715
 716             {{{60, 1},
 717               {60, 1},
 718               {60, 1},
 719               {60, 1},
 720               {60, 1},
 721               {60, 0},
 722               {60, 0},
 723               {60, 0}}},
 724
 725             {{{60, 1},
 726               {60, 1},
 727               {60, 1},
 728               {60, 1},
 729               {60, 1},
 730               {60, 1},
 731               {60, 1},
 732               {60, 1}}},
 733
 734             {{{60, 1},
 735               {60, 1},
 736               {60, 0},
 737               {60, 1},
 738               {60, 1},
 739               {60, 1},
 740               {60, 1},
 741               {60, 0}}},
 742
 743             {{{60, 1},
 744               {60, 0},
 745               {60, 1},
 746               {60, 1},
 747               {60, 1},
 748               {60, 1},
 749               {60, 0},
 750               {60, 1}}},
 751         }
 752 #endif
 753 };
 754
 755 #endif