2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
18 /* File: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_reg_map.h*/
20 /* Time: Wednesday Jan 6, 2010 [2:09:02 pm] */
22 /* Path: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top */
23 /* Arguments: /cad/denali/blueprint/3.7//Linux/blueprint -codegen */
24 /* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint/ath_ansic.codegen*/
25 /* -ath_ansic -Wdesc -I */
26 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top -I */
27 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint -I */
28 /* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint -I */
29 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig -odir */
30 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top -eval */
31 /* {$INCLUDE_SYSCONFIG_FILES=1} -eval */
32 /* $WAR_EV58615_for_ansic_codegen=1 osprey_reg.rdl */
34 /* Sources: /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/emulation_misc.rdl*/
35 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dma_reg_sysconfig.rdl*/
36 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/svd/blueprint/svd_reg.rdl*/
37 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_pcu_reg_sysconfig.rdl*/
38 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/merlin2_0_radio_reg_map.rdl*/
39 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dma_reg.rdl*/
40 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/efuse_reg.rdl*/
41 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_dcu_reg.rdl*/
42 /* /trees/yli/yli-dev/chips/osprey/2.0/ip/pcie_axi/blueprint/DWC_pcie_ep.rdl*/
43 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/apb_analog/analog_intf_reg.rdl*/
44 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_pcu/blueprint/mac_pcu_reg.rdl*/
45 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/rtc/blueprint/rtc_reg.rdl*/
46 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/DWC_pcie_dbi_axi_sysconfig.rdl*/
47 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/host_intf/rtl/blueprint/host_intf_reg.rdl*/
48 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/mac/rtl/mac_dma/blueprint/mac_qcu_reg.rdl*/
49 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/bb/blueprint/bb_reg_map.rdl*/
50 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/rtc_reg_sysconfig.rdl*/
51 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/efuse_reg_sysconfig.rdl*/
52 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/bb_reg_map_sysconfig.rdl*/
53 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/osprey_pcieconfig.rdl*/
54 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_reg.rdl*/
55 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/radio_65_reg_sysconfig.rdl*/
56 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/merlin2_0_radio_reg_sysconfig.rdl*/
57 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_qcu_reg_sysconfig.rdl*/
58 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/mac_dcu_reg_sysconfig.rdl*/
59 /* /trees/yli/yli-dev/chips/osprey/2.0/rtl/amba_mac/blueprint/rtc_sync_reg.rdl*/
60 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/analog_intf_reg_sysconfig.rdl*/
61 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/svd_reg_sysconfig.rdl*/
62 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/top/osprey_radio_reg.rdl*/
63 /* /trees/yli/yli-dev/chips/osprey/2.0/blueprint/sysconfig/host_intf_reg_sysconfig.rdl*/
64 /* /trees/yli/yli-dev/chips/osprey/2.0/env/blueprint/ath_ansic.pm*/
65 /* /cad/local/lib/perl/Pinfo.pm */
67 /* Blueprint: 3.7 (Fri Oct 5 10:32:33 PDT 2007) */
68 /* Machine: artemis */
69 /* OS: Linux 2.6.9-78.0.5.ELlargesmp */
72 /*This Register Map contains the complete register set for OSPREY. */
74 /* Copyright (C) 2010 Denali Software Inc. All rights reserved */
75 /* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
79 #ifndef __REG_OSPREY_REG_MAP_H__
80 #define __REG_OSPREY_REG_MAP_H__
82 #include "osprey_reg_map_macro.h"
83 #include "poseidon_reg_map_macro.h"
86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
96 volatile u_int32_t MAC_DMA_TXCFG; /* 0x30 - 0x34 */
97 volatile u_int32_t MAC_DMA_RXCFG; /* 0x34 - 0x38 */
98 volatile u_int32_t MAC_DMA_RXJLA; /* 0x38 - 0x3c */
99 volatile char pad__2[0x4]; /* 0x3c - 0x40 */
100 volatile u_int32_t MAC_DMA_MIBC; /* 0x40 - 0x44 */
101 volatile u_int32_t MAC_DMA_TOPS; /* 0x44 - 0x48 */
102 volatile u_int32_t MAC_DMA_RXNPTO; /* 0x48 - 0x4c */
103 volatile u_int32_t MAC_DMA_TXNPTO; /* 0x4c - 0x50 */
104 volatile u_int32_t MAC_DMA_RPGTO; /* 0x50 - 0x54 */
105 volatile char pad__3[0x4]; /* 0x54 - 0x58 */
106 volatile u_int32_t MAC_DMA_MACMISC; /* 0x58 - 0x5c */
107 volatile u_int32_t MAC_DMA_INTER; /* 0x5c - 0x60 */
108 volatile u_int32_t MAC_DMA_DATABUF; /* 0x60 - 0x64 */
109 volatile u_int32_t MAC_DMA_GTT; /* 0x64 - 0x68 */
110 volatile u_int32_t MAC_DMA_GTTM; /* 0x68 - 0x6c */
111 volatile u_int32_t MAC_DMA_CST; /* 0x6c - 0x70 */
112 volatile u_int32_t MAC_DMA_RXDP_SIZE; /* 0x70 - 0x74 */
113 volatile u_int32_t MAC_DMA_RX_QUEUE_HP_RXDP; /* 0x74 - 0x78 */
114 volatile u_int32_t MAC_DMA_RX_QUEUE_LP_RXDP; /* 0x78 - 0x7c */
115 volatile char pad__4[0x4]; /* 0x7c - 0x80 */
116 volatile u_int32_t MAC_DMA_ISR_P; /* 0x80 - 0x84 */
117 volatile u_int32_t MAC_DMA_ISR_S0; /* 0x84 - 0x88 */
118 volatile u_int32_t MAC_DMA_ISR_S1; /* 0x88 - 0x8c */
119 volatile u_int32_t MAC_DMA_ISR_S2; /* 0x8c - 0x90 */
120 volatile u_int32_t MAC_DMA_ISR_S3; /* 0x90 - 0x94 */
121 volatile u_int32_t MAC_DMA_ISR_S4; /* 0x94 - 0x98 */
122 volatile u_int32_t MAC_DMA_ISR_S5; /* 0x98 - 0x9c */
124 volatile u_int32_t MAC_DMA_ISR_S6; /* 0x9c - 0xa0 */
125 volatile u_int32_t MAC_DMA_IMR_P; /* 0xa0 - 0xa4 */
126 volatile u_int32_t MAC_DMA_IMR_S0; /* 0xa4 - 0xa8 */
127 volatile u_int32_t MAC_DMA_IMR_S1; /* 0xa8 - 0xac */
128 volatile u_int32_t MAC_DMA_IMR_S2; /* 0xac - 0xb0 */
129 volatile u_int32_t MAC_DMA_IMR_S3; /* 0xb0 - 0xb4 */
130 volatile u_int32_t MAC_DMA_IMR_S4; /* 0xb4 - 0xb8 */
131 volatile u_int32_t MAC_DMA_IMR_S5; /* 0xb8 - 0xbc */
133 volatile u_int32_t MAC_DMA_IMR_S6; /* 0xbc - 0xc0 */
134 volatile u_int32_t MAC_DMA_ISR_P_RAC; /* 0xc0 - 0xc4 */
135 volatile u_int32_t MAC_DMA_ISR_S0_S; /* 0xc4 - 0xc8 */
136 volatile u_int32_t MAC_DMA_ISR_S1_S; /* 0xc8 - 0xcc */
138 volatile u_int32_t MAC_DMA_ISR_S6_S; /* 0xcc - 0xd0 */
139 volatile u_int32_t MAC_DMA_ISR_S2_S; /* 0xd0 - 0xd4 */
140 volatile u_int32_t MAC_DMA_ISR_S3_S; /* 0xd4 - 0xd8 */
141 volatile u_int32_t MAC_DMA_ISR_S4_S; /* 0xd8 - 0xdc */
142 volatile u_int32_t MAC_DMA_ISR_S5_S; /* 0xdc - 0xe0 */
143 volatile u_int32_t MAC_DMA_DMADBG_0; /* 0xe0 - 0xe4 */
144 volatile u_int32_t MAC_DMA_DMADBG_1; /* 0xe4 - 0xe8 */
145 volatile u_int32_t MAC_DMA_DMADBG_2; /* 0xe8 - 0xec */
146 volatile u_int32_t MAC_DMA_DMADBG_3; /* 0xec - 0xf0 */
147 volatile u_int32_t MAC_DMA_DMADBG_4; /* 0xf0 - 0xf4 */
148 volatile u_int32_t MAC_DMA_DMADBG_5; /* 0xf4 - 0xf8 */
149 volatile u_int32_t MAC_DMA_DMADBG_6; /* 0xf8 - 0xfc */
150 volatile u_int32_t MAC_DMA_DMADBG_7; /* 0xfc - 0x100 */
151 volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0;
153 volatile u_int32_t MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8;
158 volatile char pad__0[0x800]; /* 0x0 - 0x800 */
159 volatile u_int32_t MAC_QCU_TXDP[10]; /* 0x800 - 0x828 */
160 volatile char pad__1[0x8]; /* 0x828 - 0x830 */
161 volatile u_int32_t MAC_QCU_STATUS_RING_START; /* 0x830 - 0x834 */
162 volatile u_int32_t MAC_QCU_STATUS_RING_END; /* 0x834 - 0x838 */
163 volatile u_int32_t MAC_QCU_STATUS_RING_CURRENT; /* 0x838 - 0x83c */
164 volatile char pad__2[0x4]; /* 0x83c - 0x840 */
165 volatile u_int32_t MAC_QCU_TXE; /* 0x840 - 0x844 */
166 volatile char pad__3[0x3c]; /* 0x844 - 0x880 */
167 volatile u_int32_t MAC_QCU_TXD; /* 0x880 - 0x884 */
168 volatile char pad__4[0x3c]; /* 0x884 - 0x8c0 */
169 volatile u_int32_t MAC_QCU_CBR[10]; /* 0x8c0 - 0x8e8 */
170 volatile char pad__5[0x18]; /* 0x8e8 - 0x900 */
171 volatile u_int32_t MAC_QCU_RDYTIME[10]; /* 0x900 - 0x928 */
172 volatile char pad__6[0x18]; /* 0x928 - 0x940 */
173 volatile u_int32_t MAC_QCU_ONESHOT_ARM_SC; /* 0x940 - 0x944 */
174 volatile char pad__7[0x3c]; /* 0x944 - 0x980 */
175 volatile u_int32_t MAC_QCU_ONESHOT_ARM_CC; /* 0x980 - 0x984 */
176 volatile char pad__8[0x3c]; /* 0x984 - 0x9c0 */
177 volatile u_int32_t MAC_QCU_MISC[10]; /* 0x9c0 - 0x9e8 */
178 volatile char pad__9[0x18]; /* 0x9e8 - 0xa00 */
179 volatile u_int32_t MAC_QCU_CNT[10]; /* 0xa00 - 0xa28 */
180 volatile char pad__10[0x18]; /* 0xa28 - 0xa40 */
181 volatile u_int32_t MAC_QCU_RDYTIME_SHDN; /* 0xa40 - 0xa44 */
182 volatile u_int32_t MAC_QCU_DESC_CRC_CHK; /* 0xa44 - 0xa48 */
184 volatile u_int32_t MAC_QCU_EOL; /* 0xa48 - 0xa4c */
188 volatile char pad__0[0x1000]; /* 0x0 - 0x1000 */
189 volatile u_int32_t MAC_DCU_QCUMASK[10]; /* 0x1000 - 0x1028 */
190 volatile char pad__1[0x8]; /* 0x1028 - 0x1030 */
191 volatile u_int32_t MAC_DCU_GBL_IFS_SIFS; /* 0x1030 - 0x1034 */
192 volatile char pad__2[0x4]; /* 0x1034 - 0x1038 */
193 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_31_0; /* 0x1038 - 0x103c */
194 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_31_0; /* 0x103c - 0x1040 */
195 volatile u_int32_t MAC_DCU_LCL_IFS[10]; /* 0x1040 - 0x1068 */
196 volatile char pad__3[0x8]; /* 0x1068 - 0x1070 */
197 volatile u_int32_t MAC_DCU_GBL_IFS_SLOT; /* 0x1070 - 0x1074 */
198 volatile char pad__4[0x4]; /* 0x1074 - 0x1078 */
199 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_63_32; /* 0x1078 - 0x107c */
200 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_63_32; /* 0x107c - 0x1080 */
201 volatile u_int32_t MAC_DCU_RETRY_LIMIT[10]; /* 0x1080 - 0x10a8 */
202 volatile char pad__5[0x8]; /* 0x10a8 - 0x10b0 */
203 volatile u_int32_t MAC_DCU_GBL_IFS_EIFS; /* 0x10b0 - 0x10b4 */
204 volatile char pad__6[0x4]; /* 0x10b4 - 0x10b8 */
205 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_95_64; /* 0x10b8 - 0x10bc */
206 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_95_64; /* 0x10bc - 0x10c0 */
207 volatile u_int32_t MAC_DCU_CHANNEL_TIME[10]; /* 0x10c0 - 0x10e8 */
208 volatile char pad__7[0x8]; /* 0x10e8 - 0x10f0 */
209 volatile u_int32_t MAC_DCU_GBL_IFS_MISC; /* 0x10f0 - 0x10f4 */
210 volatile char pad__8[0x4]; /* 0x10f4 - 0x10f8 */
211 volatile u_int32_t MAC_DCU_TXFILTER_DCU0_127_96;
212 /* 0x10f8 - 0x10fc */
213 volatile u_int32_t MAC_DCU_TXFILTER_DCU8_127_96;
214 /* 0x10fc - 0x1100 */
215 volatile u_int32_t MAC_DCU_MISC[10]; /* 0x1100 - 0x1128 */
216 volatile char pad__9[0x10]; /* 0x1128 - 0x1138 */
217 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_31_0; /* 0x1138 - 0x113c */
218 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_31_0; /* 0x113c - 0x1140 */
219 volatile u_int32_t MAC_DCU_SEQ; /* 0x1140 - 0x1144 */
220 volatile char pad__10[0x34]; /* 0x1144 - 0x1178 */
221 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_63_32; /* 0x1178 - 0x117c */
222 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_63_32; /* 0x117c - 0x1180 */
223 volatile char pad__11[0x38]; /* 0x1180 - 0x11b8 */
224 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_95_64; /* 0x11b8 - 0x11bc */
225 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_95_64; /* 0x11bc - 0x11c0 */
226 volatile char pad__12[0x38]; /* 0x11c0 - 0x11f8 */
227 volatile u_int32_t MAC_DCU_TXFILTER_DCU1_127_96;
228 /* 0x11f8 - 0x11fc */
229 volatile u_int32_t MAC_DCU_TXFILTER_DCU9_127_96;
230 /* 0x11fc - 0x1200 */
231 volatile char pad__13[0x38]; /* 0x1200 - 0x1238 */
232 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_31_0; /* 0x1238 - 0x123c */
233 volatile char pad__14[0x34]; /* 0x123c - 0x1270 */
234 volatile u_int32_t MAC_DCU_PAUSE; /* 0x1270 - 0x1274 */
235 volatile char pad__15[0x4]; /* 0x1274 - 0x1278 */
236 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_63_32; /* 0x1278 - 0x127c */
237 volatile char pad__16[0x34]; /* 0x127c - 0x12b0 */
238 volatile u_int32_t MAC_DCU_WOW_KACFG; /* 0x12b0 - 0x12b4 */
239 volatile char pad__17[0x4]; /* 0x12b4 - 0x12b8 */
240 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_95_64; /* 0x12b8 - 0x12bc */
241 volatile char pad__18[0x34]; /* 0x12bc - 0x12f0 */
242 volatile u_int32_t MAC_DCU_TXSLOT; /* 0x12f0 - 0x12f4 */
243 volatile char pad__19[0x4]; /* 0x12f4 - 0x12f8 */
244 volatile u_int32_t MAC_DCU_TXFILTER_DCU2_127_96;
245 /* 0x12f8 - 0x12fc */
246 volatile char pad__20[0x3c]; /* 0x12fc - 0x1338 */
247 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_31_0; /* 0x1338 - 0x133c */
248 volatile char pad__21[0x3c]; /* 0x133c - 0x1378 */
249 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_63_32; /* 0x1378 - 0x137c */
250 volatile char pad__22[0x3c]; /* 0x137c - 0x13b8 */
251 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_95_64; /* 0x13b8 - 0x13bc */
252 volatile char pad__23[0x3c]; /* 0x13bc - 0x13f8 */
253 volatile u_int32_t MAC_DCU_TXFILTER_DCU3_127_96;
254 /* 0x13f8 - 0x13fc */
255 volatile char pad__24[0x3c]; /* 0x13fc - 0x1438 */
256 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_31_0; /* 0x1438 - 0x143c */
257 volatile u_int32_t MAC_DCU_TXFILTER_CLEAR; /* 0x143c - 0x1440 */
258 volatile char pad__25[0x38]; /* 0x1440 - 0x1478 */
259 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_63_32; /* 0x1478 - 0x147c */
260 volatile u_int32_t MAC_DCU_TXFILTER_SET; /* 0x147c - 0x1480 */
261 volatile char pad__26[0x38]; /* 0x1480 - 0x14b8 */
262 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_95_64; /* 0x14b8 - 0x14bc */
263 volatile char pad__27[0x3c]; /* 0x14bc - 0x14f8 */
264 volatile u_int32_t MAC_DCU_TXFILTER_DCU4_127_96;
265 /* 0x14f8 - 0x14fc */
266 volatile char pad__28[0x3c]; /* 0x14fc - 0x1538 */
267 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_31_0; /* 0x1538 - 0x153c */
268 volatile char pad__29[0x3c]; /* 0x153c - 0x1578 */
269 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_63_32; /* 0x1578 - 0x157c */
270 volatile char pad__30[0x3c]; /* 0x157c - 0x15b8 */
271 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_95_64; /* 0x15b8 - 0x15bc */
272 volatile char pad__31[0x3c]; /* 0x15bc - 0x15f8 */
273 volatile u_int32_t MAC_DCU_TXFILTER_DCU5_127_96;
274 /* 0x15f8 - 0x15fc */
275 volatile char pad__32[0x3c]; /* 0x15fc - 0x1638 */
276 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_31_0; /* 0x1638 - 0x163c */
277 volatile char pad__33[0x3c]; /* 0x163c - 0x1678 */
278 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_63_32; /* 0x1678 - 0x167c */
279 volatile char pad__34[0x3c]; /* 0x167c - 0x16b8 */
280 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_95_64; /* 0x16b8 - 0x16bc */
281 volatile char pad__35[0x3c]; /* 0x16bc - 0x16f8 */
282 volatile u_int32_t MAC_DCU_TXFILTER_DCU6_127_96;
283 /* 0x16f8 - 0x16fc */
284 volatile char pad__36[0x3c]; /* 0x16fc - 0x1738 */
285 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_31_0; /* 0x1738 - 0x173c */
286 volatile char pad__37[0x3c]; /* 0x173c - 0x1778 */
287 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_63_32; /* 0x1778 - 0x177c */
288 volatile char pad__38[0x3c]; /* 0x177c - 0x17b8 */
289 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_95_64; /* 0x17b8 - 0x17bc */
290 volatile char pad__39[0x3c]; /* 0x17bc - 0x17f8 */
291 volatile u_int32_t MAC_DCU_TXFILTER_DCU7_127_96;
292 /* 0x17f8 - 0x17fc */
295 struct host_intf_reg {
296 volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */
297 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
298 volatile u_int32_t HOST_INTF_WORK_AROUND; /* 0x4004 - 0x4008 */
299 volatile u_int32_t HOST_INTF_PM_STATE; /* 0x4008 - 0x400c */
300 volatile u_int32_t HOST_INTF_CXPL_DEBUG_INFOL; /* 0x400c - 0x4010 */
301 volatile u_int32_t HOST_INTF_CXPL_DEBUG_INFOH; /* 0x4010 - 0x4014 */
302 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4014 - 0x4018 */
303 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4018 - 0x401c */
304 volatile u_int32_t HOST_INTF_EEPROM_CTRL; /* 0x401c - 0x4020 */
305 volatile u_int32_t HOST_INTF_SREV; /* 0x4020 - 0x4024 */
306 volatile char pad__1[0x4]; /* 0x4024 - 0x4028 */
307 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4028 - 0x402c */
308 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x402c - 0x4030 */
309 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4030 - 0x4034 */
310 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x4034 - 0x4038 */
311 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4038 - 0x403c */
312 volatile u_int32_t HOST_INTF_INTR_ASYNC_ENABLE; /* 0x403c - 0x4040 */
313 volatile u_int32_t HOST_INTF_PCIE_PHY_RW; /* 0x4040 - 0x4044 */
314 volatile u_int32_t HOST_INTF_PCIE_PHY_LOAD; /* 0x4044 - 0x4048 */
315 volatile u_int32_t HOST_INTF_GPIO_OUT; /* 0x4048 - 0x404c */
316 volatile u_int32_t HOST_INTF_GPIO_IN; /* 0x404c - 0x4050 */
317 volatile u_int32_t HOST_INTF_GPIO_OE; /* 0x4050 - 0x4054 */
318 volatile u_int32_t HOST_INTF_GPIO_OE1; /* 0x4054 - 0x4058 */
319 volatile u_int32_t HOST_INTF_GPIO_INTR_POLAR; /* 0x4058 - 0x405c */
320 volatile u_int32_t HOST_INTF_GPIO_INPUT_VALUE; /* 0x405c - 0x4060 */
321 volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX1; /* 0x4060 - 0x4064 */
322 volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX2; /* 0x4064 - 0x4068 */
323 volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX1; /* 0x4068 - 0x406c */
324 volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX2; /* 0x406c - 0x4070 */
325 volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX3; /* 0x4070 - 0x4074 */
326 volatile u_int32_t HOST_INTF_GPIO_INPUT_STATE; /* 0x4074 - 0x4078 */
327 volatile u_int32_t HOST_INTF_SPARE; /* 0x4078 - 0x407c */
328 volatile u_int32_t HOST_INTF_PCIE_CORE_RST_EN; /* 0x407c - 0x4080 */
329 volatile u_int32_t HOST_INTF_CLKRUN; /* 0x4080 - 0x4084 */
330 volatile u_int32_t HOST_INTF_EEPROM_STS; /* 0x4084 - 0x4088 */
331 volatile u_int32_t HOST_INTF_OBS_CTRL; /* 0x4088 - 0x408c */
332 volatile u_int32_t HOST_INTF_RFSILENT; /* 0x408c - 0x4090 */
333 volatile u_int32_t HOST_INTF_GPIO_PDPU; /* 0x4090 - 0x4094 */
334 volatile u_int32_t HOST_INTF_GPIO_PDPU1; /* 0x4094 - 0x4098 */
335 volatile u_int32_t HOST_INTF_GPIO_DS; /* 0x4098 - 0x409c */
336 volatile u_int32_t HOST_INTF_GPIO_DS1; /* 0x409c - 0x40a0 */
337 volatile u_int32_t HOST_INTF_MISC; /* 0x40a0 - 0x40a4 */
338 volatile u_int32_t HOST_INTF_PCIE_MSI; /* 0x40a4 - 0x40a8 */
339 volatile char pad__2[0x8]; /* 0x40a8 - 0x40b0 */
340 volatile u_int32_t HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ;
341 /* 0x40b0 - 0x40b4 */
342 volatile u_int32_t HOST_INTF_MAC_TDMA_CCA_CNTL; /* 0x40b4 - 0x40b8 */
343 volatile u_int32_t HOST_INTF_MAC_TXAPSYNC; /* 0x40b8 - 0x40bc */
344 volatile u_int32_t HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR;
345 /* 0x40bc - 0x40c0 */
346 volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_CAUSE;
347 /* 0x40c0 - 0x40c4 */
348 volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_ENABLE;
349 /* 0x40c4 - 0x40c8 */
350 volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_MASK;
351 /* 0x40c8 - 0x40cc */
352 volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_MASK;
353 /* 0x40cc - 0x40d0 */
354 volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE;
355 /* 0x40d0 - 0x40d4 */
356 volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE;
357 /* 0x40d4 - 0x40d8 */
358 volatile u_int32_t HOST_INTF_OTP; /* 0x40d8 - 0x40dc */
359 volatile char pad__3[0x4]; /* 0x40dc - 0x40e0 */
360 volatile u_int32_t PCIE_CO_ERR_CTR0; /* 0x40e0 - 0x40e4 */
361 volatile u_int32_t PCIE_CO_ERR_CTR1; /* 0x40e4 - 0x40e8 */
362 volatile u_int32_t PCIE_CO_ERR_CTR_CTRL; /* 0x40e8 - 0x40ec */
363 /* Poseidon, Jupiter */
364 volatile u_int32_t AXI_INTERCONNECT_CTRL; /* 0x40ec - 0x40f0 */
366 volatile u_int32_t PCIE_AXI_BRIDGE_CTRL; /* 0x40f0 - 0x40f4 */
369 struct emulation_misc_regs {
370 volatile char pad__0[0x4f00]; /* 0x0 - 0x4f00 */
371 volatile u_int32_t FPGA_PHY_LAYER_REVID; /* 0x4f00 - 0x4f04 */
372 volatile u_int32_t FPGA_LINK_LAYER_REVID; /* 0x4f04 - 0x4f08 */
373 volatile u_int32_t FPGA_REG1; /* 0x4f08 - 0x4f0c */
374 volatile u_int32_t FPGA_REG2; /* 0x4f0c - 0x4f10 */
375 volatile u_int32_t FPGA_REG3; /* 0x4f10 - 0x4f14 */
376 volatile u_int32_t FPGA_REG4; /* 0x4f14 - 0x4f18 */
377 volatile u_int32_t FPGA_REG5; /* 0x4f18 - 0x4f1c */
378 volatile u_int32_t FPGA_REG6; /* 0x4f1c - 0x4f20 */
379 volatile u_int32_t FPGA_REG7; /* 0x4f20 - 0x4f24 */
380 volatile u_int32_t FPGA_REG8; /* 0x4f24 - 0x4f28 */
381 volatile u_int32_t FPGA_REG9; /* 0x4f28 - 0x4f2c */
382 volatile u_int32_t FPGA_REG10; /* 0x4f2c - 0x4f30 */
383 /* Aphrodite-start */
384 volatile u_int32_t FPGA_REG11; /* 0x4f30 - 0x4f34 */
385 volatile u_int32_t FPGA_REG12; /* 0x4f34 - 0x4f38 */
386 volatile u_int32_t FPGA_REG13; /* 0x4f38 - 0x4f3c */
387 volatile u_int32_t FPGA_REG14; /* 0x4f3c - 0x4f40 */
391 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_0 {
392 volatile u_int32_t ID; /* 0x0 - 0x4 */
393 volatile u_int32_t STS_CMD_RGSTR; /* 0x4 - 0x8 */
394 volatile u_int32_t CLS_REV_ID; /* 0x8 - 0xc */
395 volatile u_int32_t BIST_HEAD_LAT_CACH; /* 0xc - 0x10 */
396 volatile u_int32_t BAS_ADR_0; /* 0x10 - 0x14 */
397 volatile u_int32_t BAS_ADR_1; /* 0x14 - 0x18 */
398 volatile u_int32_t BAS_ADR_2; /* 0x18 - 0x1c */
399 volatile u_int32_t BAS_ADR_3; /* 0x1c - 0x20 */
400 volatile u_int32_t BAS_ADR_4; /* 0x20 - 0x24 */
401 volatile u_int32_t BAS_ADR_5; /* 0x24 - 0x28 */
402 volatile u_int32_t CRD_CIS_PTR; /* 0x28 - 0x2c */
403 volatile u_int32_t Sub_VenID; /* 0x2c - 0x30 */
404 volatile u_int32_t EXP_ROM_ADDR; /* 0x30 - 0x34 */
405 volatile u_int32_t CAPPTR; /* 0x34 - 0x38 */
406 volatile u_int32_t RESERVE2; /* 0x38 - 0x3c */
407 volatile u_int32_t LAT_INT; /* 0x3c - 0x40 */
410 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_1 {
411 volatile u_int32_t CFG_PWR_CAP; /* 0x0 - 0x4 */
412 volatile u_int32_t PWR_CSR; /* 0x4 - 0x8 */
415 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_2 {
416 volatile u_int32_t MSG_CTR; /* 0x0 - 0x4 */
417 volatile u_int32_t MSI_L32; /* 0x4 - 0x8 */
418 volatile u_int32_t MSI_U32; /* 0x8 - 0xc */
419 volatile u_int32_t MSI_DATA; /* 0xc - 0x10 */
422 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_3 {
423 volatile u_int32_t PCIE_CAP; /* 0x0 - 0x4 */
424 volatile u_int32_t DEV_CAP; /* 0x4 - 0x8 */
425 volatile u_int32_t DEV_STS_CTRL; /* 0x8 - 0xc */
426 volatile u_int32_t LNK_CAP; /* 0xc - 0x10 */
427 volatile u_int32_t LNK_STS_CTRL; /* 0x10 - 0x14 */
428 volatile u_int32_t SLT_CAP; /* 0x14 - 0x18 */
429 volatile u_int32_t SLT_STS_CTRL; /* 0x18 - 0x1c */
432 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_5 {
433 volatile u_int32_t VPD_CAP; /* 0x0 - 0x4 */
434 volatile u_int32_t VPD_DATA; /* 0x4 - 0x8 */
437 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_6 {
438 volatile u_int32_t PCIE_EN_CAP_AER; /* 0x0 - 0x4 */
439 volatile u_int32_t UN_ERR_ST_R; /* 0x4 - 0x8 */
440 volatile u_int32_t UN_ERR_MS_R; /* 0x8 - 0xc */
441 volatile u_int32_t UN_ERR_SV_R; /* 0xc - 0x10 */
442 volatile u_int32_t CO_ERR_ST_R; /* 0x10 - 0x14 */
443 volatile u_int32_t CO_ERR_MS_R; /* 0x14 - 0x18 */
444 volatile u_int32_t ADERR_CAP_CR; /* 0x18 - 0x1c */
445 volatile u_int32_t HD_L_R0; /* 0x1c - 0x20 */
446 volatile u_int32_t HD_L_R4; /* 0x20 - 0x24 */
447 volatile u_int32_t HD_L_R8; /* 0x24 - 0x28 */
448 volatile u_int32_t HD_L_R12; /* 0x28 - 0x2c */
451 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7 {
452 volatile u_int32_t PCIE_EN_CAP_VC; /* 0x0 - 0x4 */
453 volatile u_int32_t PVC_CAP_R1; /* 0x4 - 0x8 */
454 volatile u_int32_t P_CAP_R2; /* 0x8 - 0xc */
455 volatile u_int32_t PVC_STS_CTRL; /* 0xc - 0x10 */
456 volatile u_int32_t VC_CAP_R; /* 0x10 - 0x14 */
457 volatile u_int32_t VC_CTL_R; /* 0x14 - 0x18 */
458 volatile u_int32_t VC_STS_RSV; /* 0x18 - 0x1c */
459 volatile u_int32_t VCR_CAP_R1; /* 0x1c - 0x20 */
460 volatile u_int32_t VCR_CTRL_R1; /* 0x20 - 0x24 */
461 volatile u_int32_t VCR_STS_R1; /* 0x24 - 0x28 */
464 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7_Jupiter {
465 volatile u_int32_t PCIE_EN_CAP_VC; /* 0x0 - 0x4 */
466 volatile u_int32_t PVC_CAP_R1; /* 0x4 - 0x8 */
467 volatile u_int32_t P_CAP_R2; /* 0x8 - 0xc */
468 volatile u_int32_t PVC_STS_CTRL; /* 0xc - 0x10 */
469 volatile u_int32_t VC_CAP_R; /* 0x10 - 0x14 */
470 volatile u_int32_t VC_CTL_R; /* 0x14 - 0x18 */
471 volatile u_int32_t VC_STS_RSV; /* 0x18 - 0x1c */
474 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_8 {
475 volatile u_int32_t DEV_EN_CAP; /* 0x0 - 0x4 */
476 volatile u_int32_t SN_R1; /* 0x4 - 0x8 */
477 volatile u_int32_t SN_R2; /* 0x8 - 0xc */
480 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_9 {
481 volatile u_int32_t LAT_REL_TIM; /* 0x0 - 0x4 */
482 volatile u_int32_t OT_MSG_R; /* 0x4 - 0x8 */
483 volatile u_int32_t PT_LNK_R; /* 0x8 - 0xc */
484 volatile u_int32_t ACk_FREQ_R; /* 0xc - 0x10 */
485 volatile u_int32_t PT_LNK_CTRL_R; /* 0x10 - 0x14 */
486 volatile u_int32_t LN_SKW_R; /* 0x14 - 0x18 */
487 volatile u_int32_t SYMB_N_R; /* 0x18 - 0x1c */
488 volatile u_int32_t SYMB_T_R; /* 0x1c - 0x20 */
489 volatile u_int32_t FL_MSK_R2; /* 0x20 - 0x24 */
490 volatile char pad__0[0x4]; /* 0x24 - 0x28 */
491 volatile u_int32_t DB_R0; /* 0x28 - 0x2c */
492 volatile u_int32_t DB_R1; /* 0x2c - 0x30 */
493 volatile u_int32_t TR_P_STS_R; /* 0x30 - 0x34 */
494 volatile u_int32_t TR_NP_STS_R; /* 0x34 - 0x38 */
495 volatile u_int32_t TR_C_STS_R; /* 0x38 - 0x3c */
496 volatile u_int32_t Q_STS_R; /* 0x3c - 0x40 */
497 volatile u_int32_t VC_TR_A_R1; /* 0x40 - 0x44 */
498 volatile u_int32_t VC_TR_A_R2; /* 0x44 - 0x48 */
499 volatile u_int32_t VC0_PR_Q_C; /* 0x48 - 0x4c */
500 volatile u_int32_t VC0_NPR_Q_C; /* 0x4c - 0x50 */
501 volatile u_int32_t VC0_CR_Q_C; /* 0x50 - 0x54 */
502 volatile u_int32_t VC1_PR_Q_C; /* 0x54 - 0x58 */
503 volatile u_int32_t VC1_NPR_Q_C; /* 0x58 - 0x5c */
504 volatile u_int32_t VC1_CR_Q_C; /* 0x5c - 0x60 */
505 volatile u_int32_t VC2_PR_Q_C; /* 0x60 - 0x64 */
506 volatile u_int32_t VC2_NPR_Q_C; /* 0x64 - 0x68 */
507 volatile u_int32_t VC2_CR_Q_C; /* 0x68 - 0x6c */
508 volatile u_int32_t VC3_PR_Q_C; /* 0x6c - 0x70 */
509 volatile u_int32_t VC3_NPR_Q_C; /* 0x70 - 0x74 */
510 volatile u_int32_t VC3_CR_Q_C; /* 0x74 - 0x78 */
511 volatile u_int32_t VC4_PR_Q_C; /* 0x78 - 0x7c */
512 volatile u_int32_t VC4_NPR_Q_C; /* 0x7c - 0x80 */
513 volatile u_int32_t VC4_CR_Q_C; /* 0x80 - 0x84 */
514 volatile u_int32_t VC5_PR_Q_C; /* 0x84 - 0x88 */
515 volatile u_int32_t VC5_NPR_Q_C; /* 0x88 - 0x8c */
516 volatile u_int32_t VC5_CR_Q_C; /* 0x8c - 0x90 */
517 volatile u_int32_t VC6_PR_Q_C; /* 0x90 - 0x94 */
518 volatile u_int32_t VC6_NPR_Q_C; /* 0x94 - 0x98 */
519 volatile u_int32_t VC6_CR_Q_C; /* 0x98 - 0x9c */
520 volatile u_int32_t VC7_PR_Q_C; /* 0x9c - 0xa0 */
521 volatile u_int32_t VC7_NPR_Q_C; /* 0xa0 - 0xa4 */
522 volatile u_int32_t VC7_CR_Q_C; /* 0xa4 - 0xa8 */
523 volatile u_int32_t VC0_PB_D; /* 0xa8 - 0xac */
524 volatile u_int32_t VC0_NPB_D; /* 0xac - 0xb0 */
525 volatile u_int32_t VC0_CB_D; /* 0xb0 - 0xb4 */
526 volatile u_int32_t VC1_PB_D; /* 0xb4 - 0xb8 */
527 volatile u_int32_t VC1_NPB_D; /* 0xb8 - 0xbc */
528 volatile u_int32_t VC1_CB_D; /* 0xbc - 0xc0 */
529 volatile u_int32_t VC2_PB_D; /* 0xc0 - 0xc4 */
530 volatile u_int32_t VC2_NPB_D; /* 0xc4 - 0xc8 */
531 volatile u_int32_t VC2_CB_D; /* 0xc8 - 0xcc */
532 volatile u_int32_t VC3_PB_D; /* 0xcc - 0xd0 */
533 volatile u_int32_t VC3_NPB_D; /* 0xd0 - 0xd4 */
534 volatile u_int32_t VC3_CB_D; /* 0xd4 - 0xd8 */
535 volatile u_int32_t VC4_PB_D; /* 0xd8 - 0xdc */
536 volatile u_int32_t VC4_NPB_D; /* 0xdc - 0xe0 */
537 volatile u_int32_t VC4_CB_D; /* 0xe0 - 0xe4 */
538 volatile u_int32_t VC5_PB_D; /* 0xe4 - 0xe8 */
539 volatile u_int32_t VC5_NPB_D; /* 0xe8 - 0xec */
540 volatile u_int32_t VC5_CB_D; /* 0xec - 0xf0 */
541 volatile u_int32_t VC6_PB_D; /* 0xf0 - 0xf4 */
542 volatile u_int32_t VC6_NPB_D; /* 0xf4 - 0xf8 */
543 volatile u_int32_t VC6_CB_D; /* 0xf8 - 0xfc */
544 volatile u_int32_t VC7_PB_D; /* 0xfc - 0x100 */
545 volatile u_int32_t VC7_NPB_D; /* 0x100 - 0x104 */
546 volatile u_int32_t VC7_CB_D; /* 0x104 - 0x108 */
547 volatile char pad__1[0x4]; /* 0x108 - 0x10c */
548 volatile u_int32_t GEN2; /* 0x10c - 0x110 */
549 volatile u_int32_t PHY_STS_R; /* 0x110 - 0x114 */
550 volatile u_int32_t PHY_CTRL_R; /* 0x114 - 0x118 */
553 struct DWC_pcie_dbi_axi {
554 volatile char pad__0[0x5000]; /* 0x0 - 0x5000 */
555 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_0 DWC_pcie_dbi_axi_0;
556 /* 0x5000 - 0x5040 */
557 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_1 DWC_pcie_dbi_axi_1;
558 /* 0x5040 - 0x5048 */
559 volatile char pad__1[0x8]; /* 0x5048 - 0x5050 */
560 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_2 DWC_pcie_dbi_axi_2;
561 /* 0x5050 - 0x5060 */
562 volatile char pad__2[0x10]; /* 0x5060 - 0x5070 */
563 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_3 DWC_pcie_dbi_axi_3;
564 /* 0x5070 - 0x508c */
565 volatile char pad__3[0x44]; /* 0x508c - 0x50d0 */
566 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_5 DWC_pcie_dbi_axi_5;
567 /* 0x50d0 - 0x50d8 */
568 volatile char pad__4[0x28]; /* 0x50d8 - 0x5100 */
569 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_6 DWC_pcie_dbi_axi_6;
570 /* 0x5100 - 0x512c */
571 volatile char pad__5[0x14]; /* 0x512c - 0x5140 */
574 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7 DWC_pcie_dbi_axi_7;
575 /* 0x5140 - 0x5168 */
576 volatile char pad__1[0x198]; /* 0x5168 - 0x5300 */
577 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_8 DWC_pcie_dbi_axi_8;
578 /* 0x5300 - 0x530c */
579 volatile char pad__2[0x3f4]; /* 0x530c - 0x5700 */
582 struct pcie_dbi_axi {
583 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_7_Jupiter DWC_pcie_dbi_axi_7;
584 /* 0x5140 - 0x515c */
585 volatile char pad__1[0x4]; /* 0x515c - 0x5160 */
586 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_8 DWC_pcie_dbi_axi_8;
587 /* 0x5160 - 0x516c */
588 volatile char pad__2[0x594]; /* 0x516c - 0x5700 */
590 } overlay_0x5140; /* 0x5140 - 0x5700 */
591 struct DWC_pcie_dbi_axi__DWC_pcie_dbi_axi_9 DWC_pcie_dbi_axi_9;
592 /* 0x5700 - 0x5818 */
596 volatile char pad__0[0x7000]; /* 0x0 - 0x7000 */
597 volatile u_int32_t RESET_CONTROL; /* 0x7000 - 0x7004 */
598 volatile u_int32_t XTAL_CONTROL; /* 0x7004 - 0x7008 */
599 volatile u_int32_t REG_CONTROL0; /* 0x7008 - 0x700c */
600 volatile u_int32_t REG_CONTROL1; /* 0x700c - 0x7010 */
601 volatile u_int32_t QUADRATURE; /* 0x7010 - 0x7014 */
602 volatile u_int32_t PLL_CONTROL; /* 0x7014 - 0x7018 */
603 volatile u_int32_t PLL_SETTLE; /* 0x7018 - 0x701c */
604 volatile u_int32_t XTAL_SETTLE; /* 0x701c - 0x7020 */
605 volatile u_int32_t CLOCK_OUT; /* 0x7020 - 0x7024 */
606 volatile u_int32_t BIAS_OVERRIDE; /* 0x7024 - 0x7028 */
607 volatile u_int32_t RESET_CAUSE; /* 0x7028 - 0x702c */
608 volatile u_int32_t SYSTEM_SLEEP; /* 0x702c - 0x7030 */
609 volatile u_int32_t MAC_SLEEP_CONTROL; /* 0x7030 - 0x7034 */
610 volatile u_int32_t KEEP_AWAKE; /* 0x7034 - 0x7038 */
611 volatile u_int32_t DERIVED_RTC_CLK; /* 0x7038 - 0x703c */
612 volatile u_int32_t PLL_CONTROL2; /* 0x703c - 0x7040 */
615 struct rtc_sync_reg {
616 volatile char pad__0[0x7040]; /* 0x0 - 0x7040 */
617 volatile u_int32_t RTC_SYNC_RESET; /* 0x7040 - 0x7044 */
618 volatile u_int32_t RTC_SYNC_STATUS; /* 0x7044 - 0x7048 */
619 volatile u_int32_t RTC_SYNC_DERIVED; /* 0x7048 - 0x704c */
620 volatile u_int32_t RTC_SYNC_FORCE_WAKE; /* 0x704c - 0x7050 */
621 volatile u_int32_t RTC_SYNC_INTR_CAUSE; /* 0x7050 - 0x7054 */
622 volatile u_int32_t RTC_SYNC_INTR_ENABLE; /* 0x7054 - 0x7058 */
623 volatile u_int32_t RTC_SYNC_INTR_MASK; /* 0x7058 - 0x705c */
626 struct merlin2_0_radio_reg_map {
627 volatile char pad__0[0x7800]; /* 0x0 - 0x7800 */
628 volatile u_int32_t RXTXBB1_CH1; /* 0x7800 - 0x7804 */
629 volatile u_int32_t RXTXBB2_CH1; /* 0x7804 - 0x7808 */
630 volatile u_int32_t RXTXBB3_CH1; /* 0x7808 - 0x780c */
631 volatile u_int32_t RXTXBB4_CH1; /* 0x780c - 0x7810 */
632 volatile u_int32_t RF2G1_CH1; /* 0x7810 - 0x7814 */
633 volatile u_int32_t RF2G2_CH1; /* 0x7814 - 0x7818 */
634 volatile u_int32_t RF5G1_CH1; /* 0x7818 - 0x781c */
635 volatile u_int32_t RF5G2_CH1; /* 0x781c - 0x7820 */
636 volatile u_int32_t RF5G3_CH1; /* 0x7820 - 0x7824 */
637 volatile u_int32_t RXTXBB1_CH0; /* 0x7824 - 0x7828 */
638 volatile u_int32_t RXTXBB2_CH0; /* 0x7828 - 0x782c */
639 volatile u_int32_t RXTXBB3_CH0; /* 0x782c - 0x7830 */
640 volatile u_int32_t RXTXBB4_CH0; /* 0x7830 - 0x7834 */
641 volatile u_int32_t RF5G1_CH0; /* 0x7834 - 0x7838 */
642 volatile u_int32_t RF5G2_CH0; /* 0x7838 - 0x783c */
643 volatile u_int32_t RF5G3_CH0; /* 0x783c - 0x7840 */
644 volatile u_int32_t RF2G1_CH0; /* 0x7840 - 0x7844 */
645 volatile u_int32_t RF2G2_CH0; /* 0x7844 - 0x7848 */
646 volatile u_int32_t SYNTH1; /* 0x7848 - 0x784c */
647 volatile u_int32_t SYNTH2; /* 0x784c - 0x7850 */
648 volatile u_int32_t SYNTH3; /* 0x7850 - 0x7854 */
649 volatile u_int32_t SYNTH4; /* 0x7854 - 0x7858 */
650 volatile u_int32_t SYNTH5; /* 0x7858 - 0x785c */
651 volatile u_int32_t SYNTH6; /* 0x785c - 0x7860 */
652 volatile u_int32_t SYNTH7; /* 0x7860 - 0x7864 */
653 volatile u_int32_t SYNTH8; /* 0x7864 - 0x7868 */
654 volatile u_int32_t SYNTH9; /* 0x7868 - 0x786c */
655 volatile u_int32_t SYNTH10; /* 0x786c - 0x7870 */
656 volatile u_int32_t SYNTH11; /* 0x7870 - 0x7874 */
657 volatile u_int32_t BIAS1; /* 0x7874 - 0x7878 */
658 volatile u_int32_t BIAS2; /* 0x7878 - 0x787c */
659 volatile u_int32_t BIAS3; /* 0x787c - 0x7880 */
660 volatile u_int32_t BIAS4; /* 0x7880 - 0x7884 */
661 volatile u_int32_t GAIN0; /* 0x7884 - 0x7888 */
662 volatile u_int32_t GAIN1; /* 0x7888 - 0x788c */
663 volatile u_int32_t TOP0; /* 0x788c - 0x7890 */
664 volatile u_int32_t TOP1; /* 0x7890 - 0x7894 */
665 volatile u_int32_t TOP2; /* 0x7894 - 0x7898 */
666 volatile u_int32_t TOP3; /* 0x7898 - 0x789c */
669 struct analog_intf_reg_csr {
670 volatile char pad__0[0x7900]; /* 0x0 - 0x7900 */
671 volatile u_int32_t SW_OVERRIDE; /* 0x7900 - 0x7904 */
672 volatile u_int32_t SIN_VAL; /* 0x7904 - 0x7908 */
673 volatile u_int32_t SW_SCLK; /* 0x7908 - 0x790c */
674 volatile u_int32_t SW_CNTL; /* 0x790c - 0x7910 */
678 volatile char pad__0[0x8000]; /* 0x0 - 0x8000 */
679 volatile u_int32_t MAC_PCU_STA_ADDR_L32; /* 0x8000 - 0x8004 */
680 volatile u_int32_t MAC_PCU_STA_ADDR_U16; /* 0x8004 - 0x8008 */
681 volatile u_int32_t MAC_PCU_BSSID_L32; /* 0x8008 - 0x800c */
682 volatile u_int32_t MAC_PCU_BSSID_U16; /* 0x800c - 0x8010 */
683 volatile u_int32_t MAC_PCU_BCN_RSSI_AVE; /* 0x8010 - 0x8014 */
684 volatile u_int32_t MAC_PCU_ACK_CTS_TIMEOUT; /* 0x8014 - 0x8018 */
685 volatile u_int32_t MAC_PCU_BCN_RSSI_CTL; /* 0x8018 - 0x801c */
686 volatile u_int32_t MAC_PCU_USEC_LATENCY; /* 0x801c - 0x8020 */
687 volatile u_int32_t MAC_PCU_RESET_TSF; /* 0x8020 - 0x8024 */
688 volatile char pad__1[0x14]; /* 0x8024 - 0x8038 */
689 volatile u_int32_t MAC_PCU_MAX_CFP_DUR; /* 0x8038 - 0x803c */
690 volatile u_int32_t MAC_PCU_RX_FILTER; /* 0x803c - 0x8040 */
691 volatile u_int32_t MAC_PCU_MCAST_FILTER_L32; /* 0x8040 - 0x8044 */
692 volatile u_int32_t MAC_PCU_MCAST_FILTER_U32; /* 0x8044 - 0x8048 */
693 volatile u_int32_t MAC_PCU_DIAG_SW; /* 0x8048 - 0x804c */
694 volatile u_int32_t MAC_PCU_TSF_L32; /* 0x804c - 0x8050 */
695 volatile u_int32_t MAC_PCU_TSF_U32; /* 0x8050 - 0x8054 */
696 volatile u_int32_t MAC_PCU_TST_ADDAC; /* 0x8054 - 0x8058 */
697 volatile u_int32_t MAC_PCU_DEF_ANTENNA; /* 0x8058 - 0x805c */
698 volatile u_int32_t MAC_PCU_AES_MUTE_MASK_0; /* 0x805c - 0x8060 */
699 volatile u_int32_t MAC_PCU_AES_MUTE_MASK_1; /* 0x8060 - 0x8064 */
700 volatile u_int32_t MAC_PCU_GATED_CLKS; /* 0x8064 - 0x8068 */
701 volatile u_int32_t MAC_PCU_OBS_BUS_2; /* 0x8068 - 0x806c */
702 volatile u_int32_t MAC_PCU_OBS_BUS_1; /* 0x806c - 0x8070 */
703 volatile u_int32_t MAC_PCU_DYM_MIMO_PWR_SAVE; /* 0x8070 - 0x8074 */
704 volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB;
705 /* 0x8074 - 0x8078 */
706 volatile u_int32_t MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB;
707 /* 0x8078 - 0x807c */
708 volatile char pad__2[0x4]; /* 0x807c - 0x8080 */
709 volatile u_int32_t MAC_PCU_LAST_BEACON_TSF; /* 0x8080 - 0x8084 */
710 volatile u_int32_t MAC_PCU_NAV; /* 0x8084 - 0x8088 */
711 volatile u_int32_t MAC_PCU_RTS_SUCCESS_CNT; /* 0x8088 - 0x808c */
712 volatile u_int32_t MAC_PCU_RTS_FAIL_CNT; /* 0x808c - 0x8090 */
713 volatile u_int32_t MAC_PCU_ACK_FAIL_CNT; /* 0x8090 - 0x8094 */
714 volatile u_int32_t MAC_PCU_FCS_FAIL_CNT; /* 0x8094 - 0x8098 */
715 volatile u_int32_t MAC_PCU_BEACON_CNT; /* 0x8098 - 0x809c */
716 volatile u_int32_t MAC_PCU_TDMA_SLOT_ALERT_CNTL;
717 /* 0x809c - 0x80a0 */
718 volatile u_int32_t MAC_PCU_BASIC_SET; /* 0x80a0 - 0x80a4 */
719 volatile u_int32_t MAC_PCU_MGMT_SEQ; /* 0x80a4 - 0x80a8 */
720 volatile u_int32_t MAC_PCU_BF_RPT1; /* 0x80a8 - 0x80ac */
721 volatile u_int32_t MAC_PCU_BF_RPT2; /* 0x80ac - 0x80b0 */
722 volatile u_int32_t MAC_PCU_TX_ANT_1; /* 0x80b0 - 0x80b4 */
723 volatile u_int32_t MAC_PCU_TX_ANT_2; /* 0x80b4 - 0x80b8 */
724 volatile u_int32_t MAC_PCU_TX_ANT_3; /* 0x80b8 - 0x80bc */
725 volatile u_int32_t MAC_PCU_TX_ANT_4; /* 0x80bc - 0x80c0 */
726 volatile u_int32_t MAC_PCU_XRMODE; /* 0x80c0 - 0x80c4 */
727 volatile u_int32_t MAC_PCU_XRDEL; /* 0x80c4 - 0x80c8 */
728 volatile u_int32_t MAC_PCU_XRTO; /* 0x80c8 - 0x80cc */
729 volatile u_int32_t MAC_PCU_XRCRP; /* 0x80cc - 0x80d0 */
730 volatile u_int32_t MAC_PCU_XRSTMP; /* 0x80d0 - 0x80d4 */
731 volatile u_int32_t MAC_PCU_SLP1; /* 0x80d4 - 0x80d8 */
732 volatile u_int32_t MAC_PCU_SLP2; /* 0x80d8 - 0x80dc */
733 volatile u_int32_t MAC_PCU_SELF_GEN_DEFAULT; /* 0x80dc - 0x80e0 */
734 volatile u_int32_t MAC_PCU_ADDR1_MASK_L32; /* 0x80e0 - 0x80e4 */
735 volatile u_int32_t MAC_PCU_ADDR1_MASK_U16; /* 0x80e4 - 0x80e8 */
736 volatile u_int32_t MAC_PCU_TPC; /* 0x80e8 - 0x80ec */
737 volatile u_int32_t MAC_PCU_TX_FRAME_CNT; /* 0x80ec - 0x80f0 */
738 volatile u_int32_t MAC_PCU_RX_FRAME_CNT; /* 0x80f0 - 0x80f4 */
739 volatile u_int32_t MAC_PCU_RX_CLEAR_CNT; /* 0x80f4 - 0x80f8 */
740 volatile u_int32_t MAC_PCU_CYCLE_CNT; /* 0x80f8 - 0x80fc */
741 volatile u_int32_t MAC_PCU_QUIET_TIME_1; /* 0x80fc - 0x8100 */
742 volatile u_int32_t MAC_PCU_QUIET_TIME_2; /* 0x8100 - 0x8104 */
743 volatile char pad__3[0x4]; /* 0x8104 - 0x8108 */
744 volatile u_int32_t MAC_PCU_QOS_NO_ACK; /* 0x8108 - 0x810c */
745 volatile u_int32_t MAC_PCU_PHY_ERROR_MASK; /* 0x810c - 0x8110 */
746 volatile u_int32_t MAC_PCU_XRLAT; /* 0x8110 - 0x8114 */
747 volatile u_int32_t MAC_PCU_RXBUF; /* 0x8114 - 0x8118 */
748 volatile u_int32_t MAC_PCU_MIC_QOS_CONTROL; /* 0x8118 - 0x811c */
749 volatile u_int32_t MAC_PCU_MIC_QOS_SELECT; /* 0x811c - 0x8120 */
750 volatile u_int32_t MAC_PCU_MISC_MODE; /* 0x8120 - 0x8124 */
751 volatile u_int32_t MAC_PCU_FILTER_OFDM_CNT; /* 0x8124 - 0x8128 */
752 volatile u_int32_t MAC_PCU_FILTER_CCK_CNT; /* 0x8128 - 0x812c */
753 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1; /* 0x812c - 0x8130 */
754 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_1_MASK; /* 0x8130 - 0x8134 */
755 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2; /* 0x8134 - 0x8138 */
756 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_2_MASK; /* 0x8138 - 0x813c */
757 volatile u_int32_t MAC_PCU_TSF_THRESHOLD; /* 0x813c - 0x8140 */
758 volatile char pad__4[0x4]; /* 0x8140 - 0x8144 */
759 volatile u_int32_t MAC_PCU_PHY_ERROR_EIFS_MASK; /* 0x8144 - 0x8148 */
760 volatile char pad__5[0x20]; /* 0x8148 - 0x8168 */
761 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3; /* 0x8168 - 0x816c */
762 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_3_MASK; /* 0x816c - 0x8170 */
763 volatile u_int32_t MAC_PCU_BLUETOOTH_MODE; /* 0x8170 - 0x8174 */
764 volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS0;
765 /* 0x8174 - 0x8178 */
766 volatile u_int32_t MAC_PCU_HCF_TIMEOUT; /* 0x8178 - 0x817c */
767 volatile u_int32_t MAC_PCU_BLUETOOTH_MODE2; /* 0x817c - 0x8180 */
768 volatile u_int32_t MAC_PCU_GENERIC_TIMERS2[16]; /* 0x8180 - 0x81c0 */
769 volatile u_int32_t MAC_PCU_GENERIC_TIMERS2_MODE;
770 /* 0x81c0 - 0x81c4 */
771 volatile u_int32_t MAC_PCU_BLUETOOTH_WL_WEIGHTS1;
772 /* 0x81c4 - 0x81c8 */
773 volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE;
774 /* 0x81c8 - 0x81cc */
775 volatile u_int32_t MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY;
776 /* 0x81cc - 0x81d0 */
777 volatile u_int32_t MAC_PCU_TXSIFS; /* 0x81d0 - 0x81d4 */
778 volatile u_int32_t MAC_PCU_BLUETOOTH_MODE3; /* 0x81d4 - 0x81d8 */
779 volatile char pad__6[0x14]; /* 0x81d8 - 0x81ec */
780 volatile u_int32_t MAC_PCU_TXOP_X; /* 0x81ec - 0x81f0 */
781 volatile u_int32_t MAC_PCU_TXOP_0_3; /* 0x81f0 - 0x81f4 */
782 volatile u_int32_t MAC_PCU_TXOP_4_7; /* 0x81f4 - 0x81f8 */
783 volatile u_int32_t MAC_PCU_TXOP_8_11; /* 0x81f8 - 0x81fc */
784 volatile u_int32_t MAC_PCU_TXOP_12_15; /* 0x81fc - 0x8200 */
785 volatile u_int32_t MAC_PCU_GENERIC_TIMERS[16]; /* 0x8200 - 0x8240 */
786 volatile u_int32_t MAC_PCU_GENERIC_TIMERS_MODE; /* 0x8240 - 0x8244 */
787 volatile u_int32_t MAC_PCU_SLP32_MODE; /* 0x8244 - 0x8248 */
788 volatile u_int32_t MAC_PCU_SLP32_WAKE; /* 0x8248 - 0x824c */
789 volatile u_int32_t MAC_PCU_SLP32_INC; /* 0x824c - 0x8250 */
790 volatile u_int32_t MAC_PCU_SLP_MIB1; /* 0x8250 - 0x8254 */
791 volatile u_int32_t MAC_PCU_SLP_MIB2; /* 0x8254 - 0x8258 */
792 volatile u_int32_t MAC_PCU_SLP_MIB3; /* 0x8258 - 0x825c */
793 volatile u_int32_t MAC_PCU_WOW1; /* 0x825c - 0x8260 */
794 volatile u_int32_t MAC_PCU_WOW2; /* 0x8260 - 0x8264 */
795 volatile u_int32_t MAC_PCU_LOGIC_ANALYZER; /* 0x8264 - 0x8268 */
796 volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_32L; /* 0x8268 - 0x826c */
797 volatile u_int32_t MAC_PCU_LOGIC_ANALYZER_16U; /* 0x826c - 0x8270 */
798 volatile u_int32_t MAC_PCU_WOW3_BEACON_FAIL; /* 0x8270 - 0x8274 */
799 volatile u_int32_t MAC_PCU_WOW3_BEACON; /* 0x8274 - 0x8278 */
800 volatile u_int32_t MAC_PCU_WOW3_KEEP_ALIVE; /* 0x8278 - 0x827c */
801 volatile u_int32_t MAC_PCU_WOW_KA; /* 0x827c - 0x8280 */
802 volatile char pad__7[0x4]; /* 0x8280 - 0x8284 */
803 volatile u_int32_t PCU_1US; /* 0x8284 - 0x8288 */
804 volatile u_int32_t PCU_KA; /* 0x8288 - 0x828c */
805 volatile u_int32_t WOW_EXACT; /* 0x828c - 0x8290 */
806 volatile char pad__8[0x4]; /* 0x8290 - 0x8294 */
807 volatile u_int32_t PCU_WOW4; /* 0x8294 - 0x8298 */
808 volatile u_int32_t PCU_WOW5; /* 0x8298 - 0x829c */
809 volatile u_int32_t MAC_PCU_PHY_ERR_CNT_MASK_CONT;
810 /* 0x829c - 0x82a0 */
811 volatile char pad__9[0x60]; /* 0x82a0 - 0x8300 */
812 volatile u_int32_t MAC_PCU_AZIMUTH_MODE; /* 0x8300 - 0x8304 */
813 volatile char pad__10[0x10]; /* 0x8304 - 0x8314 */
814 volatile u_int32_t MAC_PCU_AZIMUTH_TIME_STAMP; /* 0x8314 - 0x8318 */
815 volatile u_int32_t MAC_PCU_20_40_MODE; /* 0x8318 - 0x831c */
816 volatile u_int32_t MAC_PCU_H_XFER_TIMEOUT; /* 0x831c - 0x8320 */
817 volatile char pad__11[0x8]; /* 0x8320 - 0x8328 */
818 volatile u_int32_t MAC_PCU_RX_CLEAR_DIFF_CNT; /* 0x8328 - 0x832c */
819 volatile u_int32_t MAC_PCU_SELF_GEN_ANTENNA_MASK;
820 /* 0x832c - 0x8330 */
821 volatile u_int32_t MAC_PCU_BA_BAR_CONTROL; /* 0x8330 - 0x8334 */
822 volatile u_int32_t MAC_PCU_LEGACY_PLCP_SPOOF; /* 0x8334 - 0x8338 */
823 volatile u_int32_t MAC_PCU_PHY_ERROR_MASK_CONT; /* 0x8338 - 0x833c */
824 volatile u_int32_t MAC_PCU_TX_TIMER; /* 0x833c - 0x8340 */
825 volatile u_int32_t MAC_PCU_TXBUF_CTRL; /* 0x8340 - 0x8344 */
826 volatile u_int32_t MAC_PCU_MISC_MODE2; /* 0x8344 - 0x8348 */
827 volatile u_int32_t MAC_PCU_ALT_AES_MUTE_MASK; /* 0x8348 - 0x834c */
828 volatile u_int32_t MAC_PCU_WOW6; /* 0x834c - 0x8350 */
829 volatile u_int32_t ASYNC_FIFO_REG1; /* 0x8350 - 0x8354 */
830 volatile u_int32_t ASYNC_FIFO_REG2; /* 0x8354 - 0x8358 */
831 volatile u_int32_t ASYNC_FIFO_REG3; /* 0x8358 - 0x835c */
832 volatile u_int32_t MAC_PCU_WOW5; /* 0x835c - 0x8360 */
833 volatile u_int32_t MAC_PCU_WOW_LENGTH1; /* 0x8360 - 0x8364 */
834 volatile u_int32_t MAC_PCU_WOW_LENGTH2; /* 0x8364 - 0x8368 */
835 volatile u_int32_t WOW_PATTERN_MATCH_LESS_THAN_256_BYTES;
836 /* 0x8368 - 0x836c */
837 volatile char pad__12[0x4]; /* 0x836c - 0x8370 */
838 volatile u_int32_t MAC_PCU_WOW4; /* 0x8370 - 0x8374 */
839 volatile u_int32_t WOW2_EXACT; /* 0x8374 - 0x8378 */
840 volatile u_int32_t PCU_WOW6; /* 0x8378 - 0x837c */
841 volatile u_int32_t PCU_WOW7; /* 0x837c - 0x8380 */
842 volatile u_int32_t MAC_PCU_WOW_LENGTH3; /* 0x8380 - 0x8384 */
843 volatile u_int32_t MAC_PCU_WOW_LENGTH4; /* 0x8384 - 0x8388 */
844 volatile u_int32_t MAC_PCU_LOCATION_MODE_CONTROL;
845 /* 0x8388 - 0x838c */
846 volatile u_int32_t MAC_PCU_LOCATION_MODE_TIMER; /* 0x838c - 0x8390 */
847 volatile u_int32_t MAC_PCU_TSF2_L32; /* 0x8390 - 0x8394 */
848 volatile u_int32_t MAC_PCU_TSF2_U32; /* 0x8394 - 0x8398 */
849 volatile u_int32_t MAC_PCU_BSSID2_L32; /* 0x8398 - 0x839c */
850 volatile u_int32_t MAC_PCU_BSSID2_U16; /* 0x839c - 0x83a0 */
851 volatile u_int32_t MAC_PCU_DIRECT_CONNECT; /* 0x83a0 - 0x83a4 */
852 volatile u_int32_t MAC_PCU_TID_TO_AC; /* 0x83a4 - 0x83a8 */
853 volatile u_int32_t MAC_PCU_HP_QUEUE; /* 0x83a8 - 0x83ac */
854 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS0;
855 /* 0x83ac - 0x83b0 */
856 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS1;
857 /* 0x83b0 - 0x83b4 */
858 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS2;
859 /* 0x83b4 - 0x83b8 */
860 volatile u_int32_t MAC_PCU_BLUETOOTH_BT_WEIGHTS3;
861 /* 0x83b8 - 0x83bc */
862 volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT0; /* 0x83bc - 0x83c0 */
863 volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT1; /* 0x83c0 - 0x83c4 */
864 volatile u_int32_t MAC_PCU_AGC_SATURATION_CNT2; /* 0x83c4 - 0x83c8 */
865 volatile u_int32_t MAC_PCU_HW_BCN_PROC1; /* 0x83c8 - 0x83cc */
866 volatile u_int32_t MAC_PCU_HW_BCN_PROC2; /* 0x83cc - 0x83d0 */
867 volatile u_int32_t MAC_PCU_MISC_MODE3; /* 0x83d0 - 0x83d4 */
869 volatile u_int32_t MAC_PCU_FILTER_RSSI_AVE; /* 0x83d4 - 0x83d8 */
871 volatile u_int32_t MAC_PCU_GENERIC_TIMERS_TSF_SEL;
872 /* 0x83d8 - 0x83dc */
874 volatile u_int32_t MAC_PCU_BEACON2_CNT; /* 0x83dc - 0x83e0 */
876 volatile u_int32_t MAC_PCU_LAST_BEACON2_TSF; /* 0x83e0 - 0x83e4 */
878 volatile u_int32_t MAC_PCU_BMISS_TIMEOUT; /* 0x83e4 - 0x83e8 */
880 volatile u_int32_t MAC_PCU_BMISS2_TIMEOUT; /* 0x83e8 - 0x83ec */
882 volatile u_int32_t MAC_PCU_SLP3; /* 0x83ec - 0x83f0 */
884 volatile u_int32_t MAC_PCU_BCN_RSSI_CTL2; /* 0x83f0 - 0x83f4 */
886 volatile u_int32_t MAC_PCU_PHY_ERROR_AIFS_MASK; /* 0x83f4 - 0x83f8 */
888 volatile u_int32_t MAC_PCU_TBD_FILTER; /* 0x83f8 - 0x83fc */
890 volatile u_int32_t MAC_PCU_MISC_MODE4; /* 0x83fc - 0x8400 */
891 volatile u_int32_t MAC_PCU_TXBUF_BA[64]; /* 0x8400 - 0x8500 */
893 volatile u_int32_t MAC_PCU_SLP4; /* 0x8500 - 0x8504 */
894 volatile char pad__13[0x2fc]; /* 0x8504 - 0x8800 */
895 volatile u_int32_t MAC_PCU_KEY_CACHE[1024]; /* 0x8800 - 0x9800 */
896 volatile char pad__14[0x4800]; /* 0x9800 - 0xe000 */
897 volatile u_int32_t MAC_PCU_BUF[2048]; /* 0xe000 - 0x10000 */
901 volatile u_int32_t BB_timing_controls_1; /* 0x0 - 0x4 */
902 volatile u_int32_t BB_timing_controls_2; /* 0x4 - 0x8 */
903 volatile u_int32_t BB_timing_controls_3; /* 0x8 - 0xc */
904 volatile u_int32_t BB_timing_control_4; /* 0xc - 0x10 */
905 volatile u_int32_t BB_timing_control_5; /* 0x10 - 0x14 */
906 volatile u_int32_t BB_timing_control_6; /* 0x14 - 0x18 */
907 volatile u_int32_t BB_timing_control_11; /* 0x18 - 0x1c */
908 volatile u_int32_t BB_spur_mask_controls; /* 0x1c - 0x20 */
909 volatile u_int32_t BB_find_signal_low; /* 0x20 - 0x24 */
910 volatile u_int32_t BB_sfcorr; /* 0x24 - 0x28 */
911 volatile u_int32_t BB_self_corr_low; /* 0x28 - 0x2c */
912 volatile u_int32_t BB_ext_chan_scorr_thr; /* 0x2c - 0x30 */
913 volatile u_int32_t BB_ext_chan_pwr_thr_2_b0; /* 0x30 - 0x34 */
914 volatile u_int32_t BB_radar_detection; /* 0x34 - 0x38 */
915 volatile u_int32_t BB_radar_detection_2; /* 0x38 - 0x3c */
916 volatile u_int32_t BB_extension_radar; /* 0x3c - 0x40 */
917 volatile char pad__0[0x40]; /* 0x40 - 0x80 */
918 volatile u_int32_t BB_multichain_control; /* 0x80 - 0x84 */
919 volatile u_int32_t BB_per_chain_csd; /* 0x84 - 0x88 */
920 volatile char pad__1[0x18]; /* 0x88 - 0xa0 */
921 volatile u_int32_t BB_tx_crc; /* 0xa0 - 0xa4 */
922 volatile u_int32_t BB_tstdac_constant; /* 0xa4 - 0xa8 */
923 volatile u_int32_t BB_spur_report_b0; /* 0xa8 - 0xac */
924 volatile char pad__2[0x4]; /* 0xac - 0xb0 */
925 volatile u_int32_t BB_txiqcal_control_3; /* 0xb0 - 0xb4 */
926 volatile char pad__3[0x8]; /* 0xb4 - 0xbc */
927 /* Poseidon, Jupiter */
928 volatile u_int32_t BB_green_tx_control_1; /* 0xbc - 0xc0 */
929 volatile u_int32_t BB_iq_adc_meas_0_b0; /* 0xc0 - 0xc4 */
930 volatile u_int32_t BB_iq_adc_meas_1_b0; /* 0xc4 - 0xc8 */
931 volatile u_int32_t BB_iq_adc_meas_2_b0; /* 0xc8 - 0xcc */
932 volatile u_int32_t BB_iq_adc_meas_3_b0; /* 0xcc - 0xd0 */
933 volatile u_int32_t BB_tx_phase_ramp_b0; /* 0xd0 - 0xd4 */
934 volatile u_int32_t BB_adc_gain_dc_corr_b0; /* 0xd4 - 0xd8 */
935 volatile char pad__4[0x4]; /* 0xd8 - 0xdc */
936 volatile u_int32_t BB_rx_iq_corr_b0; /* 0xdc - 0xe0 */
937 volatile char pad__5[0x4]; /* 0xe0 - 0xe4 */
938 volatile u_int32_t BB_paprd_am2am_mask; /* 0xe4 - 0xe8 */
939 volatile u_int32_t BB_paprd_am2pm_mask; /* 0xe8 - 0xec */
940 volatile u_int32_t BB_paprd_ht40_mask; /* 0xec - 0xf0 */
941 volatile u_int32_t BB_paprd_ctrl0_b0; /* 0xf0 - 0xf4 */
942 volatile u_int32_t BB_paprd_ctrl1_b0; /* 0xf4 - 0xf8 */
943 volatile u_int32_t BB_pa_gain123_b0; /* 0xf8 - 0xfc */
944 volatile u_int32_t BB_pa_gain45_b0; /* 0xfc - 0x100 */
945 volatile u_int32_t BB_paprd_pre_post_scale_0_b0;
947 volatile u_int32_t BB_paprd_pre_post_scale_1_b0;
949 volatile u_int32_t BB_paprd_pre_post_scale_2_b0;
951 volatile u_int32_t BB_paprd_pre_post_scale_3_b0;
953 volatile u_int32_t BB_paprd_pre_post_scale_4_b0;
955 volatile u_int32_t BB_paprd_pre_post_scale_5_b0;
957 volatile u_int32_t BB_paprd_pre_post_scale_6_b0;
959 volatile u_int32_t BB_paprd_pre_post_scale_7_b0;
961 volatile u_int32_t BB_paprd_mem_tab_b0[120]; /* 0x120 - 0x300 */
962 volatile u_int32_t BB_chan_info_chan_tab_b0[60];
965 volatile u_int32_t BB_chn_tables_intf_addr; /* 0x3f0 - 0x3f4 */
967 volatile u_int32_t BB_chn_tables_intf_data; /* 0x3f4 - 0x3f8 */
971 volatile u_int32_t BB_timing_control_3a; /* 0x0 - 0x4 */
972 volatile u_int32_t BB_ldpc_cntl1; /* 0x4 - 0x8 */
973 volatile u_int32_t BB_ldpc_cntl2; /* 0x8 - 0xc */
974 volatile u_int32_t BB_pilot_spur_mask; /* 0xc - 0x10 */
975 volatile u_int32_t BB_chan_spur_mask; /* 0x10 - 0x14 */
976 volatile u_int32_t BB_short_gi_delta_slope; /* 0x14 - 0x18 */
977 volatile u_int32_t BB_ml_cntl1; /* 0x18 - 0x1c */
978 volatile u_int32_t BB_ml_cntl2; /* 0x1c - 0x20 */
979 volatile u_int32_t BB_tstadc; /* 0x20 - 0x24 */
983 volatile u_int32_t BB_bbb_rx_ctrl_1; /* 0x0 - 0x4 */
984 volatile u_int32_t BB_bbb_rx_ctrl_2; /* 0x4 - 0x8 */
985 volatile u_int32_t BB_bbb_rx_ctrl_3; /* 0x8 - 0xc */
986 volatile u_int32_t BB_bbb_rx_ctrl_4; /* 0xc - 0x10 */
987 volatile u_int32_t BB_bbb_rx_ctrl_5; /* 0x10 - 0x14 */
988 volatile u_int32_t BB_bbb_rx_ctrl_6; /* 0x14 - 0x18 */
989 volatile u_int32_t BB_force_clken_cck; /* 0x18 - 0x1c */
990 /* Poseidon, Jupiter_10 */
991 volatile u_int32_t BB_bb_reg_page_control; /* 0x1c - 0x20 */
995 volatile u_int32_t BB_settling_time; /* 0x0 - 0x4 */
996 volatile u_int32_t BB_gain_force_max_gains_b0; /* 0x4 - 0x8 */
997 volatile u_int32_t BB_gains_min_offsets; /* 0x8 - 0xc */
998 volatile u_int32_t BB_desired_sigsize; /* 0xc - 0x10 */
999 volatile u_int32_t BB_find_signal; /* 0x10 - 0x14 */
1000 volatile u_int32_t BB_agc; /* 0x14 - 0x18 */
1001 volatile u_int32_t BB_ext_atten_switch_ctl_b0; /* 0x18 - 0x1c */
1002 volatile u_int32_t BB_cca_b0; /* 0x1c - 0x20 */
1003 volatile u_int32_t BB_cca_ctrl_2_b0; /* 0x20 - 0x24 */
1004 volatile u_int32_t BB_restart; /* 0x24 - 0x28 */
1005 volatile u_int32_t BB_multichain_gain_ctrl; /* 0x28 - 0x2c */
1006 volatile u_int32_t BB_ext_chan_pwr_thr_1; /* 0x2c - 0x30 */
1007 volatile u_int32_t BB_ext_chan_detect_win; /* 0x30 - 0x34 */
1008 volatile u_int32_t BB_pwr_thr_20_40_det; /* 0x34 - 0x38 */
1009 volatile u_int32_t BB_rifs_srch; /* 0x38 - 0x3c */
1010 volatile u_int32_t BB_peak_det_ctrl_1; /* 0x3c - 0x40 */
1011 volatile u_int32_t BB_peak_det_ctrl_2; /* 0x40 - 0x44 */
1012 volatile u_int32_t BB_rx_gain_bounds_1; /* 0x44 - 0x48 */
1013 volatile u_int32_t BB_rx_gain_bounds_2; /* 0x48 - 0x4c */
1014 volatile u_int32_t BB_peak_det_cal_ctrl; /* 0x4c - 0x50 */
1015 volatile u_int32_t BB_agc_dig_dc_ctrl; /* 0x50 - 0x54 */
1016 volatile u_int32_t BB_bt_coex_1; /* 0x54 - 0x58 */
1017 /* Poseidon, Jupiter */
1018 volatile u_int32_t BB_bt_coex_2; /* 0x58 - 0x5c */
1019 /* Poseidon, Jupiter */
1020 volatile u_int32_t BB_bt_coex_3; /* 0x5c - 0x60 */
1021 /* Poseidon, Jupiter */
1022 volatile u_int32_t BB_bt_coex_4; /* 0x60 - 0x64 */
1023 /* Poseidon, Jupiter */
1024 volatile u_int32_t BB_bt_coex_5; /* 0x64 - 0x68 */
1026 volatile u_int32_t BB_redpwr_ctrl_1; /* 0x68 - 0x6c */
1028 volatile u_int32_t BB_redpwr_ctrl_2; /* 0x6c - 0x70 */
1029 volatile char pad__0[0x110]; /* 0x70 - 0x180 */
1030 volatile u_int32_t BB_rssi_b0; /* 0x180 - 0x184 */
1031 volatile u_int32_t BB_spur_est_cck_report_b0; /* 0x184 - 0x188 */
1032 volatile u_int32_t BB_agc_dig_dc_status_i_b0; /* 0x188 - 0x18c */
1033 volatile u_int32_t BB_agc_dig_dc_status_q_b0; /* 0x18c - 0x190 */
1034 /* Poseidon, Jupiter */
1035 volatile u_int32_t BB_dc_cal_status_b0; /* 0x190 - 0x194 */
1036 volatile char pad__1[0x2c]; /* 0x194 - 0x1c0 */
1037 volatile u_int32_t BB_bbb_sig_detect; /* 0x1c0 - 0x1c4 */
1038 volatile u_int32_t BB_bbb_dagc_ctrl; /* 0x1c4 - 0x1c8 */
1039 volatile u_int32_t BB_iqcorr_ctrl_cck; /* 0x1c8 - 0x1cc */
1040 volatile u_int32_t BB_cck_spur_mit; /* 0x1cc - 0x1d0 */
1042 volatile u_int32_t BB_mrc_cck_ctrl; /* 0x1d0 - 0x1d4 */
1044 volatile u_int32_t BB_cck_blocker_det; /* 0x1d4 - 0x1d8 */
1045 volatile char pad__2[0x28]; /* 0x1d8 - 0x200 */
1046 volatile u_int32_t BB_rx_ocgain[128]; /* 0x200 - 0x400 */
1050 volatile u_int32_t BB_D2_chip_id; /* 0x0 - 0x4 */
1051 volatile u_int32_t BB_gen_controls; /* 0x4 - 0x8 */
1052 volatile u_int32_t BB_modes_select; /* 0x8 - 0xc */
1053 volatile u_int32_t BB_active; /* 0xc - 0x10 */
1054 /* Poseidon, Jupiter_10 */
1055 volatile u_int32_t BB_bb_reg_page; /* 0x10 - 0x14 */
1056 volatile char pad__0[0xc]; /* 0x14 - 0x20 */
1057 volatile u_int32_t BB_vit_spur_mask_A; /* 0x20 - 0x24 */
1058 volatile u_int32_t BB_vit_spur_mask_B; /* 0x24 - 0x28 */
1059 volatile u_int32_t BB_spectral_scan; /* 0x28 - 0x2c */
1060 volatile u_int32_t BB_radar_bw_filter; /* 0x2c - 0x30 */
1061 volatile u_int32_t BB_search_start_delay; /* 0x30 - 0x34 */
1062 volatile u_int32_t BB_max_rx_length; /* 0x34 - 0x38 */
1063 volatile u_int32_t BB_frame_control; /* 0x38 - 0x3c */
1064 volatile u_int32_t BB_rfbus_request; /* 0x3c - 0x40 */
1065 volatile u_int32_t BB_rfbus_grant; /* 0x40 - 0x44 */
1066 volatile u_int32_t BB_rifs; /* 0x44 - 0x48 */
1068 volatile u_int32_t BB_spectral_scan_2; /* 0x48 - 0x4c */
1069 volatile char pad__1[0x4]; /* 0x4c - 0x50 */
1070 volatile u_int32_t BB_rx_clear_delay; /* 0x50 - 0x54 */
1071 volatile u_int32_t BB_analog_power_on_time; /* 0x54 - 0x58 */
1072 volatile u_int32_t BB_tx_timing_1; /* 0x58 - 0x5c */
1073 volatile u_int32_t BB_tx_timing_2; /* 0x5c - 0x60 */
1074 volatile u_int32_t BB_tx_timing_3; /* 0x60 - 0x64 */
1075 volatile u_int32_t BB_xpa_timing_control; /* 0x64 - 0x68 */
1076 volatile char pad__2[0x18]; /* 0x68 - 0x80 */
1077 volatile u_int32_t BB_misc_pa_control; /* 0x80 - 0x84 */
1078 volatile u_int32_t BB_switch_table_chn_b0; /* 0x84 - 0x88 */
1079 volatile u_int32_t BB_switch_table_com1; /* 0x88 - 0x8c */
1080 volatile u_int32_t BB_switch_table_com2; /* 0x8c - 0x90 */
1081 volatile char pad__3[0x10]; /* 0x90 - 0xa0 */
1082 volatile u_int32_t BB_multichain_enable; /* 0xa0 - 0xa4 */
1083 volatile char pad__4[0x1c]; /* 0xa4 - 0xc0 */
1084 volatile u_int32_t BB_cal_chain_mask; /* 0xc0 - 0xc4 */
1085 volatile u_int32_t BB_agc_control; /* 0xc4 - 0xc8 */
1086 volatile u_int32_t BB_iq_adc_cal_mode; /* 0xc8 - 0xcc */
1087 volatile u_int32_t BB_fcal_1; /* 0xcc - 0xd0 */
1088 volatile u_int32_t BB_fcal_2_b0; /* 0xd0 - 0xd4 */
1089 volatile u_int32_t BB_dft_tone_ctrl_b0; /* 0xd4 - 0xd8 */
1090 volatile u_int32_t BB_cl_cal_ctrl; /* 0xd8 - 0xdc */
1091 volatile u_int32_t BB_cl_map_0_b0; /* 0xdc - 0xe0 */
1092 volatile u_int32_t BB_cl_map_1_b0; /* 0xe0 - 0xe4 */
1093 volatile u_int32_t BB_cl_map_2_b0; /* 0xe4 - 0xe8 */
1094 volatile u_int32_t BB_cl_map_3_b0; /* 0xe8 - 0xec */
1095 volatile u_int32_t BB_cl_map_pal_0_b0; /* 0xec - 0xf0 */
1096 volatile u_int32_t BB_cl_map_pal_1_b0; /* 0xf0 - 0xf4 */
1097 volatile u_int32_t BB_cl_map_pal_2_b0; /* 0xf4 - 0xf8 */
1098 volatile u_int32_t BB_cl_map_pal_3_b0; /* 0xf8 - 0xfc */
1099 volatile char pad__5[0x4]; /* 0xfc - 0x100 */
1100 volatile u_int32_t BB_cl_tab_b0[16]; /* 0x100 - 0x140 */
1101 volatile u_int32_t BB_synth_control; /* 0x140 - 0x144 */
1102 volatile u_int32_t BB_addac_clk_select; /* 0x144 - 0x148 */
1103 volatile u_int32_t BB_pll_cntl; /* 0x148 - 0x14c */
1104 volatile u_int32_t BB_analog_swap; /* 0x14c - 0x150 */
1105 volatile u_int32_t BB_addac_parallel_control; /* 0x150 - 0x154 */
1106 volatile char pad__6[0x4]; /* 0x154 - 0x158 */
1107 volatile u_int32_t BB_force_analog; /* 0x158 - 0x15c */
1108 volatile char pad__7[0x4]; /* 0x15c - 0x160 */
1109 volatile u_int32_t BB_test_controls; /* 0x160 - 0x164 */
1110 volatile u_int32_t BB_test_controls_status; /* 0x164 - 0x168 */
1111 volatile u_int32_t BB_tstdac; /* 0x168 - 0x16c */
1112 volatile u_int32_t BB_channel_status; /* 0x16c - 0x170 */
1113 volatile u_int32_t BB_chaninfo_ctrl; /* 0x170 - 0x174 */
1114 volatile u_int32_t BB_chan_info_noise_pwr; /* 0x174 - 0x178 */
1115 volatile u_int32_t BB_chan_info_gain_diff; /* 0x178 - 0x17c */
1116 volatile u_int32_t BB_chan_info_fine_timing; /* 0x17c - 0x180 */
1117 volatile u_int32_t BB_chan_info_gain_b0; /* 0x180 - 0x184 */
1118 volatile char pad__8[0xc]; /* 0x184 - 0x190 */
1119 volatile u_int32_t BB_scrambler_seed; /* 0x190 - 0x194 */
1120 volatile u_int32_t BB_bbb_tx_ctrl; /* 0x194 - 0x198 */
1121 volatile u_int32_t BB_bbb_txfir_0; /* 0x198 - 0x19c */
1122 volatile u_int32_t BB_bbb_txfir_1; /* 0x19c - 0x1a0 */
1123 volatile u_int32_t BB_bbb_txfir_2; /* 0x1a0 - 0x1a4 */
1124 volatile u_int32_t BB_heavy_clip_ctrl; /* 0x1a4 - 0x1a8 */
1125 volatile u_int32_t BB_heavy_clip_20; /* 0x1a8 - 0x1ac */
1126 volatile u_int32_t BB_heavy_clip_40; /* 0x1ac - 0x1b0 */
1127 volatile u_int32_t BB_illegal_tx_rate; /* 0x1b0 - 0x1b4 */
1128 volatile char pad__9[0xc]; /* 0x1b4 - 0x1c0 */
1129 volatile u_int32_t BB_powertx_rate1; /* 0x1c0 - 0x1c4 */
1130 volatile u_int32_t BB_powertx_rate2; /* 0x1c4 - 0x1c8 */
1131 volatile u_int32_t BB_powertx_rate3; /* 0x1c8 - 0x1cc */
1132 volatile u_int32_t BB_powertx_rate4; /* 0x1cc - 0x1d0 */
1133 volatile u_int32_t BB_powertx_rate5; /* 0x1d0 - 0x1d4 */
1134 volatile u_int32_t BB_powertx_rate6; /* 0x1d4 - 0x1d8 */
1135 volatile u_int32_t BB_powertx_rate7; /* 0x1d8 - 0x1dc */
1136 volatile u_int32_t BB_powertx_rate8; /* 0x1dc - 0x1e0 */
1137 volatile u_int32_t BB_powertx_rate9; /* 0x1e0 - 0x1e4 */
1138 volatile u_int32_t BB_powertx_rate10; /* 0x1e4 - 0x1e8 */
1139 volatile u_int32_t BB_powertx_rate11; /* 0x1e8 - 0x1ec */
1140 volatile u_int32_t BB_powertx_rate12; /* 0x1ec - 0x1f0 */
1141 volatile u_int32_t BB_powertx_max; /* 0x1f0 - 0x1f4 */
1142 volatile u_int32_t BB_powertx_sub; /* 0x1f4 - 0x1f8 */
1143 volatile u_int32_t BB_tpc_1; /* 0x1f8 - 0x1fc */
1144 volatile u_int32_t BB_tpc_2; /* 0x1fc - 0x200 */
1145 volatile u_int32_t BB_tpc_3; /* 0x200 - 0x204 */
1146 volatile u_int32_t BB_tpc_4_b0; /* 0x204 - 0x208 */
1147 volatile u_int32_t BB_tpc_5_b0; /* 0x208 - 0x20c */
1148 volatile u_int32_t BB_tpc_6_b0; /* 0x20c - 0x210 */
1149 volatile u_int32_t BB_tpc_7; /* 0x210 - 0x214 */
1150 volatile u_int32_t BB_tpc_8; /* 0x214 - 0x218 */
1151 volatile u_int32_t BB_tpc_9; /* 0x218 - 0x21c */
1152 volatile u_int32_t BB_tpc_10; /* 0x21c - 0x220 */
1153 volatile u_int32_t BB_tpc_11_b0; /* 0x220 - 0x224 */
1154 volatile u_int32_t BB_tpc_12; /* 0x224 - 0x228 */
1155 volatile u_int32_t BB_tpc_13; /* 0x228 - 0x22c */
1156 volatile u_int32_t BB_tpc_14; /* 0x22c - 0x230 */
1157 volatile u_int32_t BB_tpc_15; /* 0x230 - 0x234 */
1158 volatile u_int32_t BB_tpc_16; /* 0x234 - 0x238 */
1159 volatile u_int32_t BB_tpc_17; /* 0x238 - 0x23c */
1160 volatile u_int32_t BB_tpc_18; /* 0x23c - 0x240 */
1161 volatile u_int32_t BB_tpc_19; /* 0x240 - 0x244 */
1162 volatile u_int32_t BB_tpc_20; /* 0x244 - 0x248 */
1163 volatile u_int32_t BB_therm_adc_1; /* 0x248 - 0x24c */
1164 volatile u_int32_t BB_therm_adc_2; /* 0x24c - 0x250 */
1165 volatile u_int32_t BB_therm_adc_3; /* 0x250 - 0x254 */
1166 volatile u_int32_t BB_therm_adc_4; /* 0x254 - 0x258 */
1167 volatile u_int32_t BB_tx_forced_gain; /* 0x258 - 0x25c */
1168 volatile char pad__10[0x24]; /* 0x25c - 0x280 */
1169 volatile u_int32_t BB_pdadc_tab_b0[32]; /* 0x280 - 0x300 */
1170 volatile u_int32_t BB_tx_gain_tab_1; /* 0x300 - 0x304 */
1171 volatile u_int32_t BB_tx_gain_tab_2; /* 0x304 - 0x308 */
1172 volatile u_int32_t BB_tx_gain_tab_3; /* 0x308 - 0x30c */
1173 volatile u_int32_t BB_tx_gain_tab_4; /* 0x30c - 0x310 */
1174 volatile u_int32_t BB_tx_gain_tab_5; /* 0x310 - 0x314 */
1175 volatile u_int32_t BB_tx_gain_tab_6; /* 0x314 - 0x318 */
1176 volatile u_int32_t BB_tx_gain_tab_7; /* 0x318 - 0x31c */
1177 volatile u_int32_t BB_tx_gain_tab_8; /* 0x31c - 0x320 */
1178 volatile u_int32_t BB_tx_gain_tab_9; /* 0x320 - 0x324 */
1179 volatile u_int32_t BB_tx_gain_tab_10; /* 0x324 - 0x328 */
1180 volatile u_int32_t BB_tx_gain_tab_11; /* 0x328 - 0x32c */
1181 volatile u_int32_t BB_tx_gain_tab_12; /* 0x32c - 0x330 */
1182 volatile u_int32_t BB_tx_gain_tab_13; /* 0x330 - 0x334 */
1183 volatile u_int32_t BB_tx_gain_tab_14; /* 0x334 - 0x338 */
1184 volatile u_int32_t BB_tx_gain_tab_15; /* 0x338 - 0x33c */
1185 volatile u_int32_t BB_tx_gain_tab_16; /* 0x33c - 0x340 */
1186 volatile u_int32_t BB_tx_gain_tab_17; /* 0x340 - 0x344 */
1187 volatile u_int32_t BB_tx_gain_tab_18; /* 0x344 - 0x348 */
1188 volatile u_int32_t BB_tx_gain_tab_19; /* 0x348 - 0x34c */
1189 volatile u_int32_t BB_tx_gain_tab_20; /* 0x34c - 0x350 */
1190 volatile u_int32_t BB_tx_gain_tab_21; /* 0x350 - 0x354 */
1191 volatile u_int32_t BB_tx_gain_tab_22; /* 0x354 - 0x358 */
1192 volatile u_int32_t BB_tx_gain_tab_23; /* 0x358 - 0x35c */
1193 volatile u_int32_t BB_tx_gain_tab_24; /* 0x35c - 0x360 */
1194 volatile u_int32_t BB_tx_gain_tab_25; /* 0x360 - 0x364 */
1195 volatile u_int32_t BB_tx_gain_tab_26; /* 0x364 - 0x368 */
1196 volatile u_int32_t BB_tx_gain_tab_27; /* 0x368 - 0x36c */
1197 volatile u_int32_t BB_tx_gain_tab_28; /* 0x36c - 0x370 */
1198 volatile u_int32_t BB_tx_gain_tab_29; /* 0x370 - 0x374 */
1199 volatile u_int32_t BB_tx_gain_tab_30; /* 0x374 - 0x378 */
1200 volatile u_int32_t BB_tx_gain_tab_31; /* 0x378 - 0x37c */
1201 volatile u_int32_t BB_tx_gain_tab_32; /* 0x37c - 0x380 */
1204 volatile u_int32_t BB_tx_gain_tab_pal_1; /* 0x380 - 0x384 */
1205 volatile u_int32_t BB_tx_gain_tab_pal_2; /* 0x384 - 0x388 */
1206 volatile u_int32_t BB_tx_gain_tab_pal_3; /* 0x388 - 0x38c */
1207 volatile u_int32_t BB_tx_gain_tab_pal_4; /* 0x38c - 0x390 */
1208 volatile u_int32_t BB_tx_gain_tab_pal_5; /* 0x390 - 0x394 */
1209 volatile u_int32_t BB_tx_gain_tab_pal_6; /* 0x394 - 0x398 */
1210 volatile u_int32_t BB_tx_gain_tab_pal_7; /* 0x398 - 0x39c */
1211 volatile u_int32_t BB_tx_gain_tab_pal_8; /* 0x39c - 0x3a0 */
1212 volatile u_int32_t BB_tx_gain_tab_pal_9; /* 0x3a0 - 0x3a4 */
1213 volatile u_int32_t BB_tx_gain_tab_pal_10; /* 0x3a4 - 0x3a8 */
1214 volatile u_int32_t BB_tx_gain_tab_pal_11; /* 0x3a8 - 0x3ac */
1215 volatile u_int32_t BB_tx_gain_tab_pal_12; /* 0x3ac - 0x3b0 */
1216 volatile u_int32_t BB_tx_gain_tab_pal_13; /* 0x3b0 - 0x3b4 */
1217 volatile u_int32_t BB_tx_gain_tab_pal_14; /* 0x3b4 - 0x3b8 */
1218 volatile u_int32_t BB_tx_gain_tab_pal_15; /* 0x3b8 - 0x3bc */
1219 volatile u_int32_t BB_tx_gain_tab_pal_16; /* 0x3bc - 0x3c0 */
1220 volatile u_int32_t BB_tx_gain_tab_pal_17; /* 0x3c0 - 0x3c4 */
1221 volatile u_int32_t BB_tx_gain_tab_pal_18; /* 0x3c4 - 0x3c8 */
1222 volatile u_int32_t BB_tx_gain_tab_pal_19; /* 0x3c8 - 0x3cc */
1223 volatile u_int32_t BB_tx_gain_tab_pal_20; /* 0x3cc - 0x3d0 */
1224 volatile u_int32_t BB_tx_gain_tab_pal_21; /* 0x3d0 - 0x3d4 */
1225 volatile u_int32_t BB_tx_gain_tab_pal_22; /* 0x3d4 - 0x3d8 */
1226 volatile u_int32_t BB_tx_gain_tab_pal_23; /* 0x3d8 - 0x3dc */
1227 volatile u_int32_t BB_tx_gain_tab_pal_24; /* 0x3dc - 0x3e0 */
1228 volatile u_int32_t BB_tx_gain_tab_pal_25; /* 0x3e0 - 0x3e4 */
1229 volatile u_int32_t BB_tx_gain_tab_pal_26; /* 0x3e4 - 0x3e8 */
1230 volatile u_int32_t BB_tx_gain_tab_pal_27; /* 0x3e8 - 0x3ec */
1231 volatile u_int32_t BB_tx_gain_tab_pal_28; /* 0x3ec - 0x3f0 */
1232 volatile u_int32_t BB_tx_gain_tab_pal_29; /* 0x3f0 - 0x3f4 */
1233 volatile u_int32_t BB_tx_gain_tab_pal_30; /* 0x3f4 - 0x3f8 */
1234 volatile u_int32_t BB_tx_gain_tab_pal_31; /* 0x3f8 - 0x3fc */
1235 volatile u_int32_t BB_tx_gain_tab_pal_32; /* 0x3fc - 0x400 */
1236 volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */
1237 volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */
1238 volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */
1239 volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */
1240 volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */
1241 volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */
1242 volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */
1243 volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */
1244 volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */
1245 volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */
1246 volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */
1247 volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */
1248 volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */
1249 volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */
1250 volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */
1251 volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */
1252 volatile u_int32_t BB_txiqcal_start; /* 0x440 - 0x444 */
1253 volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */
1254 volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */
1255 volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */
1256 volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */
1257 volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */
1258 volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */
1259 volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */
1260 volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */
1261 volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */
1262 volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */
1263 volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */
1264 volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */
1265 volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */
1266 volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */
1267 volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */
1268 volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */
1269 volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */
1270 volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */
1271 volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */
1272 volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */
1273 volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */
1274 volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */
1275 volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */
1276 volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */
1277 volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */
1278 volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */
1279 volatile char pad__11[0x114]; /* 0x4ac - 0x5c0 */
1282 volatile u_int32_t BB_caltx_gain_set_0; /* 0x380 - 0x384 */
1283 volatile u_int32_t BB_caltx_gain_set_2; /* 0x384 - 0x388 */
1284 volatile u_int32_t BB_caltx_gain_set_4; /* 0x388 - 0x38c */
1285 volatile u_int32_t BB_caltx_gain_set_6; /* 0x38c - 0x390 */
1286 volatile u_int32_t BB_caltx_gain_set_8; /* 0x390 - 0x394 */
1287 volatile u_int32_t BB_caltx_gain_set_10; /* 0x394 - 0x398 */
1288 volatile u_int32_t BB_caltx_gain_set_12; /* 0x398 - 0x39c */
1289 volatile u_int32_t BB_caltx_gain_set_14; /* 0x39c - 0x3a0 */
1290 volatile u_int32_t BB_caltx_gain_set_16; /* 0x3a0 - 0x3a4 */
1291 volatile u_int32_t BB_caltx_gain_set_18; /* 0x3a4 - 0x3a8 */
1292 volatile u_int32_t BB_caltx_gain_set_20; /* 0x3a8 - 0x3ac */
1293 volatile u_int32_t BB_caltx_gain_set_22; /* 0x3ac - 0x3b0 */
1294 volatile u_int32_t BB_caltx_gain_set_24; /* 0x3b0 - 0x3b4 */
1295 volatile u_int32_t BB_caltx_gain_set_26; /* 0x3b4 - 0x3b8 */
1296 volatile u_int32_t BB_caltx_gain_set_28; /* 0x3b8 - 0x3bc */
1297 volatile u_int32_t BB_caltx_gain_set_30; /* 0x3bc - 0x3c0 */
1298 volatile char pad__11[0x4]; /* 0x3c0 - 0x3c4 */
1299 volatile u_int32_t BB_txiqcal_control_0; /* 0x3c4 - 0x3c8 */
1300 volatile u_int32_t BB_txiqcal_control_1; /* 0x3c8 - 0x3cc */
1301 volatile u_int32_t BB_txiqcal_control_2; /* 0x3cc - 0x3d0 */
1302 volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x3d0 - 0x3d4 */
1303 volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x3d4 - 0x3d8 */
1304 volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x3d8 - 0x3dc */
1305 volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x3dc - 0x3e0 */
1306 volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x3e0 - 0x3e4 */
1307 volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x3e4 - 0x3e8 */
1308 volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x3e8 - 0x3ec */
1309 volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x3ec - 0x3f0 */
1310 volatile u_int32_t BB_txiqcal_status_b0; /* 0x3f0 - 0x3f4 */
1311 volatile char pad__12[0x16c]; /* 0x3f4 - 0x560 */
1312 volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x560 - 0x564 */
1313 volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x564 - 0x568 */
1314 volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x568 - 0x56c */
1315 volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x56c - 0x570 */
1316 volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x570 - 0x574 */
1317 volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x574 - 0x578 */
1318 volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x578 - 0x57c */
1319 volatile char pad__13[0x4]; /* 0x57c - 0x580 */
1320 volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x580 - 0x584 */
1321 volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x584 - 0x588 */
1322 volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x588 - 0x58c */
1323 volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x58c - 0x590 */
1324 volatile u_int32_t BB_paprd_trainer_stat1; /* 0x590 - 0x594 */
1325 volatile u_int32_t BB_paprd_trainer_stat2; /* 0x594 - 0x598 */
1326 volatile u_int32_t BB_paprd_trainer_stat3; /* 0x598 - 0x59c */
1327 volatile char pad__14[0x24]; /* 0x59c - 0x5c0 */
1330 volatile char pad__11[0x80]; /* 0x380 - 0x400 */
1331 /* 0x400 - 0x4b0 same as Osprey - start */
1332 volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */
1333 volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */
1334 volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */
1335 volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */
1336 volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */
1337 volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */
1338 volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */
1339 volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */
1340 volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */
1341 volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */
1342 volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */
1343 volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */
1344 volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */
1345 volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */
1346 volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */
1347 volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */
1348 volatile char pad__12[0x4]; /* 0x440 - 0x444 */
1349 volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */
1350 volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */
1351 volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */
1352 volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */
1353 volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */
1354 volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */
1355 volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */
1356 volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */
1357 volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */
1358 volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */
1359 volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */
1360 volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */
1361 volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */
1362 volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */
1363 volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */
1364 volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */
1365 volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */
1366 volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */
1367 volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */
1368 volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */
1369 volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */
1370 volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */
1371 volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */
1372 volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */
1373 volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */
1374 volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */
1375 volatile char pad__13[0x4]; /* 0x4ac - 0x4b0 */
1376 /* 0x400 - 0x4b0 same as Osprey - end */
1377 volatile u_int32_t BB_aic_ctrl_0_b0; /* 0x4b0 - 0x4b4 */
1378 volatile u_int32_t BB_aic_ctrl_1_b0; /* 0x4b4 - 0x4b8 */
1379 volatile u_int32_t BB_aic_ctrl_2_b0; /* 0x4b8 - 0x4bc */
1380 volatile u_int32_t BB_aic_ctrl_3_b0; /* 0x4bc - 0x4c0 */
1381 volatile u_int32_t BB_aic_stat_0_b0; /* 0x4c0 - 0x4c4 */
1382 volatile u_int32_t BB_aic_stat_1_b0; /* 0x4c4 - 0x4c8 */
1383 volatile char pad__14[0xf8]; /* 0x4c8 - 0x5c0 */
1386 volatile u_int32_t BB_rtt_ctrl; /* 0x380 - 0x384 */
1387 volatile u_int32_t BB_rtt_table_sw_intf_b0; /* 0x384 - 0x388 */
1388 volatile u_int32_t BB_rtt_table_sw_intf_1_b0; /* 0x388 - 0x38c */
1389 volatile char pad__11[0x74]; /* 0x38c - 0x400 */
1390 /* 0x400 - 0x4b0 same as Osprey - start */
1391 volatile u_int32_t BB_caltx_gain_set_0; /* 0x400 - 0x404 */
1392 volatile u_int32_t BB_caltx_gain_set_2; /* 0x404 - 0x408 */
1393 volatile u_int32_t BB_caltx_gain_set_4; /* 0x408 - 0x40c */
1394 volatile u_int32_t BB_caltx_gain_set_6; /* 0x40c - 0x410 */
1395 volatile u_int32_t BB_caltx_gain_set_8; /* 0x410 - 0x414 */
1396 volatile u_int32_t BB_caltx_gain_set_10; /* 0x414 - 0x418 */
1397 volatile u_int32_t BB_caltx_gain_set_12; /* 0x418 - 0x41c */
1398 volatile u_int32_t BB_caltx_gain_set_14; /* 0x41c - 0x420 */
1399 volatile u_int32_t BB_caltx_gain_set_16; /* 0x420 - 0x424 */
1400 volatile u_int32_t BB_caltx_gain_set_18; /* 0x424 - 0x428 */
1401 volatile u_int32_t BB_caltx_gain_set_20; /* 0x428 - 0x42c */
1402 volatile u_int32_t BB_caltx_gain_set_22; /* 0x42c - 0x430 */
1403 volatile u_int32_t BB_caltx_gain_set_24; /* 0x430 - 0x434 */
1404 volatile u_int32_t BB_caltx_gain_set_26; /* 0x434 - 0x438 */
1405 volatile u_int32_t BB_caltx_gain_set_28; /* 0x438 - 0x43c */
1406 volatile u_int32_t BB_caltx_gain_set_30; /* 0x43c - 0x440 */
1407 volatile char pad__12[0x4]; /* 0x440 - 0x444 */
1408 volatile u_int32_t BB_txiqcal_control_0; /* 0x444 - 0x448 */
1409 volatile u_int32_t BB_txiqcal_control_1; /* 0x448 - 0x44c */
1410 volatile u_int32_t BB_txiqcal_control_2; /* 0x44c - 0x450 */
1411 volatile u_int32_t BB_txiq_corr_coeff_01_b0; /* 0x450 - 0x454 */
1412 volatile u_int32_t BB_txiq_corr_coeff_23_b0; /* 0x454 - 0x458 */
1413 volatile u_int32_t BB_txiq_corr_coeff_45_b0; /* 0x458 - 0x45c */
1414 volatile u_int32_t BB_txiq_corr_coeff_67_b0; /* 0x45c - 0x460 */
1415 volatile u_int32_t BB_txiq_corr_coeff_89_b0; /* 0x460 - 0x464 */
1416 volatile u_int32_t BB_txiq_corr_coeff_ab_b0; /* 0x464 - 0x468 */
1417 volatile u_int32_t BB_txiq_corr_coeff_cd_b0; /* 0x468 - 0x46c */
1418 volatile u_int32_t BB_txiq_corr_coeff_ef_b0; /* 0x46c - 0x470 */
1419 volatile u_int32_t BB_cal_rxbb_gain_tbl_0; /* 0x470 - 0x474 */
1420 volatile u_int32_t BB_cal_rxbb_gain_tbl_4; /* 0x474 - 0x478 */
1421 volatile u_int32_t BB_cal_rxbb_gain_tbl_8; /* 0x478 - 0x47c */
1422 volatile u_int32_t BB_cal_rxbb_gain_tbl_12; /* 0x47c - 0x480 */
1423 volatile u_int32_t BB_cal_rxbb_gain_tbl_16; /* 0x480 - 0x484 */
1424 volatile u_int32_t BB_cal_rxbb_gain_tbl_20; /* 0x484 - 0x488 */
1425 volatile u_int32_t BB_cal_rxbb_gain_tbl_24; /* 0x488 - 0x48c */
1426 volatile u_int32_t BB_txiqcal_status_b0; /* 0x48c - 0x490 */
1427 volatile u_int32_t BB_paprd_trainer_cntl1; /* 0x490 - 0x494 */
1428 volatile u_int32_t BB_paprd_trainer_cntl2; /* 0x494 - 0x498 */
1429 volatile u_int32_t BB_paprd_trainer_cntl3; /* 0x498 - 0x49c */
1430 volatile u_int32_t BB_paprd_trainer_cntl4; /* 0x49c - 0x4a0 */
1431 volatile u_int32_t BB_paprd_trainer_stat1; /* 0x4a0 - 0x4a4 */
1432 volatile u_int32_t BB_paprd_trainer_stat2; /* 0x4a4 - 0x4a8 */
1433 volatile u_int32_t BB_paprd_trainer_stat3; /* 0x4a8 - 0x4ac */
1434 volatile char pad__13[0x4]; /* 0x4ac - 0x4b0 */
1435 /* 0x400 - 0x4b0 same as Osprey - end */
1436 volatile u_int32_t BB_aic_ctrl_0_b0; /* 0x4b0 - 0x4b4 */
1437 volatile u_int32_t BB_aic_ctrl_1_b0; /* 0x4b4 - 0x4b8 */
1438 volatile u_int32_t BB_aic_ctrl_2_b0; /* 0x4b8 - 0x4bc */
1439 volatile u_int32_t BB_aic_ctrl_3_b0; /* 0x4bc - 0x4c0 */
1440 volatile u_int32_t BB_aic_ctrl_4_b0; /* 0x4c0 - 0x4c4 */
1441 volatile u_int32_t BB_aic_stat_0_b0; /* 0x4c4 - 0x4c8 */
1442 volatile u_int32_t BB_aic_stat_1_b0; /* 0x4c8 - 0x4cc */
1443 volatile u_int32_t BB_aic_stat_2_b0; /* 0x4cc - 0x4d0 */
1444 volatile char pad__14[0xf0]; /* 0x4d0 - 0x5c0 */
1447 volatile u_int32_t BB_panic_watchdog_status; /* 0x5c0 - 0x5c4 */
1448 volatile u_int32_t BB_panic_watchdog_ctrl_1; /* 0x5c4 - 0x5c8 */
1449 volatile u_int32_t BB_panic_watchdog_ctrl_2; /* 0x5c8 - 0x5cc */
1450 volatile u_int32_t BB_bluetooth_cntl; /* 0x5cc - 0x5d0 */
1451 volatile u_int32_t BB_phyonly_warm_reset; /* 0x5d0 - 0x5d4 */
1452 volatile u_int32_t BB_phyonly_control; /* 0x5d4 - 0x5d8 */
1453 volatile char pad__12[0x4]; /* 0x5d8 - 0x5dc */
1454 volatile u_int32_t BB_eco_ctrl; /* 0x5dc - 0x5e0 */
1455 volatile char pad__13[0x10]; /* 0x5e0 - 0x5f0 */
1457 volatile u_int32_t BB_tables_intf_addr_b0; /* 0x5f0 - 0x5f4 */
1459 volatile u_int32_t BB_tables_intf_data_b0; /* 0x5f4 - 0x5f8 */
1462 struct chn1_reg_map {
1463 volatile u_int32_t BB_dummy_DONOTACCESS1; /* 0x0 - 0x4 */
1464 volatile char pad__0[0x2c]; /* 0x4 - 0x30 */
1465 volatile u_int32_t BB_ext_chan_pwr_thr_2_b1; /* 0x30 - 0x34 */
1466 volatile char pad__1[0x74]; /* 0x34 - 0xa8 */
1467 volatile u_int32_t BB_spur_report_b1; /* 0xa8 - 0xac */
1468 volatile char pad__2[0x14]; /* 0xac - 0xc0 */
1469 volatile u_int32_t BB_iq_adc_meas_0_b1; /* 0xc0 - 0xc4 */
1470 volatile u_int32_t BB_iq_adc_meas_1_b1; /* 0xc4 - 0xc8 */
1471 volatile u_int32_t BB_iq_adc_meas_2_b1; /* 0xc8 - 0xcc */
1472 volatile u_int32_t BB_iq_adc_meas_3_b1; /* 0xcc - 0xd0 */
1473 volatile u_int32_t BB_tx_phase_ramp_b1; /* 0xd0 - 0xd4 */
1474 volatile u_int32_t BB_adc_gain_dc_corr_b1; /* 0xd4 - 0xd8 */
1475 volatile char pad__3[0x4]; /* 0xd8 - 0xdc */
1476 volatile u_int32_t BB_rx_iq_corr_b1; /* 0xdc - 0xe0 */
1477 volatile char pad__4[0x10]; /* 0xe0 - 0xf0 */
1478 volatile u_int32_t BB_paprd_ctrl0_b1; /* 0xf0 - 0xf4 */
1479 volatile u_int32_t BB_paprd_ctrl1_b1; /* 0xf4 - 0xf8 */
1480 volatile u_int32_t BB_pa_gain123_b1; /* 0xf8 - 0xfc */
1481 volatile u_int32_t BB_pa_gain45_b1; /* 0xfc - 0x100 */
1482 volatile u_int32_t BB_paprd_pre_post_scale_0_b1;
1484 volatile u_int32_t BB_paprd_pre_post_scale_1_b1;
1486 volatile u_int32_t BB_paprd_pre_post_scale_2_b1;
1488 volatile u_int32_t BB_paprd_pre_post_scale_3_b1;
1490 volatile u_int32_t BB_paprd_pre_post_scale_4_b1;
1492 volatile u_int32_t BB_paprd_pre_post_scale_5_b1;
1494 volatile u_int32_t BB_paprd_pre_post_scale_6_b1;
1496 volatile u_int32_t BB_paprd_pre_post_scale_7_b1;
1498 volatile u_int32_t BB_paprd_mem_tab_b1[120]; /* 0x120 - 0x300 */
1499 volatile u_int32_t BB_chan_info_chan_tab_b1[60];
1502 volatile u_int32_t BB_chn1_tables_intf_addr; /* 0x3f0 - 0x3f4 */
1504 volatile u_int32_t BB_chn1_tables_intf_data; /* 0x3f4 - 0x3f8 */
1507 struct chn_ext_reg_map {
1508 volatile u_int32_t BB_paprd_pre_post_scale_0_1_b0;
1510 volatile u_int32_t BB_paprd_pre_post_scale_1_1_b0;
1512 volatile u_int32_t BB_paprd_pre_post_scale_2_1_b0;
1514 volatile u_int32_t BB_paprd_pre_post_scale_3_1_b0;
1516 volatile u_int32_t BB_paprd_pre_post_scale_4_1_b0;
1518 volatile u_int32_t BB_paprd_pre_post_scale_5_1_b0;
1520 volatile u_int32_t BB_paprd_pre_post_scale_6_1_b0;
1522 volatile u_int32_t BB_paprd_pre_post_scale_7_1_b0;
1524 volatile u_int32_t BB_paprd_pre_post_scale_0_2_b0;
1526 volatile u_int32_t BB_paprd_pre_post_scale_1_2_b0;
1528 volatile u_int32_t BB_paprd_pre_post_scale_2_2_b0;
1530 volatile u_int32_t BB_paprd_pre_post_scale_3_2_b0;
1532 volatile u_int32_t BB_paprd_pre_post_scale_4_2_b0;
1534 volatile u_int32_t BB_paprd_pre_post_scale_5_2_b0;
1536 volatile u_int32_t BB_paprd_pre_post_scale_6_2_b0;
1538 volatile u_int32_t BB_paprd_pre_post_scale_7_2_b0;
1540 volatile u_int32_t BB_paprd_pre_post_scale_0_3_b0;
1542 volatile u_int32_t BB_paprd_pre_post_scale_1_3_b0;
1544 volatile u_int32_t BB_paprd_pre_post_scale_2_3_b0;
1546 volatile u_int32_t BB_paprd_pre_post_scale_3_3_b0;
1548 volatile u_int32_t BB_paprd_pre_post_scale_4_3_b0;
1550 volatile u_int32_t BB_paprd_pre_post_scale_5_3_b0;
1552 volatile u_int32_t BB_paprd_pre_post_scale_6_3_b0;
1554 volatile u_int32_t BB_paprd_pre_post_scale_7_3_b0;
1556 volatile u_int32_t BB_paprd_pre_post_scale_0_4_b0;
1558 volatile u_int32_t BB_paprd_pre_post_scale_1_4_b0;
1560 volatile u_int32_t BB_paprd_pre_post_scale_2_4_b0;
1562 volatile u_int32_t BB_paprd_pre_post_scale_3_4_b0;
1564 volatile u_int32_t BB_paprd_pre_post_scale_4_4_b0;
1566 volatile u_int32_t BB_paprd_pre_post_scale_5_4_b0;
1568 volatile u_int32_t BB_paprd_pre_post_scale_6_4_b0;
1570 volatile u_int32_t BB_paprd_pre_post_scale_7_4_b0;
1572 volatile u_int32_t BB_paprd_power_at_am2am_cal_b0;
1574 volatile u_int32_t BB_paprd_valid_obdb_b0; /* 0x84 - 0x88 */
1575 volatile char pad__0[0x374]; /* 0x88 - 0x3fc */
1576 volatile u_int32_t BB_chn_ext_dummy_2; /* 0x3fc - 0x400 */
1579 struct sm_ext_reg_map {
1580 volatile u_int32_t BB_sm_ext_dummy1; /* 0x0 - 0x4 */
1581 volatile char pad__0[0x2fc]; /* 0x4 - 0x300 */
1582 volatile u_int32_t BB_green_tx_gain_tab_1; /* 0x300 - 0x304 */
1583 volatile u_int32_t BB_green_tx_gain_tab_2; /* 0x304 - 0x308 */
1584 volatile u_int32_t BB_green_tx_gain_tab_3; /* 0x308 - 0x30c */
1585 volatile u_int32_t BB_green_tx_gain_tab_4; /* 0x30c - 0x310 */
1586 volatile u_int32_t BB_green_tx_gain_tab_5; /* 0x310 - 0x314 */
1587 volatile u_int32_t BB_green_tx_gain_tab_6; /* 0x314 - 0x318 */
1588 volatile u_int32_t BB_green_tx_gain_tab_7; /* 0x318 - 0x31c */
1589 volatile u_int32_t BB_green_tx_gain_tab_8; /* 0x31c - 0x320 */
1590 volatile u_int32_t BB_green_tx_gain_tab_9; /* 0x320 - 0x324 */
1591 volatile u_int32_t BB_green_tx_gain_tab_10; /* 0x324 - 0x328 */
1592 volatile u_int32_t BB_green_tx_gain_tab_11; /* 0x328 - 0x32c */
1593 volatile u_int32_t BB_green_tx_gain_tab_12; /* 0x32c - 0x330 */
1594 volatile u_int32_t BB_green_tx_gain_tab_13; /* 0x330 - 0x334 */
1595 volatile u_int32_t BB_green_tx_gain_tab_14; /* 0x334 - 0x338 */
1596 volatile u_int32_t BB_green_tx_gain_tab_15; /* 0x338 - 0x33c */
1597 volatile u_int32_t BB_green_tx_gain_tab_16; /* 0x33c - 0x340 */
1598 volatile u_int32_t BB_green_tx_gain_tab_17; /* 0x340 - 0x344 */
1599 volatile u_int32_t BB_green_tx_gain_tab_18; /* 0x344 - 0x348 */
1600 volatile u_int32_t BB_green_tx_gain_tab_19; /* 0x348 - 0x34c */
1601 volatile u_int32_t BB_green_tx_gain_tab_20; /* 0x34c - 0x350 */
1602 volatile u_int32_t BB_green_tx_gain_tab_21; /* 0x350 - 0x354 */
1603 volatile u_int32_t BB_green_tx_gain_tab_22; /* 0x354 - 0x358 */
1604 volatile u_int32_t BB_green_tx_gain_tab_23; /* 0x358 - 0x35c */
1605 volatile u_int32_t BB_green_tx_gain_tab_24; /* 0x35c - 0x360 */
1606 volatile u_int32_t BB_green_tx_gain_tab_25; /* 0x360 - 0x364 */
1607 volatile u_int32_t BB_green_tx_gain_tab_26; /* 0x364 - 0x368 */
1608 volatile u_int32_t BB_green_tx_gain_tab_27; /* 0x368 - 0x36c */
1609 volatile u_int32_t BB_green_tx_gain_tab_28; /* 0x36c - 0x370 */
1610 volatile u_int32_t BB_green_tx_gain_tab_29; /* 0x370 - 0x374 */
1611 volatile u_int32_t BB_green_tx_gain_tab_30; /* 0x374 - 0x378 */
1612 volatile u_int32_t BB_green_tx_gain_tab_31; /* 0x378 - 0x37c */
1613 volatile u_int32_t BB_green_tx_gain_tab_32; /* 0x37c - 0x380 */
1614 volatile char pad__1[0x27c]; /* 0x380 - 0x5fc */
1615 volatile u_int32_t BB_sm_ext_dummy2; /* 0x5fc - 0x600 */
1618 struct agc1_reg_map {
1619 volatile u_int32_t BB_dummy_DONOTACCESS3; /* 0x0 - 0x4 */
1620 volatile u_int32_t BB_gain_force_max_gains_b1; /* 0x4 - 0x8 */
1621 volatile char pad__0[0x10]; /* 0x8 - 0x18 */
1622 volatile u_int32_t BB_ext_atten_switch_ctl_b1; /* 0x18 - 0x1c */
1624 volatile u_int32_t BB_cca_b1; /* 0x1c - 0x20 */
1626 volatile u_int32_t BB_cca_ctrl_2_b1; /* 0x20 - 0x24 */
1627 volatile char pad__1[0x15c]; /* 0x24 - 0x180 */
1628 volatile u_int32_t BB_rssi_b1; /* 0x180 - 0x184 */
1630 volatile u_int32_t BB_spur_est_cck_report_b1; /* 0x184 - 0x188 */
1632 volatile u_int32_t BB_agc_dig_dc_status_i_b1; /* 0x188 - 0x18c */
1634 volatile u_int32_t BB_agc_dig_dc_status_q_b1; /* 0x18c - 0x190 */
1636 volatile u_int32_t BB_dc_cal_status_b1; /* 0x190 - 0x194 */
1637 volatile char pad__2[0x6c]; /* 0x194 - 0x200 */
1638 volatile u_int32_t BB_rx_ocgain2[128]; /* 0x200 - 0x400 */
1641 struct sm1_reg_map {
1642 volatile u_int32_t BB_dummy_DONOTACCESS5; /* 0x0 - 0x4 */
1643 volatile char pad__0[0x80]; /* 0x4 - 0x84 */
1644 volatile u_int32_t BB_switch_table_chn_b1; /* 0x84 - 0x88 */
1645 volatile char pad__1[0x48]; /* 0x88 - 0xd0 */
1646 volatile u_int32_t BB_fcal_2_b1; /* 0xd0 - 0xd4 */
1647 volatile u_int32_t BB_dft_tone_ctrl_b1; /* 0xd4 - 0xd8 */
1648 volatile char pad__2[0x4]; /* 0xd8 - 0xdc */
1649 volatile u_int32_t BB_cl_map_0_b1; /* 0xdc - 0xe0 */
1650 volatile u_int32_t BB_cl_map_1_b1; /* 0xe0 - 0xe4 */
1651 volatile u_int32_t BB_cl_map_2_b1; /* 0xe4 - 0xe8 */
1652 volatile u_int32_t BB_cl_map_3_b1; /* 0xe8 - 0xec */
1653 volatile u_int32_t BB_cl_map_pal_0_b1; /* 0xec - 0xf0 */
1654 volatile u_int32_t BB_cl_map_pal_1_b1; /* 0xf0 - 0xf4 */
1655 volatile u_int32_t BB_cl_map_pal_2_b1; /* 0xf4 - 0xf8 */
1656 volatile u_int32_t BB_cl_map_pal_3_b1; /* 0xf8 - 0xfc */
1657 volatile char pad__3[0x4]; /* 0xfc - 0x100 */
1658 volatile u_int32_t BB_cl_tab_b1[16]; /* 0x100 - 0x140 */
1659 volatile char pad__4[0x40]; /* 0x140 - 0x180 */
1660 volatile u_int32_t BB_chan_info_gain_b1; /* 0x180 - 0x184 */
1661 volatile char pad__5[0x80]; /* 0x184 - 0x204 */
1662 volatile u_int32_t BB_tpc_4_b1; /* 0x204 - 0x208 */
1663 volatile u_int32_t BB_tpc_5_b1; /* 0x208 - 0x20c */
1664 volatile u_int32_t BB_tpc_6_b1; /* 0x20c - 0x210 */
1665 volatile char pad__6[0x10]; /* 0x210 - 0x220 */
1666 volatile u_int32_t BB_tpc_11_b1; /* 0x220 - 0x224 */
1667 volatile char pad__7[0x1c]; /* 0x224 - 0x240 */
1669 volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x240 - 0x2c0 */
1671 volatile u_int32_t BB_tpc_19_b1; /* 0x240 - 0x244 */
1672 volatile u_int32_t pad__7_1[31]; /* 0x244 - 0x2c0 */
1673 volatile char pad__8[0x190]; /* 0x2c0 - 0x450 */
1676 volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x240 - 0x2c0 */
1677 volatile char pad__8[0x190]; /* 0x2c0 - 0x450 */
1680 volatile u_int32_t BB_tpc_19_b1; /* 0x240 - 0x244 */
1681 volatile char pad__8[0x3c]; /* 0x244 - 0x280 */
1682 volatile u_int32_t BB_pdadc_tab_b1[32]; /* 0x280 - 0x300 */
1683 volatile char pad__9[0x84]; /* 0x300 - 0x384 */
1684 volatile u_int32_t BB_rtt_table_sw_intf_b1; /* 0x384 - 0x388 */
1685 volatile u_int32_t BB_rtt_table_sw_intf_1_b1; /* 0x388 - 0x38c */
1686 volatile char pad__10[0xc4]; /* 0x38c - 0x450 */
1689 volatile u_int32_t BB_txiq_corr_coeff_01_b1; /* 0x450 - 0x454 */
1690 volatile u_int32_t BB_txiq_corr_coeff_23_b1; /* 0x454 - 0x458 */
1691 volatile u_int32_t BB_txiq_corr_coeff_45_b1; /* 0x458 - 0x45c */
1692 volatile u_int32_t BB_txiq_corr_coeff_67_b1; /* 0x45c - 0x460 */
1693 volatile u_int32_t BB_txiq_corr_coeff_89_b1; /* 0x460 - 0x464 */
1694 volatile u_int32_t BB_txiq_corr_coeff_ab_b1; /* 0x464 - 0x468 */
1695 volatile u_int32_t BB_txiq_corr_coeff_cd_b1; /* 0x468 - 0x46c */
1696 volatile u_int32_t BB_txiq_corr_coeff_ef_b1; /* 0x46c - 0x470 */
1697 volatile char pad__9[0x1c]; /* 0x470 - 0x48c */
1698 volatile u_int32_t BB_txiqcal_status_b1; /* 0x48c - 0x490 */
1699 volatile char pad__10[0x20]; /* 0x490 - 0x4b0 */
1702 volatile char pad__11[0x150]; /* 0x4b0 - 0x600 */
1705 volatile u_int32_t BB_aic_ctrl_0_b1; /* 0x4b0 - 0x4b4 */
1706 volatile u_int32_t BB_aic_ctrl_1_b1; /* 0x4b4 - 0x4b8 */
1707 volatile char pad__11[0x8]; /* 0x4b8 - 0x4c0 */
1708 volatile u_int32_t BB_aic_stat_0_b1; /* 0x4c0 - 0x4c4 */
1709 volatile u_int32_t BB_aic_stat_1_b1; /* 0x4c4 - 0x4c8 */
1710 volatile char pad__12[0x128]; /* 0x4c8 - 0x5f0 */
1711 volatile u_int32_t BB_tables_intf_addr_b1; /* 0x5f0 - 0x5f4 */
1712 volatile u_int32_t BB_tables_intf_data_b1; /* 0x5f4 - 0x5f8 */
1713 volatile char pad__13[0x8]; /* 0x5f8 - 0x600 */
1716 volatile u_int32_t BB_aic_ctrl_0_b1; /* 0x4b0 - 0x4b4 */
1717 volatile u_int32_t BB_aic_ctrl_1_b1; /* 0x4b4 - 0x4b8 */
1718 volatile char pad__11[0x8]; /* 0x4b8 - 0x4c0 */
1719 volatile u_int32_t BB_aic_ctrl_4_b1; /* 0x4c0 - 0x4c4 */
1720 volatile u_int32_t BB_aic_stat_0_b1; /* 0x4c4 - 0x4c8 */
1721 volatile u_int32_t BB_aic_stat_1_b1; /* 0x4c8 - 0x4cc */
1722 volatile u_int32_t BB_aic_stat_2_b1; /* 0x4cc - 0x4d0 */
1723 volatile char pad__12[0x120]; /* 0x4d0 - 0x5f0 */
1724 volatile u_int32_t BB_tables_intf_addr_b1; /* 0x5f0 - 0x5f4 */
1725 volatile u_int32_t BB_tables_intf_data_b1; /* 0x5f4 - 0x5f8 */
1726 volatile char pad__13[0x8]; /* 0x5f8 - 0x600 */
1731 struct chn2_reg_map {
1732 volatile u_int32_t BB_dummy_DONOTACCESS2; /* 0x0 - 0x4 */
1733 volatile char pad__0[0x2c]; /* 0x4 - 0x30 */
1734 volatile u_int32_t BB_ext_chan_pwr_thr_2_b2; /* 0x30 - 0x34 */
1735 volatile char pad__1[0x74]; /* 0x34 - 0xa8 */
1736 volatile u_int32_t BB_spur_report_b2; /* 0xa8 - 0xac */
1737 volatile char pad__2[0x14]; /* 0xac - 0xc0 */
1738 volatile u_int32_t BB_iq_adc_meas_0_b2; /* 0xc0 - 0xc4 */
1739 volatile u_int32_t BB_iq_adc_meas_1_b2; /* 0xc4 - 0xc8 */
1740 volatile u_int32_t BB_iq_adc_meas_2_b2; /* 0xc8 - 0xcc */
1741 volatile u_int32_t BB_iq_adc_meas_3_b2; /* 0xcc - 0xd0 */
1742 volatile u_int32_t BB_tx_phase_ramp_b2; /* 0xd0 - 0xd4 */
1743 volatile u_int32_t BB_adc_gain_dc_corr_b2; /* 0xd4 - 0xd8 */
1744 volatile char pad__3[0x4]; /* 0xd8 - 0xdc */
1745 volatile u_int32_t BB_rx_iq_corr_b2; /* 0xdc - 0xe0 */
1746 volatile char pad__4[0x10]; /* 0xe0 - 0xf0 */
1747 volatile u_int32_t BB_paprd_ctrl0_b2; /* 0xf0 - 0xf4 */
1748 volatile u_int32_t BB_paprd_ctrl1_b2; /* 0xf4 - 0xf8 */
1749 volatile u_int32_t BB_pa_gain123_b2; /* 0xf8 - 0xfc */
1750 volatile u_int32_t BB_pa_gain45_b2; /* 0xfc - 0x100 */
1751 volatile u_int32_t BB_paprd_pre_post_scale_0_b2;
1753 volatile u_int32_t BB_paprd_pre_post_scale_1_b2;
1755 volatile u_int32_t BB_paprd_pre_post_scale_2_b2;
1757 volatile u_int32_t BB_paprd_pre_post_scale_3_b2;
1759 volatile u_int32_t BB_paprd_pre_post_scale_4_b2;
1761 volatile u_int32_t BB_paprd_pre_post_scale_5_b2;
1763 volatile u_int32_t BB_paprd_pre_post_scale_6_b2;
1765 volatile u_int32_t BB_paprd_pre_post_scale_7_b2;
1767 volatile u_int32_t BB_paprd_mem_tab_b2[120]; /* 0x120 - 0x300 */
1768 volatile u_int32_t BB_chan_info_chan_tab_b2[60];
1772 struct agc2_reg_map {
1773 volatile u_int32_t BB_dummy_DONOTACCESS4; /* 0x0 - 0x4 */
1774 volatile u_int32_t BB_gain_force_max_gains_b2; /* 0x4 - 0x8 */
1775 volatile char pad__0[0x10]; /* 0x8 - 0x18 */
1776 volatile u_int32_t BB_ext_atten_switch_ctl_b2; /* 0x18 - 0x1c */
1777 volatile u_int32_t BB_cca_b2; /* 0x1c - 0x20 */
1778 volatile u_int32_t BB_cca_ctrl_2_b2; /* 0x20 - 0x24 */
1779 volatile char pad__1[0x15c]; /* 0x24 - 0x180 */
1780 volatile u_int32_t BB_rssi_b2; /* 0x180 - 0x184 */
1781 volatile char pad__2[0x4]; /* 0x184 - 0x188 */
1782 volatile u_int32_t BB_agc_dig_dc_status_i_b2; /* 0x188 - 0x18c */
1783 volatile u_int32_t BB_agc_dig_dc_status_q_b2; /* 0x18c - 0x190 */
1786 struct sm2_reg_map {
1787 volatile u_int32_t BB_dummy_DONOTACCESS6; /* 0x0 - 0x4 */
1788 volatile char pad__0[0x80]; /* 0x4 - 0x84 */
1789 volatile u_int32_t BB_switch_table_chn_b2; /* 0x84 - 0x88 */
1790 volatile char pad__1[0x48]; /* 0x88 - 0xd0 */
1791 volatile u_int32_t BB_fcal_2_b2; /* 0xd0 - 0xd4 */
1792 volatile u_int32_t BB_dft_tone_ctrl_b2; /* 0xd4 - 0xd8 */
1793 volatile char pad__2[0x4]; /* 0xd8 - 0xdc */
1794 volatile u_int32_t BB_cl_map_0_b2; /* 0xdc - 0xe0 */
1795 volatile u_int32_t BB_cl_map_1_b2; /* 0xe0 - 0xe4 */
1796 volatile u_int32_t BB_cl_map_2_b2; /* 0xe4 - 0xe8 */
1797 volatile u_int32_t BB_cl_map_3_b2; /* 0xe8 - 0xec */
1798 volatile u_int32_t BB_cl_map_pal_0_b2; /* 0xec - 0xf0 */
1799 volatile u_int32_t BB_cl_map_pal_1_b2; /* 0xf0 - 0xf4 */
1800 volatile u_int32_t BB_cl_map_pal_2_b2; /* 0xf4 - 0xf8 */
1801 volatile u_int32_t BB_cl_map_pal_3_b2; /* 0xf8 - 0xfc */
1802 volatile char pad__3[0x4]; /* 0xfc - 0x100 */
1803 volatile u_int32_t BB_cl_tab_b2[16]; /* 0x100 - 0x140 */
1804 volatile char pad__4[0x40]; /* 0x140 - 0x180 */
1805 volatile u_int32_t BB_chan_info_gain_b2; /* 0x180 - 0x184 */
1806 volatile char pad__5[0x80]; /* 0x184 - 0x204 */
1807 volatile u_int32_t BB_tpc_4_b2; /* 0x204 - 0x208 */
1808 volatile u_int32_t BB_tpc_5_b2; /* 0x208 - 0x20c */
1809 volatile u_int32_t BB_tpc_6_b2; /* 0x20c - 0x210 */
1810 volatile char pad__6[0x10]; /* 0x210 - 0x220 */
1811 volatile u_int32_t BB_tpc_11_b2; /* 0x220 - 0x224 */
1812 volatile char pad__7[0x1c]; /* 0x224 - 0x240 */
1814 volatile u_int32_t BB_pdadc_tab_b2[32]; /* 0x240 - 0x2c0 */
1816 volatile u_int32_t BB_tpc_19_b2; /* 0x240 - 0x244 */
1817 volatile u_int32_t pad__7_1[31]; /* 0x244 - 0x2c0 */
1820 volatile char pad__8[0x190]; /* 0x2c0 - 0x450 */
1821 volatile u_int32_t BB_txiq_corr_coeff_01_b2; /* 0x450 - 0x454 */
1822 volatile u_int32_t BB_txiq_corr_coeff_23_b2; /* 0x454 - 0x458 */
1823 volatile u_int32_t BB_txiq_corr_coeff_45_b2; /* 0x458 - 0x45c */
1824 volatile u_int32_t BB_txiq_corr_coeff_67_b2; /* 0x45c - 0x460 */
1825 volatile u_int32_t BB_txiq_corr_coeff_89_b2; /* 0x460 - 0x464 */
1826 volatile u_int32_t BB_txiq_corr_coeff_ab_b2; /* 0x464 - 0x468 */
1827 volatile u_int32_t BB_txiq_corr_coeff_cd_b2; /* 0x468 - 0x46c */
1828 volatile u_int32_t BB_txiq_corr_coeff_ef_b2; /* 0x46c - 0x470 */
1829 volatile char pad__9[0x1c]; /* 0x470 - 0x48c */
1830 volatile u_int32_t BB_txiqcal_status_b2; /* 0x48c - 0x490 */
1831 volatile char pad__10[0x16c]; /* 0x490 - 0x5fc */
1832 volatile u_int32_t BB_dummy_sm2; /* 0x5fc - 0x600 */
1835 struct chn3_reg_map {
1836 volatile u_int32_t BB_dummy1[256]; /* 0x0 - 0x400 */
1839 struct agc3_reg_map {
1840 volatile u_int32_t BB_dummy; /* 0x0 - 0x4 */
1841 volatile char pad__0[0x17c]; /* 0x4 - 0x180 */
1842 volatile u_int32_t BB_rssi_b3; /* 0x180 - 0x184 */
1845 struct sm3_reg_map {
1846 volatile u_int32_t BB_dummy2[384]; /* 0x0 - 0x600 */
1850 volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */
1851 struct chn_reg_map bb_chn_reg_map; /* 0x9800 - 0x9bf8 */
1852 volatile char pad__1[0x8]; /* 0x9bf8 - 0x9c00 */
1853 struct mrc_reg_map bb_mrc_reg_map; /* 0x9c00 - 0x9c24 */
1854 volatile char pad__2[0xdc]; /* 0x9c24 - 0x9d00 */
1855 struct bbb_reg_map bb_bbb_reg_map; /* 0x9d00 - 0x9d20 */
1856 volatile char pad__3[0xe0]; /* 0x9d20 - 0x9e00 */
1857 struct agc_reg_map bb_agc_reg_map; /* 0x9e00 - 0xa200 */
1858 struct sm_reg_map bb_sm_reg_map; /* 0xa200 - 0xa7f8 */
1859 volatile char pad__4[0x8]; /* 0xa7f8 - 0xa800 */
1862 struct chn1_reg_map bb_chn1_reg_map; /* 0xa800 - 0xabf8 */
1863 volatile char pad__5[0x208]; /* 0xabf8 - 0xae00 */
1864 struct agc1_reg_map bb_agc1_reg_map; /* 0xae00 - 0xb200 */
1865 struct sm1_reg_map bb_sm1_reg_map; /* 0xb200 - 0xb800 */
1866 struct chn2_reg_map bb_chn2_reg_map; /* 0xb800 - 0xbbf0 */
1867 volatile char pad__6[0x210]; /* 0xbbf0 - 0xbe00 */
1868 struct agc2_reg_map bb_agc2_reg_map; /* 0xbe00 - 0xbf90 */
1869 volatile char pad__7[0x270]; /* 0xbf90 - 0xc200 */
1870 struct sm2_reg_map bb_sm2_reg_map; /* 0xc200 - 0xc800 */
1873 struct chn_ext_reg_map bb_chn_ext_reg_map; /* 0xa800 - 0xac00 */
1874 volatile char pad__5[0x600]; /* 0xac00 - 0xb200 */
1875 struct sm_ext_reg_map bb_sm_ext_reg_map; /* 0xb200 - 0xb800 */
1876 volatile char pad__6[0x600]; /* 0xb800 - 0xbe00 */
1877 struct agc1_reg_map bb_agc1_reg_map; /* 0xbe00 - 0xc1fc */
1878 volatile char pad__7[0x4]; /* 0xc1fc - 0xc200 */
1879 struct sm1_reg_map bb_sm1_reg_map; /* 0xc200 - 0xc800 */
1882 struct chn3_reg_map bb_chn3_reg_map; /* 0xc800 - 0xcc00 */
1883 volatile char pad__8[0x200]; /* 0xcc00 - 0xce00 */
1884 struct agc3_reg_map bb_agc3_reg_map; /* 0xce00 - 0xcf84 */
1885 volatile char pad__9[0x27c]; /* 0xcf84 - 0xd200 */
1886 struct sm3_reg_map bb_sm3_reg_map; /* 0xd200 - 0xd800 */
1890 volatile char pad__0[0x10000]; /* 0x0 - 0x10000 */
1891 volatile u_int32_t TXBF_DBG; /* 0x10000 - 0x10004 */
1892 volatile u_int32_t TXBF; /* 0x10004 - 0x10008 */
1893 volatile u_int32_t TXBF_TIMER; /* 0x10008 - 0x1000c */
1894 volatile u_int32_t TXBF_SW; /* 0x1000c - 0x10010 */
1895 volatile u_int32_t TXBF_SM; /* 0x10010 - 0x10014 */
1896 volatile u_int32_t TXBF1_CNTL; /* 0x10014 - 0x10018 */
1897 volatile u_int32_t TXBF2_CNTL; /* 0x10018 - 0x1001c */
1898 volatile u_int32_t TXBF3_CNTL; /* 0x1001c - 0x10020 */
1899 volatile u_int32_t TXBF4_CNTL; /* 0x10020 - 0x10024 */
1900 volatile u_int32_t TXBF5_CNTL; /* 0x10024 - 0x10028 */
1901 volatile u_int32_t TXBF6_CNTL; /* 0x10028 - 0x1002c */
1902 volatile u_int32_t TXBF7_CNTL; /* 0x1002c - 0x10030 */
1903 volatile u_int32_t TXBF8_CNTL; /* 0x10030 - 0x10034 */
1904 volatile char pad__1[0xfcc]; /* 0x10034 - 0x11000 */
1905 volatile u_int32_t RC0[118]; /* 0x11000 - 0x111d8 */
1906 volatile char pad__2[0x28]; /* 0x111d8 - 0x11200 */
1907 volatile u_int32_t RC1[118]; /* 0x11200 - 0x113d8 */
1908 volatile char pad__3[0x28]; /* 0x113d8 - 0x11400 */
1909 volatile u_int32_t SVD_MEM0[114]; /* 0x11400 - 0x115c8 */
1910 volatile char pad__4[0x38]; /* 0x115c8 - 0x11600 */
1911 volatile u_int32_t SVD_MEM1[114]; /* 0x11600 - 0x117c8 */
1912 volatile char pad__5[0x38]; /* 0x117c8 - 0x11800 */
1913 volatile u_int32_t SVD_MEM2[114]; /* 0x11800 - 0x119c8 */
1914 volatile char pad__6[0x38]; /* 0x119c8 - 0x11a00 */
1915 volatile u_int32_t SVD_MEM3[114]; /* 0x11a00 - 0x11bc8 */
1916 volatile char pad__7[0x38]; /* 0x11bc8 - 0x11c00 */
1917 volatile u_int32_t SVD_MEM4[114]; /* 0x11c00 - 0x11dc8 */
1918 volatile char pad__8[0x638]; /* 0x11dc8 - 0x12400 */
1919 volatile u_int32_t CVCACHE[512]; /* 0x12400 - 0x12c00 */
1922 struct efuse_reg_WLAN {
1923 volatile char pad__0[0x14000]; /* 0x0 - 0x14000 */
1924 volatile u_int32_t OTP_MEM[256]; /* 0x14000 - 0x14400 */
1925 volatile char pad__1[0x1b00]; /* 0x14400 - 0x15f00 */
1926 volatile u_int32_t OTP_INTF0; /* 0x15f00 - 0x15f04 */
1927 volatile u_int32_t OTP_INTF1; /* 0x15f04 - 0x15f08 */
1928 volatile u_int32_t OTP_INTF2; /* 0x15f08 - 0x15f0c */
1929 volatile u_int32_t OTP_INTF3; /* 0x15f0c - 0x15f10 */
1930 volatile u_int32_t OTP_INTF4; /* 0x15f10 - 0x15f14 */
1931 volatile u_int32_t OTP_INTF5; /* 0x15f14 - 0x15f18 */
1932 volatile u_int32_t OTP_STATUS0; /* 0x15f18 - 0x15f1c */
1933 volatile u_int32_t OTP_STATUS1; /* 0x15f1c - 0x15f20 */
1934 volatile u_int32_t OTP_INTF6; /* 0x15f20 - 0x15f24 */
1935 volatile u_int32_t OTP_LDO_CONTROL; /* 0x15f24 - 0x15f28 */
1936 volatile u_int32_t OTP_LDO_POWER_GOOD; /* 0x15f28 - 0x15f2c */
1937 volatile u_int32_t OTP_LDO_STATUS; /* 0x15f2c - 0x15f30 */
1938 volatile u_int32_t OTP_VDDQ_HOLD_TIME; /* 0x15f30 - 0x15f34 */
1939 volatile u_int32_t OTP_PGENB_SETUP_HOLD_TIME; /* 0x15f34 - 0x15f38 */
1940 volatile u_int32_t OTP_STROBE_PULSE_INTERVAL; /* 0x15f38 - 0x15f3c */
1941 volatile u_int32_t OTP_CSB_ADDR_LOAD_SETUP_HOLD;
1942 /* 0x15f3c - 0x15f40 */
1945 struct radio65_reg {
1946 volatile char pad__0[0x16000]; /* 0x0 - 0x16000 */
1947 volatile u_int32_t ch0_RXRF_BIAS1; /* 0x16000 - 0x16004 */
1948 volatile u_int32_t ch0_RXRF_BIAS2; /* 0x16004 - 0x16008 */
1949 volatile u_int32_t ch0_RXRF_GAINSTAGES; /* 0x16008 - 0x1600c */
1950 volatile u_int32_t ch0_RXRF_AGC; /* 0x1600c - 0x16010 */
1952 volatile u_int32_t ch0_RXRF_BIAS3; /* 0x16010 - 0x16014 */
1953 volatile char pad__1[0x2c]; /* 0x16014 - 0x16040 */
1954 volatile u_int32_t ch0_TXRF1; /* 0x16040 - 0x16044 */
1955 volatile u_int32_t ch0_TXRF2; /* 0x16044 - 0x16048 */
1956 volatile u_int32_t ch0_TXRF3; /* 0x16048 - 0x1604c */
1957 volatile u_int32_t ch0_TXRF4; /* 0x1604c - 0x16050 */
1958 volatile u_int32_t ch0_TXRF5; /* 0x16050 - 0x16054 */
1959 volatile u_int32_t ch0_TXRF6; /* 0x16054 - 0x16058 */
1961 volatile u_int32_t ch0_TXRF7; /* 0x16058 - 0x1605c */
1963 volatile u_int32_t ch0_TXRF8; /* 0x1605c - 0x16060 */
1965 volatile u_int32_t ch0_TXRF9; /* 0x16060 - 0x16064 */
1967 volatile u_int32_t ch0_TXRF10; /* 0x16064 - 0x16068 */
1969 volatile u_int32_t ch0_TXRF11; /* 0x16068 - 0x1606c */
1971 volatile u_int32_t ch0_TXRF12; /* 0x1606c - 0x16070 */
1972 volatile char pad__2[0x10]; /* 0x16070 - 0x16080 */
1973 volatile u_int32_t ch0_SYNTH1; /* 0x16080 - 0x16084 */
1974 volatile u_int32_t ch0_SYNTH2; /* 0x16084 - 0x16088 */
1975 volatile u_int32_t ch0_SYNTH3; /* 0x16088 - 0x1608c */
1976 volatile u_int32_t ch0_SYNTH4; /* 0x1608c - 0x16090 */
1977 volatile u_int32_t ch0_SYNTH5; /* 0x16090 - 0x16094 */
1978 volatile u_int32_t ch0_SYNTH6; /* 0x16094 - 0x16098 */
1979 volatile u_int32_t ch0_SYNTH7; /* 0x16098 - 0x1609c */
1980 volatile u_int32_t ch0_SYNTH8; /* 0x1609c - 0x160a0 */
1981 volatile u_int32_t ch0_SYNTH9; /* 0x160a0 - 0x160a4 */
1982 volatile u_int32_t ch0_SYNTH10; /* 0x160a4 - 0x160a8 */
1983 volatile u_int32_t ch0_SYNTH11; /* 0x160a8 - 0x160ac */
1984 volatile u_int32_t ch0_SYNTH12; /* 0x160ac - 0x160b0 */
1985 volatile u_int32_t ch0_SYNTH13; /* 0x160b0 - 0x160b4 */
1986 volatile u_int32_t ch0_SYNTH14; /* 0x160b4 - 0x160b8 */
1988 volatile u_int32_t ch0_SYNTH15; /* 0x160b8 - 0x160bc */
1990 volatile u_int32_t ch0_SYNTH16; /* 0x160bc - 0x160c0 */
1991 volatile u_int32_t ch0_BIAS1; /* 0x160c0 - 0x160c4 */
1992 volatile u_int32_t ch0_BIAS2; /* 0x160c4 - 0x160c8 */
1993 volatile u_int32_t ch0_BIAS3; /* 0x160c8 - 0x160cc */
1994 volatile u_int32_t ch0_BIAS4; /* 0x160cc - 0x160d0 */
1996 volatile u_int32_t ch0_BIAS5; /* 0x160d0 - 0x160d4 */
1997 volatile char pad__3[0x2c]; /* 0x160d4 - 0x16100 */
1998 volatile u_int32_t ch0_RXTX1; /* 0x16100 - 0x16104 */
1999 volatile u_int32_t ch0_RXTX2; /* 0x16104 - 0x16108 */
2000 volatile u_int32_t ch0_RXTX3; /* 0x16108 - 0x1610c */
2001 volatile u_int32_t ch0_RXTX4; /* 0x1610c - 0x16110 */
2003 volatile u_int32_t ch0_RXTX5; /* 0x16110 - 0x16114 */
2004 volatile char pad__4[0x2c]; /* 0x16114 - 0x16140 */
2005 volatile u_int32_t ch0_BB1; /* 0x16140 - 0x16144 */
2006 volatile u_int32_t ch0_BB2; /* 0x16144 - 0x16148 */
2007 volatile u_int32_t ch0_BB3; /* 0x16148 - 0x1614c */
2008 volatile char pad__6[0x34]; /* 0x1614c - 0x16180 */
2011 volatile u_int32_t ch0_pll_cntl; /* 0x16180 - 0x16184 */
2012 volatile u_int32_t ch0_pll_mode; /* 0x16184 - 0x16188 */
2013 volatile u_int32_t ch0_bb_dpll3; /* 0x16188 - 0x1618c */
2014 volatile u_int32_t ch0_bb_dpll4; /* 0x1618c - 0x16190 */
2015 volatile char pad__6_1[0xf0]; /* 0x16190 - 0x16280 */
2016 volatile u_int32_t ch0_PLLCLKMODA; /* 0x16280 - 0x16284 */
2017 volatile u_int32_t ch0_PLLCLKMODA2; /* 0x16284 - 0x16288 */
2018 volatile u_int32_t ch0_TOP; /* 0x16288 - 0x1628c */
2019 volatile u_int32_t ch0_TOP2; /* 0x1628c - 0x16290 */
2020 volatile u_int32_t ch0_THERM; /* 0x16290 - 0x16294 */
2021 volatile u_int32_t ch0_XTAL; /* 0x16294 - 0x16298 */
2022 volatile char pad__7[0xe8]; /* 0x16298 - 0x16380 */
2025 volatile u_int32_t ch0_BB_DPLL1; /* 0x16180 - 0x16184 */
2026 volatile u_int32_t ch0_BB_DPLL2; /* 0x16184 - 0x16188 */
2027 volatile u_int32_t ch0_BB_DPLL3; /* 0x16188 - 0x1618c */
2028 volatile u_int32_t ch0_BB_DPLL4; /* 0x1618c - 0x16190 */
2029 volatile char pad__7[0xb0]; /* 0x16190 - 0x16240 */
2030 volatile u_int32_t ch0_DDR_DPLL1; /* 0x16240 - 0x16244 */
2031 volatile u_int32_t ch0_DDR_DPLL2; /* 0x16244 - 0x16248 */
2032 volatile u_int32_t ch0_DDR_DPLL3; /* 0x16248 - 0x1624c */
2033 volatile u_int32_t ch0_DDR_DPLL4; /* 0x1624c - 0x16250 */
2034 volatile char pad__8[0x30]; /* 0x16250 - 0x16280 */
2035 volatile u_int32_t ch0_TOP; /* 0x16280 - 0x16284 */
2036 volatile u_int32_t ch0_TOP2; /* 0x16284 - 0x16288 */
2037 volatile u_int32_t ch0_TOP3; /* 0x16288 - 0x1628c */
2038 volatile u_int32_t ch0_THERM; /* 0x1628c - 0x16290 */
2039 volatile u_int32_t ch0_XTAL; /* 0x16290 - 0x16294 */
2040 volatile char pad__9[0xec]; /* 0x16294 - 0x16380 */
2043 volatile char pad__6_1[0x100]; /* 0x16180 - 0x16280 */
2044 volatile u_int32_t ch0_PLLCLKMODA1; /* 0x16280 - 0x16284 */
2045 volatile u_int32_t ch0_PLLCLKMODA2; /* 0x16284 - 0x16288 */
2046 volatile u_int32_t ch0_PLLCLKMODA3; /* 0x16288 - 0x1628c */
2047 volatile u_int32_t ch0_TOP1; /* 0x1628c - 0x16290 */
2048 volatile u_int32_t ch0_TOP2; /* 0x16290 - 0x16294 */
2049 volatile u_int32_t ch0_THERM; /* 0x16294 - 0x16298 */
2050 volatile u_int32_t ch0_XTAL; /* 0x16298 - 0x1629c */
2051 volatile char pad__7[0xa4]; /* 0x1629c - 0x16340 */
2052 volatile u_int32_t ch0_PMU1; /* 0x16340 - 0x16344 */
2053 volatile u_int32_t ch0_PMU2; /* 0x16344 - 0x16348 */
2054 volatile u_int32_t ch0_PMU3; /* 0x16348 - 0x1634c */
2055 volatile char pad__8[0x34]; /* 0x1634c - 0x16380 */
2058 volatile u_int32_t ch0_DPLL; /* 0x16180 - 0x16184 */
2059 volatile u_int32_t ch0_DPLL2; /* 0x16184 - 0x16188 */
2060 volatile u_int32_t ch0_DPLL3; /* 0x16188 - 0x1618c */
2061 volatile u_int32_t ch0_DPLL4; /* 0x1618c - 0x16190 */
2062 volatile u_int32_t ch0_DPLL5; /* 0x16190 - 0x16194 */
2063 volatile char pad__6[0xec]; /* 0x16194 - 0x16280 */
2064 volatile u_int32_t ch0_PLLCLKMODA1; /* 0x16280 - 0x16284 */
2065 volatile u_int32_t ch0_PLLCLKMODA2; /* 0x16284 - 0x16288 */
2066 volatile u_int32_t ch0_PLLCLKMODA3; /* 0x16288 - 0x1628c */
2067 volatile u_int32_t ch0_TOP1; /* 0x1628c - 0x16290 */
2068 volatile u_int32_t ch0_TOP2; /* 0x16290 - 0x16294 */
2069 volatile u_int32_t ch0_THERM; /* 0x16294 - 0x16298 */
2070 volatile u_int32_t ch0_XTAL; /* 0x16298 - 0x1629c */
2071 volatile char pad__7[0xa4]; /* 0x1629c - 0x16340 */
2072 volatile u_int32_t ch0_PMU1; /* 0x16340 - 0x16344 */
2073 volatile u_int32_t ch0_PMU2; /* 0x16344 - 0x16348 */
2074 volatile char pad__8[0x38]; /* 0x16348 - 0x16380 */
2077 volatile u_int32_t ch0_rbist_cntrl; /* 0x16380 - 0x16384 */
2078 volatile u_int32_t ch0_tx_dc_offset; /* 0x16384 - 0x16388 */
2079 volatile u_int32_t ch0_tx_tonegen0; /* 0x16388 - 0x1638c */
2080 volatile u_int32_t ch0_tx_tonegen1; /* 0x1638c - 0x16390 */
2081 volatile u_int32_t ch0_tx_lftonegen0; /* 0x16390 - 0x16394 */
2082 volatile u_int32_t ch0_tx_linear_ramp_i; /* 0x16394 - 0x16398 */
2083 volatile u_int32_t ch0_tx_linear_ramp_q; /* 0x16398 - 0x1639c */
2084 volatile u_int32_t ch0_tx_prbs_mag; /* 0x1639c - 0x163a0 */
2085 volatile u_int32_t ch0_tx_prbs_seed_i; /* 0x163a0 - 0x163a4 */
2086 volatile u_int32_t ch0_tx_prbs_seed_q; /* 0x163a4 - 0x163a8 */
2087 volatile u_int32_t ch0_cmac_dc_cancel; /* 0x163a8 - 0x163ac */
2088 volatile u_int32_t ch0_cmac_dc_offset; /* 0x163ac - 0x163b0 */
2089 volatile u_int32_t ch0_cmac_corr; /* 0x163b0 - 0x163b4 */
2090 volatile u_int32_t ch0_cmac_power; /* 0x163b4 - 0x163b8 */
2091 volatile u_int32_t ch0_cmac_cross_corr; /* 0x163b8 - 0x163bc */
2092 volatile u_int32_t ch0_cmac_i2q2; /* 0x163bc - 0x163c0 */
2093 volatile u_int32_t ch0_cmac_power_hpf; /* 0x163c0 - 0x163c4 */
2094 volatile u_int32_t ch0_rxdac_set1; /* 0x163c4 - 0x163c8 */
2095 volatile u_int32_t ch0_rxdac_set2; /* 0x163c8 - 0x163cc */
2096 volatile u_int32_t ch0_rxdac_long_shift; /* 0x163cc - 0x163d0 */
2097 volatile u_int32_t ch0_cmac_results_i; /* 0x163d0 - 0x163d4 */
2098 volatile u_int32_t ch0_cmac_results_q; /* 0x163d4 - 0x163d8 */
2099 volatile char pad__8[0x28]; /* 0x163d8 - 0x16400 */
2100 volatile u_int32_t ch1_RXRF_BIAS1; /* 0x16400 - 0x16404 */
2101 volatile u_int32_t ch1_RXRF_BIAS2; /* 0x16404 - 0x16408 */
2102 volatile u_int32_t ch1_RXRF_GAINSTAGES; /* 0x16408 - 0x1640c */
2103 volatile u_int32_t ch1_RXRF_AGC; /* 0x1640c - 0x16410 */
2105 volatile u_int32_t ch1_RXRF_BIAS3; /* 0x16410 - 0x16414 */
2106 volatile char pad__9[0x2c]; /* 0x16414 - 0x16440 */
2107 volatile u_int32_t ch1_TXRF1; /* 0x16440 - 0x16444 */
2108 volatile u_int32_t ch1_TXRF2; /* 0x16444 - 0x16448 */
2109 volatile u_int32_t ch1_TXRF3; /* 0x16448 - 0x1644c */
2110 volatile u_int32_t ch1_TXRF4; /* 0x1644c - 0x16450 */
2111 volatile u_int32_t ch1_TXRF5; /* 0x16450 - 0x16454 */
2112 volatile u_int32_t ch1_TXRF6; /* 0x16454 - 0x16458 */
2113 volatile u_int32_t ch1_TXRF7; /* 0x16458 - 0x1645c */
2114 volatile u_int32_t ch1_TXRF8; /* 0x1645c - 0x16460 */
2115 volatile u_int32_t ch1_TXRF9; /* 0x16460 - 0x16464 */
2116 volatile u_int32_t ch1_TXRF10; /* 0x16464 - 0x16468 */
2117 volatile u_int32_t ch1_TXRF11; /* 0x16468 - 0x1646c */
2118 volatile u_int32_t ch1_TXRF12; /* 0x1646c - 0x16470 */
2119 volatile char pad__10[0x90]; /* 0x16470 - 0x16500 */
2120 volatile u_int32_t ch1_RXTX1; /* 0x16500 - 0x16504 */
2121 volatile u_int32_t ch1_RXTX2; /* 0x16504 - 0x16508 */
2122 volatile u_int32_t ch1_RXTX3; /* 0x16508 - 0x1650c */
2123 volatile u_int32_t ch1_RXTX4; /* 0x1650c - 0x16510 */
2125 volatile u_int32_t ch1_RXTX5; /* 0x16510 - 0x16514 */
2126 volatile char pad__11[0x2c]; /* 0x16514 - 0x16540 */
2127 volatile u_int32_t ch1_BB1; /* 0x16540 - 0x16544 */
2128 volatile u_int32_t ch1_BB2; /* 0x16544 - 0x16548 */
2129 volatile u_int32_t ch1_BB3; /* 0x16548 - 0x1654c */
2130 volatile char pad__12[0x234]; /* 0x1654c - 0x16780 */
2131 volatile u_int32_t ch1_rbist_cntrl; /* 0x16780 - 0x16784 */
2132 volatile u_int32_t ch1_tx_dc_offset; /* 0x16784 - 0x16788 */
2133 volatile u_int32_t ch1_tx_tonegen0; /* 0x16788 - 0x1678c */
2134 volatile u_int32_t ch1_tx_tonegen1; /* 0x1678c - 0x16790 */
2135 volatile u_int32_t ch1_tx_lftonegen0; /* 0x16790 - 0x16794 */
2136 volatile u_int32_t ch1_tx_linear_ramp_i; /* 0x16794 - 0x16798 */
2137 volatile u_int32_t ch1_tx_linear_ramp_q; /* 0x16798 - 0x1679c */
2138 volatile u_int32_t ch1_tx_prbs_mag; /* 0x1679c - 0x167a0 */
2139 volatile u_int32_t ch1_tx_prbs_seed_i; /* 0x167a0 - 0x167a4 */
2140 volatile u_int32_t ch1_tx_prbs_seed_q; /* 0x167a4 - 0x167a8 */
2141 volatile u_int32_t ch1_cmac_dc_cancel; /* 0x167a8 - 0x167ac */
2142 volatile u_int32_t ch1_cmac_dc_offset; /* 0x167ac - 0x167b0 */
2143 volatile u_int32_t ch1_cmac_corr; /* 0x167b0 - 0x167b4 */
2144 volatile u_int32_t ch1_cmac_power; /* 0x167b4 - 0x167b8 */
2145 volatile u_int32_t ch1_cmac_cross_corr; /* 0x167b8 - 0x167bc */
2146 volatile u_int32_t ch1_cmac_i2q2; /* 0x167bc - 0x167c0 */
2147 volatile u_int32_t ch1_cmac_power_hpf; /* 0x167c0 - 0x167c4 */
2148 volatile u_int32_t ch1_rxdac_set1; /* 0x167c4 - 0x167c8 */
2149 volatile u_int32_t ch1_rxdac_set2; /* 0x167c8 - 0x167cc */
2150 volatile u_int32_t ch1_rxdac_long_shift; /* 0x167cc - 0x167d0 */
2151 volatile u_int32_t ch1_cmac_results_i; /* 0x167d0 - 0x167d4 */
2152 volatile u_int32_t ch1_cmac_results_q; /* 0x167d4 - 0x167d8 */
2153 volatile char pad__13[0x28]; /* 0x167d8 - 0x16800 */
2154 volatile u_int32_t ch2_RXRF_BIAS1; /* 0x16800 - 0x16804 */
2155 volatile u_int32_t ch2_RXRF_BIAS2; /* 0x16804 - 0x16808 */
2156 volatile u_int32_t ch2_RXRF_GAINSTAGES; /* 0x16808 - 0x1680c */
2157 volatile u_int32_t ch2_RXRF_AGC; /* 0x1680c - 0x16810 */
2158 volatile char pad__14[0x30]; /* 0x16810 - 0x16840 */
2159 volatile u_int32_t ch2_TXRF1; /* 0x16840 - 0x16844 */
2160 volatile u_int32_t ch2_TXRF2; /* 0x16844 - 0x16848 */
2161 volatile u_int32_t ch2_TXRF3; /* 0x16848 - 0x1684c */
2162 volatile u_int32_t ch2_TXRF4; /* 0x1684c - 0x16850 */
2163 volatile u_int32_t ch2_TXRF5; /* 0x16850 - 0x16854 */
2164 volatile u_int32_t ch2_TXRF6; /* 0x16854 - 0x16858 */
2165 volatile u_int32_t ch2_TXRF7; /* 0x16858 - 0x1685c */
2166 volatile u_int32_t ch2_TXRF8; /* 0x1685c - 0x16860 */
2167 volatile u_int32_t ch2_TXRF9; /* 0x16860 - 0x16864 */
2168 volatile u_int32_t ch2_TXRF10; /* 0x16864 - 0x16868 */
2169 volatile u_int32_t ch2_TXRF11; /* 0x16868 - 0x1686c */
2170 volatile u_int32_t ch2_TXRF12; /* 0x1686c - 0x16870 */
2171 volatile char pad__15[0x90]; /* 0x16870 - 0x16900 */
2172 volatile u_int32_t ch2_RXTX1; /* 0x16900 - 0x16904 */
2173 volatile u_int32_t ch2_RXTX2; /* 0x16904 - 0x16908 */
2174 volatile u_int32_t ch2_RXTX3; /* 0x16908 - 0x1690c */
2175 volatile u_int32_t ch2_RXTX4; /* 0x1690c - 0x16910 */
2176 volatile char pad__16[0x30]; /* 0x16910 - 0x16940 */
2177 volatile u_int32_t ch2_BB1; /* 0x16940 - 0x16944 */
2178 volatile u_int32_t ch2_BB2; /* 0x16944 - 0x16948 */
2179 volatile u_int32_t ch2_BB3; /* 0x16948 - 0x1694c */
2180 volatile char pad__17[0x234]; /* 0x1694c - 0x16b80 */
2181 volatile u_int32_t ch2_rbist_cntrl; /* 0x16b80 - 0x16b84 */
2182 volatile u_int32_t ch2_tx_dc_offset; /* 0x16b84 - 0x16b88 */
2183 volatile u_int32_t ch2_tx_tonegen0; /* 0x16b88 - 0x16b8c */
2184 volatile u_int32_t ch2_tx_tonegen1; /* 0x16b8c - 0x16b90 */
2185 volatile u_int32_t ch2_tx_lftonegen0; /* 0x16b90 - 0x16b94 */
2186 volatile u_int32_t ch2_tx_linear_ramp_i; /* 0x16b94 - 0x16b98 */
2187 volatile u_int32_t ch2_tx_linear_ramp_q; /* 0x16b98 - 0x16b9c */
2188 volatile u_int32_t ch2_tx_prbs_mag; /* 0x16b9c - 0x16ba0 */
2189 volatile u_int32_t ch2_tx_prbs_seed_i; /* 0x16ba0 - 0x16ba4 */
2190 volatile u_int32_t ch2_tx_prbs_seed_q; /* 0x16ba4 - 0x16ba8 */
2191 volatile u_int32_t ch2_cmac_dc_cancel; /* 0x16ba8 - 0x16bac */
2192 volatile u_int32_t ch2_cmac_dc_offset; /* 0x16bac - 0x16bb0 */
2193 volatile u_int32_t ch2_cmac_corr; /* 0x16bb0 - 0x16bb4 */
2194 volatile u_int32_t ch2_cmac_power; /* 0x16bb4 - 0x16bb8 */
2195 volatile u_int32_t ch2_cmac_cross_corr; /* 0x16bb8 - 0x16bbc */
2196 volatile u_int32_t ch2_cmac_i2q2; /* 0x16bbc - 0x16bc0 */
2197 volatile u_int32_t ch2_cmac_power_hpf; /* 0x16bc0 - 0x16bc4 */
2198 volatile u_int32_t ch2_rxdac_set1; /* 0x16bc4 - 0x16bc8 */
2199 volatile u_int32_t ch2_rxdac_set2; /* 0x16bc8 - 0x16bcc */
2200 volatile u_int32_t ch2_rxdac_long_shift; /* 0x16bcc - 0x16bd0 */
2201 volatile u_int32_t ch2_cmac_results_i; /* 0x16bd0 - 0x16bd4 */
2202 volatile u_int32_t ch2_cmac_results_q; /* 0x16bd4 - 0x16bd8 */
2203 volatile char pad__18[0x4c4a8]; /* 0x16bd8 - 0x63080 */
2205 volatile u_int32_t chbt_SYNTH1; /* 0x63080 - 0x63084 */
2206 volatile u_int32_t chbt_SYNTH2; /* 0x63084 - 0x63088 */
2207 volatile u_int32_t chbt_SYNTH3; /* 0x63088 - 0x6308c */
2208 volatile u_int32_t chbt_SYNTH4; /* 0x6308c - 0x63090 */
2209 volatile u_int32_t chbt_SYNTH5; /* 0x63090 - 0x63094 */
2210 volatile u_int32_t chbt_SYNTH6; /* 0x63094 - 0x63098 */
2211 volatile u_int32_t chbt_SYNTH7; /* 0x63098 - 0x6309c */
2212 volatile u_int32_t chbt_SYNTH8; /* 0x6309c - 0x630a0 */
2213 volatile char pad__19[0x20]; /* 0x630a0 - 0x630c0 */
2214 volatile u_int32_t chbt_BIAS1; /* 0x630c0 - 0x630c4 */
2215 volatile u_int32_t chbt_BIAS2; /* 0x630c4 - 0x630c8 */
2216 volatile u_int32_t chbt_BIAS3; /* 0x630c8 - 0x630cc */
2217 volatile u_int32_t chbt_BIAS4; /* 0x630cc - 0x630d0 */
2218 volatile u_int32_t chbt_BIAS5; /* 0x630d0 - 0x630d4 */
2219 volatile char pad__20[0x2c]; /* 0x630d4 - 0x63100 */
2220 volatile u_int32_t chbt_TOP1; /* 0x63100 - 0x63104 */
2221 volatile u_int32_t chbt_TOP2; /* 0x63104 - 0x63108 */
2222 volatile u_int32_t chbt_TOP3; /* 0x63108 - 0x6310c */
2223 volatile u_int32_t chbt_TOP4; /* 0x6310c - 0x63110 */
2224 volatile u_int32_t chbt_TOP5; /* 0x63110 - 0x63114 */
2225 volatile u_int32_t chbt_TOP6; /* 0x63114 - 0x63118 */
2226 volatile u_int32_t chbt_TOP7; /* 0x63118 - 0x6311c */
2227 volatile u_int32_t chbt_TOP8; /* 0x6311c - 0x63120 */
2228 volatile u_int32_t chbt_TOP9; /* 0x63120 - 0x63124 */
2229 volatile u_int32_t chbt_TOP10; /* 0x63124 - 0x63128 */
2230 volatile char pad__21[0x158]; /* 0x63128 - 0x63280 */
2231 volatile u_int32_t chbt_CLK1; /* 0x63280 - 0x63284 */
2232 volatile u_int32_t chbt_CLK2; /* 0x63284 - 0x63288 */
2233 volatile u_int32_t chbt_CLK3; /* 0x63288 - 0x6328c */
2234 volatile char pad__22[0xb4]; /* 0x6328c - 0x63340 */
2235 volatile u_int32_t chbt_PMU1; /* 0x63340 - 0x63344 */
2236 volatile u_int32_t chbt_PMU2; /* 0x63344 - 0x63348 */
2238 /* Aphrodite-start */
2239 volatile char pad__23[0x38]; /* 0x63348 - 0x63380 */
2240 volatile u_int32_t chbt_rbist_cntrl; /* 0x63380 - 0x63384 */
2241 volatile u_int32_t chbt_tx_dc_offset; /* 0x63384 - 0x63388 */
2242 volatile u_int32_t chbt_tx_tonegen0; /* 0x63388 - 0x6338c */
2243 volatile u_int32_t chbt_tx_tonegen1; /* 0x6338c - 0x63390 */
2244 volatile u_int32_t chbt_tx_lftonegen0; /* 0x63390 - 0x63394 */
2245 volatile u_int32_t chbt_tx_linear_ramp_i; /* 0x63394 - 0x63398 */
2246 volatile u_int32_t chbt_tx_linear_ramp_q; /* 0x63398 - 0x6339c */
2247 volatile u_int32_t chbt_tx_prbs_mag; /* 0x6339c - 0x633a0 */
2248 volatile u_int32_t chbt_tx_prbs_seed_i; /* 0x633a0 - 0x633a4 */
2249 volatile u_int32_t chbt_tx_prbs_seed_q; /* 0x633a4 - 0x633a8 */
2250 volatile u_int32_t chbt_cmac_dc_cancel; /* 0x633a8 - 0x633ac */
2251 volatile u_int32_t chbt_cmac_dc_offset; /* 0x633ac - 0x633b0 */
2252 volatile u_int32_t chbt_cmac_corr; /* 0x633b0 - 0x633b4 */
2253 volatile u_int32_t chbt_cmac_power; /* 0x633b4 - 0x633b8 */
2254 volatile u_int32_t chbt_cmac_cross_corr; /* 0x633b8 - 0x633bc */
2255 volatile u_int32_t chbt_cmac_i2q2; /* 0x633bc - 0x633c0 */
2256 volatile u_int32_t chbt_cmac_power_hpf; /* 0x633c0 - 0x633c4 */
2257 volatile u_int32_t chbt_rxdac_set1; /* 0x633c4 - 0x633c8 */
2258 volatile u_int32_t chbt_rxdac_set2; /* 0x633c8 - 0x633cc */
2259 volatile u_int32_t chbt_rxdac_long_shift; /* 0x633cc - 0x633d0 */
2260 volatile u_int32_t chbt_cmac_results_i; /* 0x633d0 - 0x633d4 */
2261 volatile u_int32_t chbt_cmac_results_q; /* 0x633d4 - 0x633d8 */
2265 struct pcie_phy_reg_csr {
2266 volatile char pad__0[0x18c00]; /* 0x0 - 0x18c00 */
2267 volatile u_int32_t pcie_phy_reg_1; /* 0x18c00 - 0x18c04 */
2268 volatile u_int32_t pcie_phy_reg_2; /* 0x18c04 - 0x18c08 */
2269 volatile u_int32_t pcie_phy_reg_3; /* 0x18c08 - 0x18c0c */
2273 volatile char pad__0[0x16c40]; /* 0x0 - 0x16c40 */
2274 volatile u_int32_t ch0_PMU1; /* 0x16c40 - 0x16c44 */
2275 volatile u_int32_t ch0_PMU2; /* 0x16c44 - 0x16c48 */
2278 struct wlan_coex_reg {
2279 volatile char pad__0[0x1800]; /* 0x0 - 0x1800 */
2280 volatile u_int32_t MCI_COMMAND0; /* 0x1800 - 0x1804 */
2281 volatile u_int32_t MCI_COMMAND1; /* 0x1804 - 0x1808 */
2282 volatile u_int32_t MCI_COMMAND2; /* 0x1808 - 0x180c */
2283 volatile u_int32_t MCI_RX_CTRL; /* 0x180c - 0x1810 */
2284 volatile u_int32_t MCI_TX_CTRL; /* 0x1810 - 0x1814 */
2285 volatile u_int32_t MCI_MSG_ATTRIBUTES_TABLE; /* 0x1814 - 0x1818 */
2286 volatile u_int32_t MCI_SCHD_TABLE_0; /* 0x1818 - 0x181c */
2287 volatile u_int32_t MCI_SCHD_TABLE_1; /* 0x181c - 0x1820 */
2288 volatile u_int32_t MCI_GPM_0; /* 0x1820 - 0x1824 */
2289 volatile u_int32_t MCI_GPM_1; /* 0x1824 - 0x1828 */
2290 volatile u_int32_t MCI_INTERRUPT_RAW; /* 0x1828 - 0x182c */
2291 volatile u_int32_t MCI_INTERRUPT_EN; /* 0x182c - 0x1830 */
2292 volatile u_int32_t MCI_REMOTE_CPU_INT; /* 0x1830 - 0x1834 */
2293 volatile u_int32_t MCI_REMOTE_CPU_INT_EN; /* 0x1834 - 0x1838 */
2294 volatile u_int32_t MCI_INTERRUPT_RX_MSG_RAW; /* 0x1838 - 0x183c */
2295 volatile u_int32_t MCI_INTERRUPT_RX_MSG_EN; /* 0x183c - 0x1840 */
2296 volatile u_int32_t MCI_CPU_INT; /* 0x1840 - 0x1844 */
2297 volatile u_int32_t MCI_RX_STATUS; /* 0x1844 - 0x1848 */
2298 volatile u_int32_t MCI_CONT_STATUS; /* 0x1848 - 0x184c */
2299 volatile u_int32_t MCI_BT_PRI0; /* 0x184c - 0x1850 */
2300 volatile u_int32_t MCI_BT_PRI1; /* 0x1850 - 0x1854 */
2301 volatile u_int32_t MCI_BT_PRI2; /* 0x1854 - 0x1858 */
2302 volatile u_int32_t MCI_BT_PRI3; /* 0x1858 - 0x185c */
2303 volatile u_int32_t MCI_BT_PRI; /* 0x185c - 0x1860 */
2304 volatile u_int32_t MCI_WL_FREQ0; /* 0x1860 - 0x1864 */
2305 volatile u_int32_t MCI_WL_FREQ1; /* 0x1864 - 0x1868 */
2306 volatile u_int32_t MCI_WL_FREQ2; /* 0x1868 - 0x186c */
2307 volatile u_int32_t MCI_GAIN; /* 0x186c - 0x1870 */
2308 volatile u_int32_t MCI_WBTIMER1; /* 0x1870 - 0x1874 */
2309 volatile u_int32_t MCI_WBTIMER2; /* 0x1874 - 0x1878 */
2310 volatile u_int32_t MCI_WBTIMER3; /* 0x1878 - 0x187c */
2311 volatile u_int32_t MCI_WBTIMER4; /* 0x187c - 0x1880 */
2312 volatile u_int32_t MCI_MAXGAIN; /* 0x1880 - 0x1884 */
2313 volatile u_int32_t MCI_HW_SCHD_TBL_CTL; /* 0x1884 - 0x1888 */
2314 volatile u_int32_t MCI_HW_SCHD_TBL_D0; /* 0x1888 - 0x188c */
2315 volatile u_int32_t MCI_HW_SCHD_TBL_D1; /* 0x188c - 0x1890 */
2316 volatile u_int32_t MCI_HW_SCHD_TBL_D2; /* 0x1890 - 0x1894 */
2317 volatile u_int32_t MCI_HW_SCHD_TBL_D3; /* 0x1894 - 0x1898 */
2318 volatile u_int32_t MCI_TX_PAYLOAD0; /* 0x1898 - 0x189c */
2319 volatile u_int32_t MCI_TX_PAYLOAD1; /* 0x189c - 0x18a0 */
2320 volatile u_int32_t MCI_TX_PAYLOAD2; /* 0x18a0 - 0x18a4 */
2321 volatile u_int32_t MCI_TX_PAYLOAD3; /* 0x18a4 - 0x18a8 */
2322 volatile u_int32_t BTCOEX_WBTIMER; /* 0x18a8 - 0x18ac */
2323 volatile u_int32_t BTCOEX_CTRL; /* 0x18ac - 0x18b0 */
2324 volatile u_int32_t BTCOEX_WL_WEIGHTS0; /* 0x18b0 - 0x18b4 */
2325 volatile u_int32_t BTCOEX_WL_WEIGHTS1; /* 0x18b4 - 0x18b8 */
2326 volatile u_int32_t BTCOEX_WL_WEIGHTS2; /* 0x18b8 - 0x18bc */
2327 volatile u_int32_t BTCOEX_WL_WEIGHTS3; /* 0x18bc - 0x18c0 */
2328 volatile u_int32_t BTCOEX_MAX_TXPWR[8]; /* 0x18c0 - 0x18e0 */
2329 volatile char pad__1[0x60]; /* 0x18e0 - 0x1940 */
2330 volatile u_int32_t BTCOEX_WL_LNA; /* 0x1940 - 0x1944 */
2331 volatile u_int32_t BTCOEX_RFGAIN_CTRL; /* 0x1944 - 0x1948 */
2332 volatile u_int32_t BTCOEX_CTRL2; /* 0x1948 - 0x194c */
2333 volatile u_int32_t BTCOEX_RC; /* 0x194c - 0x1950 */
2334 volatile u_int32_t BTCOEX_MAX_RFGAIN[16]; /* 0x1950 - 0x1990 */
2335 volatile char pad__2[0xc0]; /* 0x1990 - 0x1a50 */
2336 volatile u_int32_t BTCOEX_DBG; /* 0x1a50 - 0x1a54 */
2337 volatile u_int32_t MCI_LAST_HW_MSG_HDR; /* 0x1a54 - 0x1a58 */
2338 volatile u_int32_t MCI_LAST_HW_MSG_BDY; /* 0x1a58 - 0x1a5c */
2339 volatile u_int32_t MCI_SCHD_TABLE_2; /* 0x1a5c - 0x1a60 */
2340 volatile u_int32_t BTCOEX_CTRL3; /* 0x1a60 - 0x1a64 */
2341 /* Aphrodite-start */
2342 volatile u_int32_t BTCOEX_WL_LNADIV; /* 0x1a64 - 0x1a68 */
2343 volatile u_int32_t BTCOEX_TXTX_RANGE; /* 0x1a68 - 0x1a6c */
2344 volatile u_int32_t MCI_INTERRUPT_1_RAW; /* 0x1a6c - 0x1a70 */
2345 volatile u_int32_t MCI_INTERRUPT_1_EN; /* 0x1a70 - 0x1a74 */
2346 volatile u_int32_t MCI_EV_MISC; /* 0x1a74 - 0x1a78 */
2347 volatile u_int32_t MCI_DBG_CNT_CTRL; /* 0x1a78 - 0x1a7c */
2348 volatile u_int32_t MCI_DBG_CNT1; /* 0x1a7c - 0x1a80 */
2349 volatile u_int32_t MCI_DBG_CNT2; /* 0x1a80 - 0x1a84 */
2350 volatile u_int32_t MCI_DBG_CNT3; /* 0x1a84 - 0x1a88 */
2351 volatile u_int32_t MCI_DBG_CNT4; /* 0x1a88 - 0x1a8c */
2352 volatile u_int32_t MCI_DBG_CNT5; /* 0x1a8c - 0x1a90 */
2353 volatile u_int32_t MCI_DBG_CNT6; /* 0x1a90 - 0x1a94 */
2354 volatile u_int32_t MCI_DBG_CNT7; /* 0x1a94 - 0x1a98 */
2355 volatile u_int32_t MCI_DBG_CNT8; /* 0x1a98 - 0x1a9c */
2356 volatile u_int32_t MCI_DBG_CNT9; /* 0x1a9c - 0x1aa0 */
2357 volatile u_int32_t MCI_DBG_CNT10; /* 0x1aa0 - 0x1aa4 */
2358 volatile u_int32_t MCI_DBG_CNT11; /* 0x1aa4 - 0x1aa8 */
2359 volatile u_int32_t MCI_DBG_CNT12; /* 0x1aa8 - 0x1aac */
2360 volatile u_int32_t MCI_DBG_CNT13; /* 0x1aac - 0x1ab0 */
2361 volatile u_int32_t MCI_DBG_CNT14; /* 0x1ab0 - 0x1ab4 */
2362 volatile u_int32_t MCI_DBG_CNT15; /* 0x1ab4 - 0x1ab8 */
2363 volatile u_int32_t MCI_DBG_CNT16; /* 0x1ab8 - 0x1abc */
2364 volatile u_int32_t MCI_DBG_CNT17; /* 0x1abc - 0x1ac0 */
2365 volatile u_int32_t MCI_DBG_CNT18; /* 0x1ac0 - 0x1ac4 */
2366 volatile u_int32_t MCI_DBG_CNT19; /* 0x1ac4 - 0x1ac8 */
2370 struct uart1_reg_csr {
2371 volatile u_int32_t UART_DATA; /* 0x0 - 0x4 */
2372 volatile u_int32_t UART_CONTROL; /* 0x4 - 0x8 */
2373 volatile u_int32_t UART_CLKDIV; /* 0x8 - 0xc */
2374 volatile u_int32_t UART_INT; /* 0xc - 0x10 */
2375 volatile u_int32_t UART_INT_EN; /* 0x10 - 0x14 */
2378 struct wlan_bt_glb_reg_pcie {
2379 volatile char pad__0[0x20000]; /* 0x0 - 0x20000 */
2380 volatile u_int32_t GLB_GPIO_CONTROL; /* 0x20000 - 0x20004 */
2381 volatile u_int32_t GLB_WLAN_WOW_STATUS; /* 0x20004 - 0x20008 */
2382 volatile u_int32_t GLB_WLAN_WOW_ENABLE; /* 0x20008 - 0x2000c */
2383 volatile u_int32_t GLB_EMB_CPU_WOW_STATUS; /* 0x2000c - 0x20010 */
2384 volatile u_int32_t GLB_EMB_CPU_WOW_ENABLE; /* 0x20010 - 0x20014 */
2385 volatile u_int32_t GLB_MBOX_CONTROL_STATUS; /* 0x20014 - 0x20018 */
2386 volatile u_int32_t GLB_SW_WOW_CONTROL; /* 0x20018 - 0x2001c */
2387 volatile u_int32_t GLB_APB_TIMEOUT; /* 0x2001c - 0x20020 */
2388 volatile u_int32_t GLB_OTP_LDO_CONTROL; /* 0x20020 - 0x20024 */
2389 volatile u_int32_t GLB_OTP_LDO_POWER_GOOD; /* 0x20024 - 0x20028 */
2390 volatile u_int32_t GLB_OTP_LDO_STATUS; /* 0x20028 - 0x2002c */
2391 volatile u_int32_t GLB_SWREG_DISCONT_MODE; /* 0x2002c - 0x20030 */
2392 volatile u_int32_t GLB_BT_GPIO_REMAP_OUT_CONTROL0;
2393 /* 0x20030 - 0x20034 */
2394 volatile u_int32_t GLB_BT_GPIO_REMAP_OUT_CONTROL1;
2395 /* 0x20034 - 0x20038 */
2396 volatile u_int32_t GLB_BT_GPIO_REMAP_IN_CONTROL0;
2397 /* 0x20038 - 0x2003c */
2398 volatile u_int32_t GLB_BT_GPIO_REMAP_IN_CONTROL1;
2399 /* 0x2003c - 0x20040 */
2400 volatile u_int32_t GLB_BT_GPIO_REMAP_IN_CONTROL2;
2401 /* 0x20040 - 0x20044 */
2404 volatile char pad__1[0xc]; /* 0x20044 - 0x20050 */
2405 volatile u_int32_t GLB_SCRATCH[16]; /* 0x20050 - 0x20090 */
2406 volatile char pad__2[0x370]; /* 0x20090 - 0x20400 */
2409 volatile u_int32_t GLB_CONTROL; /* 0x20044 - 0x20048 */
2410 volatile u_int32_t GLB_STATUS; /* 0x20048 - 0x2004c */
2411 volatile u_int32_t GLB_SCRATCH[16]; /* 0x2004c - 0x2008c */
2412 volatile char pad__1[0x354]; /* 0x2008c - 0x203e0 */
2413 struct uart1_reg_csr shared_uart1; /* 0x203e0 - 0x203f4 */
2414 volatile char pad__2[0xc]; /* 0x203f4 - 0x20400 */
2417 volatile u_int32_t GLB_CONTROL; /* 0x20044 - 0x20048 */
2418 volatile u_int32_t GLB_STATUS; /* 0x20048 - 0x2004c */
2419 volatile char pad__1[0x4]; /* 0x2004c - 0x20050 */
2420 volatile u_int32_t GLB_SCRATCH[16]; /* 0x20050 - 0x20090 */
2421 volatile char pad__2[0x70]; /* 0x20090 - 0x20100 */
2422 volatile u_int32_t PLLOSC_CTRL; /* 0x20100 - 0x20104 */
2423 volatile u_int32_t PLLOSC_CFG; /* 0x20104 - 0x20108 */
2424 volatile char pad__3[0x4]; /* 0x20108 - 0x2010c */
2425 volatile u_int32_t INNOP_MEM_CONTROL; /* 0x2010c - 0x20110 */
2426 volatile u_int32_t USB_CONFIG; /* 0x20110 - 0x20114 */
2427 volatile u_int32_t USB_SPARE32; /* 0x20114 - 0x20118 */
2428 volatile u_int32_t PCIE_AHB_BRIDGE_CFG; /* 0x20118 - 0x2011c */
2429 volatile u_int32_t PCIE_AHB_BRIDGE_CTRL; /* 0x2011c - 0x20120 */
2430 volatile u_int32_t OPTIONAL_CTL_REG; /* 0x20120 - 0x20124 */
2431 volatile u_int32_t PCIE_PWR_CTRL_REG; /* 0x20124 - 0x20128 */
2432 volatile char pad__4[0x4]; /* 0x20128 - 0x2012c */
2433 volatile u_int32_t USBDEV_CLK_CTL_REG; /* 0x2012c - 0x20130 */
2434 volatile u_int32_t UHOST_DEBUG_FSM; /* 0x20130 - 0x20134 */
2435 volatile u_int32_t BRIDGE_DEBUG_FSM; /* 0x20134 - 0x20138 */
2436 volatile u_int32_t BRIDGE_DEBUG_PTR; /* 0x20138 - 0x2013c */
2437 volatile u_int32_t BRIDGE_DEBUG_CLIENT_LOG0; /* 0x2013c - 0x20140 */
2438 volatile u_int32_t BRIDGE_DEBUG_CLIENT_LOG1; /* 0x20140 - 0x20144 */
2439 volatile u_int32_t BRIDGE_DEBUG_CLIENT_LOG2; /* 0x20144 - 0x20148 */
2440 volatile char pad__5[0x298]; /* 0x20148 - 0x203e0 */
2441 volatile u_int32_t GLB_UART[8]; /* 0x203e0 - 0x20400 */
2446 struct jupiter_reg_map__rtc_reg_csr {
2447 volatile u_int32_t RESET_CONTROL; /* 0x0 - 0x4 */
2448 volatile u_int32_t PLL_SETTLE; /* 0x4 - 0x8 */
2449 volatile u_int32_t VDD_SETTLE; /* 0x8 - 0xc */
2450 volatile u_int32_t PWR_CONTROL; /* 0xc - 0x10 */
2451 volatile u_int32_t XTAL_SETTLE; /* 0x10 - 0x14 */
2452 volatile u_int32_t RTC_CLOCK; /* 0x14 - 0x18 */
2453 volatile u_int32_t CORE_CLOCK; /* 0x18 - 0x1c */
2454 volatile u_int32_t CLKBOOT; /* 0x1c - 0x20 */
2455 volatile u_int32_t UART_CLOCK; /* 0x20 - 0x24 */
2456 volatile u_int32_t SI_CLOCK; /* 0x24 - 0x28 */
2457 volatile u_int32_t CLOCK_CONTROL; /* 0x28 - 0x2c */
2458 volatile u_int32_t WDT_CONTROL; /* 0x2c - 0x30 */
2459 volatile u_int32_t WDT_STATUS; /* 0x30 - 0x34 */
2460 volatile u_int32_t WDT; /* 0x34 - 0x38 */
2461 volatile u_int32_t WDT_COUNT; /* 0x38 - 0x3c */
2462 volatile u_int32_t WDT_RESET; /* 0x3c - 0x40 */
2463 volatile u_int32_t RTC_INT_STATUS; /* 0x40 - 0x44 */
2464 volatile u_int32_t INT_SRC_MAPPING; /* 0x44 - 0x48 */
2465 volatile u_int32_t UART_SI_GPIO_INT_STATUS; /* 0x48 - 0x4c */
2466 volatile u_int32_t LF_TIMER0; /* 0x4c - 0x50 */
2467 volatile u_int32_t LF_TIMER_COUNT0; /* 0x50 - 0x54 */
2468 volatile u_int32_t LF_TIMER_CONTROL0; /* 0x54 - 0x58 */
2469 volatile u_int32_t LF_TIMER_STATUS0; /* 0x58 - 0x5c */
2470 volatile u_int32_t LF_TIMER1; /* 0x5c - 0x60 */
2471 volatile u_int32_t LF_TIMER_COUNT1; /* 0x60 - 0x64 */
2472 volatile u_int32_t LF_TIMER_CONTROL1; /* 0x64 - 0x68 */
2473 volatile u_int32_t LF_TIMER_STATUS1; /* 0x68 - 0x6c */
2474 volatile u_int32_t RESET_CAUSE; /* 0x6c - 0x70 */
2475 volatile u_int32_t SYSTEM_SLEEP; /* 0x70 - 0x74 */
2476 volatile u_int32_t KEEP_AWAKE; /* 0x74 - 0x78 */
2477 volatile u_int32_t LPO_CAL; /* 0x78 - 0x7c */
2478 volatile u_int32_t OBS_CLOCK; /* 0x7c - 0x80 */
2479 volatile u_int32_t CHIP_REV; /* 0x80 - 0x84 */
2480 volatile u_int32_t PWR_ON_TIME; /* 0x84 - 0x88 */
2481 volatile u_int32_t PWD_TIME; /* 0x88 - 0x8c */
2482 volatile u_int32_t USB_SUSPEND_POWER_REG; /* 0x8c - 0x90 */
2483 volatile u_int32_t USB_SUSPEND_WAKEUP_COUNTER_REG;
2485 volatile u_int32_t LPO_STEP_CFG; /* 0x94 - 0x98 */
2486 volatile u_int32_t LPO_FAST_CYL; /* 0x98 - 0x9c */
2487 volatile u_int32_t LPO_LPO1; /* 0x9c - 0xa0 */
2488 volatile u_int32_t LPO_LPO2; /* 0xa0 - 0xa4 */
2489 volatile u_int32_t LPO_INT_RAW; /* 0xa4 - 0xa8 */
2490 volatile u_int32_t LPO_N1TARGET; /* 0xa8 - 0xac */
2491 volatile u_int32_t LPO_N2TARGET; /* 0xac - 0xb0 */
2492 volatile u_int32_t LPO_DN1_MULT; /* 0xb0 - 0xb4 */
2493 volatile u_int32_t LPO_DN2_MULT; /* 0xb4 - 0xb8 */
2494 volatile u_int32_t LPO_NTARGET_MIN; /* 0xb8 - 0xbc */
2495 volatile u_int32_t LPO_NTARGET_MAX; /* 0xbc - 0xc0 */
2496 volatile u_int32_t LPO_N1TARGET_DEBUG; /* 0xc0 - 0xc4 */
2497 volatile u_int32_t LPO_N2TARGET_DEBUG; /* 0xc4 - 0xc8 */
2498 volatile u_int32_t OTP; /* 0xc8 - 0xcc */
2499 volatile u_int32_t OTP_STATUS; /* 0xcc - 0xd0 */
2500 volatile u_int32_t USB_PHY_TEST; /* 0xd0 - 0xd4 */
2501 volatile u_int32_t USB_PHY_CONFIG; /* 0xd4 - 0xd8 */
2502 volatile u_int32_t ADDAC_CLOCK_PHASE; /* 0xd8 - 0xdc */
2503 volatile u_int32_t THERM_CONTROL; /* 0xdc - 0xe0 */
2504 volatile u_int32_t THERM_TRIGGER_INTERVAL1; /* 0xe0 - 0xe4 */
2505 volatile u_int32_t THERM_TRIGGER_INTERVAL2; /* 0xe4 - 0xe8 */
2506 volatile u_int32_t THERM_CORRECTION; /* 0xe8 - 0xec */
2507 volatile u_int32_t THERM_CORRECTION_VALUE1; /* 0xec - 0xf0 */
2508 volatile u_int32_t THERM_CORRECTION_VALUE2; /* 0xf0 - 0xf4 */
2509 volatile u_int32_t PLL_CONTROL; /* 0xf4 - 0xf8 */
2510 volatile u_int32_t VDD12D_SENSE; /* 0xf8 - 0xfc */
2511 volatile u_int32_t RBIAS; /* 0xfc - 0x100 */
2512 volatile u_int32_t THERM_CONTROL_VAL; /* 0x100 - 0x104 */
2513 volatile u_int32_t PLL_OSC_CONTROL; /* 0x104 - 0x108 */
2514 volatile u_int32_t AHB_ERR_INT; /* 0x108 - 0x10c */
2515 volatile u_int32_t INT_P2_EN; /* 0x10c - 0x110 */
2516 volatile u_int32_t XTAL_CLOCK; /* 0x110 - 0x114 */
2517 volatile u_int32_t CHIP_MODES; /* 0x114 - 0x118 */
2518 volatile u_int32_t XTAL_FREQ; /* 0x118 - 0x11c */
2519 volatile u_int32_t DEBUGGER_RESET; /* 0x11c - 0x120 */
2520 volatile u_int32_t LPO_3_2K_CLK; /* 0x120 - 0x124 */
2521 volatile u_int32_t LPO1_CLK_DEBUG; /* 0x124 - 0x128 */
2522 volatile u_int32_t LPO2_CLK_DEBUG; /* 0x128 - 0x12c */
2523 volatile u_int32_t ADDR_CHECK; /* 0x12c - 0x130 */
2524 volatile u_int32_t RTC_DUMMY; /* 0x130 - 0x134 */
2527 struct jupiter_reg_map__vmc_reg_csr {
2528 volatile u_int32_t BANK0_ADDR; /* 0x0 - 0x4 */
2529 volatile u_int32_t BANK1_ADDR; /* 0x4 - 0x8 */
2530 volatile u_int32_t BANK_CONFIG; /* 0x8 - 0xc */
2531 volatile u_int32_t MC_BCAM_CONFLICT_ERROR; /* 0xc - 0x10 */
2532 volatile char pad__0[0x10]; /* 0x10 - 0x20 */
2533 volatile u_int32_t MC_BCAM_COMPARE[128]; /* 0x20 - 0x220 */
2534 volatile u_int32_t MC_BCAM_VALID[128]; /* 0x220 - 0x420 */
2535 volatile u_int32_t MC_BCAM_TARGET[128]; /* 0x420 - 0x620 */
2538 struct jupiter_reg_map__apb_map_csr__uart_reg_csr {
2539 volatile u_int32_t UART_DATA; /* 0x0 - 0x4 */
2540 volatile u_int32_t UART_CONTROL; /* 0x4 - 0x8 */
2541 volatile u_int32_t UART_CLKDIV; /* 0x8 - 0xc */
2542 volatile u_int32_t UART_INT; /* 0xc - 0x10 */
2543 volatile u_int32_t UART_INT_EN; /* 0x10 - 0x14 */
2546 struct jupiter_reg_map__si_reg_csr {
2547 volatile u_int32_t SI_CONFIG; /* 0x0 - 0x4 */
2548 volatile u_int32_t SI_CS; /* 0x4 - 0x8 */
2549 volatile u_int32_t SI_TX_DATA0; /* 0x8 - 0xc */
2550 volatile u_int32_t SI_TX_DATA1; /* 0xc - 0x10 */
2551 volatile u_int32_t SI_RX_DATA0; /* 0x10 - 0x14 */
2552 volatile u_int32_t SI_RX_DATA1; /* 0x14 - 0x18 */
2555 struct jupiter_reg_map__gpio_reg_csr {
2556 volatile u_int32_t GPIO_OUT; /* 0x0 - 0x4 */
2557 volatile u_int32_t GPIO_OUT_W1TS; /* 0x4 - 0x8 */
2558 volatile u_int32_t GPIO_OUT_W1TC; /* 0x8 - 0xc */
2559 volatile u_int32_t GPIO_ENABLE; /* 0xc - 0x10 */
2560 volatile u_int32_t GPIO_ENABLE_W1TS; /* 0x10 - 0x14 */
2561 volatile u_int32_t GPIO_ENABLE_W1TC; /* 0x14 - 0x18 */
2562 volatile u_int32_t GPIO_IN; /* 0x18 - 0x1c */
2563 volatile u_int32_t GPIO_STATUS; /* 0x1c - 0x20 */
2564 volatile u_int32_t GPIO_STATUS_W1TS; /* 0x20 - 0x24 */
2565 volatile u_int32_t GPIO_STATUS_W1TC; /* 0x24 - 0x28 */
2566 volatile u_int32_t GPIO_INT_ENABLE; /* 0x28 - 0x2c */
2567 volatile u_int32_t GPIO_INT_ENABLE_W1TS; /* 0x2c - 0x30 */
2568 volatile u_int32_t GPIO_INT_ENABLE_W1TC; /* 0x30 - 0x34 */
2569 volatile u_int32_t GPIO_PIN0; /* 0x34 - 0x38 */
2570 volatile u_int32_t GPIO_PIN1; /* 0x38 - 0x3c */
2571 volatile u_int32_t GPIO_PIN2; /* 0x3c - 0x40 */
2572 volatile u_int32_t GPIO_PIN3; /* 0x40 - 0x44 */
2573 volatile u_int32_t GPIO_PIN4; /* 0x44 - 0x48 */
2574 volatile u_int32_t GPIO_PIN5; /* 0x48 - 0x4c */
2575 volatile u_int32_t GPIO_PIN6; /* 0x4c - 0x50 */
2576 volatile u_int32_t GPIO_PIN7; /* 0x50 - 0x54 */
2577 volatile u_int32_t GPIO_PIN8; /* 0x54 - 0x58 */
2578 volatile u_int32_t GPIO_PIN9; /* 0x58 - 0x5c */
2579 volatile u_int32_t GPIO_PIN10; /* 0x5c - 0x60 */
2580 volatile u_int32_t GPIO_PIN11; /* 0x60 - 0x64 */
2581 volatile u_int32_t GPIO_PIN12; /* 0x64 - 0x68 */
2582 volatile u_int32_t GPIO_PIN13; /* 0x68 - 0x6c */
2583 volatile u_int32_t GPIO_PIN14; /* 0x6c - 0x70 */
2584 volatile u_int32_t GPIO_PIN15; /* 0x70 - 0x74 */
2585 volatile u_int32_t GPIO_PIN16; /* 0x74 - 0x78 */
2586 volatile u_int32_t GPIO_PIN17; /* 0x78 - 0x7c */
2587 volatile u_int32_t GPIO_PIN18; /* 0x7c - 0x80 */
2588 volatile u_int32_t GPIO_PIN19; /* 0x80 - 0x84 */
2589 volatile u_int32_t SIGMA_DELTA; /* 0x84 - 0x88 */
2590 volatile u_int32_t DEBUG_CONTROL; /* 0x88 - 0x8c */
2591 volatile u_int32_t DEBUG_INPUT_SEL; /* 0x8c - 0x90 */
2592 volatile u_int32_t DEBUG_PIN_SEL; /* 0x90 - 0x94 */
2593 volatile u_int32_t DEBUG_OBS_BUS; /* 0x94 - 0x98 */
2596 struct jupiter_reg_map__mbox_reg_csr {
2597 volatile u_int32_t MBOX_FIFO[4]; /* 0x0 - 0x10 */
2598 volatile u_int32_t MBOX_FIFO_STATUS; /* 0x10 - 0x14 */
2599 volatile u_int32_t MBOX_DMA_POLICY; /* 0x14 - 0x18 */
2600 volatile u_int32_t MBOX0_DMA_RX_DESCRIPTOR_BASE;
2602 volatile u_int32_t MBOX0_DMA_RX_CONTROL; /* 0x1c - 0x20 */
2603 volatile u_int32_t MBOX0_DMA_TX_DESCRIPTOR_BASE;
2605 volatile u_int32_t MBOX0_DMA_TX_CONTROL; /* 0x24 - 0x28 */
2606 volatile u_int32_t MBOX1_DMA_RX_DESCRIPTOR_BASE;
2608 volatile u_int32_t MBOX1_DMA_RX_CONTROL; /* 0x2c - 0x30 */
2609 volatile u_int32_t MBOX1_DMA_TX_DESCRIPTOR_BASE;
2611 volatile u_int32_t MBOX1_DMA_TX_CONTROL; /* 0x34 - 0x38 */
2612 volatile u_int32_t MBOX2_DMA_RX_DESCRIPTOR_BASE;
2614 volatile u_int32_t MBOX2_DMA_RX_CONTROL; /* 0x3c - 0x40 */
2615 volatile u_int32_t MBOX2_DMA_TX_DESCRIPTOR_BASE;
2617 volatile u_int32_t MBOX2_DMA_TX_CONTROL; /* 0x44 - 0x48 */
2618 volatile u_int32_t MBOX3_DMA_RX_DESCRIPTOR_BASE;
2620 volatile u_int32_t MBOX3_DMA_RX_CONTROL; /* 0x4c - 0x50 */
2621 volatile u_int32_t MBOX3_DMA_TX_DESCRIPTOR_BASE;
2623 volatile u_int32_t MBOX3_DMA_TX_CONTROL; /* 0x54 - 0x58 */
2624 volatile u_int32_t FIFO_TIMEOUT; /* 0x58 - 0x5c */
2625 volatile u_int32_t MBOX_INT_STATUS; /* 0x5c - 0x60 */
2626 volatile u_int32_t MBOX_INT_ENABLE; /* 0x60 - 0x64 */
2627 volatile u_int32_t MBOX_DEBUG; /* 0x64 - 0x68 */
2628 volatile u_int32_t MBOX_FIFO_RESET; /* 0x68 - 0x6c */
2629 volatile char pad__0[0x4]; /* 0x6c - 0x70 */
2630 volatile u_int32_t MBOX_TXFIFO_POP[4]; /* 0x70 - 0x80 */
2631 volatile u_int32_t HCI_FRAMER; /* 0x80 - 0x84 */
2632 volatile u_int32_t STEREO_CONFIG; /* 0x84 - 0x88 */
2633 volatile u_int32_t STEREO_CONFIG1; /* 0x88 - 0x8c */
2634 volatile u_int32_t STEREO_CONFIG2; /* 0x8c - 0x90 */
2635 volatile u_int32_t STEREO_VOLUME; /* 0x90 - 0x94 */
2636 volatile u_int32_t STEREO_DEBUG; /* 0x94 - 0x98 */
2637 volatile u_int32_t STEREO_CONFIG3; /* 0x98 - 0x9c */
2640 struct jupiter_reg_map__lc_dma_reg_csr {
2641 volatile u_int32_t LC_DMA_MASTER; /* 0x0 - 0x4 */
2642 volatile u_int32_t LC_DMA_TX_CONTROL; /* 0x4 - 0x8 */
2643 volatile u_int32_t LC_DMA_RX_CONTROL; /* 0x8 - 0xc */
2644 volatile u_int32_t LC_DMA_TX_HW; /* 0xc - 0x10 */
2645 volatile u_int32_t LC_DMA_RX_HW; /* 0x10 - 0x14 */
2646 volatile u_int32_t LC_DMA_INT_STATUS; /* 0x14 - 0x18 */
2647 volatile u_int32_t LC_DMA_TX_STATUS; /* 0x18 - 0x1c */
2648 volatile u_int32_t LC_DMA_TX_STATUS_W1TC; /* 0x1c - 0x20 */
2649 volatile u_int32_t LC_DMA_TX_ENABLE; /* 0x20 - 0x24 */
2650 volatile u_int32_t LC_DMA_RX_STATUS; /* 0x24 - 0x28 */
2651 volatile u_int32_t LC_DMA_RX_STATUS_W1TC; /* 0x28 - 0x2c */
2652 volatile u_int32_t LC_DMA_RX_ENABLE; /* 0x2c - 0x30 */
2653 volatile u_int32_t LC_DMA_DEBUG; /* 0x30 - 0x34 */
2656 struct jupiter_reg_map__lc_reg_csr {
2657 volatile u_int32_t LC_DEV_PARAM_DAC_L; /* 0x0 - 0x4 */
2658 volatile u_int32_t LC_DEV_PARAM_DAC_U; /* 0x4 - 0x8 */
2659 volatile u_int32_t LC_DEV_PARAM_BD_ADDR; /* 0x8 - 0xc */
2660 volatile u_int32_t LC_DEV_PARAM_FHS; /* 0xc - 0x10 */
2661 volatile u_int32_t LC_DEV_PARAM_CTL; /* 0x10 - 0x14 */
2662 volatile u_int32_t LC_DEV_PARAM_TIMING; /* 0x14 - 0x18 */
2663 volatile u_int32_t LC_DEV_PARAM_TIMING_1; /* 0x18 - 0x1c */
2664 volatile u_int32_t LC_MISC; /* 0x1c - 0x20 */
2665 volatile u_int32_t LC_DEV_PARAM_COMMAND1; /* 0x20 - 0x24 */
2666 volatile u_int32_t LC_DEV_PARAM_COMMAND2; /* 0x24 - 0x28 */
2667 volatile u_int32_t LC_DEV_PARAM_COMMAND3; /* 0x28 - 0x2c */
2668 volatile u_int32_t LC_DEV_PARAM_COMMAND4; /* 0x2c - 0x30 */
2669 volatile u_int32_t LC_DEV_PARAM_COMMAND5; /* 0x30 - 0x34 */
2670 volatile u_int32_t LC_DEV_PARAM_COMMAND6; /* 0x34 - 0x38 */
2671 volatile u_int32_t LC_DEV_PARAM_COMMAND7; /* 0x38 - 0x3c */
2672 volatile u_int32_t LC_DEV_PARAM_COMMAND8; /* 0x3c - 0x40 */
2673 volatile u_int32_t LC_DEV_PARAM_AC1_L; /* 0x40 - 0x44 */
2674 volatile u_int32_t LC_DEV_PARAM_AC1_U; /* 0x44 - 0x48 */
2675 volatile u_int32_t LC_DEV_PARAM_AC2_L; /* 0x48 - 0x4c */
2676 volatile u_int32_t LC_DEV_PARAM_AC2_U; /* 0x4c - 0x50 */
2677 volatile u_int32_t LC_DEV_PARAM_CLOCK_OFFSET; /* 0x50 - 0x54 */
2678 volatile u_int32_t LC_FREQUENCY; /* 0x54 - 0x58 */
2679 volatile u_int32_t LC_CH_ASSESS_1; /* 0x58 - 0x5c */
2680 volatile u_int32_t LC_CH_ASSESS_2; /* 0x5c - 0x60 */
2681 volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY0;
2683 volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY1;
2685 volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY2;
2687 volatile u_int32_t LC_DEV_PARAM_ENCRYPTION_KEY3;
2689 volatile u_int32_t LC_DEV_PARAM_TX_CONTROL; /* 0x70 - 0x74 */
2690 volatile u_int32_t LC_DEV_PARAM_RX_CONTROL; /* 0x74 - 0x78 */
2691 volatile u_int32_t LC_DEV_PARAM_RX_STATUS1; /* 0x78 - 0x7c */
2692 volatile u_int32_t LC_DEV_PARAM_RX_STATUS2; /* 0x7c - 0x80 */
2693 volatile char pad__0[0x4]; /* 0x80 - 0x84 */
2694 volatile u_int32_t LC_BT_CLOCK0; /* 0x84 - 0x88 */
2695 volatile u_int32_t LC_BT_CLOCK1; /* 0x88 - 0x8c */
2696 volatile u_int32_t LC_BT_CLOCK2; /* 0x8c - 0x90 */
2697 volatile u_int32_t LC_BT_CLOCK3; /* 0x90 - 0x94 */
2698 volatile u_int32_t LC_SYM_TIME0; /* 0x94 - 0x98 */
2699 volatile u_int32_t LC_SYM_TIME1; /* 0x98 - 0x9c */
2700 volatile u_int32_t LC_SYM_TIME2; /* 0x9c - 0xa0 */
2701 volatile u_int32_t LC_SYM_TIME3; /* 0xa0 - 0xa4 */
2702 volatile char pad__1[0x4]; /* 0xa4 - 0xa8 */
2703 volatile u_int32_t LC_ABORT; /* 0xa8 - 0xac */
2704 volatile u_int32_t LC_PRBS; /* 0xac - 0xb0 */
2705 volatile u_int32_t LC_LAST_CORR_HECOK; /* 0xb0 - 0xb4 */
2706 volatile char pad__2[0x4c]; /* 0xb4 - 0x100 */
2707 volatile u_int32_t LC_SM_AFH_TABLE[24]; /* 0x100 - 0x160 */
2708 volatile char pad__3[0x20]; /* 0x160 - 0x180 */
2709 volatile u_int32_t LC_SM_AFH_BITMAP_0; /* 0x180 - 0x184 */
2710 volatile u_int32_t LC_SM_AFH_BITMAP_1; /* 0x184 - 0x188 */
2711 volatile u_int32_t LC_SM_AFH_BITMAP_2; /* 0x188 - 0x18c */
2712 volatile u_int32_t LC_STAT0; /* 0x18c - 0x190 */
2713 volatile u_int32_t LC_STAT1; /* 0x190 - 0x194 */
2714 volatile u_int32_t LC_STAT2; /* 0x194 - 0x198 */
2715 volatile u_int32_t LC_STAT3; /* 0x198 - 0x19c */
2716 volatile u_int32_t LC_STAT4; /* 0x19c - 0x1a0 */
2717 volatile u_int32_t LC_STAT5; /* 0x1a0 - 0x1a4 */
2718 volatile u_int32_t LC_STAT6; /* 0x1a4 - 0x1a8 */
2719 volatile u_int32_t LC_STAT7; /* 0x1a8 - 0x1ac */
2720 volatile u_int32_t LC_STAT8; /* 0x1ac - 0x1b0 */
2721 volatile u_int32_t LC_STAT9; /* 0x1b0 - 0x1b4 */
2722 volatile char pad__4[0x14c]; /* 0x1b4 - 0x300 */
2723 volatile u_int32_t LC_INTERRUPT_RAW; /* 0x300 - 0x304 */
2724 volatile u_int32_t LC_INTERRUPT_EN; /* 0x304 - 0x308 */
2725 volatile u_int32_t LC_INTERRUPT_RX_STATUS; /* 0x308 - 0x30c */
2726 volatile u_int32_t LC_AUDIO_DATAPATH; /* 0x30c - 0x310 */
2727 volatile u_int32_t LC_VOICE_CHAN0; /* 0x310 - 0x314 */
2728 volatile u_int32_t LC_VOICE_CHAN1; /* 0x314 - 0x318 */
2729 volatile u_int32_t LC_VOICE_CHAN0_RX_ENERGY; /* 0x318 - 0x31c */
2730 volatile u_int32_t LC_VOICE_CHAN1_RX_ENERGY; /* 0x31c - 0x320 */
2731 volatile u_int32_t LC_VOICE_CHAN0_TX_ENERGY; /* 0x320 - 0x324 */
2732 volatile u_int32_t LC_VOICE_CHAN1_TX_ENERGY; /* 0x324 - 0x328 */
2733 volatile u_int32_t LC_VOICE_CHAN0_ZERO_CROSS; /* 0x328 - 0x32c */
2734 volatile u_int32_t LC_VOICE_CHAN1_ZERO_CROSS; /* 0x32c - 0x330 */
2735 volatile char pad__5[0xd0]; /* 0x330 - 0x400 */
2736 volatile u_int32_t LC_RX_CTRL_DATAPATH; /* 0x400 - 0x404 */
2737 volatile u_int32_t LC_DEBUG; /* 0x404 - 0x408 */
2738 volatile u_int32_t LC_TX_CTRL_DATAPATH; /* 0x408 - 0x40c */
2739 volatile u_int32_t LC_COMMAND9; /* 0x40c - 0x410 */
2740 volatile u_int32_t BT_CLOCK0_FREE_RUN; /* 0x410 - 0x414 */
2741 volatile u_int32_t BT_CLOCK1_FREE_RUN; /* 0x414 - 0x418 */
2742 volatile u_int32_t BT_CLOCK2_FREE_RUN; /* 0x418 - 0x41c */
2743 volatile u_int32_t BT_CLOCK3_FREE_RUN; /* 0x41c - 0x420 */
2744 volatile u_int32_t LC_DEV_PARAM_COMMAND10; /* 0x420 - 0x424 */
2745 volatile u_int32_t LC_DEV_PARAM_TIMING_2; /* 0x424 - 0x428 */
2746 volatile u_int32_t LC_DEV_PARAM_COMMAND11; /* 0x428 - 0x42c */
2747 volatile u_int32_t MCI_SUB_PRIORITY_TABLE_0; /* 0x42c - 0x430 */
2748 volatile u_int32_t MCI_SUB_PRIORITY_TABLE_1; /* 0x430 - 0x434 */
2749 volatile u_int32_t MCI_SUB_PRIORITY_TABLE_2; /* 0x434 - 0x438 */
2750 volatile u_int32_t MCI_SUB_PRIORITY_TABLE_3; /* 0x438 - 0x43c */
2751 volatile u_int32_t MCI_SUB_PRIORITY_TABLE_4; /* 0x43c - 0x440 */
2752 volatile u_int32_t MCI_COMMAND0; /* 0x440 - 0x444 */
2753 volatile u_int32_t MCI_COMMAND1; /* 0x444 - 0x448 */
2754 volatile u_int32_t MCI_COMMAND2; /* 0x448 - 0x44c */
2755 volatile u_int32_t MCI_RX_CTRL; /* 0x44c - 0x450 */
2756 volatile u_int32_t MCI_TX_CTRL; /* 0x450 - 0x454 */
2757 volatile u_int32_t MCI_MSG_ATTRIBUTES_TABLE; /* 0x454 - 0x458 */
2758 volatile u_int32_t MCI_SCHD_TABLE_0; /* 0x458 - 0x45c */
2759 volatile u_int32_t MCI_SCHD_TABLE_1; /* 0x45c - 0x460 */
2760 volatile u_int32_t MCI_GPM_0; /* 0x460 - 0x464 */
2761 volatile u_int32_t MCI_GPM_1; /* 0x464 - 0x468 */
2762 volatile u_int32_t MCI_INTERRUPT_RAW; /* 0x468 - 0x46c */
2763 volatile u_int32_t MCI_INTERRUPT_EN; /* 0x46c - 0x470 */
2764 volatile u_int32_t MCI_REMOTE_CPU_INT; /* 0x470 - 0x474 */
2765 volatile u_int32_t MCI_REMOTE_CPU_INT_EN; /* 0x474 - 0x478 */
2766 volatile u_int32_t MCI_INTERRUPT_RX_MSG_RAW; /* 0x478 - 0x47c */
2767 volatile u_int32_t MCI_INTERRUPT_RX_MSG_EN; /* 0x47c - 0x480 */
2768 volatile u_int32_t MCI_CPU_INT; /* 0x480 - 0x484 */
2769 volatile u_int32_t MCI_RX_STATUS; /* 0x484 - 0x488 */
2770 volatile u_int32_t WBTIMER; /* 0x488 - 0x48c */
2771 volatile u_int32_t WB_BTCLK_SYNC_PN0; /* 0x48c - 0x490 */
2772 volatile u_int32_t WB_BTCLK_SYNC_PN1; /* 0x490 - 0x494 */
2773 volatile u_int32_t WB_BTCLK_SYNC_PN2; /* 0x494 - 0x498 */
2774 volatile u_int32_t WB_BTCLK_SYNC_PN3; /* 0x498 - 0x49c */
2775 volatile u_int32_t LC_SERIAL; /* 0x49c - 0x4a0 */
2776 volatile u_int32_t LC_PHY_ERR; /* 0x4a0 - 0x4a4 */
2777 volatile u_int32_t LC_PHY_ERR_0; /* 0x4a4 - 0x4a8 */
2778 volatile u_int32_t LC_PHY_ERR_1; /* 0x4a8 - 0x4ac */
2779 volatile u_int32_t LC_PHY_ERR_2; /* 0x4ac - 0x4b0 */
2780 volatile u_int32_t LC_PHY_ERR_3; /* 0x4b0 - 0x4b4 */
2781 volatile u_int32_t LC_PHY_ERR_4; /* 0x4b4 - 0x4b8 */
2782 volatile u_int32_t LC_PHY_ERR_5; /* 0x4b8 - 0x4bc */
2783 volatile u_int32_t LC_SF_CTRL; /* 0x4bc - 0x4c0 */
2784 volatile u_int32_t LC_DUMMY; /* 0x4c0 - 0x4c4 */
2785 volatile u_int32_t LC_FOR_BQB; /* 0x4c4 - 0x4c8 */
2786 volatile u_int32_t SHARED_LNA_PARAM; /* 0x4c8 - 0x4cc */
2787 volatile u_int32_t LC_CHNASS0_SUB1; /* 0x4cc - 0x4d0 */
2788 volatile u_int32_t LC_CHNASS1_SUB1; /* 0x4d0 - 0x4d4 */
2789 volatile u_int32_t LC_CHNASS0_SUB2; /* 0x4d4 - 0x4d8 */
2790 volatile u_int32_t LC_CHNASS1_SUB2; /* 0x4d8 - 0x4dc */
2791 volatile u_int32_t LC_CHNASS0_SUB3; /* 0x4dc - 0x4e0 */
2792 volatile u_int32_t LC_CHNASS1_SUB3; /* 0x4e0 - 0x4e4 */
2793 volatile u_int32_t LC_CHNASS0_SUB4; /* 0x4e4 - 0x4e8 */
2794 volatile u_int32_t LC_CHNASS1_SUB4; /* 0x4e8 - 0x4ec */
2795 volatile u_int32_t LC_CHNASS0_SUB5; /* 0x4ec - 0x4f0 */
2796 volatile u_int32_t LC_CHNASS1_SUB5; /* 0x4f0 - 0x4f4 */
2797 volatile u_int32_t LC_CHNASS0_SUB6; /* 0x4f4 - 0x4f8 */
2798 volatile u_int32_t LC_CHNASS1_SUB6; /* 0x4f8 - 0x4fc */
2799 volatile u_int32_t LC_CHNASS0_SUB7; /* 0x4fc - 0x500 */
2800 volatile u_int32_t LC_CHNASS1_SUB7; /* 0x500 - 0x504 */
2801 volatile u_int32_t LC_LE; /* 0x504 - 0x508 */
2802 volatile u_int32_t MCI_SCHD_TABLE_2; /* 0x508 - 0x50c */
2803 volatile u_int32_t WB_BTCLK_SYNC_LE_PN0; /* 0x50c - 0x510 */
2804 volatile u_int32_t WB_BTCLK_SYNC_LE_PN1; /* 0x510 - 0x514 */
2805 volatile u_int32_t LC_TB_LLR; /* 0x514 - 0x518 */
2806 volatile u_int32_t LC_SYM_TIME0_FREE_RUN; /* 0x518 - 0x51c */
2807 volatile u_int32_t LC_SYM_TIME1_FREE_RUN; /* 0x51c - 0x520 */
2808 volatile u_int32_t LC_SYM_TIME2_FREE_RUN; /* 0x520 - 0x524 */
2809 volatile u_int32_t LC_SYM_TIME3_FREE_RUN; /* 0x524 - 0x528 */
2810 volatile u_int32_t WBTIMERCLK; /* 0x528 - 0x52c */
2813 struct jupiter_reg_map__synthBT_reg_csr {
2814 volatile u_int32_t SYNTHBT1; /* 0x0 - 0x4 */
2815 volatile u_int32_t SYNTHBT2; /* 0x4 - 0x8 */
2816 volatile u_int32_t SYNTHBT3; /* 0x8 - 0xc */
2817 volatile u_int32_t SYNTHBT4; /* 0xc - 0x10 */
2818 volatile u_int32_t SYNTHBT5; /* 0x10 - 0x14 */
2819 volatile u_int32_t SYNTHBT6; /* 0x14 - 0x18 */
2820 volatile u_int32_t SYNTHBT7; /* 0x18 - 0x1c */
2821 volatile u_int32_t SYNTHBT8; /* 0x1c - 0x20 */
2824 struct jupiter_reg_map__BIASBT_reg_csr {
2825 volatile u_int32_t BIASBT1; /* 0x0 - 0x4 */
2826 volatile u_int32_t BIASBT2; /* 0x4 - 0x8 */
2827 volatile u_int32_t BIASBT3; /* 0x8 - 0xc */
2828 volatile u_int32_t BIASBT4; /* 0xc - 0x10 */
2829 volatile u_int32_t BIASBT5; /* 0x10 - 0x14 */
2832 struct jupiter_reg_map__TOPBT_reg_csr {
2833 volatile u_int32_t TOPBT1; /* 0x0 - 0x4 */
2834 volatile u_int32_t TOPBT2; /* 0x4 - 0x8 */
2835 volatile u_int32_t TOPBT3; /* 0x8 - 0xc */
2836 volatile u_int32_t TOPBT4; /* 0xc - 0x10 */
2837 volatile u_int32_t TOPBT5; /* 0x10 - 0x14 */
2838 volatile u_int32_t TOPBT6; /* 0x14 - 0x18 */
2839 volatile u_int32_t TOPBT7; /* 0x18 - 0x1c */
2840 volatile u_int32_t TOPBT8; /* 0x1c - 0x20 */
2841 volatile u_int32_t TOPBT9; /* 0x20 - 0x24 */
2842 volatile u_int32_t TOPBT10; /* 0x24 - 0x28 */
2845 struct jupiter_reg_map__CLK_reg_csr {
2846 volatile u_int32_t CLK1; /* 0x0 - 0x4 */
2847 volatile u_int32_t CLK2; /* 0x4 - 0x8 */
2848 volatile u_int32_t CLK3; /* 0x8 - 0xc */
2851 struct jupiter_reg_map__analog_intf_athr_wlan_reg_csr {
2852 volatile char pad__0[0x880]; /* 0x0 - 0x880 */
2853 struct jupiter_reg_map__synthBT_reg_csr synth_reg_map;
2855 volatile char pad__1[0x20]; /* 0x8a0 - 0x8c0 */
2856 struct jupiter_reg_map__BIASBT_reg_csr BIAS_reg_map;
2858 volatile char pad__2[0x2c]; /* 0x8d4 - 0x900 */
2859 struct jupiter_reg_map__TOPBT_reg_csr TOP_reg_map;
2861 volatile char pad__3[0x158]; /* 0x928 - 0xa80 */
2862 struct jupiter_reg_map__CLK_reg_csr CLK_reg_map;
2866 struct jupiter_reg_map__efuse_reg {
2867 volatile u_int32_t OTP_MEM[128]; /* 0x0 - 0x200 */
2868 volatile char pad__0[0x1d00]; /* 0x200 - 0x1f00 */
2869 volatile u_int32_t OTP_INTF0; /* 0x1f00 - 0x1f04 */
2870 volatile u_int32_t OTP_INTF1; /* 0x1f04 - 0x1f08 */
2871 volatile u_int32_t OTP_INTF2; /* 0x1f08 - 0x1f0c */
2872 volatile u_int32_t OTP_INTF3; /* 0x1f0c - 0x1f10 */
2873 volatile u_int32_t OTP_INTF4; /* 0x1f10 - 0x1f14 */
2874 volatile u_int32_t OTP_INTF5; /* 0x1f14 - 0x1f18 */
2875 volatile u_int32_t OTP_STATUS0; /* 0x1f18 - 0x1f1c */
2876 volatile u_int32_t OTP_STATUS1; /* 0x1f1c - 0x1f20 */
2877 volatile u_int32_t OTP_INTF6; /* 0x1f20 - 0x1f24 */
2878 volatile u_int32_t OTP_LDO_CONTROL; /* 0x1f24 - 0x1f28 */
2879 volatile u_int32_t OTP_LDO_POWER_GOOD; /* 0x1f28 - 0x1f2c */
2880 volatile u_int32_t OTP_LDO_STATUS; /* 0x1f2c - 0x1f30 */
2881 volatile u_int32_t OTP_VDDQ_HOLD_TIME; /* 0x1f30 - 0x1f34 */
2882 volatile u_int32_t OTP_PGENB_SETUP_HOLD_TIME; /* 0x1f34 - 0x1f38 */
2883 volatile u_int32_t OTP_STROBE_PULSE_INTERVAL; /* 0x1f38 - 0x1f3c */
2884 volatile u_int32_t OTP_CSB_ADDR_LOAD_SETUP_HOLD;
2885 /* 0x1f3c - 0x1f40 */
2888 struct jupiter_reg_map__modem_reg_csr {
2889 volatile u_int32_t START_REG; /* 0x0 - 0x4 */
2890 volatile u_int32_t RX_STATUS; /* 0x4 - 0x8 */
2891 volatile u_int32_t AC1_L; /* 0x8 - 0xc */
2892 volatile u_int32_t AC1_U; /* 0xc - 0x10 */
2893 volatile u_int32_t AC2_L; /* 0x10 - 0x14 */
2894 volatile u_int32_t AC2_U; /* 0x14 - 0x18 */
2895 volatile u_int32_t TX_LATE; /* 0x18 - 0x1c */
2896 volatile u_int32_t RF_SYNTH; /* 0x1c - 0x20 */
2897 volatile u_int32_t RF_RX_CONTROL; /* 0x20 - 0x24 */
2898 volatile u_int32_t RF_TX_CONTROL; /* 0x24 - 0x28 */
2899 volatile u_int32_t RF_FORCE; /* 0x28 - 0x2c */
2900 volatile u_int32_t MODEM_CONTROL; /* 0x2c - 0x30 */
2901 volatile u_int32_t DC_FREQ_TRACK; /* 0x30 - 0x34 */
2902 volatile u_int32_t PSK_TRACK; /* 0x34 - 0x38 */
2903 volatile u_int32_t PSK_TRACK2; /* 0x38 - 0x3c */
2904 volatile u_int32_t DEMOD_CTRL1; /* 0x3c - 0x40 */
2905 volatile u_int32_t DEMOD_CTRL2; /* 0x40 - 0x44 */
2906 volatile u_int32_t CORR_PARAM1; /* 0x44 - 0x48 */
2907 volatile u_int32_t CORR_PARAM2; /* 0x48 - 0x4c */
2908 volatile u_int32_t RX_LFDATA; /* 0x4c - 0x50 */
2909 volatile u_int32_t ROT; /* 0x50 - 0x54 */
2910 volatile u_int32_t TX; /* 0x54 - 0x58 */
2911 volatile u_int32_t TX_GFSK1; /* 0x58 - 0x5c */
2912 volatile u_int32_t TX_GFSK2; /* 0x5c - 0x60 */
2913 volatile u_int32_t TX_POWER_CORR0; /* 0x60 - 0x64 */
2914 volatile u_int32_t TX_POWER_CORR1; /* 0x64 - 0x68 */
2915 volatile u_int32_t SYNTH_CHN0; /* 0x68 - 0x6c */
2916 volatile u_int32_t SYNTH_OFFSET; /* 0x6c - 0x70 */
2917 volatile u_int32_t MODEM_DEBUG; /* 0x70 - 0x74 */
2918 volatile u_int32_t AGC_BYPASS; /* 0x74 - 0x78 */
2919 volatile u_int32_t AGC_SAT; /* 0x78 - 0x7c */
2920 volatile u_int32_t AGC_DET1; /* 0x7c - 0x80 */
2921 volatile u_int32_t AGC_DET2; /* 0x80 - 0x84 */
2922 volatile u_int32_t AGC_GAIN1; /* 0x84 - 0x88 */
2923 volatile u_int32_t AGC_GAIN2; /* 0x88 - 0x8c */
2924 volatile u_int32_t AGC_LINEAR_BLK; /* 0x8c - 0x90 */
2925 volatile u_int32_t AGC_NONLIN_BLK; /* 0x90 - 0x94 */
2926 volatile u_int32_t AGC_MIN_POWER; /* 0x94 - 0x98 */
2927 volatile u_int32_t AGC_SLNA_SET0; /* 0x98 - 0x9c */
2928 volatile u_int32_t AGC_SLNA_SET1; /* 0x9c - 0xa0 */
2929 volatile u_int32_t AGC_SLNA_SET2; /* 0xa0 - 0xa4 */
2930 volatile u_int32_t AGC_SLNA_SET3; /* 0xa4 - 0xa8 */
2931 volatile u_int32_t AGC_GAIN1_LEAN; /* 0xa8 - 0xac */
2932 volatile u_int32_t MODEM_CTRL; /* 0xac - 0xb0 */
2933 volatile u_int32_t DEMOD_CTRL3; /* 0xb0 - 0xb4 */
2934 volatile u_int32_t DEMOD_CTRL4; /* 0xb4 - 0xb8 */
2935 volatile u_int32_t TX_GFSK3; /* 0xb8 - 0xbc */
2936 volatile u_int32_t LE_DEMOD; /* 0xbc - 0xc0 */
2937 volatile u_int32_t AGC_LE1; /* 0xc0 - 0xc4 */
2938 volatile u_int32_t AGC_LE2; /* 0xc4 - 0xc8 */
2939 volatile u_int32_t AGC_LE3; /* 0xc8 - 0xcc */
2940 volatile u_int32_t AGC_LE4; /* 0xcc - 0xd0 */
2941 volatile u_int32_t AGC_LE5; /* 0xd0 - 0xd4 */
2942 volatile u_int32_t AGC_LE6; /* 0xd4 - 0xd8 */
2943 volatile u_int32_t LE_FREQ; /* 0xd8 - 0xdc */
2944 volatile u_int32_t LE_BLOCKER; /* 0xdc - 0xe0 */
2945 volatile char pad__0[0x420]; /* 0xe0 - 0x500 */
2946 volatile u_int32_t AGC_GAIN_TABLE[128]; /* 0x500 - 0x700 */
2947 volatile u_int32_t TX_ULP_CNTRL; /* 0x700 - 0x704 */
2948 volatile u_int32_t SS_MANUAL1; /* 0x704 - 0x708 */
2949 volatile u_int32_t SS_MANUAL2; /* 0x708 - 0x70c */
2950 volatile u_int32_t SS_RADIO_CTRL; /* 0x70c - 0x710 */
2951 volatile u_int32_t PHY_ERR_CTRL1; /* 0x710 - 0x714 */
2952 volatile u_int32_t PHY_ERR_CTRL2; /* 0x714 - 0x718 */
2953 volatile u_int32_t PHY_ERR_CTRL3; /* 0x718 - 0x71c */
2954 volatile u_int32_t PHY_ERR_CTRL4; /* 0x71c - 0x720 */
2955 volatile u_int32_t PHY_ERR_STATUS; /* 0x720 - 0x724 */
2956 volatile u_int32_t RBIST_ENABLE_CONTROL; /* 0x724 - 0x728 */
2957 volatile u_int32_t RBIST_TX_DC; /* 0x728 - 0x72c */
2958 volatile u_int32_t RBIST_TX_TONE0; /* 0x72c - 0x730 */
2959 volatile u_int32_t RBIST_TX_TONE1; /* 0x730 - 0x734 */
2960 volatile u_int32_t RBIST_TX_TONE2; /* 0x734 - 0x738 */
2961 volatile u_int32_t RBIST_TX_RAMP_I; /* 0x738 - 0x73c */
2962 volatile u_int32_t RBIST_TX_RAMP_Q; /* 0x73c - 0x740 */
2963 volatile u_int32_t RBIST_TX_PRBS_MAG; /* 0x740 - 0x744 */
2964 volatile u_int32_t RBIST_TX_PRBS_SEED_I; /* 0x744 - 0x748 */
2965 volatile u_int32_t RBIST_TX_PRBS_SEED_Q; /* 0x748 - 0x74c */
2966 volatile u_int32_t RBIST_RX_DC_OFFSET; /* 0x74c - 0x750 */
2967 volatile u_int32_t RBIST_RX_DC_OFFSET_CANCEL; /* 0x750 - 0x754 */
2968 volatile u_int32_t RBIST_RX_DFT; /* 0x754 - 0x758 */
2969 volatile u_int32_t RBIST_RX_POWER; /* 0x758 - 0x75c */
2970 volatile u_int32_t RBIST_RX_IQ; /* 0x75c - 0x760 */
2971 volatile u_int32_t RBIST_RX_I2Q2; /* 0x760 - 0x764 */
2972 volatile u_int32_t RBIST_RX_HPF; /* 0x764 - 0x768 */
2973 volatile u_int32_t RBIST_RX_RESULT_Q; /* 0x768 - 0x76c */
2974 volatile u_int32_t RBIST_RX_RESULT_I; /* 0x76c - 0x770 */
2975 volatile u_int32_t CAL_EN; /* 0x770 - 0x774 */
2976 volatile u_int32_t CAL_CONFIG; /* 0x774 - 0x778 */
2977 volatile u_int32_t PASSIVE_RXIQ; /* 0x778 - 0x77c */
2978 volatile u_int32_t TX_CORR1; /* 0x77c - 0x780 */
2979 volatile u_int32_t TX_CORR2; /* 0x780 - 0x784 */
2980 volatile u_int32_t TX_CORR3; /* 0x784 - 0x788 */
2981 volatile u_int32_t TX_CORR4; /* 0x788 - 0x78c */
2982 volatile u_int32_t RX_IQCORR_0; /* 0x78c - 0x790 */
2983 volatile u_int32_t RX_IQCORR_1; /* 0x790 - 0x794 */
2984 volatile u_int32_t RX_IQCORR_2; /* 0x794 - 0x798 */
2985 volatile u_int32_t RX_IQCORR_3; /* 0x798 - 0x79c */
2986 volatile u_int32_t CAL_MEAS_I2_L; /* 0x79c - 0x7a0 */
2987 volatile u_int32_t CAL_MEAS_I2_U; /* 0x7a0 - 0x7a4 */
2988 volatile u_int32_t CAL_MEAS_IQ_L; /* 0x7a4 - 0x7a8 */
2989 volatile u_int32_t CAL_MEAS_IQ_U; /* 0x7a8 - 0x7ac */
2990 volatile u_int32_t CAL_MEAS_Q2_L; /* 0x7ac - 0x7b0 */
2991 volatile u_int32_t CAL_MEAS_Q2_U; /* 0x7b0 - 0x7b4 */
2992 volatile u_int32_t CAP_SFT_DEBUG; /* 0x7b4 - 0x7b8 */
2993 volatile u_int32_t RX_NOTCH_0; /* 0x7b8 - 0x7bc */
2994 volatile u_int32_t RX_NOTCH_1; /* 0x7bc - 0x7c0 */
2995 volatile u_int32_t RX_NOTCH_2; /* 0x7c0 - 0x7c4 */
2996 volatile u_int32_t RX_NOTCH_INDEX_0; /* 0x7c4 - 0x7c8 */
2997 volatile u_int32_t RX_NOTCH_INDEX_1; /* 0x7c8 - 0x7cc */
2998 volatile u_int32_t RX_NOTCH_INDEX_2; /* 0x7cc - 0x7d0 */
2999 volatile u_int32_t RX_NOTCH_INDEX_3; /* 0x7d0 - 0x7d4 */
3000 volatile u_int32_t RX_NOTCH_INDEX_4; /* 0x7d4 - 0x7d8 */
3001 volatile u_int32_t RX_NOTCH_INDEX_5; /* 0x7d8 - 0x7dc */
3002 volatile u_int32_t RX_NOTCH_INDEX_6; /* 0x7dc - 0x7e0 */
3003 volatile u_int32_t RX_NOTCH_INDEX_7; /* 0x7e0 - 0x7e4 */
3004 volatile u_int32_t RX_NOTCH_PARAMS_0; /* 0x7e4 - 0x7e8 */
3005 volatile u_int32_t RX_NOTCH_PARAMS_1; /* 0x7e8 - 0x7ec */
3006 volatile u_int32_t RX_NOTCH_PARAMS_2; /* 0x7ec - 0x7f0 */
3007 volatile u_int32_t RX_NOTCH_PARAMS_3; /* 0x7f0 - 0x7f4 */
3008 volatile u_int32_t RX_NOTCH_PARAMS_4; /* 0x7f4 - 0x7f8 */
3009 volatile u_int32_t RX_NOTCH_PARAMS_5; /* 0x7f8 - 0x7fc */
3010 volatile u_int32_t RX_NOTCH_PARAMS_6; /* 0x7fc - 0x800 */
3011 volatile u_int32_t CHNASS_CTRL; /* 0x800 - 0x804 */
3012 volatile u_int32_t CHNASS_SETUP_0; /* 0x804 - 0x808 */
3013 volatile u_int32_t CHNASS_SETUP_1; /* 0x808 - 0x80c */
3014 volatile u_int32_t CHNASS_SETUP_2; /* 0x80c - 0x810 */
3015 volatile u_int32_t CHNASS_SETUP_3; /* 0x810 - 0x814 */
3016 volatile u_int32_t CHNASS_RSSI_0; /* 0x814 - 0x818 */
3017 volatile u_int32_t CHNASS_RSSI_1; /* 0x818 - 0x81c */
3018 volatile u_int32_t SW_CTRL; /* 0x81c - 0x820 */
3019 volatile u_int32_t JUPITER_CTRL; /* 0x820 - 0x824 */
3020 volatile u_int32_t JUPITER_GAIN; /* 0x824 - 0x828 */
3021 volatile u_int32_t AGC_HIST_SETUP; /* 0x828 - 0x82c */
3022 volatile u_int32_t AGC_HIST_BANK_0; /* 0x82c - 0x830 */
3023 volatile u_int32_t AGC_HIST_BANK_1; /* 0x830 - 0x834 */
3024 volatile u_int32_t AGC_HIST_BANK_2; /* 0x834 - 0x838 */
3025 volatile u_int32_t AGC_HIST_BANK_3; /* 0x838 - 0x83c */
3026 volatile u_int32_t AGC_HIST_BANK_4; /* 0x83c - 0x840 */
3027 volatile u_int32_t SPARE; /* 0x840 - 0x844 */
3030 struct jupiter_reg_map__le_dma_reg_csr {
3031 volatile u_int32_t LE_DMA_MASTER; /* 0x0 - 0x4 */
3032 volatile u_int32_t LE_DMA_TX_CONTROL; /* 0x4 - 0x8 */
3033 volatile u_int32_t LE_DMA_RX_CONTROL; /* 0x8 - 0xc */
3034 volatile u_int32_t LE_DMA_TX_HW; /* 0xc - 0x10 */
3035 volatile u_int32_t LE_DMA_RX_HW; /* 0x10 - 0x14 */
3036 volatile u_int32_t LE_DMA_INT_STATUS; /* 0x14 - 0x18 */
3037 volatile u_int32_t LE_DMA_TX_STATUS; /* 0x18 - 0x1c */
3038 volatile u_int32_t LE_DMA_TX_STATUS_W1TC; /* 0x1c - 0x20 */
3039 volatile u_int32_t LE_DMA_TX_ENABLE; /* 0x20 - 0x24 */
3040 volatile u_int32_t LE_DMA_RX_STATUS; /* 0x24 - 0x28 */
3041 volatile u_int32_t LE_DMA_RX_STATUS_W1TC; /* 0x28 - 0x2c */
3042 volatile u_int32_t LE_DMA_RX_ENABLE; /* 0x2c - 0x30 */
3043 volatile u_int32_t LE_DMA_DEBUG; /* 0x30 - 0x34 */
3044 volatile u_int32_t LE_DMA_DUMMY; /* 0x34 - 0x38 */
3047 struct jupiter_reg_map__le_reg_csr {
3048 volatile u_int32_t LE_PUBLIC_ADDRESS_L; /* 0x0 - 0x4 */
3049 volatile u_int32_t LE_PUBLIC_ADDRESS_U; /* 0x4 - 0x8 */
3050 volatile u_int32_t LE_RANDOM_ADDRESS_L; /* 0x8 - 0xc */
3051 volatile u_int32_t LE_RANDOM_ADDRESS_U; /* 0xc - 0x10 */
3052 volatile u_int32_t LE_DEV_PARAM; /* 0x10 - 0x14 */
3053 volatile u_int32_t COMMAND1; /* 0x14 - 0x18 */
3054 volatile u_int32_t COMMAND2; /* 0x18 - 0x1c */
3055 volatile u_int32_t COMMAND3; /* 0x1c - 0x20 */
3056 volatile u_int32_t COMMAND4; /* 0x20 - 0x24 */
3057 volatile u_int32_t COMMAND5; /* 0x24 - 0x28 */
3058 volatile u_int32_t COMMAND6; /* 0x28 - 0x2c */
3059 volatile u_int32_t COMMAND7; /* 0x2c - 0x30 */
3060 volatile u_int32_t COMMAND8; /* 0x30 - 0x34 */
3061 volatile u_int32_t COMMAND9; /* 0x34 - 0x38 */
3062 volatile u_int32_t COMMAND10; /* 0x38 - 0x3c */
3063 volatile u_int32_t COMMAND11; /* 0x3c - 0x40 */
3064 volatile u_int32_t COMMAND12; /* 0x40 - 0x44 */
3065 volatile u_int32_t COMMAND13; /* 0x44 - 0x48 */
3066 volatile u_int32_t LE_ABORT; /* 0x48 - 0x4c */
3067 volatile u_int32_t LE_RX_STATUS1; /* 0x4c - 0x50 */
3068 volatile u_int32_t LE_RX_STATUS2; /* 0x50 - 0x54 */
3069 volatile u_int32_t LE_RX_STATUS3; /* 0x54 - 0x58 */
3070 volatile u_int32_t LE_RX_STATUS4; /* 0x58 - 0x5c */
3071 volatile u_int32_t LE_RX_STATUS5; /* 0x5c - 0x60 */
3072 volatile u_int32_t LE_RX_STATUS6; /* 0x60 - 0x64 */
3073 volatile u_int32_t LE_RX_STATUS7; /* 0x64 - 0x68 */
3074 volatile u_int32_t LE_RX_STATUS8; /* 0x68 - 0x6c */
3075 volatile u_int32_t LE_RX_STATUS9; /* 0x6c - 0x70 */
3076 volatile u_int32_t LE_INTERRUPT_EN; /* 0x70 - 0x74 */
3077 volatile u_int32_t LE_INTERRUPT; /* 0x74 - 0x78 */
3078 volatile u_int32_t LE_DATAPATH_CNTL; /* 0x78 - 0x7c */
3079 volatile u_int32_t LE_BT_CLOCK0; /* 0x7c - 0x80 */
3080 volatile u_int32_t LE_BT_CLOCK1; /* 0x80 - 0x84 */
3081 volatile u_int32_t LE_SYM_TIME0; /* 0x84 - 0x88 */
3082 volatile u_int32_t LE_SYM_TIME1; /* 0x88 - 0x8c */
3083 volatile u_int32_t LE_TIMER0; /* 0x8c - 0x90 */
3084 volatile u_int32_t LE_TIMER0_FRAME; /* 0x90 - 0x94 */
3085 volatile u_int32_t LE_TIMER1; /* 0x94 - 0x98 */
3086 volatile u_int32_t LE_TIMER1_FRAME; /* 0x98 - 0x9c */
3087 volatile u_int32_t LE_WL_TABLE[256]; /* 0x9c - 0x49c */
3088 volatile u_int32_t LE_TIM; /* 0x49c - 0x4a0 */
3089 volatile u_int32_t TX_ERROR_GENERATION; /* 0x4a0 - 0x4a4 */
3090 volatile u_int32_t LE_FREQ_MAP0; /* 0x4a4 - 0x4a8 */
3091 volatile u_int32_t LE_FREQ_MAP1; /* 0x4a8 - 0x4ac */
3092 volatile u_int32_t LE_FREQ_MAP2; /* 0x4ac - 0x4b0 */
3093 volatile u_int32_t LE_FREQ_MAP3; /* 0x4b0 - 0x4b4 */
3094 volatile u_int32_t LE_FREQ_MAP4; /* 0x4b4 - 0x4b8 */
3095 volatile u_int32_t LE_FREQ_MAP5; /* 0x4b8 - 0x4bc */
3096 volatile u_int32_t LE_FREQ_MAP6; /* 0x4bc - 0x4c0 */
3097 volatile u_int32_t LE_FREQ_MAP7; /* 0x4c0 - 0x4c4 */
3098 volatile u_int32_t LE_FREQ_MAP8; /* 0x4c4 - 0x4c8 */
3099 volatile u_int32_t LE_FREQ_MAP9; /* 0x4c8 - 0x4cc */
3100 volatile u_int32_t LE_DEBUG_CTRL; /* 0x4cc - 0x4d0 */
3101 volatile u_int32_t LE_DEBUG_OBS; /* 0x4d0 - 0x4d4 */
3102 volatile u_int32_t LE_PHY_ERR; /* 0x4d4 - 0x4d8 */
3103 volatile u_int32_t LE_PHY_ERR_0; /* 0x4d8 - 0x4dc */
3104 volatile u_int32_t LE_PHY_ERR_1; /* 0x4dc - 0x4e0 */
3105 volatile u_int32_t LE_PHY_ERR_2; /* 0x4e0 - 0x4e4 */
3106 volatile u_int32_t LE_PHY_ERR_3; /* 0x4e4 - 0x4e8 */
3107 volatile u_int32_t LE_PHY_ERR_4; /* 0x4e8 - 0x4ec */
3108 volatile u_int32_t LE_DUMMY; /* 0x4ec - 0x4f0 */
3111 struct jupiter_reg_map__apb_map_csr {
3112 volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */
3113 struct jupiter_reg_map__rtc_reg_csr rtc; /* 0x4000 - 0x4134 */
3114 volatile char pad__1[0x3ecc]; /* 0x4134 - 0x8000 */
3115 struct jupiter_reg_map__vmc_reg_csr vmc; /* 0x8000 - 0x8620 */
3116 volatile char pad__2[0x39e0]; /* 0x8620 - 0xc000 */
3117 struct jupiter_reg_map__apb_map_csr__uart_reg_csr uart;
3118 /* 0xc000 - 0xc014 */
3119 volatile char pad__3[0x3fec]; /* 0xc014 - 0x10000 */
3120 struct jupiter_reg_map__si_reg_csr si; /* 0x10000 - 0x10018 */
3121 volatile char pad__4[0x3fe8]; /* 0x10018 - 0x14000 */
3122 struct jupiter_reg_map__gpio_reg_csr gpio; /* 0x14000 - 0x14098 */
3123 volatile char pad__5[0x3f68]; /* 0x14098 - 0x18000 */
3124 struct jupiter_reg_map__mbox_reg_csr mbox; /* 0x18000 - 0x1809c */
3125 volatile char pad__6[0x3f64]; /* 0x1809c - 0x1c000 */
3126 struct jupiter_reg_map__lc_dma_reg_csr lc_dma; /* 0x1c000 - 0x1c034 */
3127 volatile char pad__7[0x3fcc]; /* 0x1c034 - 0x20000 */
3128 struct jupiter_reg_map__lc_reg_csr lc; /* 0x20000 - 0x2052c */
3129 volatile char pad__8[0x2ad4]; /* 0x2052c - 0x23000 */
3130 struct jupiter_reg_map__analog_intf_athr_wlan_reg_csr analog;
3131 /* 0x23000 - 0x23a90 */
3132 volatile char pad__9[0x570]; /* 0x23a90 - 0x24000 */
3133 struct jupiter_reg_map__efuse_reg efuse; /* 0x24000 - 0x25f40 */
3134 volatile char pad__10[0xc0]; /* 0x25f40 - 0x26000 */
3135 struct jupiter_reg_map__modem_reg_csr modem; /* 0x26000 - 0x26844 */
3136 volatile char pad__11[0x37bc]; /* 0x26844 - 0x2a000 */
3137 struct jupiter_reg_map__le_dma_reg_csr le_dma; /* 0x2a000 - 0x2a038 */
3138 volatile char pad__12[0x1fc8]; /* 0x2a038 - 0x2c000 */
3139 struct jupiter_reg_map__le_reg_csr le; /* 0x2c000 - 0x2c4f0 */
3143 volatile char pad__0[0x40000]; /* 0x0 - 0x40000 */
3144 struct jupiter_reg_map__apb_map_csr bt_apb_map_block;
3145 /* 0x40000 - 0x6c800 */
3148 struct osprey_reg_map {
3149 struct mac_dma_reg mac_dma_reg_block; /* 0x0 - 0x108 */
3150 volatile char pad__0; /* 0x108 - 0x0 */
3151 struct mac_qcu_reg mac_qcu_reg_block; /* 0x0 - 0x24c */
3152 volatile char pad__1; /* 0x24c - 0x0 */
3153 struct mac_dcu_reg mac_dcu_reg_block; /* 0x0 - 0x7fc */
3154 volatile char pad__2; /* 0x7fc - 0x0 */
3155 struct host_intf_reg host_intf_reg_block; /* 0x0 - 0xf4 */
3156 volatile char pad__3; /* 0xf4 - 0x0 */
3157 struct emulation_misc_regs emulation_misc_reg_block;
3159 volatile char pad__4; /* Osprey: 0x30 - 0x0 */
3160 struct DWC_pcie_dbi_axi DWC_pcie_dbi_axi_block; /* Osprey: 0x0 - 0x818 */
3161 volatile char pad__5; /* 0x818 - 0x0 */
3162 struct rtc_reg rtc_reg_block; /* Osprey: 0x0 - 0x3c, Poseidon: 0x0 - 0x40 */
3163 volatile char pad__6; /* Osprey: 0x3c - 0x0, Poseidon: 0x40 - 0x0 */
3164 struct rtc_sync_reg rtc_sync_reg_block; /* 0x0 - 0x1c */
3165 volatile char pad__7; /* 0x1c - 0x0 */
3166 struct merlin2_0_radio_reg_map merlin2_0_radio_reg_map;
3168 volatile char pad__8; /* 0x9c - 0x0 */
3169 struct analog_intf_reg_csr analog_intf_reg_csr_block;
3171 volatile char pad__9; /* 0x10 - 0x0 */
3172 struct mac_pcu_reg mac_pcu_reg_block; /* 0x0 - 0x8000 */
3173 volatile char pad__10; /* 0x8000 - 0x0 */
3174 struct bb_reg_map bb_reg_block; /* 0x0 - 0x4000 */
3175 volatile char pad__11; /* 0x4000 - 0x0 */
3176 struct svd_reg svd_reg_block; /* 0x0 - 0x2c00 */
3177 volatile char pad__12; /* 0x2c00 - 0x0 */
3178 struct efuse_reg_WLAN efuse_reg_block; /* 0x0 - 0x1f40 */
3179 volatile char pad__13; /* 0x1f40 - 0x0 */
3180 struct radio65_reg radio65_reg_block; /* Osprey: 0x0 - 0xbd8, Poseidon: 0x0 - 0x3d8 */
3181 volatile char pad__14; /* Osprey: 0xbd8 - 0x0, Poseidon: 0x3d8 - 0x0 */
3182 struct pmu_reg pmu_reg_block; /* Osprey: 0x0 - 0x8 */
3183 volatile char pad__15; /* Osprey: 0x8 - 0x0 */
3184 struct pcie_phy_reg_csr pcie_phy_reg_block; /* 0x0 - 0xc */
3185 volatile char pad__16; /* 0xc - 0x0 */
3186 struct wlan_coex_reg wlan_coex_reg_block; /* 0x0 - 0x264 */
3187 volatile char pad__17; /* 0x264 - 0x0 */
3188 struct wlan_bt_glb_reg_pcie glb_reg_block; /* 0x0 - 0x400 */
3189 volatile char pad__18; /* 0x400 - 0x0 */
3190 struct bt_apb_reg bt_apb_reg_block; /* Jupiter: 0x0 - 0x2c800 */
3193 #endif /* __REG_OSPREY_REG_MAP_H__ */