4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include "ena_gen_info.h"
39 /*****************************************************************************/
40 /*****************************************************************************/
42 /* Timeout in micro-sec */
43 #define ADMIN_CMD_TIMEOUT_US (3000000)
45 #define ENA_ASYNC_QUEUE_DEPTH 16
46 #define ENA_ADMIN_QUEUE_DEPTH 32
48 #ifdef ENA_EXTENDED_STATS
50 #define ENA_HISTOGRAM_ACTIVE_MASK_OFFSET 0xF08
51 #define ENA_EXTENDED_STAT_GET_FUNCT(_funct_queue) (_funct_queue & 0xFFFF)
52 #define ENA_EXTENDED_STAT_GET_QUEUE(_funct_queue) (_funct_queue >> 16)
54 #endif /* ENA_EXTENDED_STATS */
55 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \
56 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \
57 | (ENA_COMMON_SPEC_VERSION_MINOR))
59 #define ENA_CTRL_MAJOR 0
60 #define ENA_CTRL_MINOR 0
61 #define ENA_CTRL_SUB_MINOR 1
63 #define MIN_ENA_CTRL_VER \
64 (((ENA_CTRL_MAJOR) << \
65 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
66 ((ENA_CTRL_MINOR) << \
67 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
70 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
71 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
73 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
75 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
77 #define ENA_REGS_ADMIN_INTR_MASK 1
79 /*****************************************************************************/
80 /*****************************************************************************/
81 /*****************************************************************************/
86 /* Abort - canceled by the driver */
91 ena_wait_event_t wait_event;
92 struct ena_admin_acq_entry *user_cqe;
94 enum ena_cmd_status status;
95 /* status from the device */
101 struct ena_com_stats_ctx {
102 struct ena_admin_aq_get_stats_cmd get_cmd;
103 struct ena_admin_acq_get_stats_resp get_resp;
106 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
107 struct ena_common_mem_addr *ena_addr,
110 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
111 ena_trc_err("dma address has more bits that the device supports\n");
112 return ENA_COM_INVAL;
115 ena_addr->mem_addr_low = (u32)addr;
116 ena_addr->mem_addr_high = (u16)((u64)addr >> 32);
121 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
123 struct ena_com_admin_sq *sq = &queue->sq;
124 u16 size = ADMIN_SQ_SIZE(queue->q_depth);
126 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
130 ena_trc_err("memory allocation failed");
131 return ENA_COM_NO_MEM;
143 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
145 struct ena_com_admin_cq *cq = &queue->cq;
146 u16 size = ADMIN_CQ_SIZE(queue->q_depth);
148 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
152 ena_trc_err("memory allocation failed");
153 return ENA_COM_NO_MEM;
162 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
163 struct ena_aenq_handlers *aenq_handlers)
165 struct ena_com_aenq *aenq = &dev->aenq;
166 u32 addr_low, addr_high, aenq_caps;
169 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
170 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
171 ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
176 if (!aenq->entries) {
177 ena_trc_err("memory allocation failed");
178 return ENA_COM_NO_MEM;
181 aenq->head = aenq->q_depth;
184 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
185 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
187 ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
188 ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
191 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
192 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
193 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
194 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
195 ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
197 if (unlikely(!aenq_handlers)) {
198 ena_trc_err("aenq handlers pointer is NULL\n");
199 return ENA_COM_INVAL;
202 aenq->aenq_handlers = aenq_handlers;
207 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue,
208 struct ena_comp_ctx *comp_ctx)
210 comp_ctx->occupied = false;
211 ATOMIC32_DEC(&queue->outstanding_cmds);
214 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
215 u16 command_id, bool capture)
217 if (unlikely(command_id >= queue->q_depth)) {
218 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
219 command_id, queue->q_depth);
223 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
224 ena_trc_err("Completion context is occupied\n");
229 ATOMIC32_INC(&queue->outstanding_cmds);
230 queue->comp_ctx[command_id].occupied = true;
233 return &queue->comp_ctx[command_id];
236 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
237 struct ena_admin_aq_entry *cmd,
238 size_t cmd_size_in_bytes,
239 struct ena_admin_acq_entry *comp,
240 size_t comp_size_in_bytes)
242 struct ena_comp_ctx *comp_ctx;
243 u16 tail_masked, cmd_id;
247 queue_size_mask = admin_queue->q_depth - 1;
249 tail_masked = admin_queue->sq.tail & queue_size_mask;
251 /* In case of queue FULL */
252 cnt = ATOMIC32_READ(&admin_queue->outstanding_cmds);
253 if (cnt >= admin_queue->q_depth) {
254 ena_trc_dbg("admin queue is full.\n");
255 admin_queue->stats.out_of_space++;
256 return ERR_PTR(ENA_COM_NO_SPACE);
259 cmd_id = admin_queue->curr_cmd_id;
261 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
262 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
264 cmd->aq_common_descriptor.command_id |= cmd_id &
265 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
267 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
268 if (unlikely(!comp_ctx))
269 return ERR_PTR(ENA_COM_INVAL);
271 comp_ctx->status = ENA_CMD_SUBMITTED;
272 comp_ctx->comp_size = (u32)comp_size_in_bytes;
273 comp_ctx->user_cqe = comp;
274 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
276 ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
278 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
280 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
283 admin_queue->sq.tail++;
284 admin_queue->stats.submitted_cmd++;
286 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
287 admin_queue->sq.phase = !admin_queue->sq.phase;
289 ENA_DB_SYNC(&admin_queue->sq.mem_handle);
290 ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
291 admin_queue->sq.db_addr);
296 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
298 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
299 struct ena_comp_ctx *comp_ctx;
302 queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
303 if (unlikely(!queue->comp_ctx)) {
304 ena_trc_err("memory allocation failed");
305 return ENA_COM_NO_MEM;
308 for (i = 0; i < queue->q_depth; i++) {
309 comp_ctx = get_comp_ctxt(queue, i, false);
311 ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
317 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
318 struct ena_admin_aq_entry *cmd,
319 size_t cmd_size_in_bytes,
320 struct ena_admin_acq_entry *comp,
321 size_t comp_size_in_bytes)
324 struct ena_comp_ctx *comp_ctx;
326 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
327 if (unlikely(!admin_queue->running_state)) {
328 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
329 return ERR_PTR(ENA_COM_NO_DEVICE);
331 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
335 if (unlikely(IS_ERR(comp_ctx)))
336 admin_queue->running_state = false;
337 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
342 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
343 struct ena_com_create_io_ctx *ctx,
344 struct ena_com_io_sq *io_sq)
349 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
351 io_sq->desc_entry_size =
352 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
353 sizeof(struct ena_eth_io_tx_desc) :
354 sizeof(struct ena_eth_io_rx_desc);
356 size = io_sq->desc_entry_size * io_sq->q_depth;
357 io_sq->bus = ena_dev->bus;
359 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
360 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
362 io_sq->desc_addr.virt_addr,
363 io_sq->desc_addr.phys_addr,
364 io_sq->desc_addr.mem_handle,
367 if (!io_sq->desc_addr.virt_addr) {
368 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
370 io_sq->desc_addr.virt_addr,
371 io_sq->desc_addr.phys_addr,
372 io_sq->desc_addr.mem_handle);
375 if (!io_sq->desc_addr.virt_addr) {
376 ena_trc_err("memory allocation failed");
377 return ENA_COM_NO_MEM;
381 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
382 /* Allocate bounce buffers */
383 io_sq->bounce_buf_ctrl.buffer_size = ena_dev->llq_info.desc_list_entry_size;
384 io_sq->bounce_buf_ctrl.buffers_num = ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
385 io_sq->bounce_buf_ctrl.next_to_use = 0;
387 size = io_sq->bounce_buf_ctrl.buffer_size * io_sq->bounce_buf_ctrl.buffers_num;
389 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
391 io_sq->bounce_buf_ctrl.base_buffer,
394 if (!io_sq->bounce_buf_ctrl.base_buffer)
395 io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
397 if (!io_sq->bounce_buf_ctrl.base_buffer) {
398 ena_trc_err("bounce buffer memory allocation failed");
399 return ENA_COM_NO_MEM;
402 memcpy(&io_sq->llq_info, &ena_dev->llq_info, sizeof(io_sq->llq_info));
404 /* Initiate the first bounce buffer */
405 io_sq->llq_buf_ctrl.curr_bounce_buf =
406 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
407 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
408 0x0, io_sq->llq_info.desc_list_entry_size);
409 io_sq->llq_buf_ctrl.descs_left_in_line =
410 io_sq->llq_info.descs_num_before_header;
414 io_sq->next_to_comp = 0;
420 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
421 struct ena_com_create_io_ctx *ctx,
422 struct ena_com_io_cq *io_cq)
427 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
429 /* Use the basic completion descriptor for Rx */
430 io_cq->cdesc_entry_size_in_bytes =
431 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
432 sizeof(struct ena_eth_io_tx_cdesc) :
433 sizeof(struct ena_eth_io_rx_cdesc_base);
435 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
436 io_cq->bus = ena_dev->bus;
438 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
440 io_cq->cdesc_addr.virt_addr,
441 io_cq->cdesc_addr.phys_addr,
442 io_cq->cdesc_addr.mem_handle,
445 if (!io_cq->cdesc_addr.virt_addr) {
446 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
448 io_cq->cdesc_addr.virt_addr,
449 io_cq->cdesc_addr.phys_addr,
450 io_cq->cdesc_addr.mem_handle);
453 if (!io_cq->cdesc_addr.virt_addr) {
454 ena_trc_err("memory allocation failed");
455 return ENA_COM_NO_MEM;
464 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
465 struct ena_admin_acq_entry *cqe)
467 struct ena_comp_ctx *comp_ctx;
470 cmd_id = cqe->acq_common_descriptor.command &
471 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
473 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
474 if (unlikely(!comp_ctx)) {
475 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
476 admin_queue->running_state = false;
480 comp_ctx->status = ENA_CMD_COMPLETED;
481 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
483 if (comp_ctx->user_cqe)
484 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
486 if (!admin_queue->polling)
487 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
490 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
492 struct ena_admin_acq_entry *cqe = NULL;
497 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
498 phase = admin_queue->cq.phase;
500 cqe = &admin_queue->cq.entries[head_masked];
502 /* Go over all the completions */
503 while ((cqe->acq_common_descriptor.flags &
504 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
505 /* Do not read the rest of the completion entry before the
506 * phase bit was validated
509 ena_com_handle_single_admin_completion(admin_queue, cqe);
513 if (unlikely(head_masked == admin_queue->q_depth)) {
518 cqe = &admin_queue->cq.entries[head_masked];
521 admin_queue->cq.head += comp_num;
522 admin_queue->cq.phase = phase;
523 admin_queue->sq.head += comp_num;
524 admin_queue->stats.completed_cmd += comp_num;
527 static int ena_com_comp_status_to_errno(u8 comp_status)
529 if (unlikely(comp_status != 0))
530 ena_trc_err("admin command failed[%u]\n", comp_status);
532 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR))
533 return ENA_COM_INVAL;
535 switch (comp_status) {
536 case ENA_ADMIN_SUCCESS:
538 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
539 return ENA_COM_NO_MEM;
540 case ENA_ADMIN_UNSUPPORTED_OPCODE:
541 return ENA_COM_UNSUPPORTED;
542 case ENA_ADMIN_BAD_OPCODE:
543 case ENA_ADMIN_MALFORMED_REQUEST:
544 case ENA_ADMIN_ILLEGAL_PARAMETER:
545 case ENA_ADMIN_UNKNOWN_ERROR:
546 return ENA_COM_INVAL;
552 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
553 struct ena_com_admin_queue *admin_queue)
555 unsigned long flags, timeout;
558 timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
561 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
562 ena_com_handle_admin_completion(admin_queue);
563 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
565 if (comp_ctx->status != ENA_CMD_SUBMITTED)
568 if (ENA_TIME_EXPIRE(timeout)) {
569 ena_trc_err("Wait for completion (polling) timeout\n");
570 /* ENA didn't have any completion */
571 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
572 admin_queue->stats.no_completion++;
573 admin_queue->running_state = false;
574 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
576 ret = ENA_COM_TIMER_EXPIRED;
583 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
584 ena_trc_err("Command was aborted\n");
585 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
586 admin_queue->stats.aborted_cmd++;
587 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
588 ret = ENA_COM_NO_DEVICE;
592 ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
593 "Invalid comp status %d\n", comp_ctx->status);
595 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
597 comp_ctxt_release(admin_queue, comp_ctx);
601 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
602 struct ena_admin_feature_llq_desc *llq_desc)
604 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
606 memset(llq_info, 0, sizeof(*llq_info));
608 switch (llq_desc->header_location_ctrl) {
609 case ENA_ADMIN_INLINE_HEADER:
610 llq_info->inline_header = true;
612 case ENA_ADMIN_HEADER_RING:
613 llq_info->inline_header = false;
616 ena_trc_err("Invalid header location control\n");
620 switch (llq_desc->entry_size_ctrl) {
621 case ENA_ADMIN_LIST_ENTRY_SIZE_128B:
622 llq_info->desc_list_entry_size = 128;
624 case ENA_ADMIN_LIST_ENTRY_SIZE_192B:
625 llq_info->desc_list_entry_size = 192;
627 case ENA_ADMIN_LIST_ENTRY_SIZE_256B:
628 llq_info->desc_list_entry_size = 256;
631 ena_trc_err("Invalid entry_size_ctrl %d\n",
632 llq_desc->entry_size_ctrl);
636 if ((llq_info->desc_list_entry_size & 0x7)) {
637 /* The desc list entry size should be whole multiply of 8
638 * This requirement comes from __iowrite64_copy()
640 ena_trc_err("illegal entry size %d\n",
641 llq_info->desc_list_entry_size);
645 if (llq_info->inline_header) {
646 llq_info->desc_stride_ctrl = llq_desc->descriptors_stride_ctrl;
647 if ((llq_info->desc_stride_ctrl != ENA_ADMIN_SINGLE_DESC_PER_ENTRY) &&
648 (llq_info->desc_stride_ctrl != ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)) {
649 ena_trc_err("Invalid desc_stride_ctrl %d\n",
650 llq_info->desc_stride_ctrl);
654 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
657 if (llq_info->desc_stride_ctrl == ENA_ADMIN_SINGLE_DESC_PER_ENTRY)
658 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
659 sizeof(struct ena_eth_io_tx_desc);
661 llq_info->descs_per_entry = 1;
663 llq_info->descs_num_before_header = llq_desc->desc_num_before_header_ctrl;
670 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
671 struct ena_com_admin_queue *admin_queue)
676 ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
677 admin_queue->completion_timeout);
679 /* In case the command wasn't completed find out the root cause.
680 * There might be 2 kinds of errors
681 * 1) No completion (timeout reached)
682 * 2) There is completion but the device didn't get any msi-x interrupt.
684 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
685 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
686 ena_com_handle_admin_completion(admin_queue);
687 admin_queue->stats.no_completion++;
688 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
690 if (comp_ctx->status == ENA_CMD_COMPLETED)
691 ena_trc_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n",
692 comp_ctx->cmd_opcode);
694 ena_trc_err("The ena device doesn't send any completion for the admin cmd %d status %d\n",
695 comp_ctx->cmd_opcode, comp_ctx->status);
697 admin_queue->running_state = false;
698 ret = ENA_COM_TIMER_EXPIRED;
702 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
704 comp_ctxt_release(admin_queue, comp_ctx);
708 /* This method read the hardware device register through posting writes
709 * and waiting for response
710 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
712 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
714 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
715 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
716 mmio_read->read_resp;
717 u32 mmio_read_reg, ret, i;
719 u32 timeout = mmio_read->reg_read_to;
724 timeout = ENA_REG_READ_TIMEOUT;
726 /* If readless is disabled, perform regular read */
727 if (!mmio_read->readless_supported)
728 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
730 ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
731 mmio_read->seq_num++;
733 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
734 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
735 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
736 mmio_read_reg |= mmio_read->seq_num &
737 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
739 /* make sure read_resp->req_id get updated before the hw can write
744 ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
746 for (i = 0; i < timeout; i++) {
747 if (read_resp->req_id == mmio_read->seq_num)
753 if (unlikely(i == timeout)) {
754 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
759 ret = ENA_MMIO_READ_TIMEOUT;
763 if (read_resp->reg_off != offset) {
764 ena_trc_err("Read failure: wrong offset provided");
765 ret = ENA_MMIO_READ_TIMEOUT;
767 ret = read_resp->reg_val;
770 ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
775 /* There are two types to wait for completion.
776 * Polling mode - wait until the completion is available.
777 * Async mode - wait on wait queue until the completion is ready
778 * (or the timeout expired).
779 * It is expected that the IRQ called ena_com_handle_admin_completion
780 * to mark the completions.
782 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
783 struct ena_com_admin_queue *admin_queue)
785 if (admin_queue->polling)
786 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
789 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
793 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
794 struct ena_com_io_sq *io_sq)
796 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
797 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
798 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
802 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
804 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
805 direction = ENA_ADMIN_SQ_DIRECTION_TX;
807 direction = ENA_ADMIN_SQ_DIRECTION_RX;
809 destroy_cmd.sq.sq_identity |= (direction <<
810 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
811 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
813 destroy_cmd.sq.sq_idx = io_sq->idx;
814 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
816 ret = ena_com_execute_admin_command(admin_queue,
817 (struct ena_admin_aq_entry *)&destroy_cmd,
819 (struct ena_admin_acq_entry *)&destroy_resp,
820 sizeof(destroy_resp));
822 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
823 ena_trc_err("failed to destroy io sq error: %d\n", ret);
828 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
829 struct ena_com_io_sq *io_sq,
830 struct ena_com_io_cq *io_cq)
834 if (io_cq->cdesc_addr.virt_addr) {
835 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
837 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
839 io_cq->cdesc_addr.virt_addr,
840 io_cq->cdesc_addr.phys_addr,
841 io_cq->cdesc_addr.mem_handle);
843 io_cq->cdesc_addr.virt_addr = NULL;
846 if (io_sq->desc_addr.virt_addr) {
847 size = io_sq->desc_entry_size * io_sq->q_depth;
849 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
851 io_sq->desc_addr.virt_addr,
852 io_sq->desc_addr.phys_addr,
853 io_sq->desc_addr.mem_handle);
855 io_sq->desc_addr.virt_addr = NULL;
858 if (io_sq->bounce_buf_ctrl.base_buffer) {
859 size = io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
860 ENA_MEM_FREE(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
861 io_sq->bounce_buf_ctrl.base_buffer = NULL;
865 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
870 for (i = 0; i < timeout; i++) {
871 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
873 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
874 ena_trc_err("Reg read timeout occurred\n");
875 return ENA_COM_TIMER_EXPIRED;
878 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
882 /* The resolution of the timeout is 100ms */
886 return ENA_COM_TIMER_EXPIRED;
889 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
890 enum ena_admin_aq_feature_id feature_id)
892 u32 feature_mask = 1 << feature_id;
894 /* Device attributes is always supported */
895 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
896 !(ena_dev->supported_features & feature_mask))
902 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
903 struct ena_admin_get_feat_resp *get_resp,
904 enum ena_admin_aq_feature_id feature_id,
905 dma_addr_t control_buf_dma_addr,
906 u32 control_buff_size)
908 struct ena_com_admin_queue *admin_queue;
909 struct ena_admin_get_feat_cmd get_cmd;
912 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
913 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
914 return ENA_COM_UNSUPPORTED;
917 memset(&get_cmd, 0x0, sizeof(get_cmd));
918 admin_queue = &ena_dev->admin_queue;
920 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
922 if (control_buff_size)
923 get_cmd.aq_common_descriptor.flags =
924 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
926 get_cmd.aq_common_descriptor.flags = 0;
928 ret = ena_com_mem_addr_set(ena_dev,
929 &get_cmd.control_buffer.address,
930 control_buf_dma_addr);
932 ena_trc_err("memory address set failed\n");
936 get_cmd.control_buffer.length = control_buff_size;
938 get_cmd.feat_common.feature_id = feature_id;
940 ret = ena_com_execute_admin_command(admin_queue,
941 (struct ena_admin_aq_entry *)
944 (struct ena_admin_acq_entry *)
949 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
955 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
956 struct ena_admin_get_feat_resp *get_resp,
957 enum ena_admin_aq_feature_id feature_id)
959 return ena_com_get_feature_ex(ena_dev,
966 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
968 struct ena_rss *rss = &ena_dev->rss;
970 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
971 sizeof(*rss->hash_key),
973 rss->hash_key_dma_addr,
974 rss->hash_key_mem_handle);
976 if (unlikely(!rss->hash_key))
977 return ENA_COM_NO_MEM;
982 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
984 struct ena_rss *rss = &ena_dev->rss;
987 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
988 sizeof(*rss->hash_key),
990 rss->hash_key_dma_addr,
991 rss->hash_key_mem_handle);
992 rss->hash_key = NULL;
995 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
997 struct ena_rss *rss = &ena_dev->rss;
999 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1000 sizeof(*rss->hash_ctrl),
1002 rss->hash_ctrl_dma_addr,
1003 rss->hash_ctrl_mem_handle);
1005 if (unlikely(!rss->hash_ctrl))
1006 return ENA_COM_NO_MEM;
1011 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1013 struct ena_rss *rss = &ena_dev->rss;
1016 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1017 sizeof(*rss->hash_ctrl),
1019 rss->hash_ctrl_dma_addr,
1020 rss->hash_ctrl_mem_handle);
1021 rss->hash_ctrl = NULL;
1024 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1027 struct ena_rss *rss = &ena_dev->rss;
1028 struct ena_admin_get_feat_resp get_resp;
1032 ret = ena_com_get_feature(ena_dev, &get_resp,
1033 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
1037 if ((get_resp.u.ind_table.min_size > log_size) ||
1038 (get_resp.u.ind_table.max_size < log_size)) {
1039 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1041 1 << get_resp.u.ind_table.min_size,
1042 1 << get_resp.u.ind_table.max_size);
1043 return ENA_COM_INVAL;
1046 tbl_size = (1ULL << log_size) *
1047 sizeof(struct ena_admin_rss_ind_table_entry);
1049 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1052 rss->rss_ind_tbl_dma_addr,
1053 rss->rss_ind_tbl_mem_handle);
1054 if (unlikely(!rss->rss_ind_tbl))
1057 tbl_size = (1ULL << log_size) * sizeof(u16);
1058 rss->host_rss_ind_tbl =
1059 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1060 if (unlikely(!rss->host_rss_ind_tbl))
1063 rss->tbl_log_size = log_size;
1068 tbl_size = (1ULL << log_size) *
1069 sizeof(struct ena_admin_rss_ind_table_entry);
1071 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1074 rss->rss_ind_tbl_dma_addr,
1075 rss->rss_ind_tbl_mem_handle);
1076 rss->rss_ind_tbl = NULL;
1078 rss->tbl_log_size = 0;
1079 return ENA_COM_NO_MEM;
1082 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1084 struct ena_rss *rss = &ena_dev->rss;
1085 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1086 sizeof(struct ena_admin_rss_ind_table_entry);
1088 if (rss->rss_ind_tbl)
1089 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1092 rss->rss_ind_tbl_dma_addr,
1093 rss->rss_ind_tbl_mem_handle);
1094 rss->rss_ind_tbl = NULL;
1096 if (rss->host_rss_ind_tbl)
1097 ENA_MEM_FREE(ena_dev->dmadev, rss->host_rss_ind_tbl);
1098 rss->host_rss_ind_tbl = NULL;
1101 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1102 struct ena_com_io_sq *io_sq, u16 cq_idx)
1104 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1105 struct ena_admin_aq_create_sq_cmd create_cmd;
1106 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1110 memset(&create_cmd, 0x0, sizeof(create_cmd));
1112 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1114 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1115 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1117 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1119 create_cmd.sq_identity |= (direction <<
1120 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1121 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1123 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1124 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1126 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1127 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1128 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1130 create_cmd.sq_caps_3 |=
1131 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1133 create_cmd.cq_idx = cq_idx;
1134 create_cmd.sq_depth = io_sq->q_depth;
1136 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1137 ret = ena_com_mem_addr_set(ena_dev,
1139 io_sq->desc_addr.phys_addr);
1140 if (unlikely(ret)) {
1141 ena_trc_err("memory address set failed\n");
1146 ret = ena_com_execute_admin_command(admin_queue,
1147 (struct ena_admin_aq_entry *)&create_cmd,
1149 (struct ena_admin_acq_entry *)&cmd_completion,
1150 sizeof(cmd_completion));
1151 if (unlikely(ret)) {
1152 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1156 io_sq->idx = cmd_completion.sq_idx;
1158 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1159 (uintptr_t)cmd_completion.sq_doorbell_offset);
1161 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1162 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1163 + cmd_completion.llq_headers_offset);
1165 io_sq->desc_addr.pbuf_dev_addr =
1166 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1167 cmd_completion.llq_descriptors_offset);
1170 ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1175 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1177 struct ena_rss *rss = &ena_dev->rss;
1178 struct ena_com_io_sq *io_sq;
1182 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1183 qid = rss->host_rss_ind_tbl[i];
1184 if (qid >= ENA_TOTAL_NUM_QUEUES)
1185 return ENA_COM_INVAL;
1187 io_sq = &ena_dev->io_sq_queues[qid];
1189 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1190 return ENA_COM_INVAL;
1192 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1198 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev)
1200 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 };
1201 struct ena_rss *rss = &ena_dev->rss;
1205 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++)
1206 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i;
1208 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1209 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES)
1210 return ENA_COM_INVAL;
1211 idx = (u8)rss->rss_ind_tbl[i].cq_idx;
1213 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES)
1214 return ENA_COM_INVAL;
1216 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx];
1222 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev)
1226 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS;
1228 ena_dev->intr_moder_tbl = ENA_MEM_ALLOC(ena_dev->dmadev, size);
1229 if (!ena_dev->intr_moder_tbl)
1230 return ENA_COM_NO_MEM;
1232 ena_com_config_default_interrupt_moderation_table(ena_dev);
1237 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1238 u16 intr_delay_resolution)
1240 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
1243 if (!intr_delay_resolution) {
1244 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1245 intr_delay_resolution = 1;
1247 ena_dev->intr_delay_resolution = intr_delay_resolution;
1250 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++)
1251 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution;
1254 ena_dev->intr_moder_tx_interval /= intr_delay_resolution;
1257 /*****************************************************************************/
1258 /******************************* API ******************************/
1259 /*****************************************************************************/
1261 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1262 struct ena_admin_aq_entry *cmd,
1264 struct ena_admin_acq_entry *comp,
1267 struct ena_comp_ctx *comp_ctx;
1270 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1272 if (unlikely(IS_ERR(comp_ctx))) {
1273 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1274 ena_trc_dbg("Failed to submit command [%ld]\n",
1277 ena_trc_err("Failed to submit command [%ld]\n",
1280 return PTR_ERR(comp_ctx);
1283 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1284 if (unlikely(ret)) {
1285 if (admin_queue->running_state)
1286 ena_trc_err("Failed to process command. ret = %d\n",
1289 ena_trc_dbg("Failed to process command. ret = %d\n",
1295 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1296 struct ena_com_io_cq *io_cq)
1298 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1299 struct ena_admin_aq_create_cq_cmd create_cmd;
1300 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1303 memset(&create_cmd, 0x0, sizeof(create_cmd));
1305 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1307 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1308 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1309 create_cmd.cq_caps_1 |=
1310 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1312 create_cmd.msix_vector = io_cq->msix_vector;
1313 create_cmd.cq_depth = io_cq->q_depth;
1315 ret = ena_com_mem_addr_set(ena_dev,
1317 io_cq->cdesc_addr.phys_addr);
1318 if (unlikely(ret)) {
1319 ena_trc_err("memory address set failed\n");
1323 ret = ena_com_execute_admin_command(admin_queue,
1324 (struct ena_admin_aq_entry *)&create_cmd,
1326 (struct ena_admin_acq_entry *)&cmd_completion,
1327 sizeof(cmd_completion));
1328 if (unlikely(ret)) {
1329 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1333 io_cq->idx = cmd_completion.cq_idx;
1335 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1336 cmd_completion.cq_interrupt_unmask_register_offset);
1338 if (cmd_completion.cq_head_db_register_offset)
1339 io_cq->cq_head_db_reg =
1340 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1341 cmd_completion.cq_head_db_register_offset);
1343 if (cmd_completion.numa_node_register_offset)
1344 io_cq->numa_node_cfg_reg =
1345 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1346 cmd_completion.numa_node_register_offset);
1348 ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1353 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1354 struct ena_com_io_sq **io_sq,
1355 struct ena_com_io_cq **io_cq)
1357 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1358 ena_trc_err("Invalid queue number %d but the max is %d\n",
1359 qid, ENA_TOTAL_NUM_QUEUES);
1360 return ENA_COM_INVAL;
1363 *io_sq = &ena_dev->io_sq_queues[qid];
1364 *io_cq = &ena_dev->io_cq_queues[qid];
1369 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1371 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1372 struct ena_comp_ctx *comp_ctx;
1375 if (!admin_queue->comp_ctx)
1378 for (i = 0; i < admin_queue->q_depth; i++) {
1379 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1380 if (unlikely(!comp_ctx))
1383 comp_ctx->status = ENA_CMD_ABORTED;
1385 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1389 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1391 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1392 unsigned long flags;
1394 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1395 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1396 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1398 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1400 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1403 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1404 struct ena_com_io_cq *io_cq)
1406 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1407 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1408 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1411 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1413 destroy_cmd.cq_idx = io_cq->idx;
1414 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1416 ret = ena_com_execute_admin_command(admin_queue,
1417 (struct ena_admin_aq_entry *)&destroy_cmd,
1418 sizeof(destroy_cmd),
1419 (struct ena_admin_acq_entry *)&destroy_resp,
1420 sizeof(destroy_resp));
1422 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1423 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1428 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1430 return ena_dev->admin_queue.running_state;
1433 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1435 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1436 unsigned long flags;
1438 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1439 ena_dev->admin_queue.running_state = state;
1440 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1443 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1445 u16 depth = ena_dev->aenq.q_depth;
1447 ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1449 /* Init head_db to mark that all entries in the queue
1450 * are initially available
1452 ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1455 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1457 struct ena_com_admin_queue *admin_queue;
1458 struct ena_admin_set_feat_cmd cmd;
1459 struct ena_admin_set_feat_resp resp;
1460 struct ena_admin_get_feat_resp get_resp;
1463 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG);
1465 ena_trc_info("Can't get aenq configuration\n");
1469 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1470 ena_trc_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n",
1471 get_resp.u.aenq.supported_groups,
1473 return ENA_COM_UNSUPPORTED;
1476 memset(&cmd, 0x0, sizeof(cmd));
1477 admin_queue = &ena_dev->admin_queue;
1479 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1480 cmd.aq_common_descriptor.flags = 0;
1481 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1482 cmd.u.aenq.enabled_groups = groups_flag;
1484 ret = ena_com_execute_admin_command(admin_queue,
1485 (struct ena_admin_aq_entry *)&cmd,
1487 (struct ena_admin_acq_entry *)&resp,
1491 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1496 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1498 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1501 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1502 ena_trc_err("Reg read timeout occurred\n");
1503 return ENA_COM_TIMER_EXPIRED;
1506 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1507 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1509 ena_trc_dbg("ENA dma width: %d\n", width);
1511 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1512 ena_trc_err("DMA width illegal value: %d\n", width);
1513 return ENA_COM_INVAL;
1516 ena_dev->dma_addr_bits = width;
1521 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1525 u32 ctrl_ver_masked;
1527 /* Make sure the ENA version and the controller version are at least
1528 * as the driver expects
1530 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1531 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1532 ENA_REGS_CONTROLLER_VERSION_OFF);
1534 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1535 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1536 ena_trc_err("Reg read timeout occurred\n");
1537 return ENA_COM_TIMER_EXPIRED;
1540 ena_trc_info("ena device version: %d.%d\n",
1541 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1542 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1543 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1545 if (ver < MIN_ENA_VER) {
1546 ena_trc_err("ENA version is lower than the minimal version the driver supports\n");
1550 ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1551 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1552 >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1553 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1554 >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1555 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1556 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1557 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1560 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1561 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1562 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1564 /* Validate the ctrl version without the implementation ID */
1565 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1566 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1573 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1575 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1576 struct ena_com_admin_cq *cq = &admin_queue->cq;
1577 struct ena_com_admin_sq *sq = &admin_queue->sq;
1578 struct ena_com_aenq *aenq = &ena_dev->aenq;
1581 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1583 ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1585 if (admin_queue->comp_ctx)
1586 ENA_MEM_FREE(ena_dev->dmadev, admin_queue->comp_ctx);
1587 admin_queue->comp_ctx = NULL;
1588 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1590 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1591 sq->dma_addr, sq->mem_handle);
1594 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1596 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1597 cq->dma_addr, cq->mem_handle);
1600 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1601 if (ena_dev->aenq.entries)
1602 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1603 aenq->dma_addr, aenq->mem_handle);
1604 aenq->entries = NULL;
1607 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1612 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1614 ENA_REG_WRITE32(ena_dev->bus, mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1615 ena_dev->admin_queue.polling = polling;
1618 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1620 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1622 ENA_SPINLOCK_INIT(mmio_read->lock);
1623 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1624 sizeof(*mmio_read->read_resp),
1625 mmio_read->read_resp,
1626 mmio_read->read_resp_dma_addr,
1627 mmio_read->read_resp_mem_handle);
1628 if (unlikely(!mmio_read->read_resp))
1629 return ENA_COM_NO_MEM;
1631 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1633 mmio_read->read_resp->req_id = 0x0;
1634 mmio_read->seq_num = 0x0;
1635 mmio_read->readless_supported = true;
1640 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1642 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1644 mmio_read->readless_supported = readless_supported;
1647 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1649 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1651 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1652 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1654 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1655 sizeof(*mmio_read->read_resp),
1656 mmio_read->read_resp,
1657 mmio_read->read_resp_dma_addr,
1658 mmio_read->read_resp_mem_handle);
1660 mmio_read->read_resp = NULL;
1662 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1665 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1667 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1668 u32 addr_low, addr_high;
1670 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1671 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1673 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1674 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1677 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1678 struct ena_aenq_handlers *aenq_handlers,
1681 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1682 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1686 ena_trc_info("ena_defs : Version:[%s] Build date [%s]",
1687 ENA_GEN_COMMIT, ENA_GEN_DATE);
1689 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1691 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1692 ena_trc_err("Reg read timeout occurred\n");
1693 return ENA_COM_TIMER_EXPIRED;
1696 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1697 ena_trc_err("Device isn't ready, abort com init\n");
1698 return ENA_COM_NO_DEVICE;
1701 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1703 admin_queue->bus = ena_dev->bus;
1704 admin_queue->q_dmadev = ena_dev->dmadev;
1705 admin_queue->polling = false;
1706 admin_queue->curr_cmd_id = 0;
1708 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1711 ENA_SPINLOCK_INIT(admin_queue->q_lock);
1713 ret = ena_com_init_comp_ctxt(admin_queue);
1717 ret = ena_com_admin_init_sq(admin_queue);
1721 ret = ena_com_admin_init_cq(admin_queue);
1725 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1726 ENA_REGS_AQ_DB_OFF);
1728 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1729 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1731 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1732 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1734 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1735 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1737 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1738 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1741 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1742 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1743 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1744 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1747 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1748 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1749 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1750 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1752 ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1753 ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1754 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1758 admin_queue->running_state = true;
1762 ena_com_admin_destroy(ena_dev);
1767 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1768 struct ena_com_create_io_ctx *ctx)
1770 struct ena_com_io_sq *io_sq;
1771 struct ena_com_io_cq *io_cq;
1774 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1775 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1776 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1777 return ENA_COM_INVAL;
1780 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1781 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1783 memset(io_sq, 0x0, sizeof(*io_sq));
1784 memset(io_cq, 0x0, sizeof(*io_cq));
1787 io_cq->q_depth = ctx->queue_size;
1788 io_cq->direction = ctx->direction;
1789 io_cq->qid = ctx->qid;
1791 io_cq->msix_vector = ctx->msix_vector;
1793 io_sq->q_depth = ctx->queue_size;
1794 io_sq->direction = ctx->direction;
1795 io_sq->qid = ctx->qid;
1797 io_sq->mem_queue_type = ctx->mem_queue_type;
1799 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1800 /* header length is limited to 8 bits */
1801 io_sq->tx_max_header_size =
1802 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1804 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1807 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1811 ret = ena_com_create_io_cq(ena_dev, io_cq);
1815 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1822 ena_com_destroy_io_cq(ena_dev, io_cq);
1824 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1828 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1830 struct ena_com_io_sq *io_sq;
1831 struct ena_com_io_cq *io_cq;
1833 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1834 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1835 qid, ENA_TOTAL_NUM_QUEUES);
1839 io_sq = &ena_dev->io_sq_queues[qid];
1840 io_cq = &ena_dev->io_cq_queues[qid];
1842 ena_com_destroy_io_sq(ena_dev, io_sq);
1843 ena_com_destroy_io_cq(ena_dev, io_cq);
1845 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1848 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1849 struct ena_admin_get_feat_resp *resp)
1851 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG);
1854 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1855 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1857 struct ena_admin_get_feat_resp get_resp;
1860 rc = ena_com_get_feature(ena_dev, &get_resp,
1861 ENA_ADMIN_DEVICE_ATTRIBUTES);
1865 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1866 sizeof(get_resp.u.dev_attr));
1867 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1869 rc = ena_com_get_feature(ena_dev, &get_resp,
1870 ENA_ADMIN_MAX_QUEUES_NUM);
1874 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1875 sizeof(get_resp.u.max_queue));
1876 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size;
1878 rc = ena_com_get_feature(ena_dev, &get_resp,
1879 ENA_ADMIN_AENQ_CONFIG);
1883 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
1884 sizeof(get_resp.u.aenq));
1886 rc = ena_com_get_feature(ena_dev, &get_resp,
1887 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
1891 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
1892 sizeof(get_resp.u.offload));
1894 /* Driver hints isn't mandatory admin command. So in case the
1895 * command isn't supported set driver hints to 0
1897 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS);
1900 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
1901 sizeof(get_resp.u.hw_hints));
1902 else if (rc == ENA_COM_UNSUPPORTED)
1903 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
1907 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ);
1909 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
1910 sizeof(get_resp.u.llq));
1911 else if (rc == ENA_COM_UNSUPPORTED)
1912 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
1919 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
1921 ena_com_handle_admin_completion(&ena_dev->admin_queue);
1924 /* ena_handle_specific_aenq_event:
1925 * return the handler that is relevant to the specific event group
1927 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
1930 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
1932 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
1933 return aenq_handlers->handlers[group];
1935 return aenq_handlers->unimplemented_handler;
1938 /* ena_aenq_intr_handler:
1939 * handles the aenq incoming events.
1940 * pop events from the queue and apply the specific handler
1942 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
1944 struct ena_admin_aenq_entry *aenq_e;
1945 struct ena_admin_aenq_common_desc *aenq_common;
1946 struct ena_com_aenq *aenq = &dev->aenq;
1947 ena_aenq_handler handler_cb;
1948 unsigned long long timestamp;
1949 u16 masked_head, processed = 0;
1952 masked_head = aenq->head & (aenq->q_depth - 1);
1953 phase = aenq->phase;
1954 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
1955 aenq_common = &aenq_e->aenq_common_desc;
1957 /* Go over all the events */
1958 while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) ==
1960 timestamp = (unsigned long long)aenq_common->timestamp_low |
1961 ((unsigned long long)aenq_common->timestamp_high << 32);
1962 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n",
1964 aenq_common->syndrom,
1967 /* Handle specific event*/
1968 handler_cb = ena_com_get_specific_aenq_cb(dev,
1969 aenq_common->group);
1970 handler_cb(data, aenq_e); /* call the actual event handler*/
1972 /* Get next event entry */
1976 if (unlikely(masked_head == aenq->q_depth)) {
1980 aenq_e = &aenq->entries[masked_head];
1981 aenq_common = &aenq_e->aenq_common_desc;
1984 aenq->head += processed;
1985 aenq->phase = phase;
1987 /* Don't update aenq doorbell if there weren't any processed events */
1991 /* write the aenq doorbell after all AENQ descriptors were read */
1993 ENA_REG_WRITE32(dev->bus, (u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1995 #ifdef ENA_EXTENDED_STATS
1997 * Sets the function Idx and Queue Idx to be used for
1998 * get full statistics feature
2001 int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
2005 /* Function & Queue is acquired from user in the following format :
2006 * Bottom Half word: funct
2007 * Top Half Word: queue
2009 ena_dev->stats_func = ENA_EXTENDED_STAT_GET_FUNCT(func_queue);
2010 ena_dev->stats_queue = ENA_EXTENDED_STAT_GET_QUEUE(func_queue);
2015 #endif /* ENA_EXTENDED_STATS */
2017 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2018 enum ena_regs_reset_reason_types reset_reason)
2020 u32 stat, timeout, cap, reset_val;
2023 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2024 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2026 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2027 (cap == ENA_MMIO_READ_TIMEOUT))) {
2028 ena_trc_err("Reg read32 timeout occurred\n");
2029 return ENA_COM_TIMER_EXPIRED;
2032 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2033 ena_trc_err("Device isn't ready, can't reset device\n");
2034 return ENA_COM_INVAL;
2037 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2038 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2040 ena_trc_err("Invalid timeout value\n");
2041 return ENA_COM_INVAL;
2045 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2046 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2047 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2048 ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2050 /* Write again the MMIO read request address */
2051 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2053 rc = wait_for_reset_state(ena_dev, timeout,
2054 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2056 ena_trc_err("Reset indication didn't turn on\n");
2061 ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2062 rc = wait_for_reset_state(ena_dev, timeout, 0);
2064 ena_trc_err("Reset indication didn't turn off\n");
2068 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2069 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2071 /* the resolution of timeout reg is 100ms */
2072 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2074 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2079 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2080 struct ena_com_stats_ctx *ctx,
2081 enum ena_admin_get_stats_type type)
2083 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2084 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2085 struct ena_com_admin_queue *admin_queue;
2088 admin_queue = &ena_dev->admin_queue;
2090 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2091 get_cmd->aq_common_descriptor.flags = 0;
2092 get_cmd->type = type;
2094 ret = ena_com_execute_admin_command(admin_queue,
2095 (struct ena_admin_aq_entry *)get_cmd,
2097 (struct ena_admin_acq_entry *)get_resp,
2101 ena_trc_err("Failed to get stats. error: %d\n", ret);
2106 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2107 struct ena_admin_basic_stats *stats)
2109 struct ena_com_stats_ctx ctx;
2112 memset(&ctx, 0x0, sizeof(ctx));
2113 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2114 if (likely(ret == 0))
2115 memcpy(stats, &ctx.get_resp.basic_stats,
2116 sizeof(ctx.get_resp.basic_stats));
2120 #ifdef ENA_EXTENDED_STATS
2122 int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
2125 struct ena_com_stats_ctx ctx;
2126 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx.get_cmd;
2127 ena_mem_handle_t mem_handle;
2129 dma_addr_t phys_addr;
2132 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, len,
2133 virt_addr, phys_addr, mem_handle);
2135 ret = ENA_COM_NO_MEM;
2138 memset(&ctx, 0x0, sizeof(ctx));
2139 ret = ena_com_mem_addr_set(ena_dev,
2140 &get_cmd->u.control_buffer.address,
2142 if (unlikely(ret)) {
2143 ena_trc_err("memory address set failed\n");
2146 get_cmd->u.control_buffer.length = len;
2148 get_cmd->device_id = ena_dev->stats_func;
2149 get_cmd->queue_idx = ena_dev->stats_queue;
2151 ret = ena_get_dev_stats(ena_dev, &ctx,
2152 ENA_ADMIN_GET_STATS_TYPE_EXTENDED);
2154 goto free_ext_stats_mem;
2156 ret = snprintf(buff, len, "%s", (char *)virt_addr);
2159 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, len, virt_addr, phys_addr,
2166 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2168 struct ena_com_admin_queue *admin_queue;
2169 struct ena_admin_set_feat_cmd cmd;
2170 struct ena_admin_set_feat_resp resp;
2173 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2174 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2175 return ENA_COM_UNSUPPORTED;
2178 memset(&cmd, 0x0, sizeof(cmd));
2179 admin_queue = &ena_dev->admin_queue;
2181 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2182 cmd.aq_common_descriptor.flags = 0;
2183 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2184 cmd.u.mtu.mtu = mtu;
2186 ret = ena_com_execute_admin_command(admin_queue,
2187 (struct ena_admin_aq_entry *)&cmd,
2189 (struct ena_admin_acq_entry *)&resp,
2193 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2198 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2199 struct ena_admin_feature_offload_desc *offload)
2202 struct ena_admin_get_feat_resp resp;
2204 ret = ena_com_get_feature(ena_dev, &resp,
2205 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG);
2206 if (unlikely(ret)) {
2207 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2211 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2216 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2218 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2219 struct ena_rss *rss = &ena_dev->rss;
2220 struct ena_admin_set_feat_cmd cmd;
2221 struct ena_admin_set_feat_resp resp;
2222 struct ena_admin_get_feat_resp get_resp;
2225 if (!ena_com_check_supported_feature_id(ena_dev,
2226 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2227 ena_trc_dbg("Feature %d isn't supported\n",
2228 ENA_ADMIN_RSS_HASH_FUNCTION);
2229 return ENA_COM_UNSUPPORTED;
2232 /* Validate hash function is supported */
2233 ret = ena_com_get_feature(ena_dev, &get_resp,
2234 ENA_ADMIN_RSS_HASH_FUNCTION);
2238 if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) {
2239 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2241 return ENA_COM_UNSUPPORTED;
2244 memset(&cmd, 0x0, sizeof(cmd));
2246 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2247 cmd.aq_common_descriptor.flags =
2248 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2249 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2250 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2251 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2253 ret = ena_com_mem_addr_set(ena_dev,
2254 &cmd.control_buffer.address,
2255 rss->hash_key_dma_addr);
2256 if (unlikely(ret)) {
2257 ena_trc_err("memory address set failed\n");
2261 cmd.control_buffer.length = sizeof(*rss->hash_key);
2263 ret = ena_com_execute_admin_command(admin_queue,
2264 (struct ena_admin_aq_entry *)&cmd,
2266 (struct ena_admin_acq_entry *)&resp,
2268 if (unlikely(ret)) {
2269 ena_trc_err("Failed to set hash function %d. error: %d\n",
2270 rss->hash_func, ret);
2271 return ENA_COM_INVAL;
2277 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2278 enum ena_admin_hash_functions func,
2279 const u8 *key, u16 key_len, u32 init_val)
2281 struct ena_rss *rss = &ena_dev->rss;
2282 struct ena_admin_get_feat_resp get_resp;
2283 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2287 /* Make sure size is a mult of DWs */
2288 if (unlikely(key_len & 0x3))
2289 return ENA_COM_INVAL;
2291 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2292 ENA_ADMIN_RSS_HASH_FUNCTION,
2293 rss->hash_key_dma_addr,
2294 sizeof(*rss->hash_key));
2298 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) {
2299 ena_trc_err("Flow hash function %d isn't supported\n", func);
2300 return ENA_COM_UNSUPPORTED;
2304 case ENA_ADMIN_TOEPLITZ:
2305 if (key_len > sizeof(hash_key->key)) {
2306 ena_trc_err("key len (%hu) is bigger than the max supported (%zu)\n",
2307 key_len, sizeof(hash_key->key));
2308 return ENA_COM_INVAL;
2311 memcpy(hash_key->key, key, key_len);
2312 rss->hash_init_val = init_val;
2313 hash_key->keys_num = key_len >> 2;
2315 case ENA_ADMIN_CRC32:
2316 rss->hash_init_val = init_val;
2319 ena_trc_err("Invalid hash function (%d)\n", func);
2320 return ENA_COM_INVAL;
2323 rc = ena_com_set_hash_function(ena_dev);
2325 /* Restore the old function */
2327 ena_com_get_hash_function(ena_dev, NULL, NULL);
2332 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2333 enum ena_admin_hash_functions *func,
2336 struct ena_rss *rss = &ena_dev->rss;
2337 struct ena_admin_get_feat_resp get_resp;
2338 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2342 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2343 ENA_ADMIN_RSS_HASH_FUNCTION,
2344 rss->hash_key_dma_addr,
2345 sizeof(*rss->hash_key));
2349 rss->hash_func = get_resp.u.flow_hash_func.selected_func;
2351 *func = rss->hash_func;
2354 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2359 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2360 enum ena_admin_flow_hash_proto proto,
2363 struct ena_rss *rss = &ena_dev->rss;
2364 struct ena_admin_get_feat_resp get_resp;
2367 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2368 ENA_ADMIN_RSS_HASH_INPUT,
2369 rss->hash_ctrl_dma_addr,
2370 sizeof(*rss->hash_ctrl));
2375 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2380 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2382 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2383 struct ena_rss *rss = &ena_dev->rss;
2384 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2385 struct ena_admin_set_feat_cmd cmd;
2386 struct ena_admin_set_feat_resp resp;
2389 if (!ena_com_check_supported_feature_id(ena_dev,
2390 ENA_ADMIN_RSS_HASH_INPUT)) {
2391 ena_trc_dbg("Feature %d isn't supported\n",
2392 ENA_ADMIN_RSS_HASH_INPUT);
2393 return ENA_COM_UNSUPPORTED;
2396 memset(&cmd, 0x0, sizeof(cmd));
2398 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2399 cmd.aq_common_descriptor.flags =
2400 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2401 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2402 cmd.u.flow_hash_input.enabled_input_sort =
2403 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2404 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2406 ret = ena_com_mem_addr_set(ena_dev,
2407 &cmd.control_buffer.address,
2408 rss->hash_ctrl_dma_addr);
2409 if (unlikely(ret)) {
2410 ena_trc_err("memory address set failed\n");
2413 cmd.control_buffer.length = sizeof(*hash_ctrl);
2415 ret = ena_com_execute_admin_command(admin_queue,
2416 (struct ena_admin_aq_entry *)&cmd,
2418 (struct ena_admin_acq_entry *)&resp,
2421 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2426 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2428 struct ena_rss *rss = &ena_dev->rss;
2429 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2431 u16 available_fields = 0;
2434 /* Get the supported hash input */
2435 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2439 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2440 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2441 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2443 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2444 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2445 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2447 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2448 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2449 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2451 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2452 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2453 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2455 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2456 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2458 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2459 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2461 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2462 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2464 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2465 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2467 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2468 available_fields = hash_ctrl->selected_fields[i].fields &
2469 hash_ctrl->supported_fields[i].fields;
2470 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2471 ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2472 i, hash_ctrl->supported_fields[i].fields,
2473 hash_ctrl->selected_fields[i].fields);
2474 return ENA_COM_UNSUPPORTED;
2478 rc = ena_com_set_hash_ctrl(ena_dev);
2480 /* In case of failure, restore the old hash ctrl */
2482 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2487 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2488 enum ena_admin_flow_hash_proto proto,
2491 struct ena_rss *rss = &ena_dev->rss;
2492 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2493 u16 supported_fields;
2496 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2497 ena_trc_err("Invalid proto num (%u)\n", proto);
2498 return ENA_COM_INVAL;
2501 /* Get the ctrl table */
2502 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2506 /* Make sure all the fields are supported */
2507 supported_fields = hash_ctrl->supported_fields[proto].fields;
2508 if ((hash_fields & supported_fields) != hash_fields) {
2509 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2510 proto, hash_fields, supported_fields);
2513 hash_ctrl->selected_fields[proto].fields = hash_fields;
2515 rc = ena_com_set_hash_ctrl(ena_dev);
2517 /* In case of failure, restore the old hash ctrl */
2519 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2524 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2525 u16 entry_idx, u16 entry_value)
2527 struct ena_rss *rss = &ena_dev->rss;
2529 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2530 return ENA_COM_INVAL;
2532 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2533 return ENA_COM_INVAL;
2535 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2540 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2542 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2543 struct ena_rss *rss = &ena_dev->rss;
2544 struct ena_admin_set_feat_cmd cmd;
2545 struct ena_admin_set_feat_resp resp;
2548 if (!ena_com_check_supported_feature_id(ena_dev,
2549 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2550 ena_trc_dbg("Feature %d isn't supported\n",
2551 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2552 return ENA_COM_UNSUPPORTED;
2555 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2557 ena_trc_err("Failed to convert host indirection table to device table\n");
2561 memset(&cmd, 0x0, sizeof(cmd));
2563 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2564 cmd.aq_common_descriptor.flags =
2565 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2566 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2567 cmd.u.ind_table.size = rss->tbl_log_size;
2568 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2570 ret = ena_com_mem_addr_set(ena_dev,
2571 &cmd.control_buffer.address,
2572 rss->rss_ind_tbl_dma_addr);
2573 if (unlikely(ret)) {
2574 ena_trc_err("memory address set failed\n");
2578 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2579 sizeof(struct ena_admin_rss_ind_table_entry);
2581 ret = ena_com_execute_admin_command(admin_queue,
2582 (struct ena_admin_aq_entry *)&cmd,
2584 (struct ena_admin_acq_entry *)&resp,
2588 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2593 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2595 struct ena_rss *rss = &ena_dev->rss;
2596 struct ena_admin_get_feat_resp get_resp;
2600 tbl_size = (1ULL << rss->tbl_log_size) *
2601 sizeof(struct ena_admin_rss_ind_table_entry);
2603 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2604 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2605 rss->rss_ind_tbl_dma_addr,
2613 rc = ena_com_ind_tbl_convert_from_device(ena_dev);
2617 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2618 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2623 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2627 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2629 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2633 rc = ena_com_hash_key_allocate(ena_dev);
2637 rc = ena_com_hash_ctrl_init(ena_dev);
2644 ena_com_hash_key_destroy(ena_dev);
2646 ena_com_indirect_table_destroy(ena_dev);
2652 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2654 ena_com_indirect_table_destroy(ena_dev);
2655 ena_com_hash_key_destroy(ena_dev);
2656 ena_com_hash_ctrl_destroy(ena_dev);
2658 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2661 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2663 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2665 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2667 host_attr->host_info,
2668 host_attr->host_info_dma_addr,
2669 host_attr->host_info_dma_handle);
2670 if (unlikely(!host_attr->host_info))
2671 return ENA_COM_NO_MEM;
2676 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2677 u32 debug_area_size)
2679 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2681 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2683 host_attr->debug_area_virt_addr,
2684 host_attr->debug_area_dma_addr,
2685 host_attr->debug_area_dma_handle);
2686 if (unlikely(!host_attr->debug_area_virt_addr)) {
2687 host_attr->debug_area_size = 0;
2688 return ENA_COM_NO_MEM;
2691 host_attr->debug_area_size = debug_area_size;
2696 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2698 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2700 if (host_attr->host_info) {
2701 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2703 host_attr->host_info,
2704 host_attr->host_info_dma_addr,
2705 host_attr->host_info_dma_handle);
2706 host_attr->host_info = NULL;
2710 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2712 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2714 if (host_attr->debug_area_virt_addr) {
2715 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2716 host_attr->debug_area_size,
2717 host_attr->debug_area_virt_addr,
2718 host_attr->debug_area_dma_addr,
2719 host_attr->debug_area_dma_handle);
2720 host_attr->debug_area_virt_addr = NULL;
2724 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2726 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2727 struct ena_com_admin_queue *admin_queue;
2728 struct ena_admin_set_feat_cmd cmd;
2729 struct ena_admin_set_feat_resp resp;
2733 /* Host attribute config is called before ena_com_get_dev_attr_feat
2734 * so ena_com can't check if the feature is supported.
2737 memset(&cmd, 0x0, sizeof(cmd));
2738 admin_queue = &ena_dev->admin_queue;
2740 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2741 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2743 ret = ena_com_mem_addr_set(ena_dev,
2744 &cmd.u.host_attr.debug_ba,
2745 host_attr->debug_area_dma_addr);
2746 if (unlikely(ret)) {
2747 ena_trc_err("memory address set failed\n");
2751 ret = ena_com_mem_addr_set(ena_dev,
2752 &cmd.u.host_attr.os_info_ba,
2753 host_attr->host_info_dma_addr);
2754 if (unlikely(ret)) {
2755 ena_trc_err("memory address set failed\n");
2759 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2761 ret = ena_com_execute_admin_command(admin_queue,
2762 (struct ena_admin_aq_entry *)&cmd,
2764 (struct ena_admin_acq_entry *)&resp,
2768 ena_trc_err("Failed to set host attributes: %d\n", ret);
2773 /* Interrupt moderation */
2774 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2776 return ena_com_check_supported_feature_id(ena_dev,
2777 ENA_ADMIN_INTERRUPT_MODERATION);
2780 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2781 u32 tx_coalesce_usecs)
2783 if (!ena_dev->intr_delay_resolution) {
2784 ena_trc_err("Illegal interrupt delay granularity value\n");
2785 return ENA_COM_FAULT;
2788 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs /
2789 ena_dev->intr_delay_resolution;
2794 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2795 u32 rx_coalesce_usecs)
2797 if (!ena_dev->intr_delay_resolution) {
2798 ena_trc_err("Illegal interrupt delay granularity value\n");
2799 return ENA_COM_FAULT;
2802 /* We use LOWEST entry of moderation table for storing
2803 * nonadaptive interrupt coalescing values
2805 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2806 rx_coalesce_usecs / ena_dev->intr_delay_resolution;
2811 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev)
2813 if (ena_dev->intr_moder_tbl)
2814 ENA_MEM_FREE(ena_dev->dmadev, ena_dev->intr_moder_tbl);
2815 ena_dev->intr_moder_tbl = NULL;
2818 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2820 struct ena_admin_get_feat_resp get_resp;
2821 u16 delay_resolution;
2824 rc = ena_com_get_feature(ena_dev, &get_resp,
2825 ENA_ADMIN_INTERRUPT_MODERATION);
2828 if (rc == ENA_COM_UNSUPPORTED) {
2829 ena_trc_dbg("Feature %d isn't supported\n",
2830 ENA_ADMIN_INTERRUPT_MODERATION);
2833 ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
2837 /* no moderation supported, disable adaptive support */
2838 ena_com_disable_adaptive_moderation(ena_dev);
2842 rc = ena_com_init_interrupt_moderation_table(ena_dev);
2846 /* if moderation is supported by device we set adaptive moderation */
2847 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2848 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2849 ena_com_enable_adaptive_moderation(ena_dev);
2853 ena_com_destroy_interrupt_moderation(ena_dev);
2857 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev)
2859 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2861 if (!intr_moder_tbl)
2864 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval =
2865 ENA_INTR_LOWEST_USECS;
2866 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval =
2867 ENA_INTR_LOWEST_PKTS;
2868 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval =
2869 ENA_INTR_LOWEST_BYTES;
2871 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval =
2873 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval =
2875 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval =
2878 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval =
2880 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval =
2882 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval =
2885 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval =
2886 ENA_INTR_HIGH_USECS;
2887 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval =
2889 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval =
2890 ENA_INTR_HIGH_BYTES;
2892 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval =
2893 ENA_INTR_HIGHEST_USECS;
2894 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval =
2895 ENA_INTR_HIGHEST_PKTS;
2896 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval =
2897 ENA_INTR_HIGHEST_BYTES;
2900 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2902 return ena_dev->intr_moder_tx_interval;
2905 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2907 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2910 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval;
2915 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
2916 enum ena_intr_moder_level level,
2917 struct ena_intr_moder_entry *entry)
2919 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2921 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2924 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval;
2925 if (ena_dev->intr_delay_resolution)
2926 intr_moder_tbl[level].intr_moder_interval /=
2927 ena_dev->intr_delay_resolution;
2928 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval;
2930 /* use hardcoded value until ethtool supports bytecount parameter */
2931 if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED)
2932 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval;
2935 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
2936 enum ena_intr_moder_level level,
2937 struct ena_intr_moder_entry *entry)
2939 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
2941 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS)
2944 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval;
2945 if (ena_dev->intr_delay_resolution)
2946 entry->intr_moder_interval *= ena_dev->intr_delay_resolution;
2947 entry->pkts_per_interval =
2948 intr_moder_tbl[level].pkts_per_interval;
2949 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval;
2952 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2953 struct ena_admin_feature_llq_desc *llq)
2958 if (llq->max_llq_num == 0) {
2959 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2963 rc = ena_com_config_llq_info(ena_dev, llq);
2967 /* Validate the descriptor is not too big */
2968 size = ena_dev->tx_max_header_size;
2969 size += ena_dev->llq_info.descs_num_before_header *
2970 sizeof(struct ena_eth_io_tx_desc);
2972 if (unlikely(ena_dev->llq_info.desc_list_entry_size < size)) {
2973 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
2974 return ENA_COM_INVAL;
2977 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;