4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 /*****************************************************************************/
37 /*****************************************************************************/
39 /* Timeout in micro-sec */
40 #define ADMIN_CMD_TIMEOUT_US (3000000)
42 #define ENA_ASYNC_QUEUE_DEPTH 16
43 #define ENA_ADMIN_QUEUE_DEPTH 32
45 #ifdef ENA_EXTENDED_STATS
47 #define ENA_HISTOGRAM_ACTIVE_MASK_OFFSET 0xF08
48 #define ENA_EXTENDED_STAT_GET_FUNCT(_funct_queue) (_funct_queue & 0xFFFF)
49 #define ENA_EXTENDED_STAT_GET_QUEUE(_funct_queue) (_funct_queue >> 16)
51 #endif /* ENA_EXTENDED_STATS */
53 #define ENA_CTRL_MAJOR 0
54 #define ENA_CTRL_MINOR 0
55 #define ENA_CTRL_SUB_MINOR 1
57 #define MIN_ENA_CTRL_VER \
58 (((ENA_CTRL_MAJOR) << \
59 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
60 ((ENA_CTRL_MINOR) << \
61 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
64 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
65 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
67 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
69 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
71 #define ENA_REGS_ADMIN_INTR_MASK 1
73 #define ENA_MIN_POLL_US 100
75 #define ENA_MAX_POLL_US 5000
77 /*****************************************************************************/
78 /*****************************************************************************/
79 /*****************************************************************************/
84 /* Abort - canceled by the driver */
89 ena_wait_event_t wait_event;
90 struct ena_admin_acq_entry *user_cqe;
92 enum ena_cmd_status status;
93 /* status from the device */
99 struct ena_com_stats_ctx {
100 struct ena_admin_aq_get_stats_cmd get_cmd;
101 struct ena_admin_acq_get_stats_resp get_resp;
104 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
105 struct ena_common_mem_addr *ena_addr,
108 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
109 ena_trc_err("dma address has more bits that the device supports\n");
110 return ENA_COM_INVAL;
113 ena_addr->mem_addr_low = lower_32_bits(addr);
114 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
119 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue)
121 struct ena_com_admin_sq *sq = &queue->sq;
122 u16 size = ADMIN_SQ_SIZE(queue->q_depth);
124 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, sq->entries, sq->dma_addr,
128 ena_trc_err("memory allocation failed\n");
129 return ENA_COM_NO_MEM;
141 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue)
143 struct ena_com_admin_cq *cq = &queue->cq;
144 u16 size = ADMIN_CQ_SIZE(queue->q_depth);
146 ENA_MEM_ALLOC_COHERENT(queue->q_dmadev, size, cq->entries, cq->dma_addr,
150 ena_trc_err("memory allocation failed\n");
151 return ENA_COM_NO_MEM;
160 static int ena_com_admin_init_aenq(struct ena_com_dev *dev,
161 struct ena_aenq_handlers *aenq_handlers)
163 struct ena_com_aenq *aenq = &dev->aenq;
164 u32 addr_low, addr_high, aenq_caps;
167 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
168 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
169 ENA_MEM_ALLOC_COHERENT(dev->dmadev, size,
174 if (!aenq->entries) {
175 ena_trc_err("memory allocation failed\n");
176 return ENA_COM_NO_MEM;
179 aenq->head = aenq->q_depth;
182 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
183 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
185 ENA_REG_WRITE32(dev->bus, addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
186 ENA_REG_WRITE32(dev->bus, addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
189 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
190 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) <<
191 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
192 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
193 ENA_REG_WRITE32(dev->bus, aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
195 if (unlikely(!aenq_handlers)) {
196 ena_trc_err("aenq handlers pointer is NULL\n");
197 return ENA_COM_INVAL;
200 aenq->aenq_handlers = aenq_handlers;
205 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
206 struct ena_comp_ctx *comp_ctx)
208 comp_ctx->occupied = false;
209 ATOMIC32_DEC(&queue->outstanding_cmds);
212 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue,
213 u16 command_id, bool capture)
215 if (unlikely(command_id >= queue->q_depth)) {
216 ena_trc_err("command id is larger than the queue size. cmd_id: %u queue size %d\n",
217 command_id, queue->q_depth);
221 if (unlikely(!queue->comp_ctx)) {
222 ena_trc_err("Completion context is NULL\n");
226 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) {
227 ena_trc_err("Completion context is occupied\n");
232 ATOMIC32_INC(&queue->outstanding_cmds);
233 queue->comp_ctx[command_id].occupied = true;
236 return &queue->comp_ctx[command_id];
239 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
240 struct ena_admin_aq_entry *cmd,
241 size_t cmd_size_in_bytes,
242 struct ena_admin_acq_entry *comp,
243 size_t comp_size_in_bytes)
245 struct ena_comp_ctx *comp_ctx;
246 u16 tail_masked, cmd_id;
250 queue_size_mask = admin_queue->q_depth - 1;
252 tail_masked = admin_queue->sq.tail & queue_size_mask;
254 /* In case of queue FULL */
255 cnt = (u16)ATOMIC32_READ(&admin_queue->outstanding_cmds);
256 if (cnt >= admin_queue->q_depth) {
257 ena_trc_dbg("admin queue is full.\n");
258 admin_queue->stats.out_of_space++;
259 return ERR_PTR(ENA_COM_NO_SPACE);
262 cmd_id = admin_queue->curr_cmd_id;
264 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
265 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
267 cmd->aq_common_descriptor.command_id |= cmd_id &
268 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
270 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
271 if (unlikely(!comp_ctx))
272 return ERR_PTR(ENA_COM_INVAL);
274 comp_ctx->status = ENA_CMD_SUBMITTED;
275 comp_ctx->comp_size = (u32)comp_size_in_bytes;
276 comp_ctx->user_cqe = comp;
277 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
279 ENA_WAIT_EVENT_CLEAR(comp_ctx->wait_event);
281 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
283 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
286 admin_queue->sq.tail++;
287 admin_queue->stats.submitted_cmd++;
289 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
290 admin_queue->sq.phase = !admin_queue->sq.phase;
292 ENA_DB_SYNC(&admin_queue->sq.mem_handle);
293 ENA_REG_WRITE32(admin_queue->bus, admin_queue->sq.tail,
294 admin_queue->sq.db_addr);
299 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue)
301 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx);
302 struct ena_comp_ctx *comp_ctx;
305 queue->comp_ctx = ENA_MEM_ALLOC(queue->q_dmadev, size);
306 if (unlikely(!queue->comp_ctx)) {
307 ena_trc_err("memory allocation failed\n");
308 return ENA_COM_NO_MEM;
311 for (i = 0; i < queue->q_depth; i++) {
312 comp_ctx = get_comp_ctxt(queue, i, false);
314 ENA_WAIT_EVENT_INIT(comp_ctx->wait_event);
320 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
321 struct ena_admin_aq_entry *cmd,
322 size_t cmd_size_in_bytes,
323 struct ena_admin_acq_entry *comp,
324 size_t comp_size_in_bytes)
326 unsigned long flags = 0;
327 struct ena_comp_ctx *comp_ctx;
329 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
330 if (unlikely(!admin_queue->running_state)) {
331 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
332 return ERR_PTR(ENA_COM_NO_DEVICE);
334 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
338 if (IS_ERR(comp_ctx))
339 admin_queue->running_state = false;
340 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
345 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
346 struct ena_com_create_io_ctx *ctx,
347 struct ena_com_io_sq *io_sq)
352 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
354 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
355 io_sq->desc_entry_size =
356 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
357 sizeof(struct ena_eth_io_tx_desc) :
358 sizeof(struct ena_eth_io_rx_desc);
360 size = io_sq->desc_entry_size * io_sq->q_depth;
361 io_sq->bus = ena_dev->bus;
363 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
364 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
366 io_sq->desc_addr.virt_addr,
367 io_sq->desc_addr.phys_addr,
368 io_sq->desc_addr.mem_handle,
371 if (!io_sq->desc_addr.virt_addr) {
372 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
374 io_sq->desc_addr.virt_addr,
375 io_sq->desc_addr.phys_addr,
376 io_sq->desc_addr.mem_handle);
379 if (!io_sq->desc_addr.virt_addr) {
380 ena_trc_err("memory allocation failed\n");
381 return ENA_COM_NO_MEM;
385 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
386 /* Allocate bounce buffers */
387 io_sq->bounce_buf_ctrl.buffer_size =
388 ena_dev->llq_info.desc_list_entry_size;
389 io_sq->bounce_buf_ctrl.buffers_num =
390 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
391 io_sq->bounce_buf_ctrl.next_to_use = 0;
393 size = io_sq->bounce_buf_ctrl.buffer_size *
394 io_sq->bounce_buf_ctrl.buffers_num;
396 ENA_MEM_ALLOC_NODE(ena_dev->dmadev,
398 io_sq->bounce_buf_ctrl.base_buffer,
401 if (!io_sq->bounce_buf_ctrl.base_buffer)
402 io_sq->bounce_buf_ctrl.base_buffer = ENA_MEM_ALLOC(ena_dev->dmadev, size);
404 if (!io_sq->bounce_buf_ctrl.base_buffer) {
405 ena_trc_err("bounce buffer memory allocation failed\n");
406 return ENA_COM_NO_MEM;
409 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
410 sizeof(io_sq->llq_info));
412 /* Initiate the first bounce buffer */
413 io_sq->llq_buf_ctrl.curr_bounce_buf =
414 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
415 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
416 0x0, io_sq->llq_info.desc_list_entry_size);
417 io_sq->llq_buf_ctrl.descs_left_in_line =
418 io_sq->llq_info.descs_num_before_header;
419 io_sq->disable_meta_caching =
420 io_sq->llq_info.disable_meta_caching;
422 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
423 io_sq->entries_in_tx_burst_left =
424 io_sq->llq_info.max_entries_in_tx_burst;
428 io_sq->next_to_comp = 0;
434 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
435 struct ena_com_create_io_ctx *ctx,
436 struct ena_com_io_cq *io_cq)
441 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
443 /* Use the basic completion descriptor for Rx */
444 io_cq->cdesc_entry_size_in_bytes =
445 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
446 sizeof(struct ena_eth_io_tx_cdesc) :
447 sizeof(struct ena_eth_io_rx_cdesc_base);
449 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
450 io_cq->bus = ena_dev->bus;
452 ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
454 io_cq->cdesc_addr.virt_addr,
455 io_cq->cdesc_addr.phys_addr,
456 io_cq->cdesc_addr.mem_handle,
459 if (!io_cq->cdesc_addr.virt_addr) {
460 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
462 io_cq->cdesc_addr.virt_addr,
463 io_cq->cdesc_addr.phys_addr,
464 io_cq->cdesc_addr.mem_handle);
467 if (!io_cq->cdesc_addr.virt_addr) {
468 ena_trc_err("memory allocation failed\n");
469 return ENA_COM_NO_MEM;
478 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
479 struct ena_admin_acq_entry *cqe)
481 struct ena_comp_ctx *comp_ctx;
484 cmd_id = cqe->acq_common_descriptor.command &
485 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
487 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
488 if (unlikely(!comp_ctx)) {
489 ena_trc_err("comp_ctx is NULL. Changing the admin queue running state\n");
490 admin_queue->running_state = false;
494 comp_ctx->status = ENA_CMD_COMPLETED;
495 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
497 if (comp_ctx->user_cqe)
498 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
500 if (!admin_queue->polling)
501 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
504 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
506 struct ena_admin_acq_entry *cqe = NULL;
511 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
512 phase = admin_queue->cq.phase;
514 cqe = &admin_queue->cq.entries[head_masked];
516 /* Go over all the completions */
517 while ((READ_ONCE8(cqe->acq_common_descriptor.flags) &
518 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
519 /* Do not read the rest of the completion entry before the
520 * phase bit was validated
523 ena_com_handle_single_admin_completion(admin_queue, cqe);
527 if (unlikely(head_masked == admin_queue->q_depth)) {
532 cqe = &admin_queue->cq.entries[head_masked];
535 admin_queue->cq.head += comp_num;
536 admin_queue->cq.phase = phase;
537 admin_queue->sq.head += comp_num;
538 admin_queue->stats.completed_cmd += comp_num;
541 static int ena_com_comp_status_to_errno(u8 comp_status)
543 if (unlikely(comp_status != 0))
544 ena_trc_err("admin command failed[%u]\n", comp_status);
546 switch (comp_status) {
547 case ENA_ADMIN_SUCCESS:
549 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
550 return ENA_COM_NO_MEM;
551 case ENA_ADMIN_UNSUPPORTED_OPCODE:
552 return ENA_COM_UNSUPPORTED;
553 case ENA_ADMIN_BAD_OPCODE:
554 case ENA_ADMIN_MALFORMED_REQUEST:
555 case ENA_ADMIN_ILLEGAL_PARAMETER:
556 case ENA_ADMIN_UNKNOWN_ERROR:
557 return ENA_COM_INVAL;
560 return ENA_COM_INVAL;
563 static inline void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
565 delay_us = ENA_MAX32(ENA_MIN_POLL_US, delay_us);
566 delay_us = ENA_MIN32(delay_us * (1 << exp), ENA_MAX_POLL_US);
567 ENA_USLEEP(delay_us);
570 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
571 struct ena_com_admin_queue *admin_queue)
573 unsigned long flags = 0;
578 timeout = ENA_GET_SYSTEM_TIMEOUT(admin_queue->completion_timeout);
581 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
582 ena_com_handle_admin_completion(admin_queue);
583 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
585 if (comp_ctx->status != ENA_CMD_SUBMITTED)
588 if (ENA_TIME_EXPIRE(timeout)) {
589 ena_trc_err("Wait for completion (polling) timeout\n");
590 /* ENA didn't have any completion */
591 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
592 admin_queue->stats.no_completion++;
593 admin_queue->running_state = false;
594 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
596 ret = ENA_COM_TIMER_EXPIRED;
600 ena_delay_exponential_backoff_us(exp++, admin_queue->ena_dev->ena_min_poll_delay_us);
603 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
604 ena_trc_err("Command was aborted\n");
605 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
606 admin_queue->stats.aborted_cmd++;
607 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
608 ret = ENA_COM_NO_DEVICE;
612 ENA_WARN(comp_ctx->status != ENA_CMD_COMPLETED,
613 "Invalid comp status %d\n", comp_ctx->status);
615 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
617 comp_ctxt_release(admin_queue, comp_ctx);
622 * Set the LLQ configurations of the firmware
624 * The driver provides only the enabled feature values to the device,
625 * which in turn, checks if they are supported.
627 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
629 struct ena_com_admin_queue *admin_queue;
630 struct ena_admin_set_feat_cmd cmd;
631 struct ena_admin_set_feat_resp resp;
632 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
635 memset(&cmd, 0x0, sizeof(cmd));
636 admin_queue = &ena_dev->admin_queue;
638 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
639 cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
641 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
642 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
643 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
644 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
646 if (llq_info->disable_meta_caching)
647 cmd.u.llq.accel_mode.u.set.enabled_flags |=
648 BIT(ENA_ADMIN_DISABLE_META_CACHING);
650 if (llq_info->max_entries_in_tx_burst)
651 cmd.u.llq.accel_mode.u.set.enabled_flags |=
652 BIT(ENA_ADMIN_LIMIT_TX_BURST);
654 ret = ena_com_execute_admin_command(admin_queue,
655 (struct ena_admin_aq_entry *)&cmd,
657 (struct ena_admin_acq_entry *)&resp,
661 ena_trc_err("Failed to set LLQ configurations: %d\n", ret);
666 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
667 struct ena_admin_feature_llq_desc *llq_features,
668 struct ena_llq_configurations *llq_default_cfg)
670 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
674 memset(llq_info, 0, sizeof(*llq_info));
676 supported_feat = llq_features->header_location_ctrl_supported;
678 if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
679 llq_info->header_location_ctrl =
680 llq_default_cfg->llq_header_location;
682 ena_trc_err("Invalid header location control, supported: 0x%x\n",
687 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
688 supported_feat = llq_features->descriptors_stride_ctrl_supported;
689 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
690 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
692 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
693 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
694 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
695 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
697 ena_trc_err("Invalid desc_stride_ctrl, supported: 0x%x\n",
702 ena_trc_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
703 llq_default_cfg->llq_stride_ctrl,
705 llq_info->desc_stride_ctrl);
708 llq_info->desc_stride_ctrl = 0;
711 supported_feat = llq_features->entry_size_ctrl_supported;
712 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
713 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
714 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
716 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
717 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
718 llq_info->desc_list_entry_size = 128;
719 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
720 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
721 llq_info->desc_list_entry_size = 192;
722 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
723 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
724 llq_info->desc_list_entry_size = 256;
726 ena_trc_err("Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat);
730 ena_trc_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
731 llq_default_cfg->llq_ring_entry_size,
733 llq_info->desc_list_entry_size);
735 if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
736 /* The desc list entry size should be whole multiply of 8
737 * This requirement comes from __iowrite64_copy()
739 ena_trc_err("illegal entry size %d\n",
740 llq_info->desc_list_entry_size);
744 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
745 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
746 sizeof(struct ena_eth_io_tx_desc);
748 llq_info->descs_per_entry = 1;
750 supported_feat = llq_features->desc_num_before_header_supported;
751 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
752 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
754 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
755 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
756 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
757 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
758 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
759 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
760 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
761 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
763 ena_trc_err("Invalid descs_num_before_header, supported: 0x%x\n",
768 ena_trc_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
769 llq_default_cfg->llq_num_decs_before_header,
771 llq_info->descs_num_before_header);
773 /* Check for accelerated queue supported */
774 llq_info->disable_meta_caching =
775 llq_features->accel_mode.u.get.supported_flags &
776 BIT(ENA_ADMIN_DISABLE_META_CACHING);
778 if (llq_features->accel_mode.u.get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
779 llq_info->max_entries_in_tx_burst =
780 llq_features->accel_mode.u.get.max_tx_burst_size /
781 llq_default_cfg->llq_ring_entry_size_value;
783 rc = ena_com_set_llq(ena_dev);
785 ena_trc_err("Cannot set LLQ configuration: %d\n", rc);
790 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
791 struct ena_com_admin_queue *admin_queue)
793 unsigned long flags = 0;
796 ENA_WAIT_EVENT_WAIT(comp_ctx->wait_event,
797 admin_queue->completion_timeout);
799 /* In case the command wasn't completed find out the root cause.
800 * There might be 2 kinds of errors
801 * 1) No completion (timeout reached)
802 * 2) There is completion but the device didn't get any msi-x interrupt.
804 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
805 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
806 ena_com_handle_admin_completion(admin_queue);
807 admin_queue->stats.no_completion++;
808 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
810 if (comp_ctx->status == ENA_CMD_COMPLETED) {
811 ena_trc_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
812 comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF");
813 /* Check if fallback to polling is enabled */
814 if (admin_queue->auto_polling)
815 admin_queue->polling = true;
817 ena_trc_err("The ena device didn't send a completion for the admin cmd %d status %d\n",
818 comp_ctx->cmd_opcode, comp_ctx->status);
820 /* Check if shifted to polling mode.
821 * This will happen if there is a completion without an interrupt
822 * and autopolling mode is enabled. Continuing normal execution in such case
824 if (!admin_queue->polling) {
825 admin_queue->running_state = false;
826 ret = ENA_COM_TIMER_EXPIRED;
831 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status);
833 comp_ctxt_release(admin_queue, comp_ctx);
837 /* This method read the hardware device register through posting writes
838 * and waiting for response
839 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
841 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
843 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
844 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
845 mmio_read->read_resp;
846 u32 mmio_read_reg, ret, i;
847 unsigned long flags = 0;
848 u32 timeout = mmio_read->reg_read_to;
853 timeout = ENA_REG_READ_TIMEOUT;
855 /* If readless is disabled, perform regular read */
856 if (!mmio_read->readless_supported)
857 return ENA_REG_READ32(ena_dev->bus, ena_dev->reg_bar + offset);
859 ENA_SPINLOCK_LOCK(mmio_read->lock, flags);
860 mmio_read->seq_num++;
862 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
863 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
864 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
865 mmio_read_reg |= mmio_read->seq_num &
866 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
868 ENA_REG_WRITE32(ena_dev->bus, mmio_read_reg,
869 ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
871 for (i = 0; i < timeout; i++) {
872 if (READ_ONCE16(read_resp->req_id) == mmio_read->seq_num)
878 if (unlikely(i == timeout)) {
879 ena_trc_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n",
884 ret = ENA_MMIO_READ_TIMEOUT;
888 if (read_resp->reg_off != offset) {
889 ena_trc_err("Read failure: wrong offset provided\n");
890 ret = ENA_MMIO_READ_TIMEOUT;
892 ret = read_resp->reg_val;
895 ENA_SPINLOCK_UNLOCK(mmio_read->lock, flags);
900 /* There are two types to wait for completion.
901 * Polling mode - wait until the completion is available.
902 * Async mode - wait on wait queue until the completion is ready
903 * (or the timeout expired).
904 * It is expected that the IRQ called ena_com_handle_admin_completion
905 * to mark the completions.
907 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
908 struct ena_com_admin_queue *admin_queue)
910 if (admin_queue->polling)
911 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
914 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
918 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
919 struct ena_com_io_sq *io_sq)
921 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
922 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
923 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
927 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
929 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
930 direction = ENA_ADMIN_SQ_DIRECTION_TX;
932 direction = ENA_ADMIN_SQ_DIRECTION_RX;
934 destroy_cmd.sq.sq_identity |= (direction <<
935 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
936 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
938 destroy_cmd.sq.sq_idx = io_sq->idx;
939 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
941 ret = ena_com_execute_admin_command(admin_queue,
942 (struct ena_admin_aq_entry *)&destroy_cmd,
944 (struct ena_admin_acq_entry *)&destroy_resp,
945 sizeof(destroy_resp));
947 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
948 ena_trc_err("failed to destroy io sq error: %d\n", ret);
953 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
954 struct ena_com_io_sq *io_sq,
955 struct ena_com_io_cq *io_cq)
959 if (io_cq->cdesc_addr.virt_addr) {
960 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
962 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
964 io_cq->cdesc_addr.virt_addr,
965 io_cq->cdesc_addr.phys_addr,
966 io_cq->cdesc_addr.mem_handle);
968 io_cq->cdesc_addr.virt_addr = NULL;
971 if (io_sq->desc_addr.virt_addr) {
972 size = io_sq->desc_entry_size * io_sq->q_depth;
974 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
976 io_sq->desc_addr.virt_addr,
977 io_sq->desc_addr.phys_addr,
978 io_sq->desc_addr.mem_handle);
980 io_sq->desc_addr.virt_addr = NULL;
983 if (io_sq->bounce_buf_ctrl.base_buffer) {
984 ENA_MEM_FREE(ena_dev->dmadev,
985 io_sq->bounce_buf_ctrl.base_buffer,
986 (io_sq->llq_info.desc_list_entry_size * ENA_COM_BOUNCE_BUFFER_CNTRL_CNT));
987 io_sq->bounce_buf_ctrl.base_buffer = NULL;
991 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
995 ena_time_t timeout_stamp;
997 /* Convert timeout from resolution of 100ms to us resolution. */
998 timeout_stamp = ENA_GET_SYSTEM_TIMEOUT(100 * 1000 * timeout);
1001 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1003 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
1004 ena_trc_err("Reg read timeout occurred\n");
1005 return ENA_COM_TIMER_EXPIRED;
1008 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
1012 if (ENA_TIME_EXPIRE(timeout_stamp))
1013 return ENA_COM_TIMER_EXPIRED;
1015 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1019 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
1020 enum ena_admin_aq_feature_id feature_id)
1022 u32 feature_mask = 1 << feature_id;
1024 /* Device attributes is always supported */
1025 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
1026 !(ena_dev->supported_features & feature_mask))
1032 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
1033 struct ena_admin_get_feat_resp *get_resp,
1034 enum ena_admin_aq_feature_id feature_id,
1035 dma_addr_t control_buf_dma_addr,
1036 u32 control_buff_size,
1039 struct ena_com_admin_queue *admin_queue;
1040 struct ena_admin_get_feat_cmd get_cmd;
1043 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
1044 ena_trc_dbg("Feature %d isn't supported\n", feature_id);
1045 return ENA_COM_UNSUPPORTED;
1048 memset(&get_cmd, 0x0, sizeof(get_cmd));
1049 admin_queue = &ena_dev->admin_queue;
1051 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1053 if (control_buff_size)
1054 get_cmd.aq_common_descriptor.flags =
1055 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1057 get_cmd.aq_common_descriptor.flags = 0;
1059 ret = ena_com_mem_addr_set(ena_dev,
1060 &get_cmd.control_buffer.address,
1061 control_buf_dma_addr);
1062 if (unlikely(ret)) {
1063 ena_trc_err("memory address set failed\n");
1067 get_cmd.control_buffer.length = control_buff_size;
1068 get_cmd.feat_common.feature_version = feature_ver;
1069 get_cmd.feat_common.feature_id = feature_id;
1071 ret = ena_com_execute_admin_command(admin_queue,
1072 (struct ena_admin_aq_entry *)
1075 (struct ena_admin_acq_entry *)
1080 ena_trc_err("Failed to submit get_feature command %d error: %d\n",
1086 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1087 struct ena_admin_get_feat_resp *get_resp,
1088 enum ena_admin_aq_feature_id feature_id,
1091 return ena_com_get_feature_ex(ena_dev,
1099 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1101 return ena_dev->rss.hash_func;
1104 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1106 struct ena_admin_feature_rss_flow_hash_control *hash_key =
1107 (ena_dev->rss).hash_key;
1109 ENA_RSS_FILL_KEY(&hash_key->key, sizeof(hash_key->key));
1110 /* The key buffer is stored in the device in an array of
1111 * uint32 elements. Therefore the number of elements can be derived
1112 * by dividing the buffer length by the size of each array element.
1113 * In current implementation each element is sized at uint32_t
1114 * so it's actually a division by 4 but if the element size changes,
1115 * there is no need to rewrite this code.
1117 hash_key->keys_num = sizeof(hash_key->key) / sizeof(hash_key->key[0]);
1120 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1122 struct ena_rss *rss = &ena_dev->rss;
1124 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION))
1125 return ENA_COM_UNSUPPORTED;
1127 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1128 sizeof(*rss->hash_key),
1130 rss->hash_key_dma_addr,
1131 rss->hash_key_mem_handle);
1133 if (unlikely(!rss->hash_key))
1134 return ENA_COM_NO_MEM;
1139 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1141 struct ena_rss *rss = &ena_dev->rss;
1144 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1145 sizeof(*rss->hash_key),
1147 rss->hash_key_dma_addr,
1148 rss->hash_key_mem_handle);
1149 rss->hash_key = NULL;
1152 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1154 struct ena_rss *rss = &ena_dev->rss;
1156 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1157 sizeof(*rss->hash_ctrl),
1159 rss->hash_ctrl_dma_addr,
1160 rss->hash_ctrl_mem_handle);
1162 if (unlikely(!rss->hash_ctrl))
1163 return ENA_COM_NO_MEM;
1168 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1170 struct ena_rss *rss = &ena_dev->rss;
1173 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1174 sizeof(*rss->hash_ctrl),
1176 rss->hash_ctrl_dma_addr,
1177 rss->hash_ctrl_mem_handle);
1178 rss->hash_ctrl = NULL;
1181 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1184 struct ena_rss *rss = &ena_dev->rss;
1185 struct ena_admin_get_feat_resp get_resp;
1189 ret = ena_com_get_feature(ena_dev, &get_resp,
1190 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
1194 if ((get_resp.u.ind_table.min_size > log_size) ||
1195 (get_resp.u.ind_table.max_size < log_size)) {
1196 ena_trc_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1198 1 << get_resp.u.ind_table.min_size,
1199 1 << get_resp.u.ind_table.max_size);
1200 return ENA_COM_INVAL;
1203 tbl_size = (1ULL << log_size) *
1204 sizeof(struct ena_admin_rss_ind_table_entry);
1206 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1209 rss->rss_ind_tbl_dma_addr,
1210 rss->rss_ind_tbl_mem_handle);
1211 if (unlikely(!rss->rss_ind_tbl))
1214 tbl_size = (1ULL << log_size) * sizeof(u16);
1215 rss->host_rss_ind_tbl =
1216 ENA_MEM_ALLOC(ena_dev->dmadev, tbl_size);
1217 if (unlikely(!rss->host_rss_ind_tbl))
1220 rss->tbl_log_size = log_size;
1225 tbl_size = (1ULL << log_size) *
1226 sizeof(struct ena_admin_rss_ind_table_entry);
1228 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1231 rss->rss_ind_tbl_dma_addr,
1232 rss->rss_ind_tbl_mem_handle);
1233 rss->rss_ind_tbl = NULL;
1235 rss->tbl_log_size = 0;
1236 return ENA_COM_NO_MEM;
1239 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1241 struct ena_rss *rss = &ena_dev->rss;
1242 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1243 sizeof(struct ena_admin_rss_ind_table_entry);
1245 if (rss->rss_ind_tbl)
1246 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1249 rss->rss_ind_tbl_dma_addr,
1250 rss->rss_ind_tbl_mem_handle);
1251 rss->rss_ind_tbl = NULL;
1253 if (rss->host_rss_ind_tbl)
1254 ENA_MEM_FREE(ena_dev->dmadev,
1255 rss->host_rss_ind_tbl,
1256 ((1ULL << rss->tbl_log_size) * sizeof(u16)));
1257 rss->host_rss_ind_tbl = NULL;
1260 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1261 struct ena_com_io_sq *io_sq, u16 cq_idx)
1263 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1264 struct ena_admin_aq_create_sq_cmd create_cmd;
1265 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1269 memset(&create_cmd, 0x0, sizeof(create_cmd));
1271 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1273 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1274 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1276 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1278 create_cmd.sq_identity |= (direction <<
1279 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1280 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1282 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1283 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1285 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1286 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1287 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1289 create_cmd.sq_caps_3 |=
1290 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1292 create_cmd.cq_idx = cq_idx;
1293 create_cmd.sq_depth = io_sq->q_depth;
1295 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1296 ret = ena_com_mem_addr_set(ena_dev,
1298 io_sq->desc_addr.phys_addr);
1299 if (unlikely(ret)) {
1300 ena_trc_err("memory address set failed\n");
1305 ret = ena_com_execute_admin_command(admin_queue,
1306 (struct ena_admin_aq_entry *)&create_cmd,
1308 (struct ena_admin_acq_entry *)&cmd_completion,
1309 sizeof(cmd_completion));
1310 if (unlikely(ret)) {
1311 ena_trc_err("Failed to create IO SQ. error: %d\n", ret);
1315 io_sq->idx = cmd_completion.sq_idx;
1317 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1318 (uintptr_t)cmd_completion.sq_doorbell_offset);
1320 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1321 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1322 + cmd_completion.llq_headers_offset);
1324 io_sq->desc_addr.pbuf_dev_addr =
1325 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1326 cmd_completion.llq_descriptors_offset);
1329 ena_trc_dbg("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth);
1334 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1336 struct ena_rss *rss = &ena_dev->rss;
1337 struct ena_com_io_sq *io_sq;
1341 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1342 qid = rss->host_rss_ind_tbl[i];
1343 if (qid >= ENA_TOTAL_NUM_QUEUES)
1344 return ENA_COM_INVAL;
1346 io_sq = &ena_dev->io_sq_queues[qid];
1348 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1349 return ENA_COM_INVAL;
1351 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1357 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1358 u16 intr_delay_resolution)
1360 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1362 if (unlikely(!intr_delay_resolution)) {
1363 ena_trc_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1364 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1368 ena_dev->intr_moder_rx_interval =
1369 ena_dev->intr_moder_rx_interval *
1370 prev_intr_delay_resolution /
1371 intr_delay_resolution;
1374 ena_dev->intr_moder_tx_interval =
1375 ena_dev->intr_moder_tx_interval *
1376 prev_intr_delay_resolution /
1377 intr_delay_resolution;
1379 ena_dev->intr_delay_resolution = intr_delay_resolution;
1382 /*****************************************************************************/
1383 /******************************* API ******************************/
1384 /*****************************************************************************/
1386 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1387 struct ena_admin_aq_entry *cmd,
1389 struct ena_admin_acq_entry *comp,
1392 struct ena_comp_ctx *comp_ctx;
1395 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1397 if (IS_ERR(comp_ctx)) {
1398 if (comp_ctx == ERR_PTR(ENA_COM_NO_DEVICE))
1399 ena_trc_dbg("Failed to submit command [%ld]\n",
1402 ena_trc_err("Failed to submit command [%ld]\n",
1405 return PTR_ERR(comp_ctx);
1408 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1409 if (unlikely(ret)) {
1410 if (admin_queue->running_state)
1411 ena_trc_err("Failed to process command. ret = %d\n",
1414 ena_trc_dbg("Failed to process command. ret = %d\n",
1420 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1421 struct ena_com_io_cq *io_cq)
1423 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1424 struct ena_admin_aq_create_cq_cmd create_cmd;
1425 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1428 memset(&create_cmd, 0x0, sizeof(create_cmd));
1430 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1432 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1433 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1434 create_cmd.cq_caps_1 |=
1435 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1437 create_cmd.msix_vector = io_cq->msix_vector;
1438 create_cmd.cq_depth = io_cq->q_depth;
1440 ret = ena_com_mem_addr_set(ena_dev,
1442 io_cq->cdesc_addr.phys_addr);
1443 if (unlikely(ret)) {
1444 ena_trc_err("memory address set failed\n");
1448 ret = ena_com_execute_admin_command(admin_queue,
1449 (struct ena_admin_aq_entry *)&create_cmd,
1451 (struct ena_admin_acq_entry *)&cmd_completion,
1452 sizeof(cmd_completion));
1453 if (unlikely(ret)) {
1454 ena_trc_err("Failed to create IO CQ. error: %d\n", ret);
1458 io_cq->idx = cmd_completion.cq_idx;
1460 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1461 cmd_completion.cq_interrupt_unmask_register_offset);
1463 if (cmd_completion.cq_head_db_register_offset)
1464 io_cq->cq_head_db_reg =
1465 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1466 cmd_completion.cq_head_db_register_offset);
1468 if (cmd_completion.numa_node_register_offset)
1469 io_cq->numa_node_cfg_reg =
1470 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1471 cmd_completion.numa_node_register_offset);
1473 ena_trc_dbg("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth);
1478 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1479 struct ena_com_io_sq **io_sq,
1480 struct ena_com_io_cq **io_cq)
1482 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1483 ena_trc_err("Invalid queue number %d but the max is %d\n",
1484 qid, ENA_TOTAL_NUM_QUEUES);
1485 return ENA_COM_INVAL;
1488 *io_sq = &ena_dev->io_sq_queues[qid];
1489 *io_cq = &ena_dev->io_cq_queues[qid];
1494 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1496 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1497 struct ena_comp_ctx *comp_ctx;
1500 if (!admin_queue->comp_ctx)
1503 for (i = 0; i < admin_queue->q_depth; i++) {
1504 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1505 if (unlikely(!comp_ctx))
1508 comp_ctx->status = ENA_CMD_ABORTED;
1510 ENA_WAIT_EVENT_SIGNAL(comp_ctx->wait_event);
1514 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1516 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1517 unsigned long flags = 0;
1520 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1521 while (ATOMIC32_READ(&admin_queue->outstanding_cmds) != 0) {
1522 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1523 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1524 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1526 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1529 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1530 struct ena_com_io_cq *io_cq)
1532 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1533 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1534 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1537 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1539 destroy_cmd.cq_idx = io_cq->idx;
1540 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1542 ret = ena_com_execute_admin_command(admin_queue,
1543 (struct ena_admin_aq_entry *)&destroy_cmd,
1544 sizeof(destroy_cmd),
1545 (struct ena_admin_acq_entry *)&destroy_resp,
1546 sizeof(destroy_resp));
1548 if (unlikely(ret && (ret != ENA_COM_NO_DEVICE)))
1549 ena_trc_err("Failed to destroy IO CQ. error: %d\n", ret);
1554 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1556 return ena_dev->admin_queue.running_state;
1559 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1561 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1562 unsigned long flags = 0;
1564 ENA_SPINLOCK_LOCK(admin_queue->q_lock, flags);
1565 ena_dev->admin_queue.running_state = state;
1566 ENA_SPINLOCK_UNLOCK(admin_queue->q_lock, flags);
1569 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1571 u16 depth = ena_dev->aenq.q_depth;
1573 ENA_WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1575 /* Init head_db to mark that all entries in the queue
1576 * are initially available
1578 ENA_REG_WRITE32(ena_dev->bus, depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1581 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1583 struct ena_com_admin_queue *admin_queue;
1584 struct ena_admin_set_feat_cmd cmd;
1585 struct ena_admin_set_feat_resp resp;
1586 struct ena_admin_get_feat_resp get_resp;
1589 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1591 ena_trc_info("Can't get aenq configuration\n");
1595 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1596 ena_trc_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1597 get_resp.u.aenq.supported_groups,
1599 return ENA_COM_UNSUPPORTED;
1602 memset(&cmd, 0x0, sizeof(cmd));
1603 admin_queue = &ena_dev->admin_queue;
1605 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1606 cmd.aq_common_descriptor.flags = 0;
1607 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1608 cmd.u.aenq.enabled_groups = groups_flag;
1610 ret = ena_com_execute_admin_command(admin_queue,
1611 (struct ena_admin_aq_entry *)&cmd,
1613 (struct ena_admin_acq_entry *)&resp,
1617 ena_trc_err("Failed to config AENQ ret: %d\n", ret);
1622 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1624 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1627 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1628 ena_trc_err("Reg read timeout occurred\n");
1629 return ENA_COM_TIMER_EXPIRED;
1632 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1633 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1635 ena_trc_dbg("ENA dma width: %d\n", width);
1637 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1638 ena_trc_err("DMA width illegal value: %d\n", width);
1639 return ENA_COM_INVAL;
1642 ena_dev->dma_addr_bits = width;
1647 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1651 u32 ctrl_ver_masked;
1653 /* Make sure the ENA version and the controller version are at least
1654 * as the driver expects
1656 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1657 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1658 ENA_REGS_CONTROLLER_VERSION_OFF);
1660 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1661 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1662 ena_trc_err("Reg read timeout occurred\n");
1663 return ENA_COM_TIMER_EXPIRED;
1666 ena_trc_info("ena device version: %d.%d\n",
1667 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1668 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1669 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1671 ena_trc_info("ena controller version: %d.%d.%d implementation version %d\n",
1672 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK)
1673 >> ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1674 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK)
1675 >> ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1676 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1677 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1678 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1681 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1682 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1683 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1685 /* Validate the ctrl version without the implementation ID */
1686 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1687 ena_trc_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1694 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1696 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1697 struct ena_com_admin_cq *cq = &admin_queue->cq;
1698 struct ena_com_admin_sq *sq = &admin_queue->sq;
1699 struct ena_com_aenq *aenq = &ena_dev->aenq;
1702 ENA_WAIT_EVENT_DESTROY(admin_queue->comp_ctx->wait_event);
1703 if (admin_queue->comp_ctx)
1704 ENA_MEM_FREE(ena_dev->dmadev,
1705 admin_queue->comp_ctx,
1706 (admin_queue->q_depth * sizeof(struct ena_comp_ctx)));
1707 admin_queue->comp_ctx = NULL;
1708 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1710 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, sq->entries,
1711 sq->dma_addr, sq->mem_handle);
1714 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1716 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, cq->entries,
1717 cq->dma_addr, cq->mem_handle);
1720 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1721 if (ena_dev->aenq.entries)
1722 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, size, aenq->entries,
1723 aenq->dma_addr, aenq->mem_handle);
1724 aenq->entries = NULL;
1725 ENA_SPINLOCK_DESTROY(admin_queue->q_lock);
1728 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1733 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1735 ENA_REG_WRITE32(ena_dev->bus, mask_value,
1736 ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1737 ena_dev->admin_queue.polling = polling;
1740 bool ena_com_get_admin_polling_mode(struct ena_com_dev *ena_dev)
1742 return ena_dev->admin_queue.polling;
1745 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1748 ena_dev->admin_queue.auto_polling = polling;
1751 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1753 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1755 ENA_SPINLOCK_INIT(mmio_read->lock);
1756 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
1757 sizeof(*mmio_read->read_resp),
1758 mmio_read->read_resp,
1759 mmio_read->read_resp_dma_addr,
1760 mmio_read->read_resp_mem_handle);
1761 if (unlikely(!mmio_read->read_resp))
1764 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1766 mmio_read->read_resp->req_id = 0x0;
1767 mmio_read->seq_num = 0x0;
1768 mmio_read->readless_supported = true;
1773 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1774 return ENA_COM_NO_MEM;
1777 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1779 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1781 mmio_read->readless_supported = readless_supported;
1784 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1786 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1788 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1789 ENA_REG_WRITE32(ena_dev->bus, 0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1791 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
1792 sizeof(*mmio_read->read_resp),
1793 mmio_read->read_resp,
1794 mmio_read->read_resp_dma_addr,
1795 mmio_read->read_resp_mem_handle);
1797 mmio_read->read_resp = NULL;
1798 ENA_SPINLOCK_DESTROY(mmio_read->lock);
1801 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1803 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1804 u32 addr_low, addr_high;
1806 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1807 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1809 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1810 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1813 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1814 struct ena_aenq_handlers *aenq_handlers)
1816 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1817 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1820 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1822 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1823 ena_trc_err("Reg read timeout occurred\n");
1824 return ENA_COM_TIMER_EXPIRED;
1827 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1828 ena_trc_err("Device isn't ready, abort com init\n");
1829 return ENA_COM_NO_DEVICE;
1832 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1834 admin_queue->bus = ena_dev->bus;
1835 admin_queue->q_dmadev = ena_dev->dmadev;
1836 admin_queue->polling = false;
1837 admin_queue->curr_cmd_id = 0;
1839 ATOMIC32_SET(&admin_queue->outstanding_cmds, 0);
1841 ENA_SPINLOCK_INIT(admin_queue->q_lock);
1843 ret = ena_com_init_comp_ctxt(admin_queue);
1847 ret = ena_com_admin_init_sq(admin_queue);
1851 ret = ena_com_admin_init_cq(admin_queue);
1855 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1856 ENA_REGS_AQ_DB_OFF);
1858 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1859 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1861 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1862 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1864 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1865 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1867 ENA_REG_WRITE32(ena_dev->bus, addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1868 ENA_REG_WRITE32(ena_dev->bus, addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1871 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1872 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1873 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1874 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1877 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1878 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1879 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1880 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1882 ENA_REG_WRITE32(ena_dev->bus, aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1883 ENA_REG_WRITE32(ena_dev->bus, acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1884 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1888 admin_queue->ena_dev = ena_dev;
1889 admin_queue->running_state = true;
1893 ena_com_admin_destroy(ena_dev);
1898 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1899 struct ena_com_create_io_ctx *ctx)
1901 struct ena_com_io_sq *io_sq;
1902 struct ena_com_io_cq *io_cq;
1905 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1906 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1907 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1908 return ENA_COM_INVAL;
1911 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1912 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1914 memset(io_sq, 0x0, sizeof(*io_sq));
1915 memset(io_cq, 0x0, sizeof(*io_cq));
1918 io_cq->q_depth = ctx->queue_size;
1919 io_cq->direction = ctx->direction;
1920 io_cq->qid = ctx->qid;
1922 io_cq->msix_vector = ctx->msix_vector;
1924 io_sq->q_depth = ctx->queue_size;
1925 io_sq->direction = ctx->direction;
1926 io_sq->qid = ctx->qid;
1928 io_sq->mem_queue_type = ctx->mem_queue_type;
1930 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1931 /* header length is limited to 8 bits */
1932 io_sq->tx_max_header_size =
1933 ENA_MIN32(ena_dev->tx_max_header_size, SZ_256);
1935 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1938 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1942 ret = ena_com_create_io_cq(ena_dev, io_cq);
1946 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1953 ena_com_destroy_io_cq(ena_dev, io_cq);
1955 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1959 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1961 struct ena_com_io_sq *io_sq;
1962 struct ena_com_io_cq *io_cq;
1964 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1965 ena_trc_err("Qid (%d) is bigger than max num of queues (%d)\n",
1966 qid, ENA_TOTAL_NUM_QUEUES);
1970 io_sq = &ena_dev->io_sq_queues[qid];
1971 io_cq = &ena_dev->io_cq_queues[qid];
1973 ena_com_destroy_io_sq(ena_dev, io_sq);
1974 ena_com_destroy_io_cq(ena_dev, io_cq);
1976 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1979 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1980 struct ena_admin_get_feat_resp *resp)
1982 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1985 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1986 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1988 struct ena_admin_get_feat_resp get_resp;
1991 rc = ena_com_get_feature(ena_dev, &get_resp,
1992 ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1996 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1997 sizeof(get_resp.u.dev_attr));
1998 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
2000 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
2001 rc = ena_com_get_feature(ena_dev, &get_resp,
2002 ENA_ADMIN_MAX_QUEUES_EXT,
2003 ENA_FEATURE_MAX_QUEUE_EXT_VER);
2007 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER)
2010 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
2011 sizeof(get_resp.u.max_queue_ext));
2012 ena_dev->tx_max_header_size =
2013 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
2015 rc = ena_com_get_feature(ena_dev, &get_resp,
2016 ENA_ADMIN_MAX_QUEUES_NUM, 0);
2017 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
2018 sizeof(get_resp.u.max_queue));
2019 ena_dev->tx_max_header_size =
2020 get_resp.u.max_queue.max_header_size;
2026 rc = ena_com_get_feature(ena_dev, &get_resp,
2027 ENA_ADMIN_AENQ_CONFIG, 0);
2031 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
2032 sizeof(get_resp.u.aenq));
2034 rc = ena_com_get_feature(ena_dev, &get_resp,
2035 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2039 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
2040 sizeof(get_resp.u.offload));
2042 /* Driver hints isn't mandatory admin command. So in case the
2043 * command isn't supported set driver hints to 0
2045 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2048 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
2049 sizeof(get_resp.u.hw_hints));
2050 else if (rc == ENA_COM_UNSUPPORTED)
2051 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints));
2055 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2057 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
2058 sizeof(get_resp.u.llq));
2059 else if (rc == ENA_COM_UNSUPPORTED)
2060 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2064 rc = ena_com_get_feature(ena_dev, &get_resp,
2065 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0);
2067 memcpy(&get_feat_ctx->ind_table, &get_resp.u.ind_table,
2068 sizeof(get_resp.u.ind_table));
2069 else if (rc == ENA_COM_UNSUPPORTED)
2070 memset(&get_feat_ctx->ind_table, 0x0,
2071 sizeof(get_feat_ctx->ind_table));
2078 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2080 ena_com_handle_admin_completion(&ena_dev->admin_queue);
2083 /* ena_handle_specific_aenq_event:
2084 * return the handler that is relevant to the specific event group
2086 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev,
2089 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers;
2091 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2092 return aenq_handlers->handlers[group];
2094 return aenq_handlers->unimplemented_handler;
2097 /* ena_aenq_intr_handler:
2098 * handles the aenq incoming events.
2099 * pop events from the queue and apply the specific handler
2101 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data)
2103 struct ena_admin_aenq_entry *aenq_e;
2104 struct ena_admin_aenq_common_desc *aenq_common;
2105 struct ena_com_aenq *aenq = &dev->aenq;
2107 ena_aenq_handler handler_cb;
2108 u16 masked_head, processed = 0;
2111 masked_head = aenq->head & (aenq->q_depth - 1);
2112 phase = aenq->phase;
2113 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2114 aenq_common = &aenq_e->aenq_common_desc;
2116 /* Go over all the events */
2117 while ((READ_ONCE8(aenq_common->flags) &
2118 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2119 /* Make sure the phase bit (ownership) is as expected before
2120 * reading the rest of the descriptor.
2124 timestamp = (u64)aenq_common->timestamp_low |
2125 ((u64)aenq_common->timestamp_high << 32);
2126 ena_trc_dbg("AENQ! Group[%x] Syndrom[%x] timestamp: [%" ENA_PRIu64 "s]\n",
2128 aenq_common->syndrom,
2131 /* Handle specific event*/
2132 handler_cb = ena_com_get_specific_aenq_cb(dev,
2133 aenq_common->group);
2134 handler_cb(data, aenq_e); /* call the actual event handler*/
2136 /* Get next event entry */
2140 if (unlikely(masked_head == aenq->q_depth)) {
2144 aenq_e = &aenq->entries[masked_head];
2145 aenq_common = &aenq_e->aenq_common_desc;
2148 aenq->head += processed;
2149 aenq->phase = phase;
2151 /* Don't update aenq doorbell if there weren't any processed events */
2155 /* write the aenq doorbell after all AENQ descriptors were read */
2157 ENA_REG_WRITE32_RELAXED(dev->bus, (u32)aenq->head,
2158 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2161 #ifdef ENA_EXTENDED_STATS
2163 * Sets the function Idx and Queue Idx to be used for
2164 * get full statistics feature
2167 int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
2171 /* Function & Queue is acquired from user in the following format :
2172 * Bottom Half word: funct
2173 * Top Half Word: queue
2175 ena_dev->stats_func = ENA_EXTENDED_STAT_GET_FUNCT(func_queue);
2176 ena_dev->stats_queue = ENA_EXTENDED_STAT_GET_QUEUE(func_queue);
2181 #endif /* ENA_EXTENDED_STATS */
2183 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2184 enum ena_regs_reset_reason_types reset_reason)
2186 u32 stat, timeout, cap, reset_val;
2189 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2190 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2192 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2193 (cap == ENA_MMIO_READ_TIMEOUT))) {
2194 ena_trc_err("Reg read32 timeout occurred\n");
2195 return ENA_COM_TIMER_EXPIRED;
2198 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2199 ena_trc_err("Device isn't ready, can't reset device\n");
2200 return ENA_COM_INVAL;
2203 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2204 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2206 ena_trc_err("Invalid timeout value\n");
2207 return ENA_COM_INVAL;
2211 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2212 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2213 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2214 ENA_REG_WRITE32(ena_dev->bus, reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2216 /* Write again the MMIO read request address */
2217 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2219 rc = wait_for_reset_state(ena_dev, timeout,
2220 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2222 ena_trc_err("Reset indication didn't turn on\n");
2227 ENA_REG_WRITE32(ena_dev->bus, 0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2228 rc = wait_for_reset_state(ena_dev, timeout, 0);
2230 ena_trc_err("Reset indication didn't turn off\n");
2234 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2235 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2237 /* the resolution of timeout reg is 100ms */
2238 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2240 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2245 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2246 struct ena_com_stats_ctx *ctx,
2247 enum ena_admin_get_stats_type type)
2249 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2250 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2251 struct ena_com_admin_queue *admin_queue;
2254 admin_queue = &ena_dev->admin_queue;
2256 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2257 get_cmd->aq_common_descriptor.flags = 0;
2258 get_cmd->type = type;
2260 ret = ena_com_execute_admin_command(admin_queue,
2261 (struct ena_admin_aq_entry *)get_cmd,
2263 (struct ena_admin_acq_entry *)get_resp,
2267 ena_trc_err("Failed to get stats. error: %d\n", ret);
2272 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2273 struct ena_admin_basic_stats *stats)
2275 struct ena_com_stats_ctx ctx;
2278 memset(&ctx, 0x0, sizeof(ctx));
2279 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2280 if (likely(ret == 0))
2281 memcpy(stats, &ctx.get_resp.basic_stats,
2282 sizeof(ctx.get_resp.basic_stats));
2286 #ifdef ENA_EXTENDED_STATS
2288 int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
2291 struct ena_com_stats_ctx ctx;
2292 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx.get_cmd;
2293 ena_mem_handle_t mem_handle;
2295 dma_addr_t phys_addr;
2298 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev, len,
2299 virt_addr, phys_addr, mem_handle);
2301 ret = ENA_COM_NO_MEM;
2304 memset(&ctx, 0x0, sizeof(ctx));
2305 ret = ena_com_mem_addr_set(ena_dev,
2306 &get_cmd->u.control_buffer.address,
2308 if (unlikely(ret)) {
2309 ena_trc_err("memory address set failed\n");
2310 goto free_ext_stats_mem;
2312 get_cmd->u.control_buffer.length = len;
2314 get_cmd->device_id = ena_dev->stats_func;
2315 get_cmd->queue_idx = ena_dev->stats_queue;
2317 ret = ena_get_dev_stats(ena_dev, &ctx,
2318 ENA_ADMIN_GET_STATS_TYPE_EXTENDED);
2320 goto free_ext_stats_mem;
2322 ret = snprintf(buff, len, "%s", (char *)virt_addr);
2325 ENA_MEM_FREE_COHERENT(ena_dev->dmadev, len, virt_addr, phys_addr,
2332 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu)
2334 struct ena_com_admin_queue *admin_queue;
2335 struct ena_admin_set_feat_cmd cmd;
2336 struct ena_admin_set_feat_resp resp;
2339 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2340 ena_trc_dbg("Feature %d isn't supported\n", ENA_ADMIN_MTU);
2341 return ENA_COM_UNSUPPORTED;
2344 memset(&cmd, 0x0, sizeof(cmd));
2345 admin_queue = &ena_dev->admin_queue;
2347 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2348 cmd.aq_common_descriptor.flags = 0;
2349 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2350 cmd.u.mtu.mtu = mtu;
2352 ret = ena_com_execute_admin_command(admin_queue,
2353 (struct ena_admin_aq_entry *)&cmd,
2355 (struct ena_admin_acq_entry *)&resp,
2359 ena_trc_err("Failed to set mtu %d. error: %d\n", mtu, ret);
2364 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2365 struct ena_admin_feature_offload_desc *offload)
2368 struct ena_admin_get_feat_resp resp;
2370 ret = ena_com_get_feature(ena_dev, &resp,
2371 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2372 if (unlikely(ret)) {
2373 ena_trc_err("Failed to get offload capabilities %d\n", ret);
2377 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2382 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2384 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2385 struct ena_rss *rss = &ena_dev->rss;
2386 struct ena_admin_set_feat_cmd cmd;
2387 struct ena_admin_set_feat_resp resp;
2388 struct ena_admin_get_feat_resp get_resp;
2391 if (!ena_com_check_supported_feature_id(ena_dev,
2392 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2393 ena_trc_dbg("Feature %d isn't supported\n",
2394 ENA_ADMIN_RSS_HASH_FUNCTION);
2395 return ENA_COM_UNSUPPORTED;
2398 /* Validate hash function is supported */
2399 ret = ena_com_get_feature(ena_dev, &get_resp,
2400 ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2404 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2405 ena_trc_err("Func hash %d isn't supported by device, abort\n",
2407 return ENA_COM_UNSUPPORTED;
2410 memset(&cmd, 0x0, sizeof(cmd));
2412 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2413 cmd.aq_common_descriptor.flags =
2414 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2415 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2416 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2417 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2419 ret = ena_com_mem_addr_set(ena_dev,
2420 &cmd.control_buffer.address,
2421 rss->hash_key_dma_addr);
2422 if (unlikely(ret)) {
2423 ena_trc_err("memory address set failed\n");
2427 cmd.control_buffer.length = sizeof(*rss->hash_key);
2429 ret = ena_com_execute_admin_command(admin_queue,
2430 (struct ena_admin_aq_entry *)&cmd,
2432 (struct ena_admin_acq_entry *)&resp,
2434 if (unlikely(ret)) {
2435 ena_trc_err("Failed to set hash function %d. error: %d\n",
2436 rss->hash_func, ret);
2437 return ENA_COM_INVAL;
2443 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2444 enum ena_admin_hash_functions func,
2445 const u8 *key, u16 key_len, u32 init_val)
2447 struct ena_admin_feature_rss_flow_hash_control *hash_key;
2448 struct ena_admin_get_feat_resp get_resp;
2449 enum ena_admin_hash_functions old_func;
2450 struct ena_rss *rss = &ena_dev->rss;
2453 hash_key = rss->hash_key;
2455 /* Make sure size is a mult of DWs */
2456 if (unlikely(key_len & 0x3))
2457 return ENA_COM_INVAL;
2459 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2460 ENA_ADMIN_RSS_HASH_FUNCTION,
2461 rss->hash_key_dma_addr,
2462 sizeof(*rss->hash_key), 0);
2466 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2467 ena_trc_err("Flow hash function %d isn't supported\n", func);
2468 return ENA_COM_UNSUPPORTED;
2472 case ENA_ADMIN_TOEPLITZ:
2474 if (key_len != sizeof(hash_key->key)) {
2475 ena_trc_err("key len (%hu) doesn't equal the supported size (%zu)\n",
2476 key_len, sizeof(hash_key->key));
2477 return ENA_COM_INVAL;
2479 memcpy(hash_key->key, key, key_len);
2480 rss->hash_init_val = init_val;
2481 hash_key->keys_num = key_len / sizeof(hash_key->key[0]);
2484 case ENA_ADMIN_CRC32:
2485 rss->hash_init_val = init_val;
2488 ena_trc_err("Invalid hash function (%d)\n", func);
2489 return ENA_COM_INVAL;
2492 old_func = rss->hash_func;
2493 rss->hash_func = func;
2494 rc = ena_com_set_hash_function(ena_dev);
2496 /* Restore the old function */
2498 rss->hash_func = old_func;
2503 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2504 enum ena_admin_hash_functions *func)
2506 struct ena_rss *rss = &ena_dev->rss;
2507 struct ena_admin_get_feat_resp get_resp;
2510 if (unlikely(!func))
2511 return ENA_COM_INVAL;
2513 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2514 ENA_ADMIN_RSS_HASH_FUNCTION,
2515 rss->hash_key_dma_addr,
2516 sizeof(*rss->hash_key), 0);
2520 /* ENA_FFS() returns 1 in case the lsb is set */
2521 rss->hash_func = ENA_FFS(get_resp.u.flow_hash_func.selected_func);
2525 *func = rss->hash_func;
2530 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2532 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2533 ena_dev->rss.hash_key;
2536 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2);
2541 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2542 enum ena_admin_flow_hash_proto proto,
2545 struct ena_rss *rss = &ena_dev->rss;
2546 struct ena_admin_get_feat_resp get_resp;
2549 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2550 ENA_ADMIN_RSS_HASH_INPUT,
2551 rss->hash_ctrl_dma_addr,
2552 sizeof(*rss->hash_ctrl), 0);
2557 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2562 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2564 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2565 struct ena_rss *rss = &ena_dev->rss;
2566 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2567 struct ena_admin_set_feat_cmd cmd;
2568 struct ena_admin_set_feat_resp resp;
2571 if (!ena_com_check_supported_feature_id(ena_dev,
2572 ENA_ADMIN_RSS_HASH_INPUT)) {
2573 ena_trc_dbg("Feature %d isn't supported\n",
2574 ENA_ADMIN_RSS_HASH_INPUT);
2575 return ENA_COM_UNSUPPORTED;
2578 memset(&cmd, 0x0, sizeof(cmd));
2580 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2581 cmd.aq_common_descriptor.flags =
2582 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2583 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2584 cmd.u.flow_hash_input.enabled_input_sort =
2585 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2586 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2588 ret = ena_com_mem_addr_set(ena_dev,
2589 &cmd.control_buffer.address,
2590 rss->hash_ctrl_dma_addr);
2591 if (unlikely(ret)) {
2592 ena_trc_err("memory address set failed\n");
2595 cmd.control_buffer.length = sizeof(*hash_ctrl);
2597 ret = ena_com_execute_admin_command(admin_queue,
2598 (struct ena_admin_aq_entry *)&cmd,
2600 (struct ena_admin_acq_entry *)&resp,
2603 ena_trc_err("Failed to set hash input. error: %d\n", ret);
2608 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2610 struct ena_rss *rss = &ena_dev->rss;
2611 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2613 u16 available_fields = 0;
2616 /* Get the supported hash input */
2617 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2621 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2622 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2623 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2625 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2626 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2627 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2629 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2630 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2631 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2633 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2634 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2635 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2637 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2638 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2640 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2641 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2643 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2644 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2646 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2647 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2649 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2650 available_fields = hash_ctrl->selected_fields[i].fields &
2651 hash_ctrl->supported_fields[i].fields;
2652 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2653 ena_trc_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2654 i, hash_ctrl->supported_fields[i].fields,
2655 hash_ctrl->selected_fields[i].fields);
2656 return ENA_COM_UNSUPPORTED;
2660 rc = ena_com_set_hash_ctrl(ena_dev);
2662 /* In case of failure, restore the old hash ctrl */
2664 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2669 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2670 enum ena_admin_flow_hash_proto proto,
2673 struct ena_rss *rss = &ena_dev->rss;
2674 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2675 u16 supported_fields;
2678 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2679 ena_trc_err("Invalid proto num (%u)\n", proto);
2680 return ENA_COM_INVAL;
2683 /* Get the ctrl table */
2684 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2688 /* Make sure all the fields are supported */
2689 supported_fields = hash_ctrl->supported_fields[proto].fields;
2690 if ((hash_fields & supported_fields) != hash_fields) {
2691 ena_trc_err("proto %d doesn't support the required fields %x. supports only: %x\n",
2692 proto, hash_fields, supported_fields);
2695 hash_ctrl->selected_fields[proto].fields = hash_fields;
2697 rc = ena_com_set_hash_ctrl(ena_dev);
2699 /* In case of failure, restore the old hash ctrl */
2701 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2706 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2707 u16 entry_idx, u16 entry_value)
2709 struct ena_rss *rss = &ena_dev->rss;
2711 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2712 return ENA_COM_INVAL;
2714 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2715 return ENA_COM_INVAL;
2717 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2722 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2724 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2725 struct ena_rss *rss = &ena_dev->rss;
2726 struct ena_admin_set_feat_cmd cmd;
2727 struct ena_admin_set_feat_resp resp;
2730 if (!ena_com_check_supported_feature_id(ena_dev,
2731 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) {
2732 ena_trc_dbg("Feature %d isn't supported\n",
2733 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG);
2734 return ENA_COM_UNSUPPORTED;
2737 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2739 ena_trc_err("Failed to convert host indirection table to device table\n");
2743 memset(&cmd, 0x0, sizeof(cmd));
2745 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2746 cmd.aq_common_descriptor.flags =
2747 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2748 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG;
2749 cmd.u.ind_table.size = rss->tbl_log_size;
2750 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2752 ret = ena_com_mem_addr_set(ena_dev,
2753 &cmd.control_buffer.address,
2754 rss->rss_ind_tbl_dma_addr);
2755 if (unlikely(ret)) {
2756 ena_trc_err("memory address set failed\n");
2760 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2761 sizeof(struct ena_admin_rss_ind_table_entry);
2763 ret = ena_com_execute_admin_command(admin_queue,
2764 (struct ena_admin_aq_entry *)&cmd,
2766 (struct ena_admin_acq_entry *)&resp,
2770 ena_trc_err("Failed to set indirect table. error: %d\n", ret);
2775 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2777 struct ena_rss *rss = &ena_dev->rss;
2778 struct ena_admin_get_feat_resp get_resp;
2782 tbl_size = (1ULL << rss->tbl_log_size) *
2783 sizeof(struct ena_admin_rss_ind_table_entry);
2785 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2786 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG,
2787 rss->rss_ind_tbl_dma_addr,
2795 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2796 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2801 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2805 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2807 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2811 /* The following function might return unsupported in case the
2812 * device doesn't support setting the key / hash function. We can safely
2813 * ignore this error and have indirection table support only.
2815 rc = ena_com_hash_key_allocate(ena_dev);
2817 ena_com_hash_key_fill_default_key(ena_dev);
2818 else if (rc != ENA_COM_UNSUPPORTED)
2821 rc = ena_com_hash_ctrl_init(ena_dev);
2828 ena_com_hash_key_destroy(ena_dev);
2830 ena_com_indirect_table_destroy(ena_dev);
2836 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2838 ena_com_indirect_table_destroy(ena_dev);
2839 ena_com_hash_key_destroy(ena_dev);
2840 ena_com_hash_ctrl_destroy(ena_dev);
2842 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2845 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2847 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2849 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2851 host_attr->host_info,
2852 host_attr->host_info_dma_addr,
2853 host_attr->host_info_dma_handle);
2854 if (unlikely(!host_attr->host_info))
2855 return ENA_COM_NO_MEM;
2857 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2858 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2859 (ENA_COMMON_SPEC_VERSION_MINOR));
2864 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2865 u32 debug_area_size)
2867 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2869 ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
2871 host_attr->debug_area_virt_addr,
2872 host_attr->debug_area_dma_addr,
2873 host_attr->debug_area_dma_handle);
2874 if (unlikely(!host_attr->debug_area_virt_addr)) {
2875 host_attr->debug_area_size = 0;
2876 return ENA_COM_NO_MEM;
2879 host_attr->debug_area_size = debug_area_size;
2884 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2886 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2888 if (host_attr->host_info) {
2889 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2891 host_attr->host_info,
2892 host_attr->host_info_dma_addr,
2893 host_attr->host_info_dma_handle);
2894 host_attr->host_info = NULL;
2898 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2900 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2902 if (host_attr->debug_area_virt_addr) {
2903 ENA_MEM_FREE_COHERENT(ena_dev->dmadev,
2904 host_attr->debug_area_size,
2905 host_attr->debug_area_virt_addr,
2906 host_attr->debug_area_dma_addr,
2907 host_attr->debug_area_dma_handle);
2908 host_attr->debug_area_virt_addr = NULL;
2912 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2914 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2915 struct ena_com_admin_queue *admin_queue;
2916 struct ena_admin_set_feat_cmd cmd;
2917 struct ena_admin_set_feat_resp resp;
2921 /* Host attribute config is called before ena_com_get_dev_attr_feat
2922 * so ena_com can't check if the feature is supported.
2925 memset(&cmd, 0x0, sizeof(cmd));
2926 admin_queue = &ena_dev->admin_queue;
2928 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2929 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2931 ret = ena_com_mem_addr_set(ena_dev,
2932 &cmd.u.host_attr.debug_ba,
2933 host_attr->debug_area_dma_addr);
2934 if (unlikely(ret)) {
2935 ena_trc_err("memory address set failed\n");
2939 ret = ena_com_mem_addr_set(ena_dev,
2940 &cmd.u.host_attr.os_info_ba,
2941 host_attr->host_info_dma_addr);
2942 if (unlikely(ret)) {
2943 ena_trc_err("memory address set failed\n");
2947 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2949 ret = ena_com_execute_admin_command(admin_queue,
2950 (struct ena_admin_aq_entry *)&cmd,
2952 (struct ena_admin_acq_entry *)&resp,
2956 ena_trc_err("Failed to set host attributes: %d\n", ret);
2961 /* Interrupt moderation */
2962 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2964 return ena_com_check_supported_feature_id(ena_dev,
2965 ENA_ADMIN_INTERRUPT_MODERATION);
2968 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs,
2969 u32 intr_delay_resolution,
2970 u32 *intr_moder_interval)
2972 if (!intr_delay_resolution) {
2973 ena_trc_err("Illegal interrupt delay granularity value\n");
2974 return ENA_COM_FAULT;
2977 *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2983 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2984 u32 tx_coalesce_usecs)
2986 return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs,
2987 ena_dev->intr_delay_resolution,
2988 &ena_dev->intr_moder_tx_interval);
2991 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2992 u32 rx_coalesce_usecs)
2994 return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs,
2995 ena_dev->intr_delay_resolution,
2996 &ena_dev->intr_moder_rx_interval);
2999 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
3001 struct ena_admin_get_feat_resp get_resp;
3002 u16 delay_resolution;
3005 rc = ena_com_get_feature(ena_dev, &get_resp,
3006 ENA_ADMIN_INTERRUPT_MODERATION, 0);
3009 if (rc == ENA_COM_UNSUPPORTED) {
3010 ena_trc_dbg("Feature %d isn't supported\n",
3011 ENA_ADMIN_INTERRUPT_MODERATION);
3014 ena_trc_err("Failed to get interrupt moderation admin cmd. rc: %d\n",
3018 /* no moderation supported, disable adaptive support */
3019 ena_com_disable_adaptive_moderation(ena_dev);
3023 /* if moderation is supported by device we set adaptive moderation */
3024 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
3025 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
3027 /* Disable adaptive moderation by default - can be enabled later */
3028 ena_com_disable_adaptive_moderation(ena_dev);
3033 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
3035 return ena_dev->intr_moder_tx_interval;
3038 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
3040 return ena_dev->intr_moder_rx_interval;
3043 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
3044 struct ena_admin_feature_llq_desc *llq_features,
3045 struct ena_llq_configurations *llq_default_cfg)
3047 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
3050 if (!llq_features->max_llq_num) {
3051 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
3055 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
3059 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
3060 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
3062 if (unlikely(ena_dev->tx_max_header_size == 0)) {
3063 ena_trc_err("the size of the LLQ entry is smaller than needed\n");
3067 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;