4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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34 #ifndef ENA_ETH_COM_H_
35 #define ENA_ETH_COM_H_
37 #if defined(__cplusplus)
42 /* head update threshold in units of (queue size / ENA_COMP_HEAD_THRESH) */
43 #define ENA_COMP_HEAD_THRESH 4
45 struct ena_com_tx_ctx {
46 struct ena_com_tx_meta ena_meta;
47 struct ena_com_buf *ena_bufs;
48 /* For LLQ, header buffer - pushed to the device mem space */
51 enum ena_eth_io_l3_proto_index l3_proto;
52 enum ena_eth_io_l4_proto_index l4_proto;
55 /* For regular queue, indicate the size of the header
56 * For LLQ, indicate the size of the pushed buffer
65 u8 df; /* Don't fragment */
68 struct ena_com_rx_ctx {
69 struct ena_com_rx_buf_info *ena_bufs;
70 enum ena_eth_io_l3_proto_index l3_proto;
71 enum ena_eth_io_l4_proto_index l4_proto;
74 /* fragmented packet */
81 int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
82 struct ena_com_tx_ctx *ena_tx_ctx,
85 int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
86 struct ena_com_io_sq *io_sq,
87 struct ena_com_rx_ctx *ena_rx_ctx);
89 int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
90 struct ena_com_buf *ena_buf,
93 int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);
95 static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
96 struct ena_eth_io_intr_reg *intr_reg)
98 ENA_REG_WRITE32(io_cq->bus, intr_reg->intr_control, io_cq->unmask_reg);
101 static inline int ena_com_free_desc(struct ena_com_io_sq *io_sq)
103 u16 tail, next_to_comp, cnt;
105 next_to_comp = io_sq->next_to_comp;
107 cnt = tail - next_to_comp;
109 return io_sq->q_depth - 1 - cnt;
112 /* Check if the submission queue has enough space to hold required_buffers */
113 static inline bool ena_com_sq_have_enough_space(struct ena_com_io_sq *io_sq,
114 u16 required_buffers)
118 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
119 return ena_com_free_desc(io_sq) >= required_buffers;
121 /* This calculation doesn't need to be 100% accurate. So to reduce
122 * the calculation overhead just Subtract 2 lines from the free descs
123 * (one for the header line and one to compensate the devision
126 temp = required_buffers / io_sq->llq_info.descs_per_entry + 2;
128 return ena_com_free_desc(io_sq) > temp;
131 static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
137 ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n",
140 ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
145 static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
147 u16 unreported_comp, head;
151 unreported_comp = head - io_cq->last_head_update;
152 need_update = unreported_comp > (io_cq->q_depth / ENA_COMP_HEAD_THRESH);
154 if (io_cq->cq_head_db_reg && need_update) {
155 ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n",
157 ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);
158 io_cq->last_head_update = head;
164 static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
167 struct ena_eth_io_numa_node_cfg_reg numa_cfg;
169 if (!io_cq->numa_node_cfg_reg)
172 numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)
173 | ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
175 ENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
178 static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)
180 io_sq->next_to_comp += elem;
183 #if defined(__cplusplus)
186 #endif /* ENA_ETH_COM_H_ */