sys/contrib/ena-com/ena_plat.h

   1 /*-
   2  * BSD LICENSE
   3  *
   4  * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * * Redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer.
  13  * * Redistributions in binary form must reproduce the above copyright
  14  * notice, this list of conditions and the following disclaimer in
  15  * the documentation and/or other materials provided with the
  16  * distribution.
  17  * * Neither the name of copyright holder nor the names of its
  18  * contributors may be used to endorse or promote products derived
  19  * from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef ENA_PLAT_H_
  35 #define ENA_PLAT_H_
  36
  37 #include <sys/cdefs.h>
  38 __FBSDID("$FreeBSD$");
  39
  40 #include <sys/param.h>
  41 #include <sys/systm.h>
  42
  43 #include <sys/bus.h>
  44 #include <sys/condvar.h>
  45 #include <sys/endian.h>
  46 #include <sys/kernel.h>
  47 #include <sys/kthread.h>
  48 #include <sys/malloc.h>
  49 #include <sys/mbuf.h>
  50 #include <sys/module.h>
  51 #include <sys/rman.h>
  52 #include <sys/proc.h>
  53 #include <sys/smp.h>
  54 #include <sys/socket.h>
  55 #include <sys/sockio.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/taskqueue.h>
  58 #include <sys/eventhandler.h>
  59 #include <sys/types.h>
  60 #include <sys/timetc.h>
  61 #include <sys/cdefs.h>
  62
  63 #include <machine/atomic.h>
  64 #include <machine/bus.h>
  65 #include <machine/in_cksum.h>
  66 #include <machine/pcpu.h>
  67 #include <machine/resource.h>
  68
  69 #include <net/bpf.h>
  70 #include <net/ethernet.h>
  71 #include <net/if.h>
  72 #include <net/if_var.h>
  73 #include <net/if_arp.h>
  74 #include <net/if_dl.h>
  75 #include <net/if_media.h>
  76
  77 #include <net/if_types.h>
  78 #include <net/if_vlan_var.h>
  79
  80 #include <netinet/in_systm.h>
  81 #include <netinet/in.h>
  82 #include <netinet/if_ether.h>
  83 #include <netinet/ip.h>
  84 #include <netinet/ip6.h>
  85 #include <netinet/tcp.h>
  86 #include <netinet/tcp_lro.h>
  87 #include <netinet/udp.h>
  88
  89 #include <dev/led/led.h>
  90 #include <dev/pci/pcivar.h>
  91 #include <dev/pci/pcireg.h>
  92
  93 extern struct ena_bus_space ebs;
  94
  95 /* Levels */
  96 #define ENA_ALERT       (1 << 0) /* Alerts are providing more error info.     */
  97 #define ENA_WARNING     (1 << 1) /* Driver output is more error sensitive.    */
  98 #define ENA_INFO        (1 << 2) /* Provides additional driver info.          */
  99 #define ENA_DBG         (1 << 3) /* Driver output for debugging.              */
 100 /* Detailed info that will be printed with ENA_INFO or ENA_DEBUG flag.        */
 101 #define ENA_TXPTH       (1 << 4) /* Allows TX path tracing.                   */
 102 #define ENA_RXPTH       (1 << 5) /* Allows RX path tracing.                   */
 103 #define ENA_RSC         (1 << 6) /* Goes with TXPTH or RXPTH, free/alloc res. */
 104 #define ENA_IOQ         (1 << 7) /* Detailed info about IO queues.            */
 105 #define ENA_ADMQ        (1 << 8) /* Detailed info about admin queue.          */
 106 #define ENA_NETMAP      (1 << 9) /* Detailed info about netmap.               */
 107
 108 extern int ena_log_level;
 109
 110 #define ena_trace_raw(level, fmt, args...)                      \
 111         do {                                                    \
 112                 if (((level) & ena_log_level) != (level))       \
 113                         break;                                  \
 114                 printf(fmt, ##args);                            \
 115         } while (0)
 116
 117 #define ena_trace(level, fmt, args...)                          \
 118         ena_trace_raw(level, "%s() [TID:%d]: "                  \
 119             fmt, __func__, curthread->td_tid, ##args)
 120
 121
 122 #define ena_trc_dbg(format, arg...)     ena_trace(ENA_DBG, format, ##arg)
 123 #define ena_trc_info(format, arg...)    ena_trace(ENA_INFO, format, ##arg)
 124 #define ena_trc_warn(format, arg...)    ena_trace(ENA_WARNING, format, ##arg)
 125 #define ena_trc_err(format, arg...)     ena_trace(ENA_ALERT, format, ##arg)
 126
 127 #define unlikely(x)     __predict_false(x)
 128 #define likely(x)       __predict_true(x)
 129
 130 #define __iomem
 131 #define ____cacheline_aligned __aligned(CACHE_LINE_SIZE)
 132
 133 #define MAX_ERRNO 4095
 134 #define IS_ERR_VALUE(x) unlikely((x) <= (unsigned long)MAX_ERRNO)
 135
 136 #define ENA_ASSERT(cond, format, arg...)                                \
 137         do {                                                            \
 138                 if (unlikely(!(cond))) {                                \
 139                         ena_trc_err(                                    \
 140                                 "Assert failed on %s:%s:%d:" format,    \
 141                                 __FILE__, __func__, __LINE__, ##arg);   \
 142                 }                                                       \
 143         } while (0)
 144
 145 #define ENA_WARN(cond, format, arg...)                                  \
 146         do {                                                            \
 147                 if (unlikely((cond))) {                                 \
 148                         ena_trc_warn(format, ##arg);                    \
 149                 }                                                       \
 150         } while (0)
 151
 152 static inline long IS_ERR(const void *ptr)
 153 {
 154         return IS_ERR_VALUE((unsigned long)ptr);
 155 }
 156
 157 static inline void *ERR_PTR(long error)
 158 {
 159         return (void *)error;
 160 }
 161
 162 static inline long PTR_ERR(const void *ptr)
 163 {
 164         return (long) ptr;
 165 }
 166
 167 #define GENMASK(h, l)   (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h))))
 168 #define GENMASK_ULL(h, l)       (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h))))
 169 #define BIT(x)                  (1UL << (x))
 170
 171 #define ENA_ABORT()             BUG()
 172 #define BUG()                   panic("ENA BUG")
 173
 174 #define SZ_256                  (256)
 175 #define SZ_4K                   (4096)
 176
 177 #define ENA_COM_OK              0
 178 #define ENA_COM_FAULT           EFAULT
 179 #define ENA_COM_INVAL           EINVAL
 180 #define ENA_COM_NO_MEM          ENOMEM
 181 #define ENA_COM_NO_SPACE        ENOSPC
 182 #define ENA_COM_TRY_AGAIN       -1
 183 #define ENA_COM_UNSUPPORTED     EOPNOTSUPP
 184 #define ENA_COM_NO_DEVICE       ENODEV
 185 #define ENA_COM_PERMISSION      EPERM
 186 #define ENA_COM_TIMER_EXPIRED   ETIMEDOUT
 187
 188 #define ENA_MSLEEP(x)           pause_sbt("ena", SBT_1MS * (x), SBT_1MS, 0)
 189 #define ENA_UDELAY(x)           DELAY(x)
 190 #define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \
 191     ((long)cputick2usec(cpu_ticks()) + (timeout_us))
 192 #define ENA_TIME_EXPIRE(timeout)  ((timeout) < (long)cputick2usec(cpu_ticks()))
 193 #define ENA_MIGHT_SLEEP()
 194
 195 #define min_t(type, _x, _y) ((type)(_x) < (type)(_y) ? (type)(_x) : (type)(_y))
 196 #define max_t(type, _x, _y) ((type)(_x) > (type)(_y) ? (type)(_x) : (type)(_y))
 197
 198 #define ENA_MIN32(x,y)  MIN(x, y)
 199 #define ENA_MIN16(x,y)  MIN(x, y)
 200 #define ENA_MIN8(x,y)   MIN(x, y)
 201
 202 #define ENA_MAX32(x,y)  MAX(x, y)
 203 #define ENA_MAX16(x,y)  MAX(x, y)
 204 #define ENA_MAX8(x,y)   MAX(x, y)
 205
 206 /* Spinlock related methods */
 207 #define ena_spinlock_t  struct mtx
 208 #define ENA_SPINLOCK_INIT(spinlock)                             \
 209         mtx_init(&(spinlock), "ena_spin", NULL, MTX_SPIN)
 210 #define ENA_SPINLOCK_DESTROY(spinlock)                          \
 211         do {                                                    \
 212                 if (mtx_initialized(&(spinlock)))               \
 213                     mtx_destroy(&(spinlock));                   \
 214         } while (0)
 215 #define ENA_SPINLOCK_LOCK(spinlock, flags)                      \
 216         do {                                                    \
 217                 (void)(flags);                                  \
 218                 mtx_lock_spin(&(spinlock));                     \
 219         } while (0)
 220 #define ENA_SPINLOCK_UNLOCK(spinlock, flags)                    \
 221         do {                                                    \
 222                 (void)(flags);                                  \
 223                 mtx_unlock_spin(&(spinlock));                   \
 224         } while (0)
 225
 226
 227 /* Wait queue related methods */
 228 #define ena_wait_event_t struct { struct cv wq; struct mtx mtx; }
 229 #define ENA_WAIT_EVENT_INIT(waitqueue)                                  \
 230         do {                                                            \
 231                 cv_init(&((waitqueue).wq), "cv");                       \
 232                 mtx_init(&((waitqueue).mtx), "wq", NULL, MTX_DEF);      \
 233         } while (0)
 234 #define ENA_WAIT_EVENT_DESTROY(waitqueue)                               \
 235         do {                                                            \
 236                 cv_destroy(&((waitqueue).wq));                          \
 237                 mtx_destroy(&((waitqueue).mtx));                        \
 238         } while (0)
 239 #define ENA_WAIT_EVENT_CLEAR(waitqueue)                                 \
 240         cv_init(&((waitqueue).wq), (waitqueue).wq.cv_description)
 241 #define ENA_WAIT_EVENT_WAIT(waitqueue, timeout_us)                      \
 242         do {                                                            \
 243                 mtx_lock(&((waitqueue).mtx));                           \
 244                 cv_timedwait(&((waitqueue).wq), &((waitqueue).mtx),     \
 245                     timeout_us * hz / 1000 / 1000 );                    \
 246                 mtx_unlock(&((waitqueue).mtx));                         \
 247         } while (0)
 248 #define ENA_WAIT_EVENT_SIGNAL(waitqueue)                \
 249         do {                                            \
 250                 mtx_lock(&((waitqueue).mtx));           \
 251                 cv_broadcast(&((waitqueue).wq));        \
 252                 mtx_unlock(&((waitqueue).mtx));         \
 253         } while (0)
 254
 255 #define dma_addr_t      bus_addr_t
 256 #define u8              uint8_t
 257 #define u16             uint16_t
 258 #define u32             uint32_t
 259 #define u64             uint64_t
 260
 261 typedef struct {
 262         bus_addr_t              paddr;
 263         caddr_t                 vaddr;
 264         bus_dma_tag_t           tag;
 265         bus_dmamap_t            map;
 266         bus_dma_segment_t       seg;
 267         int                     nseg;
 268 } ena_mem_handle_t;
 269
 270 struct ena_bus {
 271         bus_space_handle_t      reg_bar_h;
 272         bus_space_tag_t         reg_bar_t;
 273         bus_space_handle_t      mem_bar_h;
 274         bus_space_tag_t         mem_bar_t;
 275 };
 276
 277 typedef uint32_t ena_atomic32_t;
 278
 279 void    ena_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nseg,
 280     int error);
 281 int     ena_dma_alloc(device_t dmadev, bus_size_t size, ena_mem_handle_t *dma,
 282     int mapflags);
 283
 284 #define ENA_MEMCPY_TO_DEVICE_64(dst, src, size)                         \
 285         do {                                                            \
 286                 int count, i;                                           \
 287                 volatile uint64_t *to = (volatile uint64_t *)(dst);     \
 288                 const uint64_t *from = (const uint64_t *)(src);         \
 289                 count = (size) / 8;                                     \
 290                                                                         \
 291                 for (i = 0; i < count; i++, from++, to++)               \
 292                         *to = *from;                                    \
 293         } while (0)
 294
 295 #define ENA_MEM_ALLOC(dmadev, size) malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO)
 296 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) (virt = NULL)
 297 #define ENA_MEM_FREE(dmadev, ptr) free(ptr, M_DEVBUF)
 298 #define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, handle, node, \
 299     dev_node)                                                           \
 300         do {                                                            \
 301                 ((virt) = NULL);                                        \
 302                 (void)(dev_node);                                       \
 303         } while (0)
 304
 305 #define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, dma)           \
 306         do {                                                            \
 307                 ena_dma_alloc((dmadev), (size), &(dma), 0);             \
 308                 (virt) = (void *)(dma).vaddr;                           \
 309                 (phys) = (dma).paddr;                                   \
 310         } while (0)
 311
 312 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, dma)            \
 313         do {                                                            \
 314                 (void)size;                                             \
 315                 bus_dmamap_unload((dma).tag, (dma).map);                \
 316                 bus_dmamem_free((dma).tag, (virt), (dma).map);          \
 317                 bus_dma_tag_destroy((dma).tag);                         \
 318                 (dma).tag = NULL;                                       \
 319                 (virt) = NULL;                                          \
 320         } while (0)
 321
 322 /* Register R/W methods */
 323 #define ENA_REG_WRITE32(bus, value, offset)                             \
 324         bus_space_write_4(                                              \
 325                           ((struct ena_bus*)bus)->reg_bar_t,            \
 326                           ((struct ena_bus*)bus)->reg_bar_h,            \
 327                           (bus_size_t)(offset), (value))
 328 #define ENA_REG_WRITE32_RELAXED(bus, value, offset)                     \
 329         ENA_REG_WRITE32(bus, value, offset)
 330
 331 #define ENA_REG_READ32(bus, offset)                                     \
 332         bus_space_read_4(                                               \
 333                          ((struct ena_bus*)bus)->reg_bar_t,             \
 334                          ((struct ena_bus*)bus)->reg_bar_h,             \
 335                          (bus_size_t)(offset))
 336
 337 #define ENA_DB_SYNC_WRITE(mem_handle) bus_dmamap_sync(                  \
 338         (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREWRITE)
 339 #define ENA_DB_SYNC_PREREAD(mem_handle) bus_dmamap_sync(                \
 340         (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_PREREAD)
 341 #define ENA_DB_SYNC_POSTREAD(mem_handle) bus_dmamap_sync(               \
 342         (mem_handle)->tag, (mem_handle)->map, BUS_DMASYNC_POSTREAD)
 343 #define ENA_DB_SYNC(mem_handle) ENA_DB_SYNC_WRITE(mem_handle)
 344
 345 #define time_after(a,b) ((long)((unsigned long)(b) - (unsigned long)(a)) < 0)
 346
 347 #define VLAN_HLEN       sizeof(struct ether_vlan_header)
 348 #define CSUM_OFFLOAD    (CSUM_IP|CSUM_TCP|CSUM_UDP)
 349
 350 #define prefetch(x)     (void)(x)
 351 #define prefetchw(x)    (void)(x)
 352
 353 /* DMA buffers access */
 354 #define dma_unmap_addr(p, name)                 ((p)->dma->name)
 355 #define dma_unmap_addr_set(p, name, v)          (((p)->dma->name) = (v))
 356 #define dma_unmap_len(p, name)                  ((p)->name)
 357 #define dma_unmap_len_set(p, name, v)           (((p)->name) = (v))
 358
 359 #define memcpy_toio memcpy
 360
 361 #define ATOMIC32_INC(I32_PTR)           atomic_add_int(I32_PTR, 1)
 362 #define ATOMIC32_DEC(I32_PTR)           atomic_add_int(I32_PTR, -1)
 363 #define ATOMIC32_READ(I32_PTR)          atomic_load_acq_int(I32_PTR)
 364 #define ATOMIC32_SET(I32_PTR, VAL)      atomic_store_rel_int(I32_PTR, VAL)
 365
 366 #define barrier() __asm__ __volatile__("": : :"memory")
 367 #define dma_rmb() barrier()
 368 #define mmiowb() barrier()
 369
 370 #define ACCESS_ONCE(x) (*(volatile __typeof(x) *)&(x))
 371 #define READ_ONCE(x)  ({                        \
 372                         __typeof(x) __var;      \
 373                         barrier();              \
 374                         __var = ACCESS_ONCE(x); \
 375                         barrier();              \
 376                         __var;                  \
 377                 })
 378 #define READ_ONCE8(x) READ_ONCE(x)
 379 #define READ_ONCE16(x) READ_ONCE(x)
 380 #define READ_ONCE32(x) READ_ONCE(x)
 381
 382 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
 383 #define lower_32_bits(n) ((uint32_t)(n))
 384
 385 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 386
 387 #include "ena_defs/ena_includes.h"
 388
 389 #endif /* ENA_PLAT_H_ */