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34 /******************************************************************************
37 @Description FM 10G MAC ...
38 *//***************************************************************************/
43 #include "error_ext.h"
47 #include "tgec_mii_acc.h"
51 #define DEFAULT_exceptions \
52 ((uint32_t)(TGEC_IMASK_MDIO_SCAN_EVENT | \
53 TGEC_IMASK_REM_FAULT | \
54 TGEC_IMASK_LOC_FAULT | \
55 TGEC_IMASK_TX_ECC_ER | \
56 TGEC_IMASK_TX_FIFO_UNFL | \
57 TGEC_IMASK_TX_FIFO_OVFL | \
59 TGEC_IMASK_RX_FIFO_OVFL | \
60 TGEC_IMASK_RX_ECC_ER | \
61 TGEC_IMASK_RX_JAB_FRM | \
62 TGEC_IMASK_RX_OVRSZ_FRM | \
63 TGEC_IMASK_RX_RUNT_FRM | \
64 TGEC_IMASK_RX_FRAG_FRM | \
65 TGEC_IMASK_RX_CRC_ER | \
66 TGEC_IMASK_RX_ALIGN_ER))
68 #define GET_EXCEPTION_FLAG(bitMask, exception) switch (exception){ \
69 case e_FM_MAC_EX_10G_MDIO_SCAN_EVENTMDIO: \
70 bitMask = TGEC_IMASK_MDIO_SCAN_EVENT ; break; \
71 case e_FM_MAC_EX_10G_MDIO_CMD_CMPL: \
72 bitMask = TGEC_IMASK_MDIO_CMD_CMPL ; break; \
73 case e_FM_MAC_EX_10G_REM_FAULT: \
74 bitMask = TGEC_IMASK_REM_FAULT ; break; \
75 case e_FM_MAC_EX_10G_LOC_FAULT: \
76 bitMask = TGEC_IMASK_LOC_FAULT ; break; \
77 case e_FM_MAC_EX_10G_1TX_ECC_ER: \
78 bitMask = TGEC_IMASK_TX_ECC_ER ; break; \
79 case e_FM_MAC_EX_10G_TX_FIFO_UNFL: \
80 bitMask = TGEC_IMASK_TX_FIFO_UNFL ; break; \
81 case e_FM_MAC_EX_10G_TX_FIFO_OVFL: \
82 bitMask = TGEC_IMASK_TX_FIFO_OVFL ; break; \
83 case e_FM_MAC_EX_10G_TX_ER: \
84 bitMask = TGEC_IMASK_TX_ER ; break; \
85 case e_FM_MAC_EX_10G_RX_FIFO_OVFL: \
86 bitMask = TGEC_IMASK_RX_FIFO_OVFL ; break; \
87 case e_FM_MAC_EX_10G_RX_ECC_ER: \
88 bitMask = TGEC_IMASK_RX_ECC_ER ; break; \
89 case e_FM_MAC_EX_10G_RX_JAB_FRM: \
90 bitMask = TGEC_IMASK_RX_JAB_FRM ; break; \
91 case e_FM_MAC_EX_10G_RX_OVRSZ_FRM: \
92 bitMask = TGEC_IMASK_RX_OVRSZ_FRM ; break; \
93 case e_FM_MAC_EX_10G_RX_RUNT_FRM: \
94 bitMask = TGEC_IMASK_RX_RUNT_FRM ; break; \
95 case e_FM_MAC_EX_10G_RX_FRAG_FRM: \
96 bitMask = TGEC_IMASK_RX_FRAG_FRM ; break; \
97 case e_FM_MAC_EX_10G_RX_LEN_ER: \
98 bitMask = TGEC_IMASK_RX_LEN_ER ; break; \
99 case e_FM_MAC_EX_10G_RX_CRC_ER: \
100 bitMask = TGEC_IMASK_RX_CRC_ER ; break; \
101 case e_FM_MAC_EX_10G_RX_ALIGN_ER: \
102 bitMask = TGEC_IMASK_RX_ALIGN_ER ; break; \
103 default: bitMask = 0;break;}
105 #define MAX_PACKET_ALIGNMENT 31
106 #define MAX_INTER_PACKET_GAP 0x7f
107 #define MAX_INTER_PALTERNATE_BEB 0x0f
108 #define MAX_RETRANSMISSION 0x0f
109 #define MAX_COLLISION_WINDOW 0x03ff
111 #define TGEC_NUM_OF_PADDRS 1 /* number of pattern match registers (entries) */
113 #define GROUP_ADDRESS 0x0000010000000000LL /* Group address bit indication */
115 #define HASH_TABLE_SIZE 512 /* Hash table size (= 32 bits * 8 regs) */
117 #define TGEC_TO_MII_OFFSET 0x1030 /* Offset from the MEM map to the MDIO mem map */
119 /* 10-gigabit Ethernet MAC Controller ID (10GEC_ID) */
120 #define TGEC_ID_ID 0xffff0000
121 #define TGEC_ID_MAC_VERSION 0x0000FF00
122 #define TGEC_ID_MAC_REV 0x000000ff
126 t_FmMacControllerDriver fmMacControllerDriver; /**< Upper Mac control block */
127 t_Handle h_App; /**< Handle to the upper layer application */
128 struct tgec_regs *p_MemMap; /**< pointer to 10G memory mapped registers. */
129 t_TgecMiiAccessMemMap *p_MiiMemMap; /**< pointer to MII memory mapped registers. */
130 uint64_t addr; /**< MAC address of device; */
131 e_EnetMode enetMode; /**< Ethernet physical interface */
132 t_FmMacExceptionCallback *f_Exception;
134 t_FmMacExceptionCallback *f_Event;
135 bool indAddrRegUsed[TGEC_NUM_OF_PADDRS]; /**< Whether a particular individual address recognition register is being used */
136 uint64_t paddr[TGEC_NUM_OF_PADDRS]; /**< MAC address for particular individual address recognition register */
137 uint8_t numOfIndAddrInRegs; /**< Number of individual addresses in registers for this station. */
138 t_EthHash *p_MulticastAddrHash; /**< pointer to driver's global address hash table */
139 t_EthHash *p_UnicastAddrHash; /**< pointer to driver's individual address hash table */
143 struct tgec_cfg *p_TgecDriverParam;
147 t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t data);
148 t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec, uint8_t phyAddr, uint8_t reg, uint16_t *p_Data);
151 #endif /* __TGEC_H */