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35 #include "error_ext.h"
41 #include "fm_common.h"
44 /*****************************************************************************/
45 t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec,
50 t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
51 t_TgecMiiAccessMemMap *p_MiiAccess;
52 uint32_t cfgStatusReg;
54 SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
55 SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
57 p_MiiAccess = p_Tgec->p_MiiMemMap;
60 cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
61 cfgStatusReg &= ~MIIMCOM_DIV_MASK;
62 /* (one half of fm clock => 2.5Mhz) */
63 cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
64 WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
66 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
69 WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
71 WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
75 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
78 WRITE_UINT32(p_MiiAccess->mdio_data, data);
82 while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
88 /*****************************************************************************/
89 t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
94 t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
95 t_TgecMiiAccessMemMap *p_MiiAccess;
96 uint32_t cfgStatusReg;
98 SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
99 SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
101 p_MiiAccess = p_Tgec->p_MiiMemMap;
104 cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
105 cfgStatusReg &= ~MIIMCOM_DIV_MASK;
106 /* (one half of fm clock => 2.5Mhz) */
107 cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT);
108 WRITE_UINT32(p_MiiAccess->mdio_cfg_status, cfgStatusReg);
110 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
113 WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
115 WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
117 CORE_MemoryBarrier();
119 while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
122 WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE));
124 CORE_MemoryBarrier();
126 while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
129 *p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
131 cfgStatusReg = GET_UINT32(p_MiiAccess->mdio_cfg_status);
133 if (cfgStatusReg & MIIMIND_READ_ERROR)
134 RETURN_ERROR(MINOR, E_INVALID_VALUE,
135 ("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfgStatusReg 0x%x",
136 ((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfgStatusReg));