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34 #ifndef __TGEC_MII_ACC_H
35 #define __TGEC_MII_ACC_H
40 /* MII Management Command Register */
41 #define MIIMCOM_READ_POST_INCREMENT 0x00004000
42 #define MIIMCOM_READ_CYCLE 0x00008000
43 #define MIIMCOM_SCAN_CYCLE 0x00000800
44 #define MIIMCOM_PREAMBLE_DISABLE 0x00000400
46 #define MIIMCOM_MDIO_HOLD_1_REG_CLK 0
47 #define MIIMCOM_MDIO_HOLD_2_REG_CLK 1
48 #define MIIMCOM_MDIO_HOLD_3_REG_CLK 2
49 #define MIIMCOM_MDIO_HOLD_4_REG_CLK 3
51 #define MIIMCOM_DIV_MASK 0x0000ff00
52 #define MIIMCOM_DIV_SHIFT 8
54 /* MII Management Indicator Register */
55 #define MIIMIND_BUSY 0x00000001
56 #define MIIMIND_READ_ERROR 0x00000002
58 #define MIIDATA_BUSY 0x80000000
60 #if defined(__MWERKS__) && !defined(__GNUC__)
62 #endif /* defined(__MWERKS__) && ... */
64 /*----------------------------------------------------*/
65 /* MII Configuration Control Memory Map Registers */
66 /*----------------------------------------------------*/
67 typedef _Packed struct t_TgecMiiAccessMemMap
69 volatile uint32_t mdio_cfg_status; /* 0x030 */
70 volatile uint32_t mdio_command; /* 0x034 */
71 volatile uint32_t mdio_data; /* 0x038 */
72 volatile uint32_t mdio_regaddr; /* 0x03c */
73 } _PackedType t_TgecMiiAccessMemMap ;
75 #if defined(__MWERKS__) && !defined(__GNUC__)
77 #endif /* defined(__MWERKS__) && ... */
80 #endif /* __TGEC_MII_ACC_H */