2 * Copyright 2008-2012 Freescale Semiconductor Inc.
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34 /******************************************************************************
37 @Description FM internal structures and definitions.
38 *//***************************************************************************/
42 #include "error_ext.h"
49 #define __ERR_MODULE__ MODULE_FM
51 #define FM_MAX_NUM_OF_HW_PORT_IDS 64
52 #define FM_MAX_NUM_OF_GUESTS 100
54 /**************************************************************************//**
55 @Description Exceptions
56 *//***************************************************************************/
57 #define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */
58 #define FM_EX_DMA_READ_ECC 0x40000000
59 #define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000
60 #define FM_EX_DMA_FM_WRITE_ECC 0x10000000
61 #define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */
62 #define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */
63 #define FM_EX_FPM_DOUBLE_ECC 0x02000000
64 #define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */
65 #define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */
66 #define FM_EX_QMI_DOUBLE_ECC 0x00400000
67 #define FM_EX_BMI_LIST_RAM_ECC 0x00200000
68 #define FM_EX_BMI_STORAGE_PROFILE_ECC 0x00100000
69 #define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000
70 #define FM_EX_IRAM_ECC 0x00040000
71 #define FM_EX_MURAM_ECC 0x00020000
72 #define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000
73 #define FM_EX_DMA_SINGLE_PORT_ECC 0x00008000
75 #define DMA_EMSR_EMSTR_MASK 0x0000FFFF
77 #define DMA_THRESH_COMMQ_MASK 0xFF000000
78 #define DMA_THRESH_READ_INT_BUF_MASK 0x007F0000
79 #define DMA_THRESH_WRITE_INT_BUF_MASK 0x0000007F
81 #define GET_EXCEPTION_FLAG(bitMask, exception) \
83 case e_FM_EX_DMA_BUS_ERROR: \
84 bitMask = FM_EX_DMA_BUS_ERROR; break; \
85 case e_FM_EX_DMA_SINGLE_PORT_ECC: \
86 bitMask = FM_EX_DMA_SINGLE_PORT_ECC; break; \
87 case e_FM_EX_DMA_READ_ECC: \
88 bitMask = FM_EX_DMA_READ_ECC; break; \
89 case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \
90 bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \
91 case e_FM_EX_DMA_FM_WRITE_ECC: \
92 bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \
93 case e_FM_EX_FPM_STALL_ON_TASKS: \
94 bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \
95 case e_FM_EX_FPM_SINGLE_ECC: \
96 bitMask = FM_EX_FPM_SINGLE_ECC; break; \
97 case e_FM_EX_FPM_DOUBLE_ECC: \
98 bitMask = FM_EX_FPM_DOUBLE_ECC; break; \
99 case e_FM_EX_QMI_SINGLE_ECC: \
100 bitMask = FM_EX_QMI_SINGLE_ECC; break; \
101 case e_FM_EX_QMI_DOUBLE_ECC: \
102 bitMask = FM_EX_QMI_DOUBLE_ECC; break; \
103 case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \
104 bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \
105 case e_FM_EX_BMI_LIST_RAM_ECC: \
106 bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \
107 case e_FM_EX_BMI_STORAGE_PROFILE_ECC: \
108 bitMask = FM_EX_BMI_STORAGE_PROFILE_ECC; break; \
109 case e_FM_EX_BMI_STATISTICS_RAM_ECC: \
110 bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \
111 case e_FM_EX_BMI_DISPATCH_RAM_ECC: \
112 bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \
113 case e_FM_EX_IRAM_ECC: \
114 bitMask = FM_EX_IRAM_ECC; break; \
115 case e_FM_EX_MURAM_ECC: \
116 bitMask = FM_EX_MURAM_ECC; break; \
117 default: bitMask = 0;break; \
120 #define GET_FM_MODULE_EVENT(_mod, _id, _intrType, _event) \
123 if (_id) _event = e_FM_EV_DUMMY_LAST; \
124 else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PRS : e_FM_EV_PRS; \
127 if (_id) _event = e_FM_EV_DUMMY_LAST; \
128 else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_KG : e_FM_EV_DUMMY_LAST; \
130 case e_FM_MOD_PLCR: \
131 if (_id) _event = e_FM_EV_DUMMY_LAST; \
132 else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_PLCR : e_FM_EV_PLCR; \
135 if (_id) _event = e_FM_EV_DUMMY_LAST; \
136 else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_DUMMY_LAST : e_FM_EV_TMR; \
138 case e_FM_MOD_10G_MAC: \
139 if (_id >= FM_MAX_NUM_OF_10G_MACS) _event = e_FM_EV_DUMMY_LAST; \
140 else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_10G_MAC0 + _id) : (e_FM_EV_10G_MAC0 + _id); \
142 case e_FM_MOD_1G_MAC: \
143 if (_id >= FM_MAX_NUM_OF_1G_MACS) _event = e_FM_EV_DUMMY_LAST; \
144 else _event = (_intrType == e_FM_INTR_TYPE_ERR) ? (e_FM_EV_ERR_1G_MAC0 + _id) : (e_FM_EV_1G_MAC0 + _id); \
146 case e_FM_MOD_MACSEC: \
148 case (0): _event = (_intrType == e_FM_INTR_TYPE_ERR) ? e_FM_EV_ERR_MACSEC_MAC0:e_FM_EV_MACSEC_MAC0; \
152 case e_FM_MOD_FMAN_CTRL: \
153 if (_intrType == e_FM_INTR_TYPE_ERR) _event = e_FM_EV_DUMMY_LAST; \
154 else _event = (e_FM_EV_FMAN_CTRL_0 + _id); \
156 default: _event = e_FM_EV_DUMMY_LAST; \
160 #define FMAN_CACHE_OVERRIDE_TRANS(fsl_cache_override, _cache_override) \
161 switch (_cache_override){ \
162 case e_FM_DMA_NO_CACHE_OR: \
163 fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
164 case e_FM_DMA_NO_STASH_DATA: \
165 fsl_cache_override = E_FMAN_DMA_NO_STASH_DATA; break; \
166 case e_FM_DMA_MAY_STASH_DATA: \
167 fsl_cache_override = E_FMAN_DMA_MAY_STASH_DATA; break; \
168 case e_FM_DMA_STASH_DATA: \
169 fsl_cache_override = E_FMAN_DMA_STASH_DATA; break; \
171 fsl_cache_override = E_FMAN_DMA_NO_CACHE_OR; break; \
174 #define FMAN_AID_MODE_TRANS(fsl_aid_mode, _aid_mode) \
175 switch (_aid_mode){ \
176 case e_FM_DMA_AID_OUT_PORT_ID: \
177 fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
178 case e_FM_DMA_AID_OUT_TNUM: \
179 fsl_aid_mode = E_FMAN_DMA_AID_OUT_TNUM; break; \
181 fsl_aid_mode = E_FMAN_DMA_AID_OUT_PORT_ID; break; \
184 #define FMAN_DMA_DBG_CNT_TRANS(fsl_dma_dbg_cnt, _dma_dbg_cnt) \
185 switch (_dma_dbg_cnt){ \
186 case e_FM_DMA_DBG_NO_CNT: \
187 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
188 case e_FM_DMA_DBG_CNT_DONE: \
189 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_DONE; break; \
190 case e_FM_DMA_DBG_CNT_COMM_Q_EM: \
191 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_COMM_Q_EM; break; \
192 case e_FM_DMA_DBG_CNT_INT_READ_EM: \
193 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_READ_EM; break; \
194 case e_FM_DMA_DBG_CNT_INT_WRITE_EM: \
195 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_INT_WRITE_EM ; break; \
196 case e_FM_DMA_DBG_CNT_FPM_WAIT: \
197 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_FPM_WAIT ; break; \
198 case e_FM_DMA_DBG_CNT_SIGLE_BIT_ECC: \
199 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC ; break; \
200 case e_FM_DMA_DBG_CNT_RAW_WAR_PROT: \
201 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT ; break; \
203 fsl_dma_dbg_cnt = E_FMAN_DMA_DBG_NO_CNT; break; \
206 #define FMAN_DMA_EMER_TRANS(fsl_dma_emer, _dma_emer) \
207 switch (_dma_emer){ \
208 case e_FM_DMA_EM_EBS: \
209 fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
210 case e_FM_DMA_EM_SOS: \
211 fsl_dma_emer = E_FMAN_DMA_EM_SOS; break; \
213 fsl_dma_emer = E_FMAN_DMA_EM_EBS; break; \
216 #define FMAN_DMA_ERR_TRANS(fsl_dma_err, _dma_err) \
218 case e_FM_DMA_ERR_CATASTROPHIC: \
219 fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
220 case e_FM_DMA_ERR_REPORT: \
221 fsl_dma_err = E_FMAN_DMA_ERR_REPORT; break; \
223 fsl_dma_err = E_FMAN_DMA_ERR_CATASTROPHIC; break; \
226 #define FMAN_CATASTROPHIC_ERR_TRANS(fsl_catastrophic_err, _catastrophic_err) \
227 switch (_catastrophic_err){ \
228 case e_FM_CATASTROPHIC_ERR_STALL_PORT: \
229 fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
230 case e_FM_CATASTROPHIC_ERR_STALL_TASK: \
231 fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_TASK; break; \
233 fsl_catastrophic_err = E_FMAN_CATAST_ERR_STALL_PORT; break; \
236 #define FMAN_COUNTERS_TRANS(fsl_counters, _counters) \
237 switch (_counters){ \
238 case e_FM_COUNTERS_ENQ_TOTAL_FRAME: \
239 fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
240 case e_FM_COUNTERS_DEQ_TOTAL_FRAME: \
241 fsl_counters = E_FMAN_COUNTERS_DEQ_TOTAL_FRAME; break; \
242 case e_FM_COUNTERS_DEQ_0: \
243 fsl_counters = E_FMAN_COUNTERS_DEQ_0; break; \
244 case e_FM_COUNTERS_DEQ_1: \
245 fsl_counters = E_FMAN_COUNTERS_DEQ_1; break; \
246 case e_FM_COUNTERS_DEQ_2: \
247 fsl_counters = E_FMAN_COUNTERS_DEQ_2; break; \
248 case e_FM_COUNTERS_DEQ_3: \
249 fsl_counters = E_FMAN_COUNTERS_DEQ_3; break; \
250 case e_FM_COUNTERS_DEQ_FROM_DEFAULT: \
251 fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_DEFAULT; break; \
252 case e_FM_COUNTERS_DEQ_FROM_CONTEXT: \
253 fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_CONTEXT; break; \
254 case e_FM_COUNTERS_DEQ_FROM_FD: \
255 fsl_counters = E_FMAN_COUNTERS_DEQ_FROM_FD; break; \
256 case e_FM_COUNTERS_DEQ_CONFIRM: \
257 fsl_counters = E_FMAN_COUNTERS_DEQ_CONFIRM; break; \
259 fsl_counters = E_FMAN_COUNTERS_ENQ_TOTAL_FRAME; break; \
262 /**************************************************************************//**
263 @Description defaults
264 *//***************************************************************************/
265 #define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\
266 FM_EX_DMA_READ_ECC |\
267 FM_EX_DMA_SYSTEM_WRITE_ECC |\
268 FM_EX_DMA_FM_WRITE_ECC |\
269 FM_EX_FPM_STALL_ON_TASKS |\
270 FM_EX_FPM_SINGLE_ECC |\
271 FM_EX_FPM_DOUBLE_ECC |\
272 FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\
273 FM_EX_BMI_LIST_RAM_ECC |\
274 FM_EX_BMI_STORAGE_PROFILE_ECC |\
275 FM_EX_BMI_STATISTICS_RAM_ECC |\
278 FM_EX_BMI_DISPATCH_RAM_ECC |\
279 FM_EX_QMI_DOUBLE_ECC |\
280 FM_EX_QMI_SINGLE_ECC)
282 #define DEFAULT_eccEnable FALSE
283 #ifdef FM_PEDANTIC_DMA
284 #define DEFAULT_aidOverride TRUE
286 #define DEFAULT_aidOverride FALSE
287 #endif /* FM_PEDANTIC_DMA */
288 #define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM
289 #define DEFAULT_dmaStopOnBusError FALSE
290 #define DEFAULT_stopAtBusError FALSE
291 #define DEFAULT_axiDbgNumOfBeats 1
292 #define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
293 #define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
294 #define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2)
295 #define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4)
296 #define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT
297 #define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC
298 #define DEFAULT_resetOnInit FALSE
299 #define DEFAULT_resetOnInitOverrideCallback NULL
300 #define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */
301 #define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */
302 #define DEFAULT_externalEccRamsEnable FALSE
303 #define DEFAULT_VerifyUcode FALSE
305 #if (DPAA_VERSION < 11)
306 #define DEFAULT_totalFifoSize(major, minor) \
307 (((major == 2) || (major == 5)) ? \
308 (100*KILOBYTE) : ((major == 4) ? \
309 (49*KILOBYTE) : (122*KILOBYTE)))
310 #define DEFAULT_totalNumOfTasks(major, minor) \
313 #define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2)
314 #define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4)
315 #define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
316 #define DEFAULT_dmaCamNumOfEntries 32
317 #define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
318 #define DEFAULT_dmaEnEmergency FALSE
319 #define DEFAULT_dmaSosEmergency 0
320 #define DEFAULT_dmaWatchdog 0 /* disabled */
321 #define DEFAULT_dmaEnEmergencySmoother FALSE
322 #define DEFAULT_dmaEmergencySwitchCounter 0
324 #define DEFAULT_dispLimit 0
325 #define DEFAULT_prsDispTh 16
326 #define DEFAULT_plcrDispTh 16
327 #define DEFAULT_kgDispTh 16
328 #define DEFAULT_bmiDispTh 16
329 #define DEFAULT_qmiEnqDispTh 16
330 #define DEFAULT_qmiDeqDispTh 16
331 #define DEFAULT_fmCtl1DispTh 16
332 #define DEFAULT_fmCtl2DispTh 16
334 #else /* (DPAA_VERSION < 11) */
335 /* Defaults are registers' reset values */
336 #define DEFAULT_totalFifoSize(major, minor) \
337 (((major == 6) && ((minor == 1) || (minor == 4))) ? \
338 (156*KILOBYTE) : (295*KILOBYTE))
340 /* According to the default value of FMBM_CFG2[TNTSKS] */
341 #define DEFAULT_totalNumOfTasks(major, minor) \
342 (((major == 6) && ((minor == 1) || (minor == 4))) ? 59 : 124)
344 #define DEFAULT_dmaCommQLow 0x2A
345 #define DEFAULT_dmaCommQHigh 0x3F
346 #define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR
347 #define DEFAULT_dmaCamNumOfEntries 64
348 #define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT
349 #define DEFAULT_dmaEnEmergency FALSE
350 #define DEFAULT_dmaSosEmergency 0
351 #define DEFAULT_dmaWatchdog 0 /* disabled */
352 #define DEFAULT_dmaEnEmergencySmoother FALSE
353 #define DEFAULT_dmaEmergencySwitchCounter 0
355 #define DEFAULT_dispLimit 0
356 #define DEFAULT_prsDispTh 16
357 #define DEFAULT_plcrDispTh 16
358 #define DEFAULT_kgDispTh 16
359 #define DEFAULT_bmiDispTh 16
360 #define DEFAULT_qmiEnqDispTh 16
361 #define DEFAULT_qmiDeqDispTh 16
362 #define DEFAULT_fmCtl1DispTh 16
363 #define DEFAULT_fmCtl2DispTh 16
364 #endif /* (DPAA_VERSION < 11) */
366 #define FM_TIMESTAMP_1_USEC_BIT 8
368 /**************************************************************************//**
369 @Collection Defines used for enabling/disabling FM interrupts
371 *//***************************************************************************/
372 #define ERR_INTR_EN_DMA 0x00010000
373 #define ERR_INTR_EN_FPM 0x80000000
374 #define ERR_INTR_EN_BMI 0x00800000
375 #define ERR_INTR_EN_QMI 0x00400000
376 #define ERR_INTR_EN_PRS 0x00200000
377 #define ERR_INTR_EN_KG 0x00100000
378 #define ERR_INTR_EN_PLCR 0x00080000
379 #define ERR_INTR_EN_MURAM 0x00040000
380 #define ERR_INTR_EN_IRAM 0x00020000
381 #define ERR_INTR_EN_10G_MAC0 0x00008000
382 #define ERR_INTR_EN_10G_MAC1 0x00000040
383 #define ERR_INTR_EN_1G_MAC0 0x00004000
384 #define ERR_INTR_EN_1G_MAC1 0x00002000
385 #define ERR_INTR_EN_1G_MAC2 0x00001000
386 #define ERR_INTR_EN_1G_MAC3 0x00000800
387 #define ERR_INTR_EN_1G_MAC4 0x00000400
388 #define ERR_INTR_EN_1G_MAC5 0x00000200
389 #define ERR_INTR_EN_1G_MAC6 0x00000100
390 #define ERR_INTR_EN_1G_MAC7 0x00000080
391 #define ERR_INTR_EN_MACSEC_MAC0 0x00000001
393 #define INTR_EN_QMI 0x40000000
394 #define INTR_EN_PRS 0x20000000
395 #define INTR_EN_WAKEUP 0x10000000
396 #define INTR_EN_PLCR 0x08000000
397 #define INTR_EN_1G_MAC0 0x00080000
398 #define INTR_EN_1G_MAC1 0x00040000
399 #define INTR_EN_1G_MAC2 0x00020000
400 #define INTR_EN_1G_MAC3 0x00010000
401 #define INTR_EN_1G_MAC4 0x00000040
402 #define INTR_EN_1G_MAC5 0x00000020
403 #define INTR_EN_1G_MAC6 0x00000008
404 #define INTR_EN_1G_MAC7 0x00000002
405 #define INTR_EN_10G_MAC0 0x00200000
406 #define INTR_EN_10G_MAC1 0x00100000
407 #define INTR_EN_REV0 0x00008000
408 #define INTR_EN_REV1 0x00004000
409 #define INTR_EN_REV2 0x00002000
410 #define INTR_EN_REV3 0x00001000
411 #define INTR_EN_BRK 0x00000080
412 #define INTR_EN_TMR 0x01000000
413 #define INTR_EN_MACSEC_MAC0 0x00000001
416 /**************************************************************************//**
417 @Description Memory Mapped Registers
418 *//***************************************************************************/
420 #if defined(__MWERKS__) && !defined(__GNUC__)
422 #endif /* defined(__MWERKS__) && ... */
426 volatile uint32_t iadd; /**< FM IRAM instruction address register */
427 volatile uint32_t idata; /**< FM IRAM instruction data register */
428 volatile uint32_t itcfg; /**< FM IRAM timing config register */
429 volatile uint32_t iready; /**< FM IRAM ready register */
430 volatile uint32_t res[0x1FFFC];
433 /* Trace buffer registers -
434 each FM Controller has its own trace buffer residing at FM_MM_TRB(fmCtrlIndex) offset */
435 typedef struct t_FmTrbRegs
437 volatile uint32_t tcrh;
438 volatile uint32_t tcrl;
439 volatile uint32_t tesr;
440 volatile uint32_t tecr0h;
441 volatile uint32_t tecr0l;
442 volatile uint32_t terf0h;
443 volatile uint32_t terf0l;
444 volatile uint32_t tecr1h;
445 volatile uint32_t tecr1l;
446 volatile uint32_t terf1h;
447 volatile uint32_t terf1l;
448 volatile uint32_t tpcch;
449 volatile uint32_t tpccl;
450 volatile uint32_t tpc1h;
451 volatile uint32_t tpc1l;
452 volatile uint32_t tpc2h;
453 volatile uint32_t tpc2l;
454 volatile uint32_t twdimr;
455 volatile uint32_t twicvr;
456 volatile uint32_t tar;
457 volatile uint32_t tdr;
458 volatile uint32_t tsnum1;
459 volatile uint32_t tsnum2;
460 volatile uint32_t tsnum3;
461 volatile uint32_t tsnum4;
464 #if defined(__MWERKS__) && !defined(__GNUC__)
466 #endif /* defined(__MWERKS__) && ... */
468 /**************************************************************************//**
469 @Description General defines
470 *//***************************************************************************/
471 #define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL
472 #define FM_FW_DEBUG_INSTRUCTION 0x6ffff805UL
474 /**************************************************************************//**
475 @Description FPM defines
476 *//***************************************************************************/
478 #define FPM_BRKC_RDBG 0x00000200
479 #define FPM_BRKC_SLP 0x00000800
480 /**************************************************************************//**
481 @Description BMI defines
482 *//***************************************************************************/
484 #define BMI_INIT_START 0x80000000
485 #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC 0x80000000
486 #define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000
487 #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000
488 #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000
489 /**************************************************************************//**
490 @Description QMI defines
491 *//***************************************************************************/
493 #define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000
494 #define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000
495 #define QMI_INTR_EN_SINGLE_ECC 0x80000000
497 /**************************************************************************//**
498 @Description IRAM defines
499 *//***************************************************************************/
501 #define IRAM_IADD_AIE 0x80000000
502 #define IRAM_READY 0x80000000
504 /**************************************************************************//**
505 @Description TRB defines
506 *//***************************************************************************/
508 #define TRB_TCRH_RESET 0x04000000
509 #define TRB_TCRH_ENABLE_COUNTERS 0x84008000
510 #define TRB_TCRH_DISABLE_COUNTERS 0x8400C000
511 #define TRB_TCRL_RESET 0x20000000
512 #define TRB_TCRL_UTIL 0x00000460
514 void (*f_Isr) (t_Handle h_Arg, uint32_t event);
515 t_Handle h_SrcHandle;
519 typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event);
523 /***************************/
524 /* Master/Guest parameters */
525 /***************************/
527 e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS];
529 uint16_t fmMacClkFreq;
530 t_FmRevisionInfo revInfo;
531 /**************************/
532 /* Master Only parameters */
533 /**************************/
534 bool enabledTimeStamp;
535 uint8_t count1MicroBit;
536 uint8_t totalNumOfTasks;
537 uint32_t totalFifoSize;
538 uint8_t maxNumOfOpenDmas;
539 uint8_t accumulatedNumOfTasks;
540 uint32_t accumulatedFifoSize;
541 uint8_t accumulatedNumOfOpenDmas;
542 uint8_t accumulatedNumOfDeqTnums;
543 #ifdef FM_LOW_END_RESTRICTION
544 bool lowEndRestriction;
545 #endif /* FM_LOW_END_RESTRICTION */
552 uint8_t ramsEccOwners;
553 uint32_t extraFifoPoolSize;
554 uint8_t extraTasksPoolSize;
555 uint8_t extraOpenDmasPoolSize;
556 #if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS)
557 uint16_t portMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
558 uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS];
559 #endif /* defined(FM_MAX_NUM_OF_10G_MACS) && ... */
560 uint16_t portMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
561 uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS];
564 #if (DPAA_VERSION >= 11)
565 typedef struct t_FmMapParam {
566 uint16_t profilesBase;
567 uint16_t numOfProfiles;
571 typedef struct t_FmAllocMng {
573 uint8_t ownerId; /* guestId for KG in multi-partition only,
574 portId for PLCR in any environment */
577 typedef struct t_FmPcdSpEntry {
579 t_FmAllocMng profilesMng;
582 typedef struct t_FmSp {
583 void *p_FmPcdStoragePrflRegs;
584 t_FmPcdSpEntry profiles[FM_VSP_MAX_NUM_OF_ENTRIES];
585 t_FmMapParam portsMapping[FM_MAX_NUM_OF_PORTS];
587 #endif /* (DPAA_VERSION >= 11) */
591 /***************************/
592 /* Master/Guest parameters */
593 /***************************/
594 /* locals for recovery */
597 /* un-needed for recovery */
599 char fmModuleName[MODULE_NAME_SIZE];
600 char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE];
601 t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS];
602 t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */
604 /**************************/
605 /* Master Only parameters */
606 /**************************/
607 /* locals for recovery */
608 struct fman_fpm_regs *p_FmFpmRegs;
609 struct fman_bmi_regs *p_FmBmiRegs;
610 struct fman_qmi_regs *p_FmQmiRegs;
611 struct fman_dma_regs *p_FmDmaRegs;
612 struct fman_regs *p_FmRegs;
613 t_FmExceptionsCallback *f_Exception;
614 t_FmBusErrorCallback *f_BusError;
615 t_Handle h_App; /* Application handle */
618 t_FmStateStruct *p_FmStateStruct;
619 uint16_t tnumAgingPeriod;
620 #if (DPAA_VERSION >= 11)
622 uint8_t partNumOfVSPs;
624 uintptr_t vspBaseAddr;
625 #endif /* (DPAA_VERSION >= 11) */
626 bool portsPreFetchConfigured[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
627 bool portsPreFetchValue[FM_MAX_NUM_OF_HW_PORT_IDS]; /* Prefetch configration per Tx-port */
629 /* un-needed for recovery */
630 struct fman_cfg *p_FmDriverParam;
632 uint64_t fmMuramPhysBaseAddr;
633 bool independentMode;
634 bool hcPortInitialized;
635 uintptr_t camBaseAddr; /* save for freeing */
637 uintptr_t fifoBaseAddr; /* save for freeing */
638 t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */
639 bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS];
640 t_FmFirmwareParams firmware;
643 t_FmResetOnInitOverrideCallback *f_ResetOnInitOverride;
644 uint32_t userSetExceptions;