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35 **************************************************************************/
36 /******************************************************************************
39 @Description QM private header
40 *//***************************************************************************/
41 #ifndef __QMAN_PRIVATE_H
42 #define __QMAN_PRIVATE_H
47 #define __ERR_MODULE__ MODULE_QM
49 #if defined(DEBUG) || !defined(DISABLE_ASSERTIONS)
50 /* Optionally compile-in assertion-checking */
52 #endif /* defined(DEBUG) || ... */
54 /* TODO: NB, we currently assume that CORE_MemoryBarier() and lwsync() imply compiler barriers
55 * and that dcbzl(), dcbfl(), and dcbi() won't fall victim to compiler or
56 * execution reordering with respect to other code/instructions that manipulate
57 * the same cacheline. */
61 __asm__ __volatile__ ("dcbf 0, %0" : : "r" (addr)); \
65 #define dcbt_ro(addr) \
67 __asm__ __volatile__ ("dcbt 0, %0" : : "r" (addr)); \
70 #define dcbt_rw(addr) \
72 __asm__ __volatile__ ("dcbtst 0, %0" : : "r" (addr)); \
77 __asm__ __volatile__ ("dcbzl 0,%0" : : "r" (p)); \
90 /* Commonly used combo */
101 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (p)); \
106 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (p)); \
110 __asm__ __volatile__ ("dcbz 0,%0" : : "r" (p)); \
114 dcbz((char *)p + 32); \
119 dcbf((char *)p + 32); \
122 /* Commonly used combo */
123 #define dcbit_ro(p) \
126 dcbi((char *)p + 32); \
128 dcbt_ro((char *)p + 32); \
131 #endif /* CORE_E500MC */
133 #define dcbi(p) dcbf(p)
136 void *addr_ce; /* cache-enabled */
137 void *addr_ci; /* cache-inhibited */
142 struct qm_eqcr_entry *ring, *cursor;
143 uint8_t ci, available, ithresh, vbit;
147 e_QmPortalProduceMode pmode;
148 e_QmPortalEqcrConsumeMode cmode;
149 #endif /* QM_CHECKING */
154 struct qm_dqrr_entry *ring, *cursor;
155 uint8_t pi, ci, fill, ithresh, vbit, flags;
158 e_QmPortalDequeueMode dmode;
159 e_QmPortalProduceMode pmode;
160 e_QmPortalDqrrConsumeMode cmode;
161 #endif /* QM_CHECKING */
163 #define QM_DQRR_FLAG_RE 0x01 /* Stash ring entries */
164 #define QM_DQRR_FLAG_SE 0x02 /* Stash data */
168 struct qm_mr_entry *ring, *cursor;
169 uint8_t pi, ci, fill, ithresh, vbit;
172 e_QmPortalProduceMode pmode;
173 e_QmPortalMrConsumeMode cmode;
174 #endif /* QM_CHECKING */
179 struct qm_mc_command *cr;
180 struct qm_mc_result *rr;
184 /* Can be _mc_start()ed */
186 /* Can be _mc_commit()ed or _mc_abort()ed */
188 /* Can only be _mc_retry()ed */
191 #endif /* QM_CHECKING */
194 /********************/
195 /* Portal structure */
196 /********************/
199 /* In the non-QM_CHECKING case, everything up to and
200 * including 'mc' fits in a cacheline (yay!). The 'config' part is setup-only, so isn't a
201 * cause for a concern. In other words, don't rearrange this structure
202 * on a whim, there be dragons ... */
208 struct qm_portal_config config;
210 /* Logical index (not cell-index) */
214 #endif /* __QMAN_PRIVATE_H */