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34 /**************************************************************************//**
37 @Description Core API for PowerPC cores
39 These routines must be implemented by each specific PowerPC
41 *//***************************************************************************/
48 #define CORE_IS_BIG_ENDIAN
50 #if defined(CORE_E300) || defined(CORE_E500V2)
51 #define CORE_CACHELINE_SIZE 32
52 #elif defined(CORE_E500MC) || defined(CORE_E5500) || defined(CORE_E6500)
53 #define CORE_CACHELINE_SIZE 64
55 #error "Core not defined!"
56 #endif /* defined(CORE_E300) || ... */
59 /**************************************************************************//**
60 @Function CORE_TestAndSet
62 @Description This routine tries to atomically test-and-set an integer
63 in memory to a non-zero value.
65 The memory will be set only if it is tested as zero, in which
66 case the routine returns the new non-zero value; otherwise the
69 @Param[in] p - pointer to a volatile int in memory, on which test-and-set
70 operation should be made.
72 @Retval Zero - Operation failed - memory was already set.
73 @Retval Non-zero - Operation succeeded - memory has been set.
74 *//***************************************************************************/
75 int CORE_TestAndSet(volatile int *p);
77 /**************************************************************************//**
78 @Function CORE_InstructionSync
80 @Description This routine will cause the core to wait for previous instructions
81 (including any interrupts they generate) to complete before the
82 synchronization command executes, which purges all instructions
83 from the processor's pipeline and refetches the next instruction.
86 *//***************************************************************************/
87 void CORE_InstructionSync(void);
89 /**************************************************************************//**
90 @Function CORE_DCacheEnable
92 @Description Enables the data cache for memory pages that are
96 *//***************************************************************************/
97 void CORE_DCacheEnable(void);
99 /**************************************************************************//**
100 @Function CORE_ICacheEnable
102 @Description Enables the instruction cache for memory pages that are
106 *//***************************************************************************/
107 void CORE_ICacheEnable(void);
109 /**************************************************************************//**
110 @Function CORE_DCacheDisable
112 @Description Disables the data cache.
115 *//***************************************************************************/
116 void CORE_DCacheDisable(void);
118 /**************************************************************************//**
119 @Function CORE_ICacheDisable
121 @Description Disables the instruction cache.
124 *//***************************************************************************/
125 void CORE_ICacheDisable(void);
129 #include "e500v2_ext.h"
131 #endif /* __PPC_EXT_H */