sys/contrib/ncsw/inc/flib/fsl_fman.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *     * Redistributions of source code must retain the above copyright
   7  *       notice, this list of conditions and the following disclaimer.
   8  *     * Redistributions in binary form must reproduce the above copyright
   9  *       notice, this list of conditions and the following disclaimer in the
  10  *       documentation and/or other materials provided with the distribution.
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  12  *       names of its contributors may be used to endorse or promote products
  13  *       derived from this software without specific prior written permission.
  14  *
  15  *
  16  * ALTERNATIVELY, this software may be distributed under the terms of the
  17  * GNU General Public License ("GPL") as published by the Free Software
  18  * Foundation, either version 2 of that License or (at your option) any
  19  * later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef __FSL_FMAN_H
  34 #define __FSL_FMAN_H
  35
  36 #include "common/general.h"
  37
  38 struct fman_ext_pool_params {
  39         uint8_t                 id;    /**< External buffer pool id */
  40         uint16_t                size;  /**< External buffer pool buffer size */
  41 };
  42
  43 struct fman_ext_pools {
  44         uint8_t num_pools_used;        /**< Number of pools use by this port */
  45         struct fman_ext_pool_params *ext_buf_pool;
  46                                         /**< Parameters for each port */
  47 };
  48
  49 struct fman_backup_bm_pools {
  50         uint8_t          num_backup_pools; /**< Number of BM backup pools -
  51                                         must be smaller than the total number
  52                                         of pools defined for the specified
  53                                         port.*/
  54         uint8_t         *pool_ids;      /**< numOfBackupPools pool id's,
  55                                         specifying which pools should be used
  56                                         only as backup. Pool id's specified
  57                                         here must be a subset of the pools
  58                                         used by the specified port.*/
  59 };
  60
  61 /**************************************************************************//**
  62  @Description   A structure for defining BM pool depletion criteria
  63 *//***************************************************************************/
  64 struct fman_buf_pool_depletion {
  65         bool buf_pool_depletion_enabled;
  66         bool pools_grp_mode_enable;    /**< select mode in which pause frames
  67                                         will be sent after a number of pools
  68                                         (all together!) are depleted */
  69         uint8_t num_pools;             /**< the number of depleted pools that
  70                                         will invoke pause frames transmission.
  71                                         */
  72         bool *pools_to_consider;       /**< For each pool, TRUE if it should be
  73                                         considered for depletion (Note - this
  74                                         pool must be used by this port!). */
  75         bool single_pool_mode_enable;  /**< select mode in which pause frames
  76                                         will be sent after a single-pool
  77                                         is depleted; */
  78         bool *pools_to_consider_for_single_mode;
  79                                        /**< For each pool, TRUE if it should be
  80                                         considered for depletion (Note - this
  81                                         pool must be used by this port!) */
  82         bool has_pfc_priorities;
  83         bool *pfc_priorities_en;       /**< This field is used by the MAC as
  84                                         the Priority Enable Vector in the PFC
  85                                         frame which is transmitted */
  86 };
  87
  88 /**************************************************************************//**
  89  @Description   Enum for defining port DMA swap mode
  90 *//***************************************************************************/
  91 enum fman_dma_swap_option {
  92         FMAN_DMA_NO_SWP,           /**< No swap, transfer data as is.*/
  93         FMAN_DMA_SWP_PPC_LE,       /**< The transferred data should be swapped
  94                                         in PowerPc Little Endian mode. */
  95         FMAN_DMA_SWP_BE            /**< The transferred data should be swapped
  96                                         in Big Endian mode */
  97 };
  98
  99 /**************************************************************************//**
 100  @Description   Enum for defining port DMA cache attributes
 101 *//***************************************************************************/
 102 enum fman_dma_cache_option {
 103         FMAN_DMA_NO_STASH = 0,     /**< Cacheable, no Allocate (No Stashing) */
 104         FMAN_DMA_STASH = 1         /**< Cacheable and Allocate (Stashing on) */
 105 };
 106
 107 typedef struct t_FmPrsResult fm_prs_result_t;
 108 typedef enum e_EnetMode enet_mode_t;
 109 typedef t_Handle handle_t;
 110
 111 struct fman_revision_info {
 112         uint8_t         majorRev;               /**< Major revision */
 113         uint8_t         minorRev;               /**< Minor revision */
 114 };
 115
 116 /* sizes */
 117 #define CAPWAP_FRAG_EXTRA_SPACE                 32
 118 #define OFFSET_UNITS                            16
 119 #define MAX_INT_OFFSET                          240
 120 #define MAX_IC_SIZE                             256
 121 #define MAX_EXT_OFFSET                          496
 122 #define MAX_EXT_BUFFER_OFFSET                   511
 123
 124 /**************************************************************************
 125  @Description       Memory Mapped Registers
 126 ***************************************************************************/
 127 #define FMAN_LIODN_TBL  64      /* size of LIODN table */
 128
 129 struct fman_fpm_regs {
 130         uint32_t fmfp_tnc;      /**< FPM TNUM Control 0x00 */
 131         uint32_t fmfp_prc;      /**< FPM Port_ID FmCtl Association 0x04 */
 132         uint32_t fmfp_brkc;             /**< FPM Breakpoint Control 0x08 */
 133         uint32_t fmfp_mxd;      /**< FPM Flush Control 0x0c */
 134         uint32_t fmfp_dist1;    /**< FPM Dispatch Thresholds1 0x10 */
 135         uint32_t fmfp_dist2;    /**< FPM Dispatch Thresholds2 0x14 */
 136         uint32_t fm_epi;        /**< FM Error Pending Interrupts 0x18 */
 137         uint32_t fm_rie;        /**< FM Error Interrupt Enable 0x1c */
 138         uint32_t fmfp_fcev[4];  /**< FPM FMan-Controller Event 1-4 0x20-0x2f */
 139         uint32_t res0030[4];    /**< res 0x30 - 0x3f */
 140         uint32_t fmfp_cee[4];   /**< PM FMan-Controller Event 1-4 0x40-0x4f */
 141         uint32_t res0050[4];    /**< res 0x50-0x5f */
 142         uint32_t fmfp_tsc1;     /**< FPM TimeStamp Control1 0x60 */
 143         uint32_t fmfp_tsc2;     /**< FPM TimeStamp Control2 0x64 */
 144         uint32_t fmfp_tsp;      /**< FPM Time Stamp 0x68 */
 145         uint32_t fmfp_tsf;      /**< FPM Time Stamp Fraction 0x6c */
 146         uint32_t fm_rcr;        /**< FM Rams Control 0x70 */
 147         uint32_t fmfp_extc;     /**< FPM External Requests Control 0x74 */
 148         uint32_t fmfp_ext1;     /**< FPM External Requests Config1 0x78 */
 149         uint32_t fmfp_ext2;     /**< FPM External Requests Config2 0x7c */
 150         uint32_t fmfp_drd[16];  /**< FPM Data_Ram Data 0-15 0x80 - 0xbf */
 151         uint32_t fmfp_dra;      /**< FPM Data Ram Access 0xc0 */
 152         uint32_t fm_ip_rev_1;   /**< FM IP Block Revision 1 0xc4 */
 153         uint32_t fm_ip_rev_2;   /**< FM IP Block Revision 2 0xc8 */
 154         uint32_t fm_rstc;       /**< FM Reset Command 0xcc */
 155         uint32_t fm_cld;        /**< FM Classifier Debug 0xd0 */
 156         uint32_t fm_npi;        /**< FM Normal Pending Interrupts 0xd4 */
 157         uint32_t fmfp_exte;     /**< FPM External Requests Enable 0xd8 */
 158         uint32_t fmfp_ee;       /**< FPM Event & Mask 0xdc */
 159         uint32_t fmfp_cev[4];   /**< FPM CPU Event 1-4 0xe0-0xef */
 160         uint32_t res00f0[4];    /**< res 0xf0-0xff */
 161         uint32_t fmfp_ps[64];   /**< FPM Port Status 0x100-0x1ff */
 162         uint32_t fmfp_clfabc;   /**< FPM CLFABC 0x200 */
 163         uint32_t fmfp_clfcc;    /**< FPM CLFCC 0x204 */
 164         uint32_t fmfp_clfaval;  /**< FPM CLFAVAL 0x208 */
 165         uint32_t fmfp_clfbval;  /**< FPM CLFBVAL 0x20c */
 166         uint32_t fmfp_clfcval;  /**< FPM CLFCVAL 0x210 */
 167         uint32_t fmfp_clfamsk;  /**< FPM CLFAMSK 0x214 */
 168         uint32_t fmfp_clfbmsk;  /**< FPM CLFBMSK 0x218 */
 169         uint32_t fmfp_clfcmsk;  /**< FPM CLFCMSK 0x21c */
 170         uint32_t fmfp_clfamc;   /**< FPM CLFAMC 0x220 */
 171         uint32_t fmfp_clfbmc;   /**< FPM CLFBMC 0x224 */
 172         uint32_t fmfp_clfcmc;   /**< FPM CLFCMC 0x228 */
 173         uint32_t fmfp_decceh;   /**< FPM DECCEH 0x22c */
 174         uint32_t res0230[116];  /**< res 0x230 - 0x3ff */
 175         uint32_t fmfp_ts[128];  /**< 0x400: FPM Task Status 0x400 - 0x5ff */
 176         uint32_t res0600[0x400 - 384];
 177 };
 178
 179 struct fman_bmi_regs {
 180         uint32_t fmbm_init; /**< BMI Initialization 0x00 */
 181         uint32_t fmbm_cfg1; /**< BMI Configuration 1 0x04 */
 182         uint32_t fmbm_cfg2; /**< BMI Configuration 2 0x08 */
 183         uint32_t res000c[5]; /**< 0x0c - 0x1f */
 184         uint32_t fmbm_ievr; /**< Interrupt Event Register 0x20 */
 185         uint32_t fmbm_ier; /**< Interrupt Enable Register 0x24 */
 186         uint32_t fmbm_ifr; /**< Interrupt Force Register 0x28 */
 187         uint32_t res002c[5]; /**< 0x2c - 0x3f */
 188         uint32_t fmbm_arb[8]; /**< BMI Arbitration 0x40 - 0x5f */
 189         uint32_t res0060[12]; /**<0x60 - 0x8f */
 190         uint32_t fmbm_dtc[3]; /**< Debug Trap Counter 0x90 - 0x9b */
 191         uint32_t res009c; /**< 0x9c */
 192         uint32_t fmbm_dcv[3][4]; /**< Debug Compare val 0xa0-0xcf */
 193         uint32_t fmbm_dcm[3][4]; /**< Debug Compare Mask 0xd0-0xff */
 194         uint32_t fmbm_gde; /**< BMI Global Debug Enable 0x100 */
 195         uint32_t fmbm_pp[63]; /**< BMI Port Parameters 0x104 - 0x1ff */
 196         uint32_t res0200; /**< 0x200 */
 197         uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size 0x204 - 0x2ff */
 198         uint32_t res0300; /**< 0x300 */
 199         uint32_t fmbm_spliodn[63]; /**< Port Partition ID 0x304 - 0x3ff */
 200 };
 201
 202 struct fman_qmi_regs {
 203         uint32_t fmqm_gc; /**< General Configuration Register 0x00 */
 204         uint32_t res0004; /**< 0x04 */
 205         uint32_t fmqm_eie; /**< Error Interrupt Event Register 0x08 */
 206         uint32_t fmqm_eien; /**< Error Interrupt Enable Register 0x0c */
 207         uint32_t fmqm_eif; /**< Error Interrupt Force Register 0x10 */
 208         uint32_t fmqm_ie; /**< Interrupt Event Register 0x14 */
 209         uint32_t fmqm_ien; /**< Interrupt Enable Register 0x18 */
 210         uint32_t fmqm_if; /**< Interrupt Force Register 0x1c */
 211         uint32_t fmqm_gs; /**< Global Status Register 0x20 */
 212         uint32_t fmqm_ts; /**< Task Status Register 0x24 */
 213         uint32_t fmqm_etfc; /**< Enqueue Total Frame Counter 0x28 */
 214         uint32_t fmqm_dtfc; /**< Dequeue Total Frame Counter 0x2c */
 215         uint32_t fmqm_dc0; /**< Dequeue Counter 0 0x30 */
 216         uint32_t fmqm_dc1; /**< Dequeue Counter 1 0x34 */
 217         uint32_t fmqm_dc2; /**< Dequeue Counter 2 0x38 */
 218         uint32_t fmqm_dc3; /**< Dequeue Counter 3 0x3c */
 219         uint32_t fmqm_dfdc; /**< Dequeue FQID from Default Counter 0x40 */
 220         uint32_t fmqm_dfcc; /**< Dequeue FQID from Context Counter 0x44 */
 221         uint32_t fmqm_dffc; /**< Dequeue FQID from FD Counter 0x48 */
 222         uint32_t fmqm_dcc; /**< Dequeue Confirm Counter 0x4c */
 223         uint32_t res0050[7]; /**< 0x50 - 0x6b */
 224         uint32_t fmqm_tapc; /**< Tnum Aging Period Control 0x6c */
 225         uint32_t fmqm_dmcvc; /**< Dequeue MAC Command Valid Counter 0x70 */
 226         uint32_t fmqm_difdcc; /**< Dequeue Invalid FD Command Counter 0x74 */
 227         uint32_t fmqm_da1v; /**< Dequeue A1 Valid Counter 0x78 */
 228         uint32_t res007c; /**< 0x7c */
 229         uint32_t fmqm_dtc; /**< 0x80 Debug Trap Counter 0x80 */
 230         uint32_t fmqm_efddd; /**< 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
 231         uint32_t res0088[2]; /**< 0x88 - 0x8f */
 232         struct {
 233                 uint32_t fmqm_dtcfg1; /**< 0x90 dbg trap cfg 1 Register 0x00 */
 234                 uint32_t fmqm_dtval1; /**< Debug Trap Value 1 Register 0x04 */
 235                 uint32_t fmqm_dtm1; /**< Debug Trap Mask 1 Register 0x08 */
 236                 uint32_t fmqm_dtc1; /**< Debug Trap Counter 1 Register 0x0c */
 237                 uint32_t fmqm_dtcfg2; /**< dbg Trap cfg 2 Register 0x10 */
 238                 uint32_t fmqm_dtval2; /**< Debug Trap Value 2 Register 0x14 */
 239                 uint32_t fmqm_dtm2; /**< Debug Trap Mask 2 Register 0x18 */
 240                 uint32_t res001c; /**< 0x1c */
 241         } dbg_traps[3]; /**< 0x90 - 0xef */
 242         uint8_t res00f0[0x400 - 0xf0]; /**< 0xf0 - 0x3ff */
 243 };
 244
 245 struct fman_dma_regs {
 246         uint32_t fmdmsr; /**< FM DMA status register 0x00 */
 247         uint32_t fmdmmr; /**< FM DMA mode register 0x04 */
 248         uint32_t fmdmtr; /**< FM DMA bus threshold register 0x08 */
 249         uint32_t fmdmhy; /**< FM DMA bus hysteresis register 0x0c */
 250         uint32_t fmdmsetr; /**< FM DMA SOS emergency Threshold Register 0x10 */
 251         uint32_t fmdmtah; /**< FM DMA transfer bus address high reg 0x14 */
 252         uint32_t fmdmtal; /**< FM DMA transfer bus address low reg 0x18 */
 253         uint32_t fmdmtcid; /**< FM DMA transfer bus communication ID reg 0x1c */
 254         uint32_t fmdmra; /**< FM DMA bus internal ram address register 0x20 */
 255         uint32_t fmdmrd; /**< FM DMA bus internal ram data register 0x24 */
 256         uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x28 */
 257         uint32_t fmdmebcr; /**< FM DMA CAM base in MURAM register 0x2c */
 258         uint32_t fmdmccqdr; /**< FM DMA CAM and CMD Queue Debug reg 0x30 */
 259         uint32_t fmdmccqvr1; /**< FM DMA CAM and CMD Queue Value reg #1 0x34 */
 260         uint32_t fmdmccqvr2; /**< FM DMA CAM and CMD Queue Value reg #2 0x38 */
 261         uint32_t fmdmcqvr3; /**< FM DMA CMD Queue Value register #3 0x3c */
 262         uint32_t fmdmcqvr4; /**< FM DMA CMD Queue Value register #4 0x40 */
 263         uint32_t fmdmcqvr5; /**< FM DMA CMD Queue Value register #5 0x44 */
 264         uint32_t fmdmsefrc; /**< FM DMA Semaphore Entry Full Reject Cntr 0x48 */
 265         uint32_t fmdmsqfrc; /**< FM DMA Semaphore Queue Full Reject Cntr 0x4c */
 266         uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x50 */
 267         uint32_t fmdmdcr;  /**< FM DMA Debug Counter 0x54 */
 268         uint32_t fmdmemsr; /**< FM DMA Emergency Smoother Register 0x58 */
 269         uint32_t res005c; /**< 0x5c */
 270         uint32_t fmdmplr[FMAN_LIODN_TBL / 2]; /**< DMA LIODN regs 0x60-0xdf */
 271         uint32_t res00e0[0x400 - 56];
 272 };
 273
 274 struct fman_rg {
 275         struct fman_fpm_regs *fpm_rg;
 276         struct fman_dma_regs *dma_rg;
 277         struct fman_bmi_regs *bmi_rg;
 278         struct fman_qmi_regs *qmi_rg;
 279 };
 280
 281 enum fman_dma_cache_override {
 282         E_FMAN_DMA_NO_CACHE_OR = 0, /**< No override of the Cache field */
 283         E_FMAN_DMA_NO_STASH_DATA, /**< No data stashing in system level cache */
 284         E_FMAN_DMA_MAY_STASH_DATA, /**< Stashing allowed in sys level cache */
 285         E_FMAN_DMA_STASH_DATA /**< Stashing performed in system level cache */
 286 };
 287
 288 enum fman_dma_aid_mode {
 289         E_FMAN_DMA_AID_OUT_PORT_ID = 0,           /**< 4 LSB of PORT_ID */
 290         E_FMAN_DMA_AID_OUT_TNUM                   /**< 4 LSB of TNUM */
 291 };
 292
 293 enum fman_dma_dbg_cnt_mode {
 294         E_FMAN_DMA_DBG_NO_CNT = 0, /**< No counting */
 295         E_FMAN_DMA_DBG_CNT_DONE, /**< Count DONE commands */
 296         E_FMAN_DMA_DBG_CNT_COMM_Q_EM, /**< command Q emergency signal */
 297         E_FMAN_DMA_DBG_CNT_INT_READ_EM, /**< Read buf emergency signal */
 298         E_FMAN_DMA_DBG_CNT_INT_WRITE_EM, /**< Write buf emergency signal */
 299         E_FMAN_DMA_DBG_CNT_FPM_WAIT, /**< FPM WAIT signal */
 300         E_FMAN_DMA_DBG_CNT_SIGLE_BIT_ECC, /**< Single bit ECC errors */
 301         E_FMAN_DMA_DBG_CNT_RAW_WAR_PROT /**< RAW & WAR protection counter */
 302 };
 303
 304 enum fman_dma_emergency_level {
 305         E_FMAN_DMA_EM_EBS = 0, /**< EBS emergency */
 306         E_FMAN_DMA_EM_SOS /**< SOS emergency */
 307 };
 308
 309 enum fman_catastrophic_err {
 310         E_FMAN_CATAST_ERR_STALL_PORT = 0, /**< Port_ID stalled reset required */
 311         E_FMAN_CATAST_ERR_STALL_TASK /**< Only erroneous task is stalled */
 312 };
 313
 314 enum fman_dma_err {
 315         E_FMAN_DMA_ERR_CATASTROPHIC = 0, /**< Catastrophic DMA error */
 316         E_FMAN_DMA_ERR_REPORT /**< Reported DMA error */
 317 };
 318
 319 struct fman_cfg {
 320         uint16_t        liodn_bs_pr_port[FMAN_LIODN_TBL];/* base per port */
 321         bool            en_counters;
 322         uint8_t         disp_limit_tsh;
 323         uint8_t         prs_disp_tsh;
 324         uint8_t         plcr_disp_tsh;
 325         uint8_t         kg_disp_tsh;
 326         uint8_t         bmi_disp_tsh;
 327         uint8_t         qmi_enq_disp_tsh;
 328         uint8_t         qmi_deq_disp_tsh;
 329         uint8_t         fm_ctl1_disp_tsh;
 330         uint8_t         fm_ctl2_disp_tsh;
 331         enum fman_dma_cache_override    dma_cache_override;
 332         enum fman_dma_aid_mode          dma_aid_mode;
 333         bool            dma_aid_override;
 334         uint8_t         dma_axi_dbg_num_of_beats;
 335         uint8_t         dma_cam_num_of_entries;
 336         uint32_t        dma_watchdog;
 337         uint8_t         dma_comm_qtsh_asrt_emer;
 338         uint8_t         dma_write_buf_tsh_asrt_emer;
 339         uint8_t         dma_read_buf_tsh_asrt_emer;
 340         uint8_t         dma_comm_qtsh_clr_emer;
 341         uint8_t         dma_write_buf_tsh_clr_emer;
 342         uint8_t         dma_read_buf_tsh_clr_emer;
 343         uint32_t        dma_sos_emergency;
 344         enum fman_dma_dbg_cnt_mode      dma_dbg_cnt_mode;
 345         bool            dma_stop_on_bus_error;
 346         bool            dma_en_emergency;
 347         uint32_t        dma_emergency_bus_select;
 348         enum fman_dma_emergency_level   dma_emergency_level;
 349         bool            dma_en_emergency_smoother;
 350         uint32_t        dma_emergency_switch_counter;
 351         bool            halt_on_external_activ;
 352         bool            halt_on_unrecov_ecc_err;
 353         enum fman_catastrophic_err      catastrophic_err;
 354         enum fman_dma_err               dma_err;
 355         bool            en_muram_test_mode;
 356         bool            en_iram_test_mode;
 357         bool            external_ecc_rams_enable;
 358         uint16_t        tnum_aging_period;
 359         uint32_t        exceptions;
 360         uint16_t        clk_freq;
 361         bool            pedantic_dma;
 362         uint32_t        cam_base_addr;
 363         uint32_t        fifo_base_addr;
 364         uint32_t        total_fifo_size;
 365         uint8_t         total_num_of_tasks;
 366         bool            qmi_deq_option_support;
 367         uint32_t        qmi_def_tnums_thresh;
 368         bool            fman_partition_array;
 369         uint8_t         num_of_fman_ctrl_evnt_regs;
 370 };
 371
 372 /**************************************************************************//**
 373  @Description       Exceptions
 374 *//***************************************************************************/
 375 #define FMAN_EX_DMA_BUS_ERROR                   0x80000000
 376 #define FMAN_EX_DMA_READ_ECC                    0x40000000
 377 #define FMAN_EX_DMA_SYSTEM_WRITE_ECC            0x20000000
 378 #define FMAN_EX_DMA_FM_WRITE_ECC                0x10000000
 379 #define FMAN_EX_FPM_STALL_ON_TASKS              0x08000000
 380 #define FMAN_EX_FPM_SINGLE_ECC                  0x04000000
 381 #define FMAN_EX_FPM_DOUBLE_ECC                  0x02000000
 382 #define FMAN_EX_QMI_SINGLE_ECC                  0x01000000
 383 #define FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID     0x00800000
 384 #define FMAN_EX_QMI_DOUBLE_ECC                  0x00400000
 385 #define FMAN_EX_BMI_LIST_RAM_ECC                0x00200000
 386 #define FMAN_EX_BMI_PIPELINE_ECC                0x00100000
 387 #define FMAN_EX_BMI_STATISTICS_RAM_ECC          0x00080000
 388 #define FMAN_EX_IRAM_ECC                        0x00040000
 389 #define FMAN_EX_NURAM_ECC                       0x00020000
 390 #define FMAN_EX_BMI_DISPATCH_RAM_ECC            0x00010000
 391
 392 enum fman_exceptions {
 393         E_FMAN_EX_DMA_BUS_ERROR = 0, /**< DMA bus error. */
 394         E_FMAN_EX_DMA_READ_ECC, /**< Read Buffer ECC error */
 395         E_FMAN_EX_DMA_SYSTEM_WRITE_ECC, /**< Write Buffer ECC err on sys side */
 396         E_FMAN_EX_DMA_FM_WRITE_ECC, /**< Write Buffer ECC error on FM side */
 397         E_FMAN_EX_FPM_STALL_ON_TASKS, /**< Stall of tasks on FPM */
 398         E_FMAN_EX_FPM_SINGLE_ECC, /**< Single ECC on FPM. */
 399         E_FMAN_EX_FPM_DOUBLE_ECC, /**< Double ECC error on FPM ram access */
 400         E_FMAN_EX_QMI_SINGLE_ECC, /**< Single ECC on QMI. */
 401         E_FMAN_EX_QMI_DOUBLE_ECC, /**< Double bit ECC occurred on QMI */
 402         E_FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/**< DeQ from unknown port id */
 403         E_FMAN_EX_BMI_LIST_RAM_ECC, /**< Linked List RAM ECC error */
 404         E_FMAN_EX_BMI_STORAGE_PROFILE_ECC, /**< storage profile */
 405         E_FMAN_EX_BMI_STATISTICS_RAM_ECC, /**< Statistics RAM ECC Err Enable */
 406         E_FMAN_EX_BMI_DISPATCH_RAM_ECC, /**< Dispatch RAM ECC Error Enable */
 407         E_FMAN_EX_IRAM_ECC, /**< Double bit ECC occurred on IRAM*/
 408         E_FMAN_EX_MURAM_ECC /**< Double bit ECC occurred on MURAM*/
 409 };
 410
 411 enum fman_counters {
 412         E_FMAN_COUNTERS_ENQ_TOTAL_FRAME = 0, /**< QMI tot enQ frames counter */
 413         E_FMAN_COUNTERS_DEQ_TOTAL_FRAME, /**< QMI tot deQ frames counter */
 414         E_FMAN_COUNTERS_DEQ_0, /**< QMI 0 frames from QMan counter */
 415         E_FMAN_COUNTERS_DEQ_1, /**< QMI 1 frames from QMan counter */
 416         E_FMAN_COUNTERS_DEQ_2, /**< QMI 2 frames from QMan counter */
 417         E_FMAN_COUNTERS_DEQ_3, /**< QMI 3 frames from QMan counter */
 418         E_FMAN_COUNTERS_DEQ_FROM_DEFAULT, /**< QMI deQ from dflt queue cntr */
 419         E_FMAN_COUNTERS_DEQ_FROM_CONTEXT, /**< QMI deQ from FQ context cntr */
 420         E_FMAN_COUNTERS_DEQ_FROM_FD, /**< QMI deQ from FD command field cntr */
 421         E_FMAN_COUNTERS_DEQ_CONFIRM, /**< QMI dequeue confirm counter */
 422         E_FMAN_COUNTERS_SEMAPHOR_ENTRY_FULL_REJECT, /**< DMA full entry cntr */
 423         E_FMAN_COUNTERS_SEMAPHOR_QUEUE_FULL_REJECT, /**< DMA full CAM Q cntr */
 424         E_FMAN_COUNTERS_SEMAPHOR_SYNC_REJECT /**< DMA sync counter */
 425 };
 426
 427 #define FPM_PRT_FM_CTL1 0x00000001
 428 #define FPM_PRT_FM_CTL2 0x00000002
 429
 430 /**************************************************************************//**
 431  @Description       DMA definitions
 432 *//***************************************************************************/
 433
 434 /* masks */
 435 #define DMA_MODE_AID_OR                 0x20000000
 436 #define DMA_MODE_SBER                   0x10000000
 437 #define DMA_MODE_BER                    0x00200000
 438 #define DMA_MODE_EB             0x00100000
 439 #define DMA_MODE_ECC                    0x00000020
 440 #define DMA_MODE_PRIVILEGE_PROT 0x00001000
 441 #define DMA_MODE_SECURE_PROT    0x00000800
 442 #define DMA_MODE_EMER_READ              0x00080000
 443 #define DMA_MODE_EMER_WRITE             0x00040000
 444 #define DMA_MODE_CACHE_OR_MASK  0xC0000000
 445 #define DMA_MODE_CEN_MASK       0x0000E000
 446 #define DMA_MODE_DBG_MASK       0x00000380
 447 #define DMA_MODE_AXI_DBG_MASK   0x0F000000
 448
 449 #define DMA_EMSR_EMSTR_MASK         0x0000FFFF
 450
 451 #define DMA_TRANSFER_PORTID_MASK        0xFF000000
 452 #define DMA_TRANSFER_TNUM_MASK          0x00FF0000
 453 #define DMA_TRANSFER_LIODN_MASK         0x00000FFF
 454
 455 #define DMA_HIGH_LIODN_MASK             0x0FFF0000
 456 #define DMA_LOW_LIODN_MASK              0x00000FFF
 457
 458 #define DMA_STATUS_CMD_QUEUE_NOT_EMPTY  0x10000000
 459 #define DMA_STATUS_BUS_ERR              0x08000000
 460 #define DMA_STATUS_READ_ECC             0x04000000
 461 #define DMA_STATUS_SYSTEM_WRITE_ECC     0x02000000
 462 #define DMA_STATUS_FM_WRITE_ECC         0x01000000
 463 #define DMA_STATUS_SYSTEM_DPEXT_ECC     0x00800000
 464 #define DMA_STATUS_FM_DPEXT_ECC         0x00400000
 465 #define DMA_STATUS_SYSTEM_DPDAT_ECC     0x00200000
 466 #define DMA_STATUS_FM_DPDAT_ECC         0x00100000
 467 #define DMA_STATUS_FM_SPDAT_ECC         0x00080000
 468
 469 #define FM_LIODN_BASE_MASK              0x00000FFF
 470
 471 /* shifts */
 472 #define DMA_MODE_CACHE_OR_SHIFT                 30
 473 #define DMA_MODE_BUS_PRI_SHIFT                  16
 474 #define DMA_MODE_AXI_DBG_SHIFT                  24
 475 #define DMA_MODE_CEN_SHIFT                      13
 476 #define DMA_MODE_BUS_PROT_SHIFT                 10
 477 #define DMA_MODE_DBG_SHIFT                      7
 478 #define DMA_MODE_EMER_LVL_SHIFT                 6
 479 #define DMA_MODE_AID_MODE_SHIFT                 4
 480 #define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS       16
 481 #define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES         32
 482
 483 #define DMA_THRESH_COMMQ_SHIFT                  24
 484 #define DMA_THRESH_READ_INT_BUF_SHIFT           16
 485
 486 #define DMA_LIODN_SHIFT                         16
 487
 488 #define DMA_TRANSFER_PORTID_SHIFT               24
 489 #define DMA_TRANSFER_TNUM_SHIFT                 16
 490
 491 /* sizes */
 492 #define DMA_MAX_WATCHDOG                        0xffffffff
 493
 494 /* others */
 495 #define DMA_CAM_SIZEOF_ENTRY                    0x40
 496 #define DMA_CAM_ALIGN                           0x1000
 497 #define DMA_CAM_UNITS                           8
 498
 499 /**************************************************************************//**
 500  @Description       General defines
 501 *//***************************************************************************/
 502
 503 #define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL
 504 #define FM_UCODE_DEBUG_INSTRUCTION      0x6ffff805UL
 505
 506 /**************************************************************************//**
 507  @Description       FPM defines
 508 *//***************************************************************************/
 509
 510 /* masks */
 511 #define FPM_EV_MASK_DOUBLE_ECC          0x80000000
 512 #define FPM_EV_MASK_STALL               0x40000000
 513 #define FPM_EV_MASK_SINGLE_ECC          0x20000000
 514 #define FPM_EV_MASK_RELEASE_FM          0x00010000
 515 #define FPM_EV_MASK_DOUBLE_ECC_EN       0x00008000
 516 #define FPM_EV_MASK_STALL_EN            0x00004000
 517 #define FPM_EV_MASK_SINGLE_ECC_EN       0x00002000
 518 #define FPM_EV_MASK_EXTERNAL_HALT       0x00000008
 519 #define FPM_EV_MASK_ECC_ERR_HALT        0x00000004
 520
 521 #define FPM_RAM_RAMS_ECC_EN             0x80000000
 522 #define FPM_RAM_IRAM_ECC_EN             0x40000000
 523 #define FPM_RAM_MURAM_ECC               0x00008000
 524 #define FPM_RAM_IRAM_ECC                0x00004000
 525 #define FPM_RAM_MURAM_TEST_ECC          0x20000000
 526 #define FPM_RAM_IRAM_TEST_ECC           0x10000000
 527 #define FPM_RAM_RAMS_ECC_EN_SRC_SEL     0x08000000
 528
 529 #define FPM_IRAM_ECC_ERR_EX_EN          0x00020000
 530 #define FPM_MURAM_ECC_ERR_EX_EN         0x00040000
 531
 532 #define FPM_REV1_MAJOR_MASK             0x0000FF00
 533 #define FPM_REV1_MINOR_MASK             0x000000FF
 534
 535 #define FPM_REV2_INTEG_MASK             0x00FF0000
 536 #define FPM_REV2_ERR_MASK               0x0000FF00
 537 #define FPM_REV2_CFG_MASK               0x000000FF
 538
 539 #define FPM_TS_FRACTION_MASK            0x0000FFFF
 540 #define FPM_TS_CTL_EN                   0x80000000
 541
 542 #define FPM_PRC_REALSE_STALLED          0x00800000
 543
 544 #define FPM_PS_STALLED                  0x00800000
 545 #define FPM_PS_FM_CTL1_SEL              0x80000000
 546 #define FPM_PS_FM_CTL2_SEL              0x40000000
 547 #define FPM_PS_FM_CTL_SEL_MASK  (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL)
 548
 549 #define FPM_RSTC_FM_RESET               0x80000000
 550 #define FPM_RSTC_10G0_RESET             0x04000000
 551 #define FPM_RSTC_1G0_RESET              0x40000000
 552 #define FPM_RSTC_1G1_RESET              0x20000000
 553 #define FPM_RSTC_1G2_RESET              0x10000000
 554 #define FPM_RSTC_1G3_RESET              0x08000000
 555 #define FPM_RSTC_1G4_RESET              0x02000000
 556
 557
 558 #define FPM_DISP_LIMIT_MASK             0x1F000000
 559 #define FPM_THR1_PRS_MASK               0xFF000000
 560 #define FPM_THR1_KG_MASK                0x00FF0000
 561 #define FPM_THR1_PLCR_MASK              0x0000FF00
 562 #define FPM_THR1_BMI_MASK               0x000000FF
 563
 564 #define FPM_THR2_QMI_ENQ_MASK           0xFF000000
 565 #define FPM_THR2_QMI_DEQ_MASK           0x000000FF
 566 #define FPM_THR2_FM_CTL1_MASK           0x00FF0000
 567 #define FPM_THR2_FM_CTL2_MASK           0x0000FF00
 568
 569 /* shifts */
 570 #define FPM_DISP_LIMIT_SHIFT            24
 571
 572 #define FPM_THR1_PRS_SHIFT              24
 573 #define FPM_THR1_KG_SHIFT               16
 574 #define FPM_THR1_PLCR_SHIFT             8
 575 #define FPM_THR1_BMI_SHIFT              0
 576
 577 #define FPM_THR2_QMI_ENQ_SHIFT          24
 578 #define FPM_THR2_QMI_DEQ_SHIFT          0
 579 #define FPM_THR2_FM_CTL1_SHIFT          16
 580 #define FPM_THR2_FM_CTL2_SHIFT          8
 581
 582 #define FPM_EV_MASK_CAT_ERR_SHIFT       1
 583 #define FPM_EV_MASK_DMA_ERR_SHIFT       0
 584
 585 #define FPM_REV1_MAJOR_SHIFT            8
 586 #define FPM_REV1_MINOR_SHIFT            0
 587
 588 #define FPM_REV2_INTEG_SHIFT            16
 589 #define FPM_REV2_ERR_SHIFT              8
 590 #define FPM_REV2_CFG_SHIFT              0
 591
 592 #define FPM_TS_INT_SHIFT                16
 593
 594 #define FPM_PORT_FM_CTL_PORTID_SHIFT    24
 595
 596 #define FPM_PS_FM_CTL_SEL_SHIFT         30
 597 #define FPM_PRC_ORA_FM_CTL_SEL_SHIFT    16
 598
 599 #define FPM_DISP_LIMIT_SHIFT            24
 600
 601 /* Interrupts defines */
 602 #define FPM_EVENT_FM_CTL_0              0x00008000
 603 #define FPM_EVENT_FM_CTL                0x0000FF00
 604 #define FPM_EVENT_FM_CTL_BRK            0x00000080
 605
 606 /* others */
 607 #define FPM_MAX_DISP_LIMIT              31
 608 #define FPM_RSTC_FM_RESET               0x80000000
 609 #define FPM_RSTC_1G0_RESET              0x40000000
 610 #define FPM_RSTC_1G1_RESET              0x20000000
 611 #define FPM_RSTC_1G2_RESET              0x10000000
 612 #define FPM_RSTC_1G3_RESET              0x08000000
 613 #define FPM_RSTC_10G0_RESET             0x04000000
 614 #define FPM_RSTC_1G4_RESET              0x02000000
 615 #define FPM_RSTC_1G5_RESET              0x01000000
 616 #define FPM_RSTC_1G6_RESET              0x00800000
 617 #define FPM_RSTC_1G7_RESET              0x00400000
 618 #define FPM_RSTC_10G1_RESET             0x00200000
 619 /**************************************************************************//**
 620  @Description       BMI defines
 621 *//***************************************************************************/
 622 /* masks */
 623 #define BMI_INIT_START                          0x80000000
 624 #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC     0x80000000
 625 #define BMI_ERR_INTR_EN_LIST_RAM_ECC            0x40000000
 626 #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC      0x20000000
 627 #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC        0x10000000
 628 #define BMI_NUM_OF_TASKS_MASK                   0x3F000000
 629 #define BMI_NUM_OF_EXTRA_TASKS_MASK             0x000F0000
 630 #define BMI_NUM_OF_DMAS_MASK                    0x00000F00
 631 #define BMI_NUM_OF_EXTRA_DMAS_MASK              0x0000000F
 632 #define BMI_FIFO_SIZE_MASK                      0x000003FF
 633 #define BMI_EXTRA_FIFO_SIZE_MASK                0x03FF0000
 634 #define BMI_CFG2_DMAS_MASK                      0x0000003F
 635 #define BMI_TOTAL_FIFO_SIZE_MASK           0x07FF0000
 636 #define BMI_TOTAL_NUM_OF_TASKS_MASK        0x007F0000
 637
 638 /* shifts */
 639 #define BMI_CFG2_TASKS_SHIFT            16
 640 #define BMI_CFG2_DMAS_SHIFT             0
 641 #define BMI_CFG1_FIFO_SIZE_SHIFT        16
 642 #define BMI_FIFO_SIZE_SHIFT             0
 643 #define BMI_EXTRA_FIFO_SIZE_SHIFT       16
 644 #define BMI_NUM_OF_TASKS_SHIFT          24
 645 #define BMI_EXTRA_NUM_OF_TASKS_SHIFT    16
 646 #define BMI_NUM_OF_DMAS_SHIFT           8
 647 #define BMI_EXTRA_NUM_OF_DMAS_SHIFT     0
 648
 649 /* others */
 650 #define BMI_FIFO_ALIGN                  0x100
 651 #define FMAN_BMI_FIFO_UNITS             0x100
 652
 653
 654 /**************************************************************************//**
 655  @Description       QMI defines
 656 *//***************************************************************************/
 657 /* masks */
 658 #define QMI_CFG_ENQ_EN                  0x80000000
 659 #define QMI_CFG_DEQ_EN                  0x40000000
 660 #define QMI_CFG_EN_COUNTERS             0x10000000
 661 #define QMI_CFG_SOFT_RESET              0x01000000
 662 #define QMI_CFG_DEQ_MASK                0x0000003F
 663 #define QMI_CFG_ENQ_MASK                0x00003F00
 664
 665 #define QMI_ERR_INTR_EN_DOUBLE_ECC      0x80000000
 666 #define QMI_ERR_INTR_EN_DEQ_FROM_DEF    0x40000000
 667 #define QMI_INTR_EN_SINGLE_ECC          0x80000000
 668
 669 /* shifts */
 670 #define QMI_CFG_ENQ_SHIFT               8
 671 #define QMI_TAPC_TAP                    22
 672
 673 #define QMI_GS_HALT_NOT_BUSY            0x00000002
 674
 675 /**************************************************************************//**
 676  @Description       IRAM defines
 677 *//***************************************************************************/
 678 /* masks */
 679 #define IRAM_IADD_AIE                   0x80000000
 680 #define IRAM_READY                      0x80000000
 681
 682 uint32_t fman_get_bmi_err_event(struct fman_bmi_regs *bmi_rg);
 683 uint32_t fman_get_qmi_err_event(struct fman_qmi_regs *qmi_rg);
 684 uint32_t fman_get_dma_com_id(struct fman_dma_regs *dma_rg);
 685 uint64_t fman_get_dma_addr(struct fman_dma_regs *dma_rg);
 686 uint32_t fman_get_dma_err_event(struct fman_dma_regs *dma_rg);
 687 uint32_t fman_get_fpm_err_event(struct fman_fpm_regs *fpm_rg);
 688 uint32_t fman_get_muram_err_event(struct fman_fpm_regs *fpm_rg);
 689 uint32_t fman_get_iram_err_event(struct fman_fpm_regs *fpm_rg);
 690 uint32_t fman_get_qmi_event(struct fman_qmi_regs *qmi_rg);
 691 uint32_t fman_get_fpm_error_interrupts(struct fman_fpm_regs *fpm_rg);
 692 uint32_t fman_get_ctrl_intr(struct fman_fpm_regs *fpm_rg,
 693                                 uint8_t event_reg_id);
 694 uint8_t fman_get_qmi_deq_th(struct fman_qmi_regs *qmi_rg);
 695 uint8_t fman_get_qmi_enq_th(struct fman_qmi_regs *qmi_rg);
 696 uint16_t fman_get_size_of_fifo(struct fman_bmi_regs *bmi_rg, uint8_t port_id);
 697 uint32_t fman_get_total_fifo_size(struct fman_bmi_regs *bmi_rg);
 698 uint16_t fman_get_size_of_extra_fifo(struct fman_bmi_regs *bmi_rg,
 699                                 uint8_t port_id);
 700 uint8_t fman_get_num_of_tasks(struct fman_bmi_regs *bmi_rg, uint8_t port_id);
 701 uint8_t fman_get_num_extra_tasks(struct fman_bmi_regs *bmi_rg,
 702                                 uint8_t port_id);
 703 uint8_t fman_get_num_of_dmas(struct fman_bmi_regs *bmi_rg, uint8_t port_id);
 704 uint8_t fman_get_num_extra_dmas(struct fman_bmi_regs *bmi_rg,
 705                                 uint8_t port_id);
 706 uint32_t fman_get_normal_pending(struct fman_fpm_regs *fpm_rg);
 707 uint32_t fman_get_controller_event(struct fman_fpm_regs *fpm_rg,
 708                                         uint8_t reg_id);
 709 uint32_t fman_get_error_pending(struct fman_fpm_regs *fpm_rg);
 710 void fman_get_revision(struct fman_fpm_regs *fpm_rg, uint8_t *major,
 711                                 uint8_t *minor);
 712 uint32_t fman_get_counter(struct fman_rg *fman_rg,
 713                                 enum fman_counters reg_name);
 714 uint32_t fman_get_dma_status(struct fman_dma_regs *dma_rg);
 715
 716
 717 int fman_set_erratum_10gmac_a004_wa(struct fman_fpm_regs *fpm_rg);
 718 void fman_set_ctrl_intr(struct fman_fpm_regs *fpm_rg, uint8_t event_reg_id,
 719                                 uint32_t enable_events);
 720 void fman_set_num_of_riscs_per_port(struct fman_fpm_regs *fpm_rg,
 721                                 uint8_t port_id,
 722                                 uint8_t num_fman_ctrls,
 723                                 uint32_t or_fman_ctrl);
 724 void fman_set_order_restoration_per_port(struct fman_fpm_regs *fpm_rg,
 725                                 uint8_t port_id,
 726                                 bool independent_mode,
 727                                 bool is_rx_port);
 728 void fman_set_qmi_enq_th(struct fman_qmi_regs *qmi_rg, uint8_t val);
 729 void fman_set_qmi_deq_th(struct fman_qmi_regs *qmi_rg, uint8_t val);
 730 void fman_set_liodn_per_port(struct fman_rg *fman_rg,
 731                                 uint8_t port_id,
 732                                 uint16_t liodn_base,
 733                                 uint16_t liodn_offset);
 734 void fman_set_size_of_fifo(struct fman_bmi_regs *bmi_rg,
 735                                 uint8_t port_id,
 736                                 uint32_t size_of_fifo,
 737                                 uint32_t extra_size_of_fifo);
 738 void fman_set_num_of_tasks(struct fman_bmi_regs *bmi_rg,
 739                                 uint8_t port_id,
 740                                 uint8_t num_of_tasks,
 741                                 uint8_t num_of_extra_tasks);
 742 void fman_set_num_of_open_dmas(struct fman_bmi_regs *bmi_rg,
 743                                 uint8_t port_id,
 744                                 uint8_t num_of_open_dmas,
 745                                 uint8_t num_of_extra_open_dmas,
 746                                 uint8_t total_num_of_dmas);
 747 void fman_set_ports_bandwidth(struct fman_bmi_regs *bmi_rg, uint8_t *weights);
 748 int fman_set_exception(struct fman_rg *fman_rg,
 749                                 enum fman_exceptions exception,
 750                                 bool enable);
 751 void fman_set_dma_emergency(struct fman_dma_regs *dma_rg, bool is_write,
 752                                 bool enable);
 753 void fman_set_dma_ext_bus_pri(struct fman_dma_regs *dma_rg, uint32_t pri);
 754 void fman_set_congestion_group_pfc_priority(uint32_t *cpg_rg,
 755                                             uint32_t congestion_group_id,
 756                                             uint8_t piority_bit_map,
 757                                             uint32_t reg_num);
 758
 759
 760 void fman_defconfig(struct fman_cfg *cfg, bool is_master);
 761 void fman_regconfig(struct fman_rg *fman_rg, struct fman_cfg *cfg);
 762 int fman_fpm_init(struct fman_fpm_regs *fpm_rg, struct fman_cfg *cfg);
 763 int fman_bmi_init(struct fman_bmi_regs *bmi_rg, struct fman_cfg *cfg);
 764 int fman_qmi_init(struct fman_qmi_regs *qmi_rg, struct fman_cfg *cfg);
 765 int fman_dma_init(struct fman_dma_regs *dma_rg, struct fman_cfg *cfg);
 766 void fman_free_resources(struct fman_rg *fman_rg);
 767 int fman_enable(struct fman_rg *fman_rg, struct fman_cfg *cfg);
 768 void fman_reset(struct fman_fpm_regs *fpm_rg);
 769 void fman_resume(struct fman_fpm_regs *fpm_rg);
 770
 771
 772 void fman_enable_time_stamp(struct fman_fpm_regs *fpm_rg,
 773                                 uint8_t count1ubit,
 774                                 uint16_t fm_clk_freq);
 775 void fman_enable_rams_ecc(struct fman_fpm_regs *fpm_rg);
 776 void fman_qmi_disable_dispatch_limit(struct fman_fpm_regs *fpm_rg);
 777 void fman_disable_rams_ecc(struct fman_fpm_regs *fpm_rg);
 778 void fman_resume_stalled_port(struct fman_fpm_regs *fpm_rg, uint8_t port_id);
 779 int fman_reset_mac(struct fman_fpm_regs *fpm_rg, uint8_t macId, bool is_10g);
 780 bool fman_is_port_stalled(struct fman_fpm_regs *fpm_rg, uint8_t port_id);
 781 bool fman_rams_ecc_is_external_ctl(struct fman_fpm_regs *fpm_rg);
 782 bool fman_is_qmi_halt_not_busy_state(struct fman_qmi_regs *qmi_rg);
 783 int fman_modify_counter(struct fman_rg *fman_rg,
 784                                 enum fman_counters reg_name,
 785                                 uint32_t val);
 786 void fman_force_intr(struct fman_rg *fman_rg,
 787                                 enum fman_exceptions exception);
 788 void fman_set_vsp_window(struct fman_bmi_regs *bmi_rg,
 789                                      uint8_t port_id,
 790                                          uint8_t base_storage_profile,
 791                                          uint8_t log2_num_of_profiles);
 792
 793 /**************************************************************************//**
 794  @Description       default values
 795 *//***************************************************************************/
 796 #define DEFAULT_CATASTROPHIC_ERR                E_FMAN_CATAST_ERR_STALL_PORT
 797 #define DEFAULT_DMA_ERR                         E_FMAN_DMA_ERR_CATASTROPHIC
 798 #define DEFAULT_HALT_ON_EXTERNAL_ACTIVATION     FALSE   /* do not change! if changed, must be disabled for rev1 ! */
 799 #define DEFAULT_HALT_ON_UNRECOVERABLE_ECC_ERROR FALSE   /* do not change! if changed, must be disabled for rev1 ! */
 800 #define DEFAULT_EXTERNAL_ECC_RAMS_ENABLE        FALSE
 801 #define DEFAULT_AID_OVERRIDE                    FALSE
 802 #define DEFAULT_AID_MODE                        E_FMAN_DMA_AID_OUT_TNUM
 803 #define DEFAULT_DMA_COMM_Q_LOW                  0x2A
 804 #define DEFAULT_DMA_COMM_Q_HIGH                 0x3F
 805 #define DEFAULT_CACHE_OVERRIDE                  E_FMAN_DMA_NO_CACHE_OR
 806 #define DEFAULT_DMA_CAM_NUM_OF_ENTRIES          64
 807 #define DEFAULT_DMA_DBG_CNT_MODE                E_FMAN_DMA_DBG_NO_CNT
 808 #define DEFAULT_DMA_EN_EMERGENCY                FALSE
 809 #define DEFAULT_DMA_SOS_EMERGENCY               0
 810 #define DEFAULT_DMA_WATCHDOG                    0 /* disabled */
 811 #define DEFAULT_DMA_EN_EMERGENCY_SMOOTHER       FALSE
 812 #define DEFAULT_DMA_EMERGENCY_SWITCH_COUNTER    0
 813 #define DEFAULT_DISP_LIMIT                      0
 814 #define DEFAULT_PRS_DISP_TH                     16
 815 #define DEFAULT_PLCR_DISP_TH                    16
 816 #define DEFAULT_KG_DISP_TH                      16
 817 #define DEFAULT_BMI_DISP_TH                     16
 818 #define DEFAULT_QMI_ENQ_DISP_TH                 16
 819 #define DEFAULT_QMI_DEQ_DISP_TH                 16
 820 #define DEFAULT_FM_CTL1_DISP_TH                 16
 821 #define DEFAULT_FM_CTL2_DISP_TH                 16
 822 #define DEFAULT_TNUM_AGING_PERIOD               4
 823
 824
 825 #endif /* __FSL_FMAN_H */