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33 #ifndef __FSL_FMAN_MEMAC_MII_ACC_H
34 #define __FSL_FMAN_MEMAC_MII_ACC_H
36 #include "common/general.h"
38 /* MII Management Registers */
39 #define MDIO_CFG_CLK_DIV_MASK 0x0080ff80
40 #define MDIO_CFG_CLK_DIV_SHIFT 7
41 #define MDIO_CFG_HOLD_MASK 0x0000001c
42 #define MDIO_CFG_ENC45 0x00000040
43 #define MDIO_CFG_READ_ERR 0x00000002
44 #define MDIO_CFG_BSY 0x00000001
46 #define MDIO_CTL_PHY_ADDR_SHIFT 5
47 #define MDIO_CTL_READ 0x00008000
49 #define MDIO_DATA_BSY 0x80000000
51 /*MEMAC Internal PHY Registers - SGMII */
52 #define PHY_SGMII_CR_PHY_RESET 0x8000
53 #define PHY_SGMII_CR_RESET_AN 0x0200
54 #define PHY_SGMII_CR_DEF_VAL 0x1140
55 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
56 #define PHY_SGMII_DEV_ABILITY_1000X 0x01A0
57 #define PHY_SGMII_IF_MODE_AN 0x0002
58 #define PHY_SGMII_IF_MODE_SGMII 0x0001
59 #define PHY_SGMII_IF_MODE_1000X 0x0000
61 /*----------------------------------------------------*/
62 /* MII Configuration Control Memory Map Registers */
63 /*----------------------------------------------------*/
64 struct memac_mii_access_mem_map {
65 uint32_t mdio_cfg; /* 0x030 */
66 uint32_t mdio_ctrl; /* 0x034 */
67 uint32_t mdio_data; /* 0x038 */
68 uint32_t mdio_addr; /* 0x03c */
71 int fman_memac_mii_read_phy_reg(struct memac_mii_access_mem_map *mii_regs,
72 uint8_t phy_addr, uint8_t reg, uint16_t *data,
73 enum enet_speed enet_speed);
74 int fman_memac_mii_write_phy_reg(struct memac_mii_access_mem_map *mii_regs,
75 uint8_t phy_addr, uint8_t reg, uint16_t data,
76 enum enet_speed enet_speed);
78 #endif /* __MAC_API_MEMAC_MII_ACC_H */