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33 #ifndef __FSL_FMAN_PORT_H
34 #define __FSL_FMAN_PORT_H
36 #include "fsl_fman_sp.h"
38 /** @Collection Registers bit fields */
40 /** @Description BMI defines */
41 #define BMI_EBD_EN 0x80000000
43 #define BMI_PORT_CFG_EN 0x80000000
44 #define BMI_PORT_CFG_FDOVR 0x02000000
45 #define BMI_PORT_CFG_IM 0x01000000
47 #define BMI_PORT_STATUS_BSY 0x80000000
49 #define BMI_DMA_ATTR_SWP_SHIFT FMAN_SP_DMA_ATTR_SWP_SHIFT
50 #define BMI_DMA_ATTR_IC_STASH_ON 0x10000000
51 #define BMI_DMA_ATTR_HDR_STASH_ON 0x04000000
52 #define BMI_DMA_ATTR_SG_STASH_ON 0x01000000
53 #define BMI_DMA_ATTR_WRITE_OPTIMIZE FMAN_SP_DMA_ATTR_WRITE_OPTIMIZE
55 #define BMI_RX_FIFO_PRI_ELEVATION_SHIFT 16
56 #define BMI_RX_FIFO_THRESHOLD_ETHE 0x80000000
58 #define BMI_TX_FRAME_END_CS_IGNORE_SHIFT 24
59 #define BMI_RX_FRAME_END_CS_IGNORE_SHIFT 24
60 #define BMI_RX_FRAME_END_CUT_SHIFT 16
62 #define BMI_IC_TO_EXT_SHIFT FMAN_SP_IC_TO_EXT_SHIFT
63 #define BMI_IC_FROM_INT_SHIFT FMAN_SP_IC_FROM_INT_SHIFT
65 #define BMI_INT_BUF_MARG_SHIFT 28
66 #define BMI_EXT_BUF_MARG_START_SHIFT FMAN_SP_EXT_BUF_MARG_START_SHIFT
68 #define BMI_CMD_MR_LEAC 0x00200000
69 #define BMI_CMD_MR_SLEAC 0x00100000
70 #define BMI_CMD_MR_MA 0x00080000
71 #define BMI_CMD_MR_DEAS 0x00040000
72 #define BMI_CMD_RX_MR_DEF (BMI_CMD_MR_LEAC | \
76 #define BMI_CMD_TX_MR_DEF 0
77 #define BMI_CMD_OP_MR_DEF (BMI_CMD_MR_DEAS | \
80 #define BMI_CMD_ATTR_ORDER 0x80000000
81 #define BMI_CMD_ATTR_SYNC 0x02000000
82 #define BMI_CMD_ATTR_COLOR_SHIFT 26
84 #define BMI_FIFO_PIPELINE_DEPTH_SHIFT 12
85 #define BMI_NEXT_ENG_FD_BITS_SHIFT 24
86 #define BMI_FRAME_END_CS_IGNORE_SHIFT 24
88 #define BMI_COUNTERS_EN 0x80000000
90 #define BMI_EXT_BUF_POOL_VALID FMAN_SP_EXT_BUF_POOL_VALID
91 #define BMI_EXT_BUF_POOL_EN_COUNTER FMAN_SP_EXT_BUF_POOL_EN_COUNTER
92 #define BMI_EXT_BUF_POOL_BACKUP FMAN_SP_EXT_BUF_POOL_BACKUP
93 #define BMI_EXT_BUF_POOL_ID_SHIFT 16
94 #define BMI_EXT_BUF_POOL_ID_MASK 0x003F0000
95 #define BMI_POOL_DEP_NUM_OF_POOLS_SHIFT 16
97 #define BMI_TX_FIFO_MIN_FILL_SHIFT 16
98 #define BMI_TX_FIFO_PIPELINE_DEPTH_SHIFT 12
100 #define MAX_PERFORMANCE_TASK_COMP 64
101 #define MAX_PERFORMANCE_RX_QUEUE_COMP 64
102 #define MAX_PERFORMANCE_TX_QUEUE_COMP 8
103 #define MAX_PERFORMANCE_DMA_COMP 16
104 #define MAX_PERFORMANCE_FIFO_COMP 1024
106 #define BMI_PERFORMANCE_TASK_COMP_SHIFT 24
107 #define BMI_PERFORMANCE_QUEUE_COMP_SHIFT 16
108 #define BMI_PERFORMANCE_DMA_COMP_SHIFT 12
110 #define BMI_RATE_LIMIT_GRAN_TX 16000 /* In Kbps */
111 #define BMI_RATE_LIMIT_GRAN_OP 10000 /* In frames */
112 #define BMI_RATE_LIMIT_MAX_RATE_IN_GRAN_UNITS 1024
113 #define BMI_RATE_LIMIT_MAX_BURST_SIZE 1024 /* In KBytes */
114 #define BMI_RATE_LIMIT_MAX_BURST_SHIFT 16
115 #define BMI_RATE_LIMIT_HIGH_BURST_SIZE_GRAN 0x80000000
116 #define BMI_RATE_LIMIT_SCALE_TSBS_SHIFT 16
117 #define BMI_RATE_LIMIT_SCALE_EN 0x80000000
118 #define BMI_SG_DISABLE FMAN_SP_SG_DISABLE
120 /** @Description QMI defines */
121 #define QMI_PORT_CFG_EN 0x80000000
122 #define QMI_PORT_CFG_EN_COUNTERS 0x10000000
124 #define QMI_PORT_STATUS_DEQ_TNUM_BSY 0x80000000
125 #define QMI_PORT_STATUS_DEQ_FD_BSY 0x20000000
127 #define QMI_DEQ_CFG_PRI 0x80000000
128 #define QMI_DEQ_CFG_TYPE1 0x10000000
129 #define QMI_DEQ_CFG_TYPE2 0x20000000
130 #define QMI_DEQ_CFG_TYPE3 0x30000000
131 #define QMI_DEQ_CFG_PREFETCH_PARTIAL 0x01000000
132 #define QMI_DEQ_CFG_PREFETCH_FULL 0x03000000
133 #define QMI_DEQ_CFG_SP_MASK 0xf
134 #define QMI_DEQ_CFG_SP_SHIFT 20
137 /** @Description General port defines */
138 #define FMAN_PORT_EXT_POOLS_NUM(fm_rev_maj) \
139 (((fm_rev_maj) == 4) ? 4 : 8)
140 #define FMAN_PORT_MAX_EXT_POOLS_NUM 8
141 #define FMAN_PORT_OBS_EXT_POOLS_NUM 2
142 #define FMAN_PORT_CG_MAP_NUM 8
143 #define FMAN_PORT_PRS_RESULT_WORDS_NUM 8
144 #define FMAN_PORT_BMI_FIFO_UNITS 0x100
145 #define FMAN_PORT_IC_OFFSET_UNITS 0x10
148 /** @Collection FM Port Register Map */
150 /** @Description BMI Rx port register map */
151 struct fman_port_rx_bmi_regs {
152 uint32_t fmbm_rcfg; /**< Rx Configuration */
153 uint32_t fmbm_rst; /**< Rx Status */
154 uint32_t fmbm_rda; /**< Rx DMA attributes*/
155 uint32_t fmbm_rfp; /**< Rx FIFO Parameters*/
156 uint32_t fmbm_rfed; /**< Rx Frame End Data*/
157 uint32_t fmbm_ricp; /**< Rx Internal Context Parameters*/
158 uint32_t fmbm_rim; /**< Rx Internal Buffer Margins*/
159 uint32_t fmbm_rebm; /**< Rx External Buffer Margins*/
160 uint32_t fmbm_rfne; /**< Rx Frame Next Engine*/
161 uint32_t fmbm_rfca; /**< Rx Frame Command Attributes.*/
162 uint32_t fmbm_rfpne; /**< Rx Frame Parser Next Engine*/
163 uint32_t fmbm_rpso; /**< Rx Parse Start Offset*/
164 uint32_t fmbm_rpp; /**< Rx Policer Profile */
165 uint32_t fmbm_rccb; /**< Rx Coarse Classification Base */
166 uint32_t fmbm_reth; /**< Rx Excessive Threshold */
167 uint32_t reserved003c[1]; /**< (0x03C 0x03F) */
168 uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
169 /**< Rx Parse Results Array Init*/
170 uint32_t fmbm_rfqid; /**< Rx Frame Queue ID*/
171 uint32_t fmbm_refqid; /**< Rx Error Frame Queue ID*/
172 uint32_t fmbm_rfsdm; /**< Rx Frame Status Discard Mask*/
173 uint32_t fmbm_rfsem; /**< Rx Frame Status Error Mask*/
174 uint32_t fmbm_rfene; /**< Rx Frame Enqueue Next Engine */
175 uint32_t reserved0074[0x2]; /**< (0x074-0x07C) */
176 uint32_t fmbm_rcmne; /**< Rx Frame Continuous Mode Next Engine */
177 uint32_t reserved0080[0x20];/**< (0x080 0x0FF) */
178 uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
179 /**< Buffer Manager pool Information-*/
180 uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];
181 /**< Allocate Counter-*/
182 uint32_t reserved0130[8];
183 /**< 0x130/0x140 - 0x15F reserved -*/
184 uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM];
185 /**< Congestion Group Map*/
186 uint32_t fmbm_mpd; /**< BM Pool Depletion */
187 uint32_t reserved0184[0x1F]; /**< (0x184 0x1FF) */
188 uint32_t fmbm_rstc; /**< Rx Statistics Counters*/
189 uint32_t fmbm_rfrc; /**< Rx Frame Counter*/
190 uint32_t fmbm_rfbc; /**< Rx Bad Frames Counter*/
191 uint32_t fmbm_rlfc; /**< Rx Large Frames Counter*/
192 uint32_t fmbm_rffc; /**< Rx Filter Frames Counter*/
193 uint32_t fmbm_rfdc; /**< Rx Frame Discard Counter*/
194 uint32_t fmbm_rfldec; /**< Rx Frames List DMA Error Counter*/
195 uint32_t fmbm_rodc; /**< Rx Out of Buffers Discard nntr*/
196 uint32_t fmbm_rbdc; /**< Rx Buffers Deallocate Counter*/
197 uint32_t reserved0224[0x17]; /**< (0x224 0x27F) */
198 uint32_t fmbm_rpc; /**< Rx Performance Counters*/
199 uint32_t fmbm_rpcp; /**< Rx Performance Count Parameters*/
200 uint32_t fmbm_rccn; /**< Rx Cycle Counter*/
201 uint32_t fmbm_rtuc; /**< Rx Tasks Utilization Counter*/
202 uint32_t fmbm_rrquc; /**< Rx Receive Queue Utilization cntr*/
203 uint32_t fmbm_rduc; /**< Rx DMA Utilization Counter*/
204 uint32_t fmbm_rfuc; /**< Rx FIFO Utilization Counter*/
205 uint32_t fmbm_rpac; /**< Rx Pause Activation Counter*/
206 uint32_t reserved02a0[0x18]; /**< (0x2A0 0x2FF) */
207 uint32_t fmbm_rdbg; /**< Rx Debug-*/
210 /** @Description BMI Tx port register map */
211 struct fman_port_tx_bmi_regs {
212 uint32_t fmbm_tcfg; /**< Tx Configuration */
213 uint32_t fmbm_tst; /**< Tx Status */
214 uint32_t fmbm_tda; /**< Tx DMA attributes */
215 uint32_t fmbm_tfp; /**< Tx FIFO Parameters */
216 uint32_t fmbm_tfed; /**< Tx Frame End Data */
217 uint32_t fmbm_ticp; /**< Tx Internal Context Parameters */
218 uint32_t fmbm_tfdne; /**< Tx Frame Dequeue Next Engine. */
219 uint32_t fmbm_tfca; /**< Tx Frame Command attribute. */
220 uint32_t fmbm_tcfqid; /**< Tx Confirmation Frame Queue ID. */
221 uint32_t fmbm_tefqid; /**< Tx Frame Error Queue ID */
222 uint32_t fmbm_tfene; /**< Tx Frame Enqueue Next Engine */
223 uint32_t fmbm_trlmts; /**< Tx Rate Limiter Scale */
224 uint32_t fmbm_trlmt; /**< Tx Rate Limiter */
225 uint32_t reserved0034[0x0e]; /**< (0x034-0x6c) */
226 uint32_t fmbm_tccb; /**< Tx Coarse Classification base */
227 uint32_t fmbm_tfne; /**< Tx Frame Next Engine */
228 uint32_t fmbm_tpfcm[0x02]; /**< Tx Priority based Flow Control (PFC) Mapping */
229 uint32_t fmbm_tcmne; /**< Tx Frame Continuous Mode Next Engine */
230 uint32_t reserved0080[0x60]; /**< (0x080-0x200) */
231 uint32_t fmbm_tstc; /**< Tx Statistics Counters */
232 uint32_t fmbm_tfrc; /**< Tx Frame Counter */
233 uint32_t fmbm_tfdc; /**< Tx Frames Discard Counter */
234 uint32_t fmbm_tfledc; /**< Tx Frame len error discard cntr */
235 uint32_t fmbm_tfufdc; /**< Tx Frame unsprt frmt discard cntr*/
236 uint32_t fmbm_tbdc; /**< Tx Buffers Deallocate Counter */
237 uint32_t reserved0218[0x1A]; /**< (0x218-0x280) */
238 uint32_t fmbm_tpc; /**< Tx Performance Counters*/
239 uint32_t fmbm_tpcp; /**< Tx Performance Count Parameters*/
240 uint32_t fmbm_tccn; /**< Tx Cycle Counter*/
241 uint32_t fmbm_ttuc; /**< Tx Tasks Utilization Counter*/
242 uint32_t fmbm_ttcquc; /**< Tx Transmit conf Q util Counter*/
243 uint32_t fmbm_tduc; /**< Tx DMA Utilization Counter*/
244 uint32_t fmbm_tfuc; /**< Tx FIFO Utilization Counter*/
247 /** @Description BMI O/H port register map */
248 struct fman_port_oh_bmi_regs {
249 uint32_t fmbm_ocfg; /**< O/H Configuration */
250 uint32_t fmbm_ost; /**< O/H Status */
251 uint32_t fmbm_oda; /**< O/H DMA attributes */
252 uint32_t fmbm_oicp; /**< O/H Internal Context Parameters */
253 uint32_t fmbm_ofdne; /**< O/H Frame Dequeue Next Engine */
254 uint32_t fmbm_ofne; /**< O/H Frame Next Engine */
255 uint32_t fmbm_ofca; /**< O/H Frame Command Attributes. */
256 uint32_t fmbm_ofpne; /**< O/H Frame Parser Next Engine */
257 uint32_t fmbm_opso; /**< O/H Parse Start Offset */
258 uint32_t fmbm_opp; /**< O/H Policer Profile */
259 uint32_t fmbm_occb; /**< O/H Coarse Classification base */
260 uint32_t fmbm_oim; /**< O/H Internal margins*/
261 uint32_t fmbm_ofp; /**< O/H Fifo Parameters*/
262 uint32_t fmbm_ofed; /**< O/H Frame End Data*/
263 uint32_t reserved0030[2]; /**< (0x038 - 0x03F) */
264 uint32_t fmbm_oprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
265 /**< O/H Parse Results Array Initialization */
266 uint32_t fmbm_ofqid; /**< O/H Frame Queue ID */
267 uint32_t fmbm_oefqid; /**< O/H Error Frame Queue ID */
268 uint32_t fmbm_ofsdm; /**< O/H Frame Status Discard Mask */
269 uint32_t fmbm_ofsem; /**< O/H Frame Status Error Mask */
270 uint32_t fmbm_ofene; /**< O/H Frame Enqueue Next Engine */
271 uint32_t fmbm_orlmts; /**< O/H Rate Limiter Scale */
272 uint32_t fmbm_orlmt; /**< O/H Rate Limiter */
273 uint32_t fmbm_ocmne; /**< O/H Continuous Mode Next Engine */
274 uint32_t reserved0080[0x20]; /**< 0x080 - 0x0FF Reserved */
275 uint32_t fmbm_oebmpi[2]; /**< Buf Mngr Observed Pool Info */
276 uint32_t reserved0108[0x16]; /**< 0x108 - 0x15F Reserved */
277 uint32_t fmbm_ocgm[FMAN_PORT_CG_MAP_NUM]; /**< Observed Congestion Group Map */
278 uint32_t fmbm_ompd; /**< Observed BMan Pool Depletion */
279 uint32_t reserved0184[0x1F]; /**< 0x184 - 0x1FF Reserved */
280 uint32_t fmbm_ostc; /**< O/H Statistics Counters */
281 uint32_t fmbm_ofrc; /**< O/H Frame Counter */
282 uint32_t fmbm_ofdc; /**< O/H Frames Discard Counter */
283 uint32_t fmbm_ofledc; /**< O/H Frames Len Err Discard Cntr */
284 uint32_t fmbm_ofufdc; /**< O/H Frames Unsprtd Discard Cutr */
285 uint32_t fmbm_offc; /**< O/H Filter Frames Counter */
286 uint32_t fmbm_ofwdc; /**< Rx Frames WRED Discard Counter */
287 uint32_t fmbm_ofldec; /**< O/H Frames List DMA Error Cntr */
288 uint32_t fmbm_obdc; /**< O/H Buffers Deallocate Counter */
289 uint32_t reserved0218[0x17]; /**< (0x218 - 0x27F) */
290 uint32_t fmbm_opc; /**< O/H Performance Counters */
291 uint32_t fmbm_opcp; /**< O/H Performance Count Parameters */
292 uint32_t fmbm_occn; /**< O/H Cycle Counter */
293 uint32_t fmbm_otuc; /**< O/H Tasks Utilization Counter */
294 uint32_t fmbm_oduc; /**< O/H DMA Utilization Counter */
295 uint32_t fmbm_ofuc; /**< O/H FIFO Utilization Counter */
298 /** @Description BMI port register map */
299 union fman_port_bmi_regs {
300 struct fman_port_rx_bmi_regs rx;
301 struct fman_port_tx_bmi_regs tx;
302 struct fman_port_oh_bmi_regs oh;
305 /** @Description QMI port register map */
306 struct fman_port_qmi_regs {
307 uint32_t fmqm_pnc; /**< PortID n Configuration Register */
308 uint32_t fmqm_pns; /**< PortID n Status Register */
309 uint32_t fmqm_pnts; /**< PortID n Task Status Register */
310 uint32_t reserved00c[4]; /**< 0xn00C - 0xn01B */
311 uint32_t fmqm_pnen; /**< PortID n Enqueue NIA Register */
312 uint32_t fmqm_pnetfc; /**< PortID n Enq Total Frame Counter */
313 uint32_t reserved024[2]; /**< 0xn024 - 0x02B */
314 uint32_t fmqm_pndn; /**< PortID n Dequeue NIA Register */
315 uint32_t fmqm_pndc; /**< PortID n Dequeue Config Register */
316 uint32_t fmqm_pndtfc; /**< PortID n Dequeue tot Frame cntr */
317 uint32_t fmqm_pndfdc; /**< PortID n Dequeue FQID Dflt Cntr */
318 uint32_t fmqm_pndcc; /**< PortID n Dequeue Confirm Counter */
322 enum fman_port_dma_swap {
323 E_FMAN_PORT_DMA_NO_SWAP, /**< No swap, transfer data as is */
324 E_FMAN_PORT_DMA_SWAP_LE,
325 /**< The transferred data should be swapped in PPC Little Endian mode */
326 E_FMAN_PORT_DMA_SWAP_BE
327 /**< The transferred data should be swapped in Big Endian mode */
330 /* Default port color */
331 enum fman_port_color {
332 E_FMAN_PORT_COLOR_GREEN, /**< Default port color is green */
333 E_FMAN_PORT_COLOR_YELLOW, /**< Default port color is yellow */
334 E_FMAN_PORT_COLOR_RED, /**< Default port color is red */
335 E_FMAN_PORT_COLOR_OVERRIDE /**< Ignore color */
338 /* QMI dequeue from the SP channel - types */
339 enum fman_port_deq_type {
340 E_FMAN_PORT_DEQ_BY_PRI,
341 /**< Priority precedence and Intra-Class scheduling */
342 E_FMAN_PORT_DEQ_ACTIVE_FQ,
343 /**< Active FQ precedence and Intra-Class scheduling */
344 E_FMAN_PORT_DEQ_ACTIVE_FQ_NO_ICS
345 /**< Active FQ precedence and override Intra-Class scheduling */
348 /* QMI dequeue prefetch modes */
349 enum fman_port_deq_prefetch {
350 E_FMAN_PORT_DEQ_NO_PREFETCH, /**< No prefetch mode */
351 E_FMAN_PORT_DEQ_PART_PREFETCH, /**< Partial prefetch mode */
352 E_FMAN_PORT_DEQ_FULL_PREFETCH /**< Full prefetch mode */
355 /* Parameters for defining performance counters behavior */
356 struct fman_port_perf_cnt_params {
357 uint8_t task_val; /**< Task compare value */
359 /**< Rx or Tx conf queue compare value (unused for O/H ports) */
360 uint8_t dma_val; /**< Dma compare value */
361 uint32_t fifo_val; /**< Fifo compare value (in bytes) */
364 /** @Description FM Port configuration structure, used at init */
365 struct fman_port_cfg {
366 struct fman_port_perf_cnt_params perf_cnt_params;
368 enum fman_port_dma_swap dma_swap_data;
369 bool dma_ic_stash_on;
370 bool dma_header_stash_on;
371 bool dma_sg_stash_on;
372 bool dma_write_optimize;
373 uint16_t ic_ext_offset;
374 uint8_t ic_int_offset;
376 enum fman_port_color color;
378 bool discard_override;
379 uint8_t checksum_bytes_ignore;
380 uint8_t rx_cut_end_bytes;
381 uint32_t rx_pri_elevation;
382 uint32_t rx_fifo_thr;
384 uint8_t int_buf_start_margin;
385 uint16_t ext_buf_start_margin;
386 uint16_t ext_buf_end_margin;
387 uint32_t tx_fifo_min_level;
388 uint32_t tx_fifo_low_comf_level;
389 uint8_t tx_fifo_deq_pipeline_depth;
390 bool stats_counters_enable;
391 bool perf_counters_enable;
394 enum fman_port_deq_type deq_type;
395 enum fman_port_deq_prefetch deq_prefetch_opt;
396 uint16_t deq_byte_cnt;
397 bool queue_counters_enable;
398 bool no_scatter_gather;
401 int excessive_threshold_register;
402 int fmbm_rebm_has_sgd;
403 int fmbm_tfne_has_features;
404 int qmi_deq_options_support;
407 enum fman_port_type {
408 E_FMAN_PORT_TYPE_OP = 0,
409 /**< Offline parsing port, shares id-s with
410 * host command, so must have exclusive id-s */
411 E_FMAN_PORT_TYPE_RX, /**< 1G Rx port */
412 E_FMAN_PORT_TYPE_RX_10G, /**< 10G Rx port */
413 E_FMAN_PORT_TYPE_TX, /**< 1G Tx port */
414 E_FMAN_PORT_TYPE_TX_10G, /**< 10G Tx port */
415 E_FMAN_PORT_TYPE_DUMMY,
416 E_FMAN_PORT_TYPE_HC = E_FMAN_PORT_TYPE_DUMMY
417 /**< Host command port, shares id-s with
418 * offline parsing ports, so must have exclusive id-s */
421 struct fman_port_params {
422 uint32_t discard_mask;
427 bool dont_release_buf;
430 /* Port context - used by most API functions */
432 enum fman_port_type type;
435 union fman_port_bmi_regs *bmi_regs;
436 struct fman_port_qmi_regs *qmi_regs;
438 uint8_t ext_pools_num;
441 /** @Description External buffer pools configuration */
442 struct fman_port_bpools {
443 uint8_t count; /**< Num of pools to set up */
444 bool counters_enable; /**< Enable allocate counters */
445 uint8_t grp_bp_depleted_num;
446 /**< Number of depleted pools - if reached the BMI indicates
447 * the MAC to send a pause frame */
449 uint8_t bpid; /**< BM pool ID */
451 /**< Pool's size - must be in ascending order */
453 /**< If this is a backup pool */
454 bool grp_bp_depleted;
455 /**< Consider this buffer in multiple pools depletion criteria*/
456 bool single_bp_depleted;
457 /**< Consider this buffer in single pool depletion criteria */
458 bool pfc_priorities_en;
459 } bpool[FMAN_PORT_MAX_EXT_POOLS_NUM];
462 enum fman_port_rate_limiter_scale_down {
463 E_FMAN_PORT_RATE_DOWN_NONE,
464 E_FMAN_PORT_RATE_DOWN_BY_2,
465 E_FMAN_PORT_RATE_DOWN_BY_4,
466 E_FMAN_PORT_RATE_DOWN_BY_8
469 /* Rate limiter configuration */
470 struct fman_port_rate_limiter {
471 uint8_t count_1micro_bit;
472 bool high_burst_size_gran;
473 /**< Defines burst_size granularity for OP ports; when TRUE,
474 * burst_size below counts in frames, otherwise in 10^3 frames */
476 /**< Max burst size, in KBytes for Tx port, according to
477 * high_burst_size_gran definition for OP port */
479 /**< In Kbps for Tx port, in frames/sec for OP port */
480 enum fman_port_rate_limiter_scale_down rate_factor;
483 /* BMI statistics counters */
484 enum fman_port_stats_counters {
485 E_FMAN_PORT_STATS_CNT_FRAME,
486 /**< Number of processed frames; valid for all ports */
487 E_FMAN_PORT_STATS_CNT_DISCARD,
488 /**< For Rx ports - frames discarded by QMAN, for Tx or O/H ports -
489 * frames discarded due to DMA error; valid for all ports */
490 E_FMAN_PORT_STATS_CNT_DEALLOC_BUF,
491 /**< Number of buffer deallocate operations; valid for all ports */
492 E_FMAN_PORT_STATS_CNT_RX_BAD_FRAME,
493 /**< Number of bad Rx frames, like CRC error, Rx FIFO overflow etc;
494 * valid for Rx ports only */
495 E_FMAN_PORT_STATS_CNT_RX_LARGE_FRAME,
496 /**< Number of Rx oversized frames, that is frames exceeding max frame
497 * size configured for the corresponding ETH controller;
498 * valid for Rx ports only */
499 E_FMAN_PORT_STATS_CNT_RX_OUT_OF_BUF,
500 /**< Frames discarded due to lack of external buffers; valid for
502 E_FMAN_PORT_STATS_CNT_LEN_ERR,
503 /**< Frames discarded due to frame length error; valid for Tx and
505 E_FMAN_PORT_STATS_CNT_UNSUPPORTED_FORMAT,
506 /**< Frames discarded due to unsupported FD format; valid for Tx
507 * and O/H ports only */
508 E_FMAN_PORT_STATS_CNT_FILTERED_FRAME,
509 /**< Number of frames filtered out by PCD module; valid for
510 * Rx and OP ports only */
511 E_FMAN_PORT_STATS_CNT_DMA_ERR,
512 /**< Frames rejected by QMAN that were not able to release their
513 * buffers due to DMA error; valid for Rx and O/H ports only */
514 E_FMAN_PORT_STATS_CNT_WRED_DISCARD
515 /**< Frames going through O/H port that were not able to to enter the
516 * return queue due to WRED algorithm; valid for O/H ports only */
519 /* BMI performance counters */
520 enum fman_port_perf_counters {
521 E_FMAN_PORT_PERF_CNT_CYCLE, /**< Cycle counter */
522 E_FMAN_PORT_PERF_CNT_TASK_UTIL, /**< Tasks utilization counter */
523 E_FMAN_PORT_PERF_CNT_QUEUE_UTIL,
524 /**< For Rx ports - Rx queue utilization, for Tx ports - Tx conf queue
525 * utilization; not valid for O/H ports */
526 E_FMAN_PORT_PERF_CNT_DMA_UTIL, /**< DMA utilization counter */
527 E_FMAN_PORT_PERF_CNT_FIFO_UTIL, /**< FIFO utilization counter */
528 E_FMAN_PORT_PERF_CNT_RX_PAUSE
529 /**< Number of cycles in which Rx pause activation control is on;
530 * valid for Rx ports only */
534 enum fman_port_qmi_counters {
535 E_FMAN_PORT_ENQ_TOTAL, /**< EnQ tot frame cntr */
536 E_FMAN_PORT_DEQ_TOTAL, /**< DeQ tot frame cntr; invalid for Rx ports */
537 E_FMAN_PORT_DEQ_FROM_DFLT,
538 /**< Dequeue from default FQID counter not valid for Rx ports */
539 E_FMAN_PORT_DEQ_CONFIRM /**< DeQ confirm cntr invalid for Rx ports */
543 /** @Collection FM Port API */
544 void fman_port_defconfig(struct fman_port_cfg *cfg, enum fman_port_type type);
545 int fman_port_init(struct fman_port *port,
546 struct fman_port_cfg *cfg,
547 struct fman_port_params *params);
548 int fman_port_enable(struct fman_port *port);
549 int fman_port_disable(const struct fman_port *port);
550 int fman_port_set_bpools(const struct fman_port *port,
551 const struct fman_port_bpools *bp);
552 int fman_port_set_rate_limiter(struct fman_port *port,
553 struct fman_port_rate_limiter *rate_limiter);
554 int fman_port_delete_rate_limiter(struct fman_port *port);
555 int fman_port_set_err_mask(struct fman_port *port, uint32_t err_mask);
556 int fman_port_set_discard_mask(struct fman_port *port, uint32_t discard_mask);
557 int fman_port_modify_rx_fd_bits(struct fman_port *port,
560 int fman_port_set_perf_cnt_params(struct fman_port *port,
561 struct fman_port_perf_cnt_params *params);
562 int fman_port_set_stats_cnt_mode(struct fman_port *port, bool enable);
563 int fman_port_set_perf_cnt_mode(struct fman_port *port, bool enable);
564 int fman_port_set_queue_cnt_mode(struct fman_port *port, bool enable);
565 int fman_port_set_bpool_cnt_mode(struct fman_port *port,
568 uint32_t fman_port_get_stats_counter(struct fman_port *port,
569 enum fman_port_stats_counters counter);
570 void fman_port_set_stats_counter(struct fman_port *port,
571 enum fman_port_stats_counters counter,
573 uint32_t fman_port_get_perf_counter(struct fman_port *port,
574 enum fman_port_perf_counters counter);
575 void fman_port_set_perf_counter(struct fman_port *port,
576 enum fman_port_perf_counters counter,
578 uint32_t fman_port_get_qmi_counter(struct fman_port *port,
579 enum fman_port_qmi_counters counter);
580 void fman_port_set_qmi_counter(struct fman_port *port,
581 enum fman_port_qmi_counters counter,
583 uint32_t fman_port_get_bpool_counter(struct fman_port *port, uint8_t bpid);
584 void fman_port_set_bpool_counter(struct fman_port *port,
587 int fman_port_add_congestion_grps(struct fman_port *port,
588 uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]);
589 int fman_port_remove_congestion_grps(struct fman_port *port,
590 uint32_t grps_map[FMAN_PORT_CG_MAP_NUM]);
593 #endif /* __FSL_FMAN_PORT_H */