1 /******************************************************************************
3 © 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
6 This is proprietary source code of Freescale Semiconductor Inc.,
7 and its use is subject to the NetComm Device Drivers EULA.
8 The copyright notice above does not evidence any actual or intended
9 publication of such source code.
11 ALTERNATIVELY, redistribution and use in source and binary forms, with
12 or without modification, are permitted provided that the following
14 * Redistributions of source code must retain the above copyright
15 notice, this list of conditions and the following disclaimer.
16 * Redistributions in binary form must reproduce the above copyright
17 notice, this list of conditions and the following disclaimer in the
18 documentation and/or other materials provided with the distribution.
19 * Neither the name of Freescale Semiconductor nor the
20 names of its contributors may be used to endorse or promote products
21 derived from this software without specific prior written permission.
23 THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 **************************************************************************/
37 @File part_integration_ext.h
39 @Description P3041 external definitions and structures.
40 *//***************************************************************************/
41 #ifndef __PART_INTEGRATION_EXT_H
42 #define __PART_INTEGRATION_EXT_H
45 #include "ddr_std_ext.h"
47 #include "dpaa_integration_ext.h"
50 /**************************************************************************//**
51 @Group P3041_chip_id P3041 Application Programming Interface
53 @Description P3041 Chip functions,definitions and enums.
56 *//***************************************************************************/
60 #define INTG_MAX_NUM_OF_CORES 4
63 /**************************************************************************//**
64 @Description Module types.
65 *//***************************************************************************/
66 typedef enum e_ModuleId
68 e_MODULE_ID_DUART_1 = 0,
75 e_MODULE_ID_QM, /**< Queue manager module */
76 e_MODULE_ID_BM, /**< Buffer manager module */
77 e_MODULE_ID_QM_CE_PORTAL_0,
78 e_MODULE_ID_QM_CI_PORTAL_0,
79 e_MODULE_ID_QM_CE_PORTAL_1,
80 e_MODULE_ID_QM_CI_PORTAL_1,
81 e_MODULE_ID_QM_CE_PORTAL_2,
82 e_MODULE_ID_QM_CI_PORTAL_2,
83 e_MODULE_ID_QM_CE_PORTAL_3,
84 e_MODULE_ID_QM_CI_PORTAL_3,
85 e_MODULE_ID_QM_CE_PORTAL_4,
86 e_MODULE_ID_QM_CI_PORTAL_4,
87 e_MODULE_ID_QM_CE_PORTAL_5,
88 e_MODULE_ID_QM_CI_PORTAL_5,
89 e_MODULE_ID_QM_CE_PORTAL_6,
90 e_MODULE_ID_QM_CI_PORTAL_6,
91 e_MODULE_ID_QM_CE_PORTAL_7,
92 e_MODULE_ID_QM_CI_PORTAL_7,
93 e_MODULE_ID_QM_CE_PORTAL_8,
94 e_MODULE_ID_QM_CI_PORTAL_8,
95 e_MODULE_ID_QM_CE_PORTAL_9,
96 e_MODULE_ID_QM_CI_PORTAL_9,
97 e_MODULE_ID_BM_CE_PORTAL_0,
98 e_MODULE_ID_BM_CI_PORTAL_0,
99 e_MODULE_ID_BM_CE_PORTAL_1,
100 e_MODULE_ID_BM_CI_PORTAL_1,
101 e_MODULE_ID_BM_CE_PORTAL_2,
102 e_MODULE_ID_BM_CI_PORTAL_2,
103 e_MODULE_ID_BM_CE_PORTAL_3,
104 e_MODULE_ID_BM_CI_PORTAL_3,
105 e_MODULE_ID_BM_CE_PORTAL_4,
106 e_MODULE_ID_BM_CI_PORTAL_4,
107 e_MODULE_ID_BM_CE_PORTAL_5,
108 e_MODULE_ID_BM_CI_PORTAL_5,
109 e_MODULE_ID_BM_CE_PORTAL_6,
110 e_MODULE_ID_BM_CI_PORTAL_6,
111 e_MODULE_ID_BM_CE_PORTAL_7,
112 e_MODULE_ID_BM_CI_PORTAL_7,
113 e_MODULE_ID_BM_CE_PORTAL_8,
114 e_MODULE_ID_BM_CI_PORTAL_8,
115 e_MODULE_ID_BM_CE_PORTAL_9,
116 e_MODULE_ID_BM_CI_PORTAL_9,
117 e_MODULE_ID_FM, /**< Frame manager module */
118 e_MODULE_ID_FM_RTC, /**< FM Real-Time-Clock */
119 e_MODULE_ID_FM_MURAM, /**< FM Multi-User-RAM */
120 e_MODULE_ID_FM_BMI, /**< FM BMI block */
121 e_MODULE_ID_FM_QMI, /**< FM QMI block */
122 e_MODULE_ID_FM_PARSER, /**< FM parser block */
123 e_MODULE_ID_FM_PORT_HO1, /**< FM Host-command/offline-parsing port block */
124 e_MODULE_ID_FM_PORT_HO2, /**< FM Host-command/offline-parsing port block */
125 e_MODULE_ID_FM_PORT_HO3, /**< FM Host-command/offline-parsing port block */
126 e_MODULE_ID_FM_PORT_HO4, /**< FM Host-command/offline-parsing port block */
127 e_MODULE_ID_FM_PORT_HO5, /**< FM Host-command/offline-parsing port block */
128 e_MODULE_ID_FM_PORT_HO6, /**< FM Host-command/offline-parsing port block */
129 e_MODULE_ID_FM_PORT_HO7, /**< FM Host-command/offline-parsing port block */
130 e_MODULE_ID_FM_PORT_1GRx1, /**< FM Rx 1G MAC port block */
131 e_MODULE_ID_FM_PORT_1GRx2, /**< FM Rx 1G MAC port block */
132 e_MODULE_ID_FM_PORT_1GRx3, /**< FM Rx 1G MAC port block */
133 e_MODULE_ID_FM_PORT_1GRx4, /**< FM Rx 1G MAC port block */
134 e_MODULE_ID_FM_PORT_1GRx5, /**< FM Rx 1G MAC port block */
135 e_MODULE_ID_FM_PORT_10GRx, /**< FM Rx 10G MAC port block */
136 e_MODULE_ID_FM_PORT_1GTx1, /**< FM Tx 1G MAC port block */
137 e_MODULE_ID_FM_PORT_1GTx2, /**< FM Tx 1G MAC port block */
138 e_MODULE_ID_FM_PORT_1GTx3, /**< FM Tx 1G MAC port block */
139 e_MODULE_ID_FM_PORT_1GTx4, /**< FM Tx 1G MAC port block */
140 e_MODULE_ID_FM_PORT_1GTx5, /**< FM Tx 1G MAC port block */
141 e_MODULE_ID_FM_PORT_10GTx, /**< FM Tx 10G MAC port block */
142 e_MODULE_ID_FM_PLCR, /**< FM Policer */
143 e_MODULE_ID_FM_KG, /**< FM Keygen */
144 e_MODULE_ID_FM_DMA, /**< FM DMA */
145 e_MODULE_ID_FM_FPM, /**< FM FPM */
146 e_MODULE_ID_FM_IRAM, /**< FM Instruction-RAM */
147 e_MODULE_ID_FM_1GMDIO1, /**< FM 1G MDIO MAC 1*/
148 e_MODULE_ID_FM_1GMDIO2, /**< FM 1G MDIO MAC 2*/
149 e_MODULE_ID_FM_1GMDIO3, /**< FM 1G MDIO MAC 3*/
150 e_MODULE_ID_FM_1GMDIO4, /**< FM 1G MDIO MAC 4*/
151 e_MODULE_ID_FM_1GMDIO5, /**< FM 1G MDIO MAC 5*/
152 e_MODULE_ID_FM_10GMDIO, /**< FM 10G MDIO */
153 e_MODULE_ID_FM_PRS_IRAM, /**< FM SW-parser Instruction-RAM */
154 e_MODULE_ID_FM_1GMAC1, /**< FM 1G MAC #1 */
155 e_MODULE_ID_FM_1GMAC2, /**< FM 1G MAC #2 */
156 e_MODULE_ID_FM_1GMAC3, /**< FM 1G MAC #3 */
157 e_MODULE_ID_FM_1GMAC4, /**< FM 1G MAC #4 */
158 e_MODULE_ID_FM_1GMAC5, /**< FM 1G MAC #5 */
159 e_MODULE_ID_FM_10GMAC, /**< FM 10G MAC */
161 e_MODULE_ID_SEC_GEN, /**< SEC 4.0 General registers */
162 e_MODULE_ID_SEC_QI, /**< SEC 4.0 QI registers */
163 e_MODULE_ID_SEC_JQ0, /**< SEC 4.0 JQ-0 registers */
164 e_MODULE_ID_SEC_JQ1, /**< SEC 4.0 JQ-1 registers */
165 e_MODULE_ID_SEC_JQ2, /**< SEC 4.0 JQ-2 registers */
166 e_MODULE_ID_SEC_JQ3, /**< SEC 4.0 JQ-3 registers */
167 e_MODULE_ID_SEC_RTIC, /**< SEC 4.0 RTIC registers */
168 e_MODULE_ID_SEC_DECO0_CCB0, /**< SEC 4.0 DECO-0/CCB-0 registers */
169 e_MODULE_ID_SEC_DECO1_CCB1, /**< SEC 4.0 DECO-1/CCB-1 registers */
170 e_MODULE_ID_SEC_DECO2_CCB2, /**< SEC 4.0 DECO-2/CCB-2 registers */
171 e_MODULE_ID_SEC_DECO3_CCB3, /**< SEC 4.0 DECO-3/CCB-3 registers */
172 e_MODULE_ID_SEC_DECO4_CCB4, /**< SEC 4.0 DECO-4/CCB-4 registers */
174 e_MODULE_ID_PIC, /**< PIC */
175 e_MODULE_ID_GPIO, /**< GPIO */
176 e_MODULE_ID_SERDES, /**< SERDES */
177 e_MODULE_ID_CPC, /**< CoreNet-Platform-Cache */
178 e_MODULE_ID_DUMMY_LAST
181 #define NUM_OF_MODULES e_MODULE_ID_DUMMY_LAST
183 /* Offsets relative to CCSR base */
184 #define P3041_OFFSET_LAW 0x00000c00
185 #define P3041_OFFSET_DDR 0x00008000
186 #define P3041_OFFSET_CPC 0x00010000
187 #define P3041_OFFSET_CCM 0x00018000
188 #define P3041_OFFSET_PAMU 0x00020000
189 #define P3041_OFFSET_PIC 0x00040000
190 #define P3041_OFFSET_GUTIL 0x000e0000
191 #define P3041_OFFSET_RCPM 0x000e2000
192 #define P3041_OFFSET_SERDES 0x000ea000
193 #define P3041_OFFSET_DMA1 0x00100100
194 #define P3041_OFFSET_DMA2 0x00101100
195 #define P3041_OFFSET_ESPI 0x00110000
196 #define P3041_OFFSET_ESDHC 0x00114000
197 #define P3041_OFFSET_I2C1 0x00118000
198 #define P3041_OFFSET_I2C2 0x00118100
199 #define P3041_OFFSET_I2C3 0x00119000
200 #define P3041_OFFSET_I2C4 0x00119100
201 #define P3041_OFFSET_DUART1 0x0011c500
202 #define P3041_OFFSET_DUART2 0x0011c600
203 #define P3041_OFFSET_DUART3 0x0011d500
204 #define P3041_OFFSET_DUART4 0x0011d600
205 #define P3041_OFFSET_LBC 0x00124000
206 #define P3041_OFFSET_GPIO 0x00130000
207 #define P3041_OFFSET_PCIE1 0x00200000
208 #define P3041_OFFSET_PCIE2 0x00201000
209 #define P3041_OFFSET_PCIE3 0x00202000
210 #define P3041_OFFSET_PCIE4 0x00203000
211 #define P3041_OFFSET_USB1 0x00210000
212 #define P3041_OFFSET_USB2 0x00211000
213 #define P3041_OFFSET_USB_PHY 0x00214000
214 #define P3041_OFFSET_SATA1 0x00220000
215 #define P3041_OFFSET_SATA2 0x00221000
216 #define P3041_OFFSET_SEC_GEN 0x00300000
217 #define P3041_OFFSET_SEC_JQ0 0x00301000
218 #define P3041_OFFSET_SEC_JQ1 0x00302000
219 #define P3041_OFFSET_SEC_JQ2 0x00303000
220 #define P3041_OFFSET_SEC_JQ3 0x00304000
221 #define P3041_OFFSET_SEC_RESERVED 0x00305000
222 #define P3041_OFFSET_SEC_RTIC 0x00306000
223 #define P3041_OFFSET_SEC_QI 0x00307000
224 #define P3041_OFFSET_SEC_DECO0_CCB0 0x00308000
225 #define P3041_OFFSET_SEC_DECO1_CCB1 0x00309000
226 #define P3041_OFFSET_PME 0x00316000
227 #define P3041_OFFSET_QM 0x00318000
228 #define P3041_OFFSET_BM 0x0031a000
229 #define P3041_OFFSET_FM 0x00400000
231 #define P3041_OFFSET_FM_MURAM P3041_OFFSET_FM
232 #define P3041_OFFSET_FM_BMI (P3041_OFFSET_FM + 0x00080000)
233 #define P3041_OFFSET_FM_QMI (P3041_OFFSET_FM + 0x00080400)
234 #define P3041_OFFSET_FM_PARSER (P3041_OFFSET_FM + 0x00080800)
235 #define P3041_OFFSET_FM_PORT_HO1 (P3041_OFFSET_FM + 0x00081000) /* host command/offline parser */
236 #define P3041_OFFSET_FM_PORT_HO2 (P3041_OFFSET_FM + 0x00082000)
237 #define P3041_OFFSET_FM_PORT_HO3 (P3041_OFFSET_FM + 0x00083000)
238 #define P3041_OFFSET_FM_PORT_HO4 (P3041_OFFSET_FM + 0x00084000)
239 #define P3041_OFFSET_FM_PORT_HO5 (P3041_OFFSET_FM + 0x00085000)
240 #define P3041_OFFSET_FM_PORT_HO6 (P3041_OFFSET_FM + 0x00086000)
241 #define P3041_OFFSET_FM_PORT_HO7 (P3041_OFFSET_FM + 0x00087000)
242 #define P3041_OFFSET_FM_PORT_1GRX1 (P3041_OFFSET_FM + 0x00088000)
243 #define P3041_OFFSET_FM_PORT_1GRX2 (P3041_OFFSET_FM + 0x00089000)
244 #define P3041_OFFSET_FM_PORT_1GRX3 (P3041_OFFSET_FM + 0x0008a000)
245 #define P3041_OFFSET_FM_PORT_1GRX4 (P3041_OFFSET_FM + 0x0008b000)
246 #define P3041_OFFSET_FM_PORT_1GRX5 (P3041_OFFSET_FM + 0x0008c000)
247 #define P3041_OFFSET_FM_PORT_10GRX (P3041_OFFSET_FM + 0x00090000)
248 #define P3041_OFFSET_FM_PORT_1GTX1 (P3041_OFFSET_FM + 0x000a8000)
249 #define P3041_OFFSET_FM_PORT_1GTX2 (P3041_OFFSET_FM + 0x000a9000)
250 #define P3041_OFFSET_FM_PORT_1GTX3 (P3041_OFFSET_FM + 0x000aa000)
251 #define P3041_OFFSET_FM_PORT_1GTX4 (P3041_OFFSET_FM + 0x000ab000)
252 #define P3041_OFFSET_FM_PORT_1GTX5 (P3041_OFFSET_FM + 0x000ac000)
253 #define P3041_OFFSET_FM_PORT_10GTX (P3041_OFFSET_FM + 0x000b0000)
254 #define P3041_OFFSET_FM_PLCR (P3041_OFFSET_FM + 0x000c0000)
255 #define P3041_OFFSET_FM_KG (P3041_OFFSET_FM + 0x000c1000)
256 #define P3041_OFFSET_FM_DMA (P3041_OFFSET_FM + 0x000c2000)
257 #define P3041_OFFSET_FM_FPM (P3041_OFFSET_FM + 0x000c3000)
258 #define P3041_OFFSET_FM_IRAM (P3041_OFFSET_FM + 0x000c4000)
259 #define P3041_OFFSET_FM_PARSER_IRAM (P3041_OFFSET_FM + 0x000c7000)
260 #define P3041_OFFSET_FM_1GMAC1 (P3041_OFFSET_FM + 0x000e0000)
261 #define P3041_OFFSET_FM_1GMDIO (P3041_OFFSET_FM + 0x000e1000 + 0x120)
262 #define P3041_OFFSET_FM_1GMAC2 (P3041_OFFSET_FM + 0x000e2000)
263 #define P3041_OFFSET_FM_1GMAC3 (P3041_OFFSET_FM + 0x000e4000)
264 #define P3041_OFFSET_FM_1GMAC4 (P3041_OFFSET_FM + 0x000e6000)
265 #define P3041_OFFSET_FM_1GMAC5 (P3041_OFFSET_FM + 0x000e8000)
266 #define P3041_OFFSET_FM_10GMAC (P3041_OFFSET_FM + 0x000f0000)
267 #define P3041_OFFSET_FM_10GMDIO (P3041_OFFSET_FM + 0x000f1000 + 0x030)
268 #define P3041_OFFSET_FM_RTC (P3041_OFFSET_FM + 0x000fe000)
270 /* Offsets relative to QM or BM portals base */
271 #define P3041_OFFSET_PORTALS_CE_AREA 0x000000 /* cache enabled area */
272 #define P3041_OFFSET_PORTALS_CI_AREA 0x100000 /* cache inhibited area */
274 #define P3041_CE_PORTAL_SIZE 0x4000
275 #define P3041_CI_PORTAL_SIZE 0x1000
277 #define P3041_OFFSET_PORTALS_CE(portal) \
278 (P3041_OFFSET_PORTALS_CE_AREA + P3041_CE_PORTAL_SIZE * (portal))
279 #define P3041_OFFSET_PORTALS_CI(portal) \
280 (P3041_OFFSET_PORTALS_CI_AREA + P3041_CI_PORTAL_SIZE * (portal))
283 /**************************************************************************//**
284 @Description Transaction source ID (for memory controllers error reporting).
285 *//***************************************************************************/
286 typedef enum e_TransSrc
288 e_TRANS_SRC_PCIE_1 = 0x0, /**< PCI Express 1 */
289 e_TRANS_SRC_PCIE_2 = 0x1, /**< PCI Express 2 */
290 e_TRANS_SRC_PCIE_3 = 0x2, /**< PCI Express 3 */
291 e_TRANS_SRC_PCIE_4 = 0x3, /**< PCI Express 4 */
292 e_TRANS_SRC_SRIO_1 = 0x8, /**< SRIO 1 */
293 e_TRANS_SRC_SRIO_2 = 0x9, /**< SRIO 2 */
294 e_TRANS_SRC_BMAN = 0x18, /**< BMan */
295 e_TRANS_SRC_PAMU = 0x1C, /**< PAMU */
296 e_TRANS_SRC_PME = 0x20, /**< PME */
297 e_TRANS_SRC_SEC = 0x21, /**< Security engine */
298 e_TRANS_SRC_QMAN = 0x3C, /**< QMan */
299 e_TRANS_SRC_USB_1 = 0x40, /**< USB 1 */
300 e_TRANS_SRC_USB_2 = 0x41, /**< USB 2 */
301 e_TRANS_SRC_ESDHC = 0x44, /**< eSDHC */
302 e_TRANS_SRC_PBL = 0x48, /**< Pre-boot loader */
303 e_TRANS_SRC_NPC = 0x4B, /**< Nexus port controller */
304 e_TRANS_SRC_RMAN = 0x5D, /**< RIO message manager */
305 e_TRANS_SRC_SATA_1 = 0x60, /**< SATA 1 */
306 e_TRANS_SRC_SATA_2 = 0x61, /**< SATA 2 */
307 e_TRANS_SRC_DMA_1 = 0x70, /**< DMA 1 */
308 e_TRANS_SRC_DMA_2 = 0x71, /**< DMA 2 */
309 e_TRANS_SRC_CORE_0_INST = 0x80, /**< Processor 0 (instruction) */
310 e_TRANS_SRC_CORE_0_DATA = 0x81, /**< Processor 0 (data) */
311 e_TRANS_SRC_CORE_1_INST = 0x82, /**< Processor 1 (instruction) */
312 e_TRANS_SRC_CORE_1_DATA = 0x83, /**< Processor 1 (data) */
313 e_TRANS_SRC_CORE_2_INST = 0x84, /**< Processor 2 (instruction) */
314 e_TRANS_SRC_CORE_2_DATA = 0x85, /**< Processor 2 (data) */
315 e_TRANS_SRC_CORE_3_INST = 0x86, /**< Processor 3 (instruction) */
316 e_TRANS_SRC_CORE_3_DATA = 0x87, /**< Processor 3 (data) */
317 e_TRANS_SRC_FM_10G = 0xC0, /**< FM XAUI */
318 e_TRANS_SRC_FM_HO_1 = 0xC1, /**< FM offline, host 1 */
319 e_TRANS_SRC_FM_HO_2 = 0xC2, /**< FM offline, host 2 */
320 e_TRANS_SRC_FM_HO_3 = 0xC3, /**< FM offline, host 3 */
321 e_TRANS_SRC_FM_HO_4 = 0xC4, /**< FM offline, host 4 */
322 e_TRANS_SRC_FM_HO_5 = 0xC5, /**< FM offline, host 5 */
323 e_TRANS_SRC_FM_HO_6 = 0xC6, /**< FM offline, host 6 */
324 e_TRANS_SRC_FM_HO_7 = 0xC7, /**< FM offline, host 7 */
325 e_TRANS_SRC_FM_GETH_1 = 0xC8, /**< FM GETH 1 */
326 e_TRANS_SRC_FM_GETH_2 = 0xC9, /**< FM GETH 2 */
327 e_TRANS_SRC_FM_GETH_3 = 0xCA, /**< FM GETH 3 */
328 e_TRANS_SRC_FM_GETH_4 = 0xCB, /**< FM GETH 4 */
329 e_TRANS_SRC_FM_GETH_5 = 0xCC /**< FM GETH 5 */
332 /**************************************************************************//**
333 @Description Local Access Window Target interface ID
334 *//***************************************************************************/
335 typedef enum e_P3041LawTargetId
337 e_P3041_LAW_TARGET_PCIE_1 = 0x0, /**< PCI Express 1 */
338 e_P3041_LAW_TARGET_PCIE_2 = 0x1, /**< PCI Express 2 */
339 e_P3041_LAW_TARGET_PCIE_3 = 0x2, /**< PCI Express 3 */
340 e_P3041_LAW_TARGET_PCIE_4 = 0x3, /**< PCI Express 4 */
341 e_P3041_LAW_TARGET_SRIO_1 = 0x8, /**< SRIO 1 */
342 e_P3041_LAW_TARGET_SRIO_2 = 0x9, /**< SRIO 2 */
343 e_P3041_LAW_TARGET_DDR_CPC = 0x10, /**< DDR controller or CPC SRAM */
344 e_P3041_LAW_TARGET_BMAN = 0x18, /**< BMAN target interface ID */
345 e_P3041_LAW_TARGET_DCSR = 0x1D, /**< DCSR */
346 e_P3041_LAW_TARGET_LBC = 0x1F, /**< Local Bus target interface ID */
347 e_P3041_LAW_TARGET_QMAN = 0x3C, /**< QMAN target interface ID */
348 e_P3041_LAW_TARGET_NONE = 0xFF /**< None */
349 } e_P3041LawTargetId;
351 /***************************************************************
352 P3041 general routines
353 ****************************************************************/
354 /**************************************************************************//**
355 @Group P3041_init_grp P3041 Initialization Unit
357 @Description P3041 initialization unit API functions, definitions and enums
360 *//***************************************************************************/
362 /**************************************************************************//**
363 @Description Part ID and revision number
364 *//***************************************************************************/
365 typedef enum e_P3041DeviceName
367 e_P3041_REV_INVALID = 0x00000000, /**< Invalid revision */
368 e_P3041_REV_1_0 = (int)0x82190310, /**< P3041 with security, revision 1.0 */
369 e_P3041_REV_1_0_NO_SEC = (int)0x82110310 /**< P3041 without security, revision 1.0 */
372 /**************************************************************************//**
373 @Description Device Disable Register
374 *//***************************************************************************/
375 typedef enum e_P3041DeviceDisable
377 e_P3041_DEV_DISABLE_PCIE_1 = 0, /**< PCI Express controller 1 disable */
378 e_P3041_DEV_DISABLE_PCIE_2, /**< PCI Express controller 2 disable */
379 e_P3041_DEV_DISABLE_PCIE_3, /**< PCI Express controller 3 disable */
380 e_P3041_DEV_DISABLE_PCIE_4, /**< PCI Express controller 4 disable */
381 e_P3041_DEV_DISABLE_RMAN, /**< RapidIO message manager disable */
382 e_P3041_DEV_DISABLE_SRIO_1, /**< Serial RapidIO controller 1 disable */
383 e_P3041_DEV_DISABLE_SRIO_2, /**< Serial RapidIO controller 2 disable */
384 e_P3041_DEV_DISABLE_DMA_1 = 9, /**< DMA controller 1 disable */
385 e_P3041_DEV_DISABLE_DMA_2, /**< DMA controller 2 disable */
386 e_P3041_DEV_DISABLE_DDR, /**< DDR controller disable */
387 e_P3041_DEV_DISABLE_SATA_1 = 17, /**< SATA controller 1 disable */
388 e_P3041_DEV_DISABLE_SATA_2, /**< SATA controller 2 disable */
389 e_P3041_DEV_DISABLE_LBC, /**< eLBC controller disable */
390 e_P3041_DEV_DISABLE_USB_1, /**< USB controller 1 disable */
391 e_P3041_DEV_DISABLE_USB_2, /**< USB controller 2 disable */
392 e_P3041_DEV_DISABLE_ESDHC = 23, /**< eSDHC controller disable */
393 e_P3041_DEV_DISABLE_GPIO, /**< GPIO controller disable */
394 e_P3041_DEV_DISABLE_ESPI, /**< eSPI controller disable */
395 e_P3041_DEV_DISABLE_I2C_1, /**< I2C module 1 (controllers 1 and 2) disable */
396 e_P3041_DEV_DISABLE_I2C_2, /**< I2C module 2 (controllers 3 and 4) disable */
397 e_P3041_DEV_DISABLE_DUART_1 = 30, /**< DUART controller 1 disable */
398 e_P3041_DEV_DISABLE_DUART_2, /**< DUART controller 2 disable */
399 e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST = 32,
400 /**< Dummy entry signing end of DEVDISR1 register controllers */
401 e_P3041_DEV_DISABLE_PME = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST,
402 /**< Pattern match engine disable */
403 e_P3041_DEV_DISABLE_SEC, /**< Security disable */
404 e_P3041_DEV_DISABLE_QM_BM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 4,
405 /**< Queue manager/buffer manager disable */
406 e_P3041_DEV_DISABLE_FM = e_P3041_DEV_DISABLE_DISR1_DUMMY_LAST + 6,
407 /**< Frame manager disable */
408 e_P3041_DEV_DISABLE_10G, /**< 10G Ethernet controller disable */
409 e_P3041_DEV_DISABLE_DTSEC_1, /**< dTSEC controller 1 disable */
410 e_P3041_DEV_DISABLE_DTSEC_2, /**< dTSEC controller 2 disable */
411 e_P3041_DEV_DISABLE_DTSEC_3, /**< dTSEC controller 3 disable */
412 e_P3041_DEV_DISABLE_DTSEC_4, /**< dTSEC controller 4 disable */
413 e_P3041_DEV_DISABLE_DTSEC_5 /**< dTSEC controller 5 disable */
414 } e_P3041DeviceDisable;
417 /**************************************************************************//*
418 @Description structure representing P3041 devices configuration
419 *//***************************************************************************/
420 typedef struct t_P3041Devices
428 uint16_t serdesLane; /**< Most significant bits represent lanes used by this bank,
429 one bit for lane, lane A is the first and so on, e.g.,
430 set 0xF000 for ABCD lanes */
431 e_EnetInterface ethIf;
435 } dtsecs[FM_MAX_NUM_OF_1G_MACS];
445 /**************************************************************************//**
446 @Function P3041_GetRevInfo
448 @Description Obtain revision information.
450 @Param[in] gutilBase - Gutil memory map virtual base address.
452 @Return Part ID and revision.
453 *//***************************************************************************/
454 e_P3041DeviceName P3041_GetRevInfo(uintptr_t gutilBase);
456 /**************************************************************************//**
457 @Function P3041_GetE500Factor
459 @Description Obtain core's multiplication factors.
461 @Param[in] gutilBase - Gutil memory map virtual base address.
462 @Param[in] coreIndex - Core index.
463 @Param[out] p_E500MulFactor - E500 to CCB multification factor.
464 @Param[out] p_E500DivFactor - E500 to CCB division factor.
466 *//***************************************************************************/
467 void P3041_GetE500Factor(uintptr_t gutilBase,
469 uint32_t *p_E500MulFactor,
470 uint32_t *p_E500DivFactor);
472 /**************************************************************************//**
473 @Function P3041_GetCcbFactor
475 @Description Obtain system multiplication factor.
477 @Param[in] gutilBase - Gutil memory map virtual base address.
479 @Return System multiplication factor.
480 *//***************************************************************************/
481 uint32_t P3041_GetCcbFactor(uintptr_t gutilBase);
483 /**************************************************************************//**
484 @Function P3041_GetDdrFactor
486 @Description Obtain DDR clock multiplication factor.
488 @Param[in] gutilBase - Gutil memory map virtual base address.
490 @Return DDR clock multiplication factor.
491 *//***************************************************************************/
492 uint32_t P3041_GetDdrFactor(uintptr_t gutilBase);
494 /**************************************************************************//**
495 @Function P3041_GetDdrType
497 @Description Obtain DDR memory type.
499 @Param[in] gutilBase - Gutil memory map virtual base address.
502 *//***************************************************************************/
503 e_DdrType P3041_GetDdrType(uintptr_t gutilBase);
505 /**************************************************************************//**
506 @Function P3041_GetFmFactor
508 @Description returns FM multiplication factors. (This value is returned using
509 two parameters to avoid using float parameter).
511 @Param[in] gutilBase - Gutil memory map virtual base address.
512 @Param[out] p_FmMulFactor - FM to CCB multification factor.
513 @Param[out] p_FmDivFactor - FM to CCB division factor.
515 *//***************************************************************************/
516 void P3041_GetFmFactor(uintptr_t gutilBase,
517 uint32_t *p_FmMulFactor,
518 uint32_t *p_FmDivFactor);
521 void P3041_CoreTimeBaseEnable(uintptr_t rcpmBase);
522 void P3041_CoreTimeBaseDisable(uintptr_t rcpmBase);
524 typedef enum e_SerdesProtocol
526 SRDS_PROTOCOL_NONE = 0,
533 SRDS_PROTOCOL_SGMII_FM,
534 SRDS_PROTOCOL_XAUI_FM,
540 t_Error P3041_DeviceDisable(uintptr_t gutilBase, e_P3041DeviceDisable device, bool disable);
541 void P3041_GetDevicesConfiguration(uintptr_t gutilBase, t_P3041Devices *p_Devices);
542 t_Error P3041_PamuDisableBypass(uintptr_t gutilBase, uint8_t pamuId, bool disable);
543 uint32_t P3041_SerdesRcwGetProtocol(uintptr_t gutilBase);
544 bool P3041_SerdesRcwIsDeviceConfigured(uintptr_t gutilBase, e_SerdesProtocol device);
545 bool P3041_SerdesRcwIsLaneEnabled(uintptr_t gutilBase, uint32_t lane);
547 /** @} */ /* end of P3041_init_grp group */
548 /** @} */ /* end of P3041_grp group */
551 /*****************************************************************************
552 INTEGRATION-SPECIFIC MODULE CODES
553 ******************************************************************************/
554 #define MODULE_UNKNOWN 0x00000000
555 #define MODULE_MEM 0x00010000
556 #define MODULE_MM 0x00020000
557 #define MODULE_CORE 0x00030000
558 #define MODULE_P3041 0x00040000
559 #define MODULE_P3041_PLATFORM 0x00050000
560 #define MODULE_PM 0x00060000
561 #define MODULE_MMU 0x00070000
562 #define MODULE_PIC 0x00080000
563 #define MODULE_CPC 0x00090000
564 #define MODULE_DUART 0x000a0000
565 #define MODULE_SERDES 0x000b0000
566 #define MODULE_PIO 0x000c0000
567 #define MODULE_QM 0x000d0000
568 #define MODULE_BM 0x000e0000
569 #define MODULE_SEC 0x000f0000
570 #define MODULE_LAW 0x00100000
571 #define MODULE_LBC 0x00110000
572 #define MODULE_PAMU 0x00120000
573 #define MODULE_FM 0x00130000
574 #define MODULE_FM_MURAM 0x00140000
575 #define MODULE_FM_PCD 0x00150000
576 #define MODULE_FM_RTC 0x00160000
577 #define MODULE_FM_MAC 0x00170000
578 #define MODULE_FM_PORT 0x00180000
579 #define MODULE_DPA 0x00190000
580 #define MODULE_MII 0x001a0000
581 #define MODULE_I2C 0x001b0000
582 #define MODULE_DMA 0x001c0000
583 #define MODULE_DDR 0x001d0000
584 #define MODULE_ESPI 0x001e0000
586 /*****************************************************************************
587 PAMU INTEGRATION-SPECIFIC DEFINITIONS
588 ******************************************************************************/
589 #define PAMU_NUM_OF_PARTITIONS 4
592 /*****************************************************************************
593 LAW INTEGRATION-SPECIFIC DEFINITIONS
594 ******************************************************************************/
595 #define LAW_NUM_OF_WINDOWS 32
596 #define LAW_MIN_WINDOW_SIZE 0x0000000000001000LL /**< 4KB */
597 #define LAW_MAX_WINDOW_SIZE 0x0000002000000000LL /**< 64GB */
600 /*****************************************************************************
601 LBC INTEGRATION-SPECIFIC DEFINITIONS
602 ******************************************************************************/
603 /**************************************************************************//**
604 @Group lbc_exception_grp LBC Exception Unit
606 @Description LBC Exception unit API functions, definitions and enums
609 *//***************************************************************************/
611 /**************************************************************************//**
614 @Collection LBC Errors Bit Mask
616 These errors are reported through the exceptions callback..
617 The values can be or'ed in any combination in the errors mask
618 parameter of the errors report structure.
620 These errors can also be passed as a bit-mask to
621 LBC_EnableErrorChecking() or LBC_DisableErrorChecking(),
622 for enabling or disabling error checking.
624 *//***************************************************************************/
625 #define LBC_ERR_BUS_MONITOR 0x80000000 /**< Bus monitor error */
626 #define LBC_ERR_PARITY_ECC 0x20000000 /**< Parity error for GPCM/UPM */
627 #define LBC_ERR_WRITE_PROTECT 0x04000000 /**< Write protection error */
628 #define LBC_ERR_CHIP_SELECT 0x00080000 /**< Unrecognized chip select */
630 #define LBC_ERR_ALL (LBC_ERR_BUS_MONITOR | LBC_ERR_PARITY_ECC | \
631 LBC_ERR_WRITE_PROTECT | LBC_ERR_CHIP_SELECT)
632 /**< All possible errors */
634 /** @} */ /* end of lbc_exception_grp group */
636 #define LBC_INCORRECT_ERROR_REPORT_ERRATA
638 #define LBC_NUM_OF_BANKS 8
639 #define LBC_MAX_CS_SIZE 0x0000000100000000LL /* Up to 4G memory block size */
640 #define LBC_PARITY_SUPPORT
641 #define LBC_HIGH_CLK_DIVIDERS
642 #define LBC_FCM_AVAILABLE
644 /*****************************************************************************
645 GPIO INTEGRATION-SPECIFIC DEFINITIONS
646 ******************************************************************************/
647 #define GPIO_NUM_OF_PORTS 1 /**< Number of ports in GPIO module;
648 Each port contains up to 32 I/O pins. */
650 #define GPIO_VALID_PIN_MASKS \
651 { /* Port A */ 0xFFFFFFFF }
653 #define GPIO_VALID_INTR_MASKS \
654 { /* Port A */ 0xFFFFFFFF }
657 /*****************************************************************************
658 SERDES INTEGRATION-SPECIFIC DEFINITIONS
659 ******************************************************************************/
660 #define SRDS_MAX_LANES 18
661 #define SRDS_MAX_BANK 3
663 /* Serdes lanes general information provided in the following form:
664 1) Lane index in Serdes Control Registers Map
665 2) Lane enable/disable bit number in RCW
666 3) Lane bank index */
689 #define SRDS_PROTOCOL_ALL_OPTIONS
690 /* Serdes lanes assignment and multiplexing.
691 Each option is selected by SRDS_PRTCL bits of RCW. */
692 #define SRDS_PROTOCOL_OPTIONS \
693 /* Protocol Lane assignment */ \
695 /* 0x00 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
696 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
697 SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
698 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
699 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
700 /* 0x01 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
701 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
702 SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
703 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
704 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
705 /* 0x02 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
706 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
707 SRDS_PROTOCOL_PCIE4, SRDS_PROTOCOL_AURORA, \
708 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
709 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
710 /* 0x03 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
711 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
712 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
713 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
714 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
715 /* 0x04 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
716 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
717 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
718 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
719 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
720 /* 0x05 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
721 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
722 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
723 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
724 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
725 /* 0x06 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
726 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
727 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
728 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
729 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
730 /* 0x07 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
731 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
732 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
733 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
734 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
735 /* 0x08 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
736 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
737 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
738 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
739 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
740 /* 0x09 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
741 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
742 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
743 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
744 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
745 /* 0x0A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
746 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
747 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
748 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
749 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
750 /* 0x0B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
751 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
752 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_AURORA, \
753 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
754 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
755 /* 0x0C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
756 SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
757 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
758 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
759 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
760 /* 0x0D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
761 SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
762 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
763 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
764 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
765 /* 0x0E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
766 SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
767 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
768 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
769 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
770 /* 0x0F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
771 SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
772 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
773 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
774 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
775 /* 0x10 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
776 SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
777 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
778 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
779 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
780 /* 0x11 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
781 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
782 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
783 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
784 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
785 /* 0x12 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
786 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
787 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
788 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
789 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
790 /* 0x13 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
791 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
792 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
793 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
794 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
795 /* 0x14 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
796 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
797 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
798 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
799 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
800 /* 0x15 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
801 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
802 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
803 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
804 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
805 /* 0x16 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
806 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
807 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
808 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
809 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1}, \
810 /* 0x17 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
811 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
812 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
813 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
814 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
815 /* 0x18 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
816 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
817 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
818 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
819 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
820 /* 0x19 */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
821 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
822 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
823 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
824 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
825 /* 0x1A */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
826 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
827 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
828 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
829 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
830 /* 0x1B */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
831 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
832 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
833 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
834 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
835 /* 0x1C */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
836 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
837 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
838 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
839 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
840 /* 0x1D */ {SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, \
841 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
842 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
843 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
844 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
845 /* 0x1E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
846 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
847 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
848 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
849 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
850 /* 0x1F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
851 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
852 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
853 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
854 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
855 /* 0x20 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
856 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
857 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
858 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
859 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
860 /* 0x21 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
861 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
862 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
863 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
864 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
865 /* 0x22 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
866 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
867 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
868 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
869 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
870 /* 0x23 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
871 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
872 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
873 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
874 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
875 /* 0x24 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
876 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
877 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
878 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
879 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
880 /* 0x25 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
881 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
882 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
883 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
884 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
885 /* 0x26 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
886 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
887 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
888 SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
889 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM}, \
890 /* 0x27 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
891 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
892 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
893 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
894 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
895 /* 0x28 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
896 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
897 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
898 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
899 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
900 /* 0x29 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
901 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
902 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
903 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
904 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
905 /* 0x2A */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
906 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
907 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
908 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
909 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
910 /* 0x2B */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
911 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, \
912 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
913 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
914 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
915 /* 0x2C */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
916 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
917 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
918 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
919 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
920 /* 0x2D */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
921 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
922 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
923 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
924 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
925 /* 0x2E */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
926 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
927 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
928 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
929 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
930 /* 0x2F */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
931 SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO2, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
932 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
933 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
934 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
935 /* 0x30 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
936 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
937 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
938 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
939 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
940 /* 0x31 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
941 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
942 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
943 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
944 SRDS_PROTOCOL_SGMII_FM, 0, 0, 0}, \
945 /* 0x32 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
946 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
947 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
948 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
949 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM}, \
950 /* 0x33 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
951 SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, SRDS_PROTOCOL_SRIO1, \
952 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
953 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
954 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
955 /* 0x34 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
956 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
957 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
958 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
959 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
960 /* 0x35 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, \
961 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
962 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
963 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
964 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
965 /* 0x36 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
966 SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
967 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
968 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
969 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2}, \
970 /* 0x37 */ {SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE1, SRDS_PROTOCOL_PCIE3, SRDS_PROTOCOL_PCIE3, \
971 SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_PCIE2, SRDS_PROTOCOL_SGMII_FM, SRDS_PROTOCOL_SGMII_FM, \
972 SRDS_PROTOCOL_AURORA, SRDS_PROTOCOL_AURORA, \
973 SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, SRDS_PROTOCOL_XAUI_FM, \
974 0, 0, SRDS_PROTOCOL_SATA1, SRDS_PROTOCOL_SATA2} \
977 /*****************************************************************************
978 DDR INTEGRATION-SPECIFIC DEFINITIONS
979 ******************************************************************************/
980 #define DDR_NUM_OF_VALID_CS 4
982 /*****************************************************************************
983 DMA INTEGRATION-SPECIFIC DEFINITIONS
984 ******************************************************************************/
985 #define DMA_NUM_OF_CONTROLLERS 2
987 /*****************************************************************************
988 CPC INTEGRATION-SPECIFIC DEFINITIONS
989 ******************************************************************************/
991 #define CPC_MAX_SIZE_SRAM_ERRATA_CPC4
992 #define CPC_HARDWARE_FLUSH_ERRATA_CPC10
995 #endif /* __PART_INTEGRATION_EXT_H */