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43 * Functions for accessing memory and CSRs on Octeon when we are compiling
46 * <hr>$Revision: 38306 $<hr>
48 #ifndef __CVMX_ACCESS_NATIVE_H__
49 #define __CVMX_ACCESS_NATIVE_H__
56 * Returns the Octeon processor ID.
58 * @return Octeon processor ID from COP0
60 static inline uint32_t cvmx_get_proc_id(void)
62 #ifdef CVMX_BUILD_FOR_LINUX_USER
63 extern uint32_t cvmx_app_init_processor_id;
64 return cvmx_app_init_processor_id;
67 asm ("mfc0 %0, $15,0" : "=r" (id));
73 * Convert a memory pointer (void*) into a hardware compatable
74 * memory address (uint64_t). Octeon hardware widgets don't
75 * understand logical addresses.
77 * @param ptr C style memory pointer
78 * @return Hardware physical address
80 static inline uint64_t cvmx_ptr_to_phys(void *ptr)
82 if (CVMX_ENABLE_PARAMETER_CHECKING)
83 cvmx_warn_if(ptr==NULL, "cvmx_ptr_to_phys() passed a NULL pointer\n");
85 #ifdef CVMX_BUILD_FOR_UBOOT
86 uint64_t uboot_tlb_ptr_to_phys(void *ptr);
88 if (((uint32_t)ptr) < 0x80000000)
90 /* Handle useg (unmapped due to ERL) here*/
91 return(CAST64(ptr) & 0x7FFFFFFF);
93 else if (((uint32_t)ptr) < 0xC0000000)
95 /* Here we handle KSEG0/KSEG1 _pointers_. We know we are dealing
96 ** with 32 bit only values, so we treat them that way. Note that
97 ** a cvmx_phys_to_ptr(cvmx_ptr_to_phys(X)) will not return X in this case,
98 ** but the physical address of the KSEG0/KSEG1 address. */
99 return(CAST64(ptr) & 0x1FFFFFFF);
102 return(uboot_tlb_ptr_to_phys(ptr)); /* Should not get get here in !TLB case */
107 if (sizeof(void*) == 8)
109 /* We're running in 64 bit mode. Normally this means that we can use
110 40 bits of address space (the hardware limit). Unfortunately there
111 is one case were we need to limit this to 30 bits, sign extended
112 32 bit. Although these are 64 bits wide, only 30 bits can be used */
113 if ((CAST64(ptr) >> 62) == 3)
114 return CAST64(ptr) & cvmx_build_mask(30);
116 return CAST64(ptr) & cvmx_build_mask(40);
121 return (long)(ptr) & 0x1fffffff;
123 extern uint64_t linux_mem32_offset;
124 if (cvmx_likely(ptr))
125 return CAST64(ptr) - linux_mem32_offset;
130 #elif defined(_WRS_KERNEL)
131 return (long)(ptr) & 0x7fffffff;
132 #elif defined(VXWORKS_USER_MAPPINGS)
133 /* This mapping mode is used in vxWorks 5.5 to support 2GB of ram. The
134 2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
135 uint64_t address = (long)ptr;
136 if (address & 0x80000000)
137 return address & 0x1fffffff; /* KSEG pointers directly map the lower 256MB and bootbus */
138 else if ((address >= 0x10000000) && (address < 0x20000000))
139 return address + 0x400000000ull; /* 256MB-512MB is a virtual mapping for the 2nd 256MB */
141 return address; /* Looks to be a 1:1 mapped userspace pointer */
142 #elif defined(__FreeBSD__) && defined(_KERNEL)
143 return (pmap_kextract((vm_offset_t)ptr));
145 #if CVMX_USE_1_TO_1_TLB_MAPPINGS
146 /* We are assumung we're running the Simple Executive standalone. In this
147 mode the TLB is setup to perform 1:1 mapping and 32 bit sign extended
148 addresses are never used. Since we know all this, save the masking
149 cycles and do nothing */
153 if (sizeof(void*) == 8)
155 /* We're running in 64 bit mode. Normally this means that we can use
156 40 bits of address space (the hardware limit). Unfortunately there
157 is one case were we need to limit this to 30 bits, sign extended
158 32 bit. Although these are 64 bits wide, only 30 bits can be used */
159 if ((CAST64(ptr) >> 62) == 3)
160 return CAST64(ptr) & cvmx_build_mask(30);
162 return CAST64(ptr) & cvmx_build_mask(40);
165 return (long)(ptr) & 0x7fffffff;
173 * Convert a hardware physical address (uint64_t) into a
174 * memory pointer (void *).
176 * @param physical_address
177 * Hardware physical address to memory
178 * @return Pointer to memory
180 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
182 if (CVMX_ENABLE_PARAMETER_CHECKING)
183 cvmx_warn_if(physical_address==0, "cvmx_phys_to_ptr() passed a zero address\n");
185 #ifdef CVMX_BUILD_FOR_UBOOT
187 /* U-boot is a special case, as it is running in 32 bit mode, using the TLB to map code/data
188 ** which can have a physical address above the 32 bit address space. 1-1 mappings are used
189 ** to allow the low 2 GBytes to be accessed as in error level.
191 ** NOTE: This conversion can cause problems in u-boot, as users may want to enter addresses
192 ** like 0xBFC00000 (kseg1 boot bus address), which is a valid 64 bit physical address,
193 ** but is likely intended to be a boot bus address. */
195 if (physical_address < 0x80000000)
197 /* Handle useg here. ERL is set, so useg is unmapped. This is the only physical
198 ** address range that is directly addressable by u-boot. */
199 return CASTPTR(void, physical_address);
203 DECLARE_GLOBAL_DATA_PTR;
204 extern char uboot_start;
205 /* Above 0x80000000 we can only support one case - a physical address
206 ** that is mapped for u-boot code/data. We check against the u-boot mem range,
207 ** and return NULL if it is out of this range.
209 if (physical_address >= gd->bd->bi_uboot_ram_addr
210 && physical_address < gd->bd->bi_uboot_ram_addr + gd->bd->bi_uboot_ram_used_size)
212 return ((char *)&uboot_start + (physical_address - gd->bd->bi_uboot_ram_addr));
218 if (physical_address >= 0x80000000)
224 if (sizeof(void*) == 8)
226 /* Just set the top bit, avoiding any TLB uglyness */
227 return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
232 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
234 extern uint64_t linux_mem32_offset;
235 if (cvmx_likely(physical_address))
236 return CASTPTR(void, physical_address + linux_mem32_offset);
241 #elif defined(_WRS_KERNEL)
242 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
243 #elif defined(VXWORKS_USER_MAPPINGS)
244 /* This mapping mode is used in vxWorks 5.5 to support 2GB of ram. The
245 2nd 256MB is mapped at 0x10000000 and the rest of memory is 1:1 */
246 if ((physical_address >= 0x10000000) && (physical_address < 0x20000000))
247 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
248 else if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX))
249 && (physical_address >= 0x410000000ull)
250 && (physical_address < 0x420000000ull))
251 return CASTPTR(void, physical_address - 0x400000000ull);
253 return CASTPTR(void, physical_address);
254 #elif defined(__FreeBSD__) && defined(_KERNEL)
255 #if defined(__mips_n64)
256 return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
258 if (physical_address < 0x20000000)
259 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
261 panic("%s: mapping high address (%#jx) not yet supported.\n", __func__, (uintmax_t)physical_address);
265 #if CVMX_USE_1_TO_1_TLB_MAPPINGS
266 /* We are assumung we're running the Simple Executive standalone. In this
267 mode the TLB is setup to perform 1:1 mapping and 32 bit sign extended
268 addresses are never used. Since we know all this, save bit insert
269 cycles and do nothing */
270 return CASTPTR(void, physical_address);
272 /* Set the XKPHYS/KSEG0 bit as appropriate based on ABI */
273 if (sizeof(void*) == 8)
274 return CASTPTR(void, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, physical_address));
276 return CASTPTR(void, CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0, physical_address));
284 /* The following #if controls the definition of the macro
285 CVMX_BUILD_WRITE64. This macro is used to build a store operation to
286 a full 64bit address. With a 64bit ABI, this can be done with a simple
287 pointer access. 32bit ABIs require more complicated assembly */
288 #if defined(CVMX_ABI_N64) || defined(CVMX_ABI_EABI)
290 /* We have a full 64bit ABI. Writing to a 64bit address can be done with
291 a simple volatile pointer */
292 #define CVMX_BUILD_WRITE64(TYPE, ST) \
293 static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
295 *CASTPTR(volatile TYPE##_t, addr) = val; \
298 #elif defined(CVMX_ABI_N32)
300 /* The N32 ABI passes all 64bit quantities in a single register, so it is
301 possible to use the arguments directly. We have to use inline assembly
302 for the actual store since a pointer would truncate the address */
303 #define CVMX_BUILD_WRITE64(TYPE, ST) \
304 static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
306 asm volatile (ST " %[v], 0(%[c])" ::[v] "r" (val), [c] "r" (addr)); \
309 #elif defined(CVMX_ABI_O32)
312 #define CVMX_BUILD_WRITE64(TYPE, LT) extern void cvmx_write64_##TYPE(uint64_t csr_addr, TYPE##_t val);
315 /* Ok, now the ugly stuff starts. O32 splits 64bit quantities into two
316 separate registers. Assembly must be used to put them back together
317 before they're used. What should be a simple store becomes a
318 convoluted mess of shifts and ors */
319 #define CVMX_BUILD_WRITE64(TYPE, ST) \
320 static inline void cvmx_write64_##TYPE(uint64_t csr_addr, TYPE##_t val) \
322 if (sizeof(TYPE##_t) == 8) \
324 uint32_t csr_addrh = csr_addr>>32; \
325 uint32_t csr_addrl = csr_addr; \
326 uint32_t valh = (uint64_t)val>>32; \
327 uint32_t vall = val; \
335 "dsll %[tmp1], %[valh], 32\n" \
336 "dsll %[tmp2], %[csrh], 32\n" \
337 "dsll %[tmp3], %[vall], 32\n" \
338 "dsrl %[tmp3], %[tmp3], 32\n" \
339 "or %[tmp1], %[tmp1], %[tmp3]\n" \
340 "dsll %[tmp3], %[csrl], 32\n" \
341 "dsrl %[tmp3], %[tmp3], 32\n" \
342 "or %[tmp2], %[tmp2], %[tmp3]\n" \
343 ST " %[tmp1], 0(%[tmp2])\n" \
345 : [tmp1] "=&r" (tmp1), [tmp2] "=&r" (tmp2), [tmp3] "=&r" (tmp3)\
346 : [valh] "r" (valh), [vall] "r" (vall), \
347 [csrh] "r" (csr_addrh), [csrl] "r" (csr_addrl) \
352 uint32_t csr_addrh = csr_addr>>32; \
353 uint32_t csr_addrl = csr_addr; \
360 "dsll %[tmp1], %[csrh], 32\n" \
361 "dsll %[tmp2], %[csrl], 32\n" \
362 "dsrl %[tmp2], %[tmp2], 32\n" \
363 "or %[tmp1], %[tmp1], %[tmp2]\n" \
364 ST " %[val], 0(%[tmp1])\n" \
366 : [tmp1] "=&r" (tmp1), [tmp2] "=&r" (tmp2) \
367 : [val] "r" (val), [csrh] "r" (csr_addrh), \
368 [csrl] "r" (csr_addrl) \
377 /* cvmx-abi.h didn't recognize the ABI. Force the compile to fail. */
378 #error: Unsupported ABI
382 /* The following #if controls the definition of the macro
383 CVMX_BUILD_READ64. This macro is used to build a load operation from
384 a full 64bit address. With a 64bit ABI, this can be done with a simple
385 pointer access. 32bit ABIs require more complicated assembly */
386 #if defined(CVMX_ABI_N64) || defined(CVMX_ABI_EABI)
388 /* We have a full 64bit ABI. Writing to a 64bit address can be done with
389 a simple volatile pointer */
390 #define CVMX_BUILD_READ64(TYPE, LT) \
391 static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
393 return *CASTPTR(volatile TYPE##_t, addr); \
396 #elif defined(CVMX_ABI_N32)
398 /* The N32 ABI passes all 64bit quantities in a single register, so it is
399 possible to use the arguments directly. We have to use inline assembly
400 for the actual store since a pointer would truncate the address */
401 #define CVMX_BUILD_READ64(TYPE, LT) \
402 static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
405 asm volatile (LT " %[v], 0(%[c])": [v] "=r" (val) : [c] "r" (addr));\
409 #elif defined(CVMX_ABI_O32)
412 #define CVMX_BUILD_READ64(TYPE, LT) extern TYPE##_t cvmx_read64_##TYPE(uint64_t csr_addr);
415 /* Ok, now the ugly stuff starts. O32 splits 64bit quantities into two
416 separate registers. Assembly must be used to put them back together
417 before they're used. What should be a simple load becomes a
418 convoluted mess of shifts and ors */
419 #define CVMX_BUILD_READ64(TYPE, LT) \
420 static inline TYPE##_t cvmx_read64_##TYPE(uint64_t csr_addr) \
422 if (sizeof(TYPE##_t) == 8) \
424 uint32_t csr_addrh = csr_addr>>32; \
425 uint32_t csr_addrl = csr_addr; \
432 "dsll %[valh], %[csrh], 32\n" \
433 "dsll %[vall], %[csrl], 32\n" \
434 "dsrl %[vall], %[vall], 32\n" \
435 "or %[valh], %[valh], %[vall]\n" \
436 LT " %[vall], 0(%[valh])\n" \
437 "dsrl %[valh], %[vall], 32\n" \
441 : [valh] "=&r" (valh), [vall] "=&r" (vall) \
442 : [csrh] "r" (csr_addrh), [csrl] "r" (csr_addrl) \
444 return ((uint64_t)valh<<32) | vall; \
448 uint32_t csr_addrh = csr_addr>>32; \
449 uint32_t csr_addrl = csr_addr; \
456 "dsll %[val], %[csrh], 32\n" \
457 "dsll %[tmp], %[csrl], 32\n" \
458 "dsrl %[tmp], %[tmp], 32\n" \
459 "or %[val], %[val], %[tmp]\n" \
460 LT " %[val], 0(%[val])\n" \
462 : [val] "=&r" (val), [tmp] "=&r" (tmp) \
463 : [csrh] "r" (csr_addrh), [csrl] "r" (csr_addrl) \
469 #endif /* __KERNEL__ */
473 /* cvmx-abi.h didn't recognize the ABI. Force the compile to fail. */
474 #error: Unsupported ABI
478 /* The following defines 8 functions for writing to a 64bit address. Each
479 takes two arguments, the address and the value to write.
480 cvmx_write64_int64 cvmx_write64_uint64
481 cvmx_write64_int32 cvmx_write64_uint32
482 cvmx_write64_int16 cvmx_write64_uint16
483 cvmx_write64_int8 cvmx_write64_uint8 */
484 CVMX_BUILD_WRITE64(int64, "sd");
485 CVMX_BUILD_WRITE64(int32, "sw");
486 CVMX_BUILD_WRITE64(int16, "sh");
487 CVMX_BUILD_WRITE64(int8, "sb");
488 CVMX_BUILD_WRITE64(uint64, "sd");
489 CVMX_BUILD_WRITE64(uint32, "sw");
490 CVMX_BUILD_WRITE64(uint16, "sh");
491 CVMX_BUILD_WRITE64(uint8, "sb");
493 /* The following defines 8 functions for reading from a 64bit address. Each
494 takes the address as the only argument
495 cvmx_read64_int64 cvmx_read64_uint64
496 cvmx_read64_int32 cvmx_read64_uint32
497 cvmx_read64_int16 cvmx_read64_uint16
498 cvmx_read64_int8 cvmx_read64_uint8 */
499 CVMX_BUILD_READ64(int64, "ld");
500 CVMX_BUILD_READ64(int32, "lw");
501 CVMX_BUILD_READ64(int16, "lh");
502 CVMX_BUILD_READ64(int8, "lb");
503 CVMX_BUILD_READ64(uint64, "ld");
504 CVMX_BUILD_READ64(uint32, "lw");
505 CVMX_BUILD_READ64(uint16, "lhu");
506 CVMX_BUILD_READ64(uint8, "lbu");
508 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
510 cvmx_write64_uint64(csr_addr, val);
512 /* Perform an immediate read after every write to an RSL register to force
513 the write to complete. It doesn't matter what RSL read we do, so we
514 choose CVMX_MIO_BOOT_BIST_STAT because it is fast and harmless */
515 if (((csr_addr >> 40) & 0x7ffff) == (0x118))
516 cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT);
519 static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
521 cvmx_write64_uint64(io_addr, val);
524 static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
526 return cvmx_read64_uint64(csr_addr);
529 static inline void cvmx_send_single(uint64_t data)
531 const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
532 cvmx_write64_uint64(CVMX_IOBDMA_SENDSINGLE, data);
535 static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
541 uint64_t scraddr : 8;
547 addr.s.scraddr = scraddr >> 3;
549 cvmx_send_single(addr.u64);
554 * Number of the Core on which the program is currently running.
556 * @return Number of cores
558 static inline unsigned int cvmx_get_core_num(void)
560 unsigned int core_num;
561 CVMX_RDHWRNV(core_num, 0);
567 * Returns the number of bits set in the provided value.
568 * Simple wrapper for POP instruction.
570 * @param val 32 bit value to count set bits in
572 * @return Number of bits set
574 static inline uint32_t cvmx_pop(uint32_t val)
583 * Returns the number of bits set in the provided value.
584 * Simple wrapper for DPOP instruction.
586 * @param val 64 bit value to count set bits in
588 * @return Number of bits set
590 static inline int cvmx_dpop(uint64_t val)
600 * Provide current cycle counter as a return value. Deprecated, use
601 * cvmx_clock_get_count(CVMX_CLOCK_CORE) to get cycle counter.
603 * @return current cycle counter
605 static inline uint64_t cvmx_get_cycle(void)
607 return cvmx_clock_get_count(CVMX_CLOCK_CORE);
613 * Reads a chip global cycle counter. This counts SCLK cycles since
614 * chip reset. The counter is 64 bit. This function is deprecated as the rate
615 * of the global cycle counter is different between Octeon+ and Octeon2, use
616 * cvmx_clock_get_count(CVMX_CLOCK_SCLK) instead. For Octeon2, the clock rate
617 * of SCLK may be differnet than the core clock.
619 * @return Global chip cycle count since chip reset.
621 static inline uint64_t cvmx_get_cycle_global(void)
623 return cvmx_clock_get_count(CVMX_CLOCK_IPD);
628 * Wait for the specified number of core clock cycles
632 static inline void cvmx_wait(uint64_t cycles)
634 uint64_t done = cvmx_get_cycle() + cycles;
636 while (cvmx_get_cycle() < done)
644 * Wait for the specified number of micro seconds
646 * @param usec micro seconds to wait
648 static inline void cvmx_wait_usec(uint64_t usec)
650 uint64_t done = cvmx_get_cycle() + usec * cvmx_clock_get_rate(CVMX_CLOCK_CORE) / 1000000;
651 while (cvmx_get_cycle() < done)
659 * Wait for the specified number of io clock cycles
663 static inline void cvmx_wait_io(uint64_t cycles)
665 uint64_t done = cvmx_clock_get_count(CVMX_CLOCK_SCLK) + cycles;
667 while (cvmx_clock_get_count(CVMX_CLOCK_SCLK) < done)
675 * Perform a soft reset of Octeon
679 static inline void cvmx_reset_octeon(void)
681 cvmx_ciu_soft_rst_t ciu_soft_rst;
682 ciu_soft_rst.u64 = 0;
683 ciu_soft_rst.s.soft_rst = 1;
684 cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
689 * Read a byte of fuse data
690 * @param byte_addr address to read
692 * @return fuse value: 0 or 1
694 static inline uint8_t cvmx_fuse_read_byte(int byte_addr)
696 cvmx_mio_fus_rcmd_t read_cmd;
699 read_cmd.s.addr = byte_addr;
701 cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
702 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD)) && read_cmd.s.pend)
704 return(read_cmd.s.dat);
709 * Read a single fuse bit
711 * @param fuse Fuse number (0-1024)
713 * @return fuse value: 0 or 1
715 static inline int cvmx_fuse_read(int fuse)
717 return((cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1);
724 #endif /* __CVMX_ACCESS_NATIVE_H__ */