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43 * Typedefs and defines for working with Octeon physical addresses.
45 * <hr>$Revision: 38306 $<hr>
47 #ifndef __CVMX_ADDRESS_H__
48 #define __CVMX_ADDRESS_H__
50 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
59 CVMX_MIPS_SPACE_XKSEG = 3LL,
60 CVMX_MIPS_SPACE_XKPHYS = 2LL,
61 CVMX_MIPS_SPACE_XSSEG = 1LL,
62 CVMX_MIPS_SPACE_XUSEG = 0LL
66 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
67 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
68 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
69 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
70 } cvmx_mips_xkseg_space_t;
72 /* decodes <14:13> of a kseg3 window address */
74 CVMX_ADD_WIN_SCR = 0L,
75 CVMX_ADD_WIN_DMA = 1L, /* see cvmx_add_win_dma_dec_t for further decode */
76 CVMX_ADD_WIN_UNUSED = 2L,
77 CVMX_ADD_WIN_UNUSED2 = 3L
80 /* decode within DMA space */
82 CVMX_ADD_WIN_DMA_ADD = 0L, /* add store data to the write buffer entry, allocating it if necessary */
83 CVMX_ADD_WIN_DMA_SENDMEM = 1L, /* send out the write buffer entry to DRAM */
84 /* store data must be normal DRAM memory space address in this case */
85 CVMX_ADD_WIN_DMA_SENDDMA = 2L, /* send out the write buffer entry as an IOBDMA command */
86 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
87 CVMX_ADD_WIN_DMA_SENDIO = 3L, /* send out the write buffer entry as an IO write */
88 /* store data must be normal IO space address in this case */
89 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, /* send out a single-tick command on the NCB bus */
90 /* no write buffer data needed/used */
91 } cvmx_add_win_dma_dec_t;
94 * Physical Address Decode
96 * Octeon-I HW never interprets this X (<39:36> reserved
97 * for future expansion), software should set to 0.
99 * - 0x0 XXX0 0000 0000 to DRAM Cached
100 * - 0x0 XXX0 0FFF FFFF
102 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000
103 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF)
105 * - 0x0 XXX0 2000 0000 to DRAM Cached
106 * - 0x0 XXXF FFFF FFFF
108 * - 0x1 00X0 0000 0000 to Boot Bus Uncached
109 * - 0x1 00XF FFFF FFFF
111 * - 0x1 01X0 0000 0000 to Other NCB Uncached
112 * - 0x1 FFXF FFFF FFFF devices
114 * Decode of all Octeon addresses
121 cvmx_mips_space_t R : 2;
123 } sva; /* mapped or unmapped virtual address */
128 } suseg; /* mapped USEG virtual addresses (typically) */
132 cvmx_mips_xkseg_space_t sp : 2;
134 } sxkseg; /* mapped or unmapped virtual address */
137 cvmx_mips_space_t R : 2; /* CVMX_MIPS_SPACE_XKPHYS in this case */
138 uint64_t cca : 3; /* ignored by octeon */
140 uint64_t pa :49; /* physical address */
141 } sxkphys; /* physical address accessed through xkphys unmapped virtual address */
145 uint64_t is_io : 1; /* if set, the address is uncached and resides on MCB bus */
146 uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */
147 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
149 } sphys; /* physical address */
152 uint64_t zeroes :24; /* techically, <47:40> are dont-cares */
153 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
155 } smem; /* physical mem address */
158 uint64_t mem_region :2;
160 uint64_t is_io : 1; /* 1 in this case */
161 uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */
162 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */
164 } sio; /* physical IO address */
168 cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_SCR (0) in this case */
170 } sscr; /* scratchpad virtual address - accessed through a window at the end of kseg3 */
172 /* there should only be stores to IOBDMA space, no loads */
175 cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_DMA (1) in this case */
177 cvmx_add_win_dma_dec_t type : 3;
179 } sdma; /* IOBDMA virtual address - accessed through a window at the end of kseg3 */
182 uint64_t didspace : 24;
183 uint64_t unused : 40;
188 /* These macros for used by 32 bit applications */
190 #define CVMX_MIPS32_SPACE_KSEG0 1l
191 #define CVMX_ADD_SEG32(segment, add) (((int32_t)segment << 31) | (int32_t)(add))
193 /* Currently all IOs are performed using XKPHYS addressing. Linux uses the
194 CvmMemCtl register to enable XKPHYS addressing to IO space from user mode.
195 Future OSes may need to change the upper bits of IO addresses. The
196 following define controls the upper two bits for all IO addresses generated
197 by the simple executive library */
198 #define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
200 /* These macros simplify the process of creating common IO addresses */
201 #define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
202 #ifndef CVMX_ADD_IO_SEG
203 #define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
205 #define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
206 #define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
207 #define CVMX_FULL_DID(did,subdid) (((did) << 3) | (subdid))
210 /* from include/ncb_rsl_id.v */
211 #define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
212 #define CVMX_OCT_DID_GMX0 1ULL
213 #define CVMX_OCT_DID_GMX1 2ULL
214 #define CVMX_OCT_DID_PCI 3ULL
215 #define CVMX_OCT_DID_KEY 4ULL
216 #define CVMX_OCT_DID_FPA 5ULL
217 #define CVMX_OCT_DID_DFA 6ULL
218 #define CVMX_OCT_DID_ZIP 7ULL
219 #define CVMX_OCT_DID_RNG 8ULL
220 #define CVMX_OCT_DID_IPD 9ULL
221 #define CVMX_OCT_DID_PKT 10ULL
222 #define CVMX_OCT_DID_TIM 11ULL
223 #define CVMX_OCT_DID_TAG 12ULL
224 /* the rest are not on the IO bus */
225 #define CVMX_OCT_DID_L2C 16ULL
226 #define CVMX_OCT_DID_LMC 17ULL
227 #define CVMX_OCT_DID_SPX0 18ULL
228 #define CVMX_OCT_DID_SPX1 19ULL
229 #define CVMX_OCT_DID_PIP 20ULL
230 #define CVMX_OCT_DID_ASX0 22ULL
231 #define CVMX_OCT_DID_ASX1 23ULL
232 #define CVMX_OCT_DID_IOB 30ULL
234 #define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT,2ULL)
235 #define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG,0ULL)
236 #define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG,1ULL)
237 #define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
238 #define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
239 #define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
240 #define CVMX_OCT_DID_TAG_TAG5 CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL)
241 #define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
242 #define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
243 #define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
244 #define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY,0ULL)
245 #define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI,6ULL)
246 #define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS,0ULL)
247 #define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI,0ULL)
248 #define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD,7ULL)
249 #define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA,7ULL)
250 #define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
251 #define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
253 #ifndef CVMX_BUILD_FOR_LINUX_KERNEL
255 #define UNMAPPED_PTR(x) ( (1U << 31) | x )
257 #define UNMAPPED_PTR(x) ( (1ULL << 63) | x )
265 #endif /* __CVMX_ADDRESS_H__ */