1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_ASXX_DEFS_H__
53 #define __CVMX_ASXX_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
62 cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id);
63 return CVMX_ADD_IO_SEG(0x00011800B0000180ull);
66 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
68 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
69 static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
72 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
74 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
75 cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
76 return CVMX_ADD_IO_SEG(0x00011800B0000188ull);
79 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
81 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
82 static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
85 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
87 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
88 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
89 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
90 cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id);
91 return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull;
94 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
96 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
97 static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
100 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
101 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
102 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
103 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
104 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
105 cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id);
106 return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull;
109 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
111 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
112 static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
115 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
116 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
117 cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
118 return CVMX_ADD_IO_SEG(0x00011800B0000190ull);
121 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
124 static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
127 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
128 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
129 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
130 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
131 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
132 cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id);
133 return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull;
136 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
138 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
139 static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
142 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
143 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
144 cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id);
145 return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull;
148 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
150 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
151 static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
154 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
155 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
156 cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id);
157 return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull;
160 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
162 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
163 static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
166 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
167 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
168 cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id);
169 return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull;
172 #define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
174 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
175 static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
179 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
180 cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id);
181 return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull;
184 #define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
186 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
187 static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
190 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
191 cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id);
192 return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull;
195 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
197 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
198 static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
201 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
203 cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id);
204 return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull;
207 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
210 static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
213 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
214 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
215 cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id);
216 return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull;
219 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
222 static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
225 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
227 cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id);
228 return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull;
231 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
234 static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
237 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
238 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
239 cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id);
240 return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull;
243 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
245 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
246 static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
249 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
250 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
251 cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id);
252 return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull;
255 #define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
257 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
258 static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id)
261 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
262 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
265 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
266 cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
267 return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
270 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
272 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
273 static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
276 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
277 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
278 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
279 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
280 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
281 cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id);
282 return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull;
285 #define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
288 static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
291 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
292 cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id);
293 return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull;
296 #define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
298 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
299 static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
302 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
303 cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id);
304 return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull;
307 #define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
309 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
310 static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
313 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
314 cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id);
315 return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull;
318 #define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
320 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
321 static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
324 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
325 cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id);
326 return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull;
329 #define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
331 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
332 static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id)
335 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
336 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
337 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
338 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
339 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
340 cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
341 return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
344 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
346 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
347 static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
350 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
351 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
352 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
353 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
354 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
355 cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id);
356 return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull;
359 #define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
361 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
362 static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id)
365 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
366 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
367 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
368 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
369 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
370 cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id);
371 return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
374 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
376 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
377 static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
380 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
381 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
382 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
383 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
384 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
385 cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id);
386 return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull;
389 #define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
393 * cvmx_asx#_gmii_rx_clk_set
395 * ASX_GMII_RX_CLK_SET = GMII Clock delay setting
398 union cvmx_asxx_gmii_rx_clk_set {
400 struct cvmx_asxx_gmii_rx_clk_set_s {
401 #ifdef __BIG_ENDIAN_BITFIELD
402 uint64_t reserved_5_63 : 59;
403 uint64_t setting : 5; /**< Setting to place on the RXCLK (GMII receive clk)
404 delay line. The intrinsic delay can range from
405 50ps to 80ps per tap. */
407 uint64_t setting : 5;
408 uint64_t reserved_5_63 : 59;
411 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
412 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
413 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
415 typedef union cvmx_asxx_gmii_rx_clk_set cvmx_asxx_gmii_rx_clk_set_t;
418 * cvmx_asx#_gmii_rx_dat_set
420 * ASX_GMII_RX_DAT_SET = GMII Clock delay setting
423 union cvmx_asxx_gmii_rx_dat_set {
425 struct cvmx_asxx_gmii_rx_dat_set_s {
426 #ifdef __BIG_ENDIAN_BITFIELD
427 uint64_t reserved_5_63 : 59;
428 uint64_t setting : 5; /**< Setting to place on the RXD (GMII receive data)
429 delay lines. The intrinsic delay can range from
430 50ps to 80ps per tap. */
432 uint64_t setting : 5;
433 uint64_t reserved_5_63 : 59;
436 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
437 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
438 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
440 typedef union cvmx_asxx_gmii_rx_dat_set cvmx_asxx_gmii_rx_dat_set_t;
445 * ASX_INT_EN = Interrupt Enable
448 union cvmx_asxx_int_en {
450 struct cvmx_asxx_int_en_s {
451 #ifdef __BIG_ENDIAN_BITFIELD
452 uint64_t reserved_12_63 : 52;
453 uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */
454 uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */
455 uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */
460 uint64_t reserved_12_63 : 52;
463 struct cvmx_asxx_int_en_cn30xx {
464 #ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t reserved_11_63 : 53;
466 uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */
467 uint64_t reserved_7_7 : 1;
468 uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */
469 uint64_t reserved_3_3 : 1;
470 uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */
473 uint64_t reserved_3_3 : 1;
475 uint64_t reserved_7_7 : 1;
477 uint64_t reserved_11_63 : 53;
480 struct cvmx_asxx_int_en_cn30xx cn31xx;
481 struct cvmx_asxx_int_en_s cn38xx;
482 struct cvmx_asxx_int_en_s cn38xxp2;
483 struct cvmx_asxx_int_en_cn30xx cn50xx;
484 struct cvmx_asxx_int_en_s cn58xx;
485 struct cvmx_asxx_int_en_s cn58xxp1;
487 typedef union cvmx_asxx_int_en cvmx_asxx_int_en_t;
492 * ASX_INT_REG = Interrupt Register
495 union cvmx_asxx_int_reg {
497 struct cvmx_asxx_int_reg_s {
498 #ifdef __BIG_ENDIAN_BITFIELD
499 uint64_t reserved_12_63 : 52;
500 uint64_t txpsh : 4; /**< TX FIFO overflow on RMGII port */
501 uint64_t txpop : 4; /**< TX FIFO underflow on RMGII port */
502 uint64_t ovrflw : 4; /**< RX FIFO overflow on RMGII port */
507 uint64_t reserved_12_63 : 52;
510 struct cvmx_asxx_int_reg_cn30xx {
511 #ifdef __BIG_ENDIAN_BITFIELD
512 uint64_t reserved_11_63 : 53;
513 uint64_t txpsh : 3; /**< TX FIFO overflow on RMGII port */
514 uint64_t reserved_7_7 : 1;
515 uint64_t txpop : 3; /**< TX FIFO underflow on RMGII port */
516 uint64_t reserved_3_3 : 1;
517 uint64_t ovrflw : 3; /**< RX FIFO overflow on RMGII port */
520 uint64_t reserved_3_3 : 1;
522 uint64_t reserved_7_7 : 1;
524 uint64_t reserved_11_63 : 53;
527 struct cvmx_asxx_int_reg_cn30xx cn31xx;
528 struct cvmx_asxx_int_reg_s cn38xx;
529 struct cvmx_asxx_int_reg_s cn38xxp2;
530 struct cvmx_asxx_int_reg_cn30xx cn50xx;
531 struct cvmx_asxx_int_reg_s cn58xx;
532 struct cvmx_asxx_int_reg_s cn58xxp1;
534 typedef union cvmx_asxx_int_reg cvmx_asxx_int_reg_t;
537 * cvmx_asx#_mii_rx_dat_set
539 * ASX_MII_RX_DAT_SET = GMII Clock delay setting
542 union cvmx_asxx_mii_rx_dat_set {
544 struct cvmx_asxx_mii_rx_dat_set_s {
545 #ifdef __BIG_ENDIAN_BITFIELD
546 uint64_t reserved_5_63 : 59;
547 uint64_t setting : 5; /**< Setting to place on the RXD (MII receive data)
548 delay lines. The intrinsic delay can range from
549 50ps to 80ps per tap. */
551 uint64_t setting : 5;
552 uint64_t reserved_5_63 : 59;
555 struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
556 struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
558 typedef union cvmx_asxx_mii_rx_dat_set cvmx_asxx_mii_rx_dat_set_t;
563 * ASX_PRT_LOOP = Internal Loopback mode - TX FIFO output goes into RX FIFO (and maybe pins)
566 union cvmx_asxx_prt_loop {
568 struct cvmx_asxx_prt_loop_s {
569 #ifdef __BIG_ENDIAN_BITFIELD
570 uint64_t reserved_8_63 : 56;
571 uint64_t ext_loop : 4; /**< External Loopback Enable
572 0 = No Loopback (TX FIFO is filled by RMGII)
573 1 = RX FIFO drives the TX FIFO
574 - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
575 - GMX_PRT_CFG[SPEED] must be 1 (GigE speed)
576 - core clock > 250MHZ
577 - rxc must not deviate from the +-50ppm
578 - if txc>rxc, idle cycle may drop over time */
579 uint64_t int_loop : 4; /**< Internal Loopback Enable
580 0 = No Loopback (RX FIFO is filled by RMGII pins)
581 1 = TX FIFO drives the RX FIFO
582 Note, in internal loop-back mode, the RGMII link
583 status is not used (since there is no real PHY).
584 Software cannot use the inband status. */
586 uint64_t int_loop : 4;
587 uint64_t ext_loop : 4;
588 uint64_t reserved_8_63 : 56;
591 struct cvmx_asxx_prt_loop_cn30xx {
592 #ifdef __BIG_ENDIAN_BITFIELD
593 uint64_t reserved_7_63 : 57;
594 uint64_t ext_loop : 3; /**< External Loopback Enable
595 0 = No Loopback (TX FIFO is filled by RMGII)
596 1 = RX FIFO drives the TX FIFO
597 - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
598 - GMX_PRT_CFG[SPEED] must be 1 (GigE speed)
599 - core clock > 250MHZ
600 - rxc must not deviate from the +-50ppm
601 - if txc>rxc, idle cycle may drop over time */
602 uint64_t reserved_3_3 : 1;
603 uint64_t int_loop : 3; /**< Internal Loopback Enable
604 0 = No Loopback (RX FIFO is filled by RMGII pins)
605 1 = TX FIFO drives the RX FIFO
606 - GMX_PRT_CFG[DUPLEX] must be 1 (FullDuplex)
607 - GMX_PRT_CFG[SPEED] must be 1 (GigE speed)
608 - GMX_TX_CLK[CLK_CNT] must be 1
609 Note, in internal loop-back mode, the RGMII link
610 status is not used (since there is no real PHY).
611 Software cannot use the inband status. */
613 uint64_t int_loop : 3;
614 uint64_t reserved_3_3 : 1;
615 uint64_t ext_loop : 3;
616 uint64_t reserved_7_63 : 57;
619 struct cvmx_asxx_prt_loop_cn30xx cn31xx;
620 struct cvmx_asxx_prt_loop_s cn38xx;
621 struct cvmx_asxx_prt_loop_s cn38xxp2;
622 struct cvmx_asxx_prt_loop_cn30xx cn50xx;
623 struct cvmx_asxx_prt_loop_s cn58xx;
624 struct cvmx_asxx_prt_loop_s cn58xxp1;
626 typedef union cvmx_asxx_prt_loop cvmx_asxx_prt_loop_t;
629 * cvmx_asx#_rld_bypass
634 union cvmx_asxx_rld_bypass {
636 struct cvmx_asxx_rld_bypass_s {
637 #ifdef __BIG_ENDIAN_BITFIELD
638 uint64_t reserved_1_63 : 63;
639 uint64_t bypass : 1; /**< When set, the rld_dll setting is bypassed with
640 ASX_RLD_BYPASS_SETTING */
643 uint64_t reserved_1_63 : 63;
646 struct cvmx_asxx_rld_bypass_s cn38xx;
647 struct cvmx_asxx_rld_bypass_s cn38xxp2;
648 struct cvmx_asxx_rld_bypass_s cn58xx;
649 struct cvmx_asxx_rld_bypass_s cn58xxp1;
651 typedef union cvmx_asxx_rld_bypass cvmx_asxx_rld_bypass_t;
654 * cvmx_asx#_rld_bypass_setting
656 * ASX_RLD_BYPASS_SETTING
659 union cvmx_asxx_rld_bypass_setting {
661 struct cvmx_asxx_rld_bypass_setting_s {
662 #ifdef __BIG_ENDIAN_BITFIELD
663 uint64_t reserved_5_63 : 59;
664 uint64_t setting : 5; /**< The rld_dll setting bypass value */
666 uint64_t setting : 5;
667 uint64_t reserved_5_63 : 59;
670 struct cvmx_asxx_rld_bypass_setting_s cn38xx;
671 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
672 struct cvmx_asxx_rld_bypass_setting_s cn58xx;
673 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
675 typedef union cvmx_asxx_rld_bypass_setting cvmx_asxx_rld_bypass_setting_t;
683 union cvmx_asxx_rld_comp {
685 struct cvmx_asxx_rld_comp_s {
686 #ifdef __BIG_ENDIAN_BITFIELD
687 uint64_t reserved_9_63 : 55;
688 uint64_t pctl : 5; /**< PCTL Compensation Value
689 These bits reflect the computed compensation
690 values from the built-in compensation circuit. */
691 uint64_t nctl : 4; /**< These bits reflect the computed compensation
692 values from the built-in compensation circuit. */
696 uint64_t reserved_9_63 : 55;
699 struct cvmx_asxx_rld_comp_cn38xx {
700 #ifdef __BIG_ENDIAN_BITFIELD
701 uint64_t reserved_8_63 : 56;
702 uint64_t pctl : 4; /**< These bits reflect the computed compensation
703 values from the built-in compensation circuit. */
704 uint64_t nctl : 4; /**< These bits reflect the computed compensation
705 values from the built-in compensation circuit. */
709 uint64_t reserved_8_63 : 56;
712 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
713 struct cvmx_asxx_rld_comp_s cn58xx;
714 struct cvmx_asxx_rld_comp_s cn58xxp1;
716 typedef union cvmx_asxx_rld_comp cvmx_asxx_rld_comp_t;
719 * cvmx_asx#_rld_data_drv
724 union cvmx_asxx_rld_data_drv {
726 struct cvmx_asxx_rld_data_drv_s {
727 #ifdef __BIG_ENDIAN_BITFIELD
728 uint64_t reserved_8_63 : 56;
729 uint64_t pctl : 4; /**< These bits specify a driving strength (positive
730 integer) for the RLD I/Os when the built-in
731 compensation circuit is bypassed. */
732 uint64_t nctl : 4; /**< These bits specify a driving strength (positive
733 integer) for the RLD I/Os when the built-in
734 compensation circuit is bypassed. */
738 uint64_t reserved_8_63 : 56;
741 struct cvmx_asxx_rld_data_drv_s cn38xx;
742 struct cvmx_asxx_rld_data_drv_s cn38xxp2;
743 struct cvmx_asxx_rld_data_drv_s cn58xx;
744 struct cvmx_asxx_rld_data_drv_s cn58xxp1;
746 typedef union cvmx_asxx_rld_data_drv cvmx_asxx_rld_data_drv_t;
749 * cvmx_asx#_rld_fcram_mode
754 union cvmx_asxx_rld_fcram_mode {
756 struct cvmx_asxx_rld_fcram_mode_s {
757 #ifdef __BIG_ENDIAN_BITFIELD
758 uint64_t reserved_1_63 : 63;
759 uint64_t mode : 1; /**< Memory Mode
764 uint64_t reserved_1_63 : 63;
767 struct cvmx_asxx_rld_fcram_mode_s cn38xx;
768 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
770 typedef union cvmx_asxx_rld_fcram_mode cvmx_asxx_rld_fcram_mode_t;
773 * cvmx_asx#_rld_nctl_strong
775 * ASX_RLD_NCTL_STRONG
778 union cvmx_asxx_rld_nctl_strong {
780 struct cvmx_asxx_rld_nctl_strong_s {
781 #ifdef __BIG_ENDIAN_BITFIELD
782 uint64_t reserved_5_63 : 59;
783 uint64_t nctl : 5; /**< Duke's drive control */
786 uint64_t reserved_5_63 : 59;
789 struct cvmx_asxx_rld_nctl_strong_s cn38xx;
790 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
791 struct cvmx_asxx_rld_nctl_strong_s cn58xx;
792 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
794 typedef union cvmx_asxx_rld_nctl_strong cvmx_asxx_rld_nctl_strong_t;
797 * cvmx_asx#_rld_nctl_weak
802 union cvmx_asxx_rld_nctl_weak {
804 struct cvmx_asxx_rld_nctl_weak_s {
805 #ifdef __BIG_ENDIAN_BITFIELD
806 uint64_t reserved_5_63 : 59;
807 uint64_t nctl : 5; /**< UNUSED (not needed for CN58XX) */
810 uint64_t reserved_5_63 : 59;
813 struct cvmx_asxx_rld_nctl_weak_s cn38xx;
814 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
815 struct cvmx_asxx_rld_nctl_weak_s cn58xx;
816 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
818 typedef union cvmx_asxx_rld_nctl_weak cvmx_asxx_rld_nctl_weak_t;
821 * cvmx_asx#_rld_pctl_strong
823 * ASX_RLD_PCTL_STRONG
826 union cvmx_asxx_rld_pctl_strong {
828 struct cvmx_asxx_rld_pctl_strong_s {
829 #ifdef __BIG_ENDIAN_BITFIELD
830 uint64_t reserved_5_63 : 59;
831 uint64_t pctl : 5; /**< Duke's drive control */
834 uint64_t reserved_5_63 : 59;
837 struct cvmx_asxx_rld_pctl_strong_s cn38xx;
838 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
839 struct cvmx_asxx_rld_pctl_strong_s cn58xx;
840 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
842 typedef union cvmx_asxx_rld_pctl_strong cvmx_asxx_rld_pctl_strong_t;
845 * cvmx_asx#_rld_pctl_weak
850 union cvmx_asxx_rld_pctl_weak {
852 struct cvmx_asxx_rld_pctl_weak_s {
853 #ifdef __BIG_ENDIAN_BITFIELD
854 uint64_t reserved_5_63 : 59;
855 uint64_t pctl : 5; /**< UNUSED (not needed for CN58XX) */
858 uint64_t reserved_5_63 : 59;
861 struct cvmx_asxx_rld_pctl_weak_s cn38xx;
862 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
863 struct cvmx_asxx_rld_pctl_weak_s cn58xx;
864 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
866 typedef union cvmx_asxx_rld_pctl_weak cvmx_asxx_rld_pctl_weak_t;
869 * cvmx_asx#_rld_setting
874 union cvmx_asxx_rld_setting {
876 struct cvmx_asxx_rld_setting_s {
877 #ifdef __BIG_ENDIAN_BITFIELD
878 uint64_t reserved_13_63 : 51;
879 uint64_t dfaset : 5; /**< RLD ClkGen DLL Setting(debug) */
880 uint64_t dfalag : 1; /**< RLD ClkGen DLL Lag Error(debug) */
881 uint64_t dfalead : 1; /**< RLD ClkGen DLL Lead Error(debug) */
882 uint64_t dfalock : 1; /**< RLD ClkGen DLL Lock acquisition(debug) */
883 uint64_t setting : 5; /**< RLDCK90 DLL Setting(debug) */
885 uint64_t setting : 5;
886 uint64_t dfalock : 1;
887 uint64_t dfalead : 1;
890 uint64_t reserved_13_63 : 51;
893 struct cvmx_asxx_rld_setting_cn38xx {
894 #ifdef __BIG_ENDIAN_BITFIELD
895 uint64_t reserved_5_63 : 59;
896 uint64_t setting : 5; /**< This is the read-only true rld dll_setting. */
898 uint64_t setting : 5;
899 uint64_t reserved_5_63 : 59;
902 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
903 struct cvmx_asxx_rld_setting_s cn58xx;
904 struct cvmx_asxx_rld_setting_s cn58xxp1;
906 typedef union cvmx_asxx_rld_setting cvmx_asxx_rld_setting_t;
909 * cvmx_asx#_rx_clk_set#
911 * ASX_RX_CLK_SET = RGMII Clock delay setting
915 * Setting to place on the open-loop RXC (RGMII receive clk)
916 * delay line, which can delay the recieved clock. This
917 * can be used if the board and/or transmitting device
918 * has not otherwise delayed the clock.
920 * A value of SETTING=0 disables the delay line. The delay
921 * line should be disabled unless the transmitter or board
922 * does not delay the clock.
924 * Note that this delay line provides only a coarse control
925 * over the delay. Generally, it can only reliably provide
926 * a delay in the range 1.25-2.5ns, which may not be adequate
927 * for some system applications.
929 * The open loop delay line selects
930 * from among a series of tap positions. Each incremental
931 * tap position adds a delay of 50ps to 135ps per tap, depending
932 * on the chip, its temperature, and the voltage.
933 * To achieve from 1.25-2.5ns of delay on the recieved
934 * clock, a fixed value of SETTING=24 may work.
935 * For more precision, we recommend the following settings
936 * based on the chip voltage:
939 * -----------------------------
948 union cvmx_asxx_rx_clk_setx {
950 struct cvmx_asxx_rx_clk_setx_s {
951 #ifdef __BIG_ENDIAN_BITFIELD
952 uint64_t reserved_5_63 : 59;
953 uint64_t setting : 5; /**< Setting to place on the open-loop RXC delay line */
955 uint64_t setting : 5;
956 uint64_t reserved_5_63 : 59;
959 struct cvmx_asxx_rx_clk_setx_s cn30xx;
960 struct cvmx_asxx_rx_clk_setx_s cn31xx;
961 struct cvmx_asxx_rx_clk_setx_s cn38xx;
962 struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
963 struct cvmx_asxx_rx_clk_setx_s cn50xx;
964 struct cvmx_asxx_rx_clk_setx_s cn58xx;
965 struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
967 typedef union cvmx_asxx_rx_clk_setx cvmx_asxx_rx_clk_setx_t;
970 * cvmx_asx#_rx_prt_en
972 * ASX_RX_PRT_EN = RGMII Port Enable
975 union cvmx_asxx_rx_prt_en {
977 struct cvmx_asxx_rx_prt_en_s {
978 #ifdef __BIG_ENDIAN_BITFIELD
979 uint64_t reserved_4_63 : 60;
980 uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to receive
981 RMGII traffic. When this bit clear on a given
982 port, then the all RGMII cycles will appear as
983 inter-frame cycles. */
986 uint64_t reserved_4_63 : 60;
989 struct cvmx_asxx_rx_prt_en_cn30xx {
990 #ifdef __BIG_ENDIAN_BITFIELD
991 uint64_t reserved_3_63 : 61;
992 uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to receive
993 RMGII traffic. When this bit clear on a given
994 port, then the all RGMII cycles will appear as
995 inter-frame cycles. */
998 uint64_t reserved_3_63 : 61;
1001 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
1002 struct cvmx_asxx_rx_prt_en_s cn38xx;
1003 struct cvmx_asxx_rx_prt_en_s cn38xxp2;
1004 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
1005 struct cvmx_asxx_rx_prt_en_s cn58xx;
1006 struct cvmx_asxx_rx_prt_en_s cn58xxp1;
1008 typedef union cvmx_asxx_rx_prt_en cvmx_asxx_rx_prt_en_t;
1013 * ASX_RX_WOL = RGMII RX Wake on LAN status register
1016 union cvmx_asxx_rx_wol {
1018 struct cvmx_asxx_rx_wol_s {
1019 #ifdef __BIG_ENDIAN_BITFIELD
1020 uint64_t reserved_2_63 : 62;
1021 uint64_t status : 1; /**< Copy of PMCSR[15] - PME_status */
1022 uint64_t enable : 1; /**< Copy of PMCSR[8] - PME_enable */
1024 uint64_t enable : 1;
1025 uint64_t status : 1;
1026 uint64_t reserved_2_63 : 62;
1029 struct cvmx_asxx_rx_wol_s cn38xx;
1030 struct cvmx_asxx_rx_wol_s cn38xxp2;
1032 typedef union cvmx_asxx_rx_wol cvmx_asxx_rx_wol_t;
1035 * cvmx_asx#_rx_wol_msk
1037 * ASX_RX_WOL_MSK = RGMII RX Wake on LAN byte mask
1040 union cvmx_asxx_rx_wol_msk {
1042 struct cvmx_asxx_rx_wol_msk_s {
1043 #ifdef __BIG_ENDIAN_BITFIELD
1044 uint64_t msk : 64; /**< Bytes to include in the CRC signature */
1049 struct cvmx_asxx_rx_wol_msk_s cn38xx;
1050 struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
1052 typedef union cvmx_asxx_rx_wol_msk cvmx_asxx_rx_wol_msk_t;
1055 * cvmx_asx#_rx_wol_powok
1057 * ASX_RX_WOL_POWOK = RGMII RX Wake on LAN Power OK
1060 union cvmx_asxx_rx_wol_powok {
1062 struct cvmx_asxx_rx_wol_powok_s {
1063 #ifdef __BIG_ENDIAN_BITFIELD
1064 uint64_t reserved_1_63 : 63;
1065 uint64_t powerok : 1; /**< Power OK */
1067 uint64_t powerok : 1;
1068 uint64_t reserved_1_63 : 63;
1071 struct cvmx_asxx_rx_wol_powok_s cn38xx;
1072 struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
1074 typedef union cvmx_asxx_rx_wol_powok cvmx_asxx_rx_wol_powok_t;
1077 * cvmx_asx#_rx_wol_sig
1079 * ASX_RX_WOL_SIG = RGMII RX Wake on LAN CRC signature
1082 union cvmx_asxx_rx_wol_sig {
1084 struct cvmx_asxx_rx_wol_sig_s {
1085 #ifdef __BIG_ENDIAN_BITFIELD
1086 uint64_t reserved_32_63 : 32;
1087 uint64_t sig : 32; /**< CRC signature */
1090 uint64_t reserved_32_63 : 32;
1093 struct cvmx_asxx_rx_wol_sig_s cn38xx;
1094 struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
1096 typedef union cvmx_asxx_rx_wol_sig cvmx_asxx_rx_wol_sig_t;
1099 * cvmx_asx#_tx_clk_set#
1101 * ASX_TX_CLK_SET = RGMII Clock delay setting
1105 * Setting to place on the open-loop TXC (RGMII transmit clk)
1106 * delay line, which can delay the transmited clock. This
1107 * can be used if the board and/or transmitting device
1108 * has not otherwise delayed the clock.
1110 * A value of SETTING=0 disables the delay line. The delay
1111 * line should be disabled unless the transmitter or board
1112 * does not delay the clock.
1114 * Note that this delay line provides only a coarse control
1115 * over the delay. Generally, it can only reliably provide
1116 * a delay in the range 1.25-2.5ns, which may not be adequate
1117 * for some system applications.
1119 * The open loop delay line selects
1120 * from among a series of tap positions. Each incremental
1121 * tap position adds a delay of 50ps to 135ps per tap, depending
1122 * on the chip, its temperature, and the voltage.
1123 * To achieve from 1.25-2.5ns of delay on the recieved
1124 * clock, a fixed value of SETTING=24 may work.
1125 * For more precision, we recommend the following settings
1126 * based on the chip voltage:
1129 * -----------------------------
1138 union cvmx_asxx_tx_clk_setx {
1140 struct cvmx_asxx_tx_clk_setx_s {
1141 #ifdef __BIG_ENDIAN_BITFIELD
1142 uint64_t reserved_5_63 : 59;
1143 uint64_t setting : 5; /**< Setting to place on the open-loop TXC delay line */
1145 uint64_t setting : 5;
1146 uint64_t reserved_5_63 : 59;
1149 struct cvmx_asxx_tx_clk_setx_s cn30xx;
1150 struct cvmx_asxx_tx_clk_setx_s cn31xx;
1151 struct cvmx_asxx_tx_clk_setx_s cn38xx;
1152 struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
1153 struct cvmx_asxx_tx_clk_setx_s cn50xx;
1154 struct cvmx_asxx_tx_clk_setx_s cn58xx;
1155 struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
1157 typedef union cvmx_asxx_tx_clk_setx cvmx_asxx_tx_clk_setx_t;
1160 * cvmx_asx#_tx_comp_byp
1162 * ASX_TX_COMP_BYP = RGMII Clock delay setting
1165 union cvmx_asxx_tx_comp_byp {
1167 struct cvmx_asxx_tx_comp_byp_s {
1168 #ifdef __BIG_ENDIAN_BITFIELD
1169 uint64_t reserved_0_63 : 64;
1171 uint64_t reserved_0_63 : 64;
1174 struct cvmx_asxx_tx_comp_byp_cn30xx {
1175 #ifdef __BIG_ENDIAN_BITFIELD
1176 uint64_t reserved_9_63 : 55;
1177 uint64_t bypass : 1; /**< Compensation bypass */
1178 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */
1179 uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */
1183 uint64_t bypass : 1;
1184 uint64_t reserved_9_63 : 55;
1187 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
1188 struct cvmx_asxx_tx_comp_byp_cn38xx {
1189 #ifdef __BIG_ENDIAN_BITFIELD
1190 uint64_t reserved_8_63 : 56;
1191 uint64_t pctl : 4; /**< PCTL Compensation Value (see Duke) */
1192 uint64_t nctl : 4; /**< NCTL Compensation Value (see Duke) */
1196 uint64_t reserved_8_63 : 56;
1199 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
1200 struct cvmx_asxx_tx_comp_byp_cn50xx {
1201 #ifdef __BIG_ENDIAN_BITFIELD
1202 uint64_t reserved_17_63 : 47;
1203 uint64_t bypass : 1; /**< Compensation bypass */
1204 uint64_t reserved_13_15 : 3;
1205 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */
1206 uint64_t reserved_5_7 : 3;
1207 uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */
1210 uint64_t reserved_5_7 : 3;
1212 uint64_t reserved_13_15 : 3;
1213 uint64_t bypass : 1;
1214 uint64_t reserved_17_63 : 47;
1217 struct cvmx_asxx_tx_comp_byp_cn58xx {
1218 #ifdef __BIG_ENDIAN_BITFIELD
1219 uint64_t reserved_13_63 : 51;
1220 uint64_t pctl : 5; /**< PCTL Compensation Value (see Duke) */
1221 uint64_t reserved_5_7 : 3;
1222 uint64_t nctl : 5; /**< NCTL Compensation Value (see Duke) */
1225 uint64_t reserved_5_7 : 3;
1227 uint64_t reserved_13_63 : 51;
1230 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
1232 typedef union cvmx_asxx_tx_comp_byp cvmx_asxx_tx_comp_byp_t;
1235 * cvmx_asx#_tx_hi_water#
1237 * ASX_TX_HI_WATER = RGMII TX FIFO Hi WaterMark
1240 union cvmx_asxx_tx_hi_waterx {
1242 struct cvmx_asxx_tx_hi_waterx_s {
1243 #ifdef __BIG_ENDIAN_BITFIELD
1244 uint64_t reserved_4_63 : 60;
1245 uint64_t mark : 4; /**< TX FIFO HiWatermark to stall GMX
1246 Value of 0 maps to 16
1247 Reset value changed from 10 in pass1
1248 Pass1 settings (assuming 125 tclk)
1255 uint64_t reserved_4_63 : 60;
1258 struct cvmx_asxx_tx_hi_waterx_cn30xx {
1259 #ifdef __BIG_ENDIAN_BITFIELD
1260 uint64_t reserved_3_63 : 61;
1261 uint64_t mark : 3; /**< TX FIFO HiWatermark to stall GMX
1262 Value 0 maps to 8. */
1265 uint64_t reserved_3_63 : 61;
1268 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
1269 struct cvmx_asxx_tx_hi_waterx_s cn38xx;
1270 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
1271 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
1272 struct cvmx_asxx_tx_hi_waterx_s cn58xx;
1273 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
1275 typedef union cvmx_asxx_tx_hi_waterx cvmx_asxx_tx_hi_waterx_t;
1278 * cvmx_asx#_tx_prt_en
1280 * ASX_TX_PRT_EN = RGMII Port Enable
1283 union cvmx_asxx_tx_prt_en {
1285 struct cvmx_asxx_tx_prt_en_s {
1286 #ifdef __BIG_ENDIAN_BITFIELD
1287 uint64_t reserved_4_63 : 60;
1288 uint64_t prt_en : 4; /**< Port enable. Must be set for Octane to send
1289 RMGII traffic. When this bit clear on a given
1290 port, then all RGMII cycles will appear as
1291 inter-frame cycles. */
1293 uint64_t prt_en : 4;
1294 uint64_t reserved_4_63 : 60;
1297 struct cvmx_asxx_tx_prt_en_cn30xx {
1298 #ifdef __BIG_ENDIAN_BITFIELD
1299 uint64_t reserved_3_63 : 61;
1300 uint64_t prt_en : 3; /**< Port enable. Must be set for Octane to send
1301 RMGII traffic. When this bit clear on a given
1302 port, then all RGMII cycles will appear as
1303 inter-frame cycles. */
1305 uint64_t prt_en : 3;
1306 uint64_t reserved_3_63 : 61;
1309 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
1310 struct cvmx_asxx_tx_prt_en_s cn38xx;
1311 struct cvmx_asxx_tx_prt_en_s cn38xxp2;
1312 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
1313 struct cvmx_asxx_tx_prt_en_s cn58xx;
1314 struct cvmx_asxx_tx_prt_en_s cn58xxp1;
1316 typedef union cvmx_asxx_tx_prt_en cvmx_asxx_tx_prt_en_t;