1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Inc. nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_CIU_DEFS_H__
53 #define __CVMX_CIU_DEFS_H__
55 #define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull))
56 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
57 #define CVMX_CIU_BLOCK_INT CVMX_CIU_BLOCK_INT_FUNC()
58 static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void)
60 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
61 cvmx_warn("CVMX_CIU_BLOCK_INT not supported on this chip\n");
62 return CVMX_ADD_IO_SEG(0x00010700000007C0ull);
65 #define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull))
67 #define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull))
68 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
69 static inline uint64_t CVMX_CIU_EN2_IOX_INT(unsigned long offset)
72 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
74 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
75 cvmx_warn("CVMX_CIU_EN2_IOX_INT(%lu) is invalid on this chip\n", offset);
76 return CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8;
79 #define CVMX_CIU_EN2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x000107000000A600ull) + ((offset) & 1) * 8)
81 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
82 static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1C(unsigned long offset)
85 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
86 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
87 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
88 cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1C(%lu) is invalid on this chip\n", offset);
89 return CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8;
92 #define CVMX_CIU_EN2_IOX_INT_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CE00ull) + ((offset) & 1) * 8)
94 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
95 static inline uint64_t CVMX_CIU_EN2_IOX_INT_W1S(unsigned long offset)
98 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
99 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
100 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
101 cvmx_warn("CVMX_CIU_EN2_IOX_INT_W1S(%lu) is invalid on this chip\n", offset);
102 return CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8;
105 #define CVMX_CIU_EN2_IOX_INT_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AE00ull) + ((offset) & 1) * 8)
107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
108 static inline uint64_t CVMX_CIU_EN2_PPX_IP2(unsigned long offset)
111 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
112 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
113 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
114 cvmx_warn("CVMX_CIU_EN2_PPX_IP2(%lu) is invalid on this chip\n", offset);
115 return CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8;
118 #define CVMX_CIU_EN2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x000107000000A000ull) + ((offset) & 15) * 8)
120 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
121 static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1C(unsigned long offset)
124 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
125 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
126 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
127 cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1C(%lu) is invalid on this chip\n", offset);
128 return CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8;
131 #define CVMX_CIU_EN2_PPX_IP2_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000C800ull) + ((offset) & 15) * 8)
133 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
134 static inline uint64_t CVMX_CIU_EN2_PPX_IP2_W1S(unsigned long offset)
137 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
138 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
139 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
140 cvmx_warn("CVMX_CIU_EN2_PPX_IP2_W1S(%lu) is invalid on this chip\n", offset);
141 return CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8;
144 #define CVMX_CIU_EN2_PPX_IP2_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000A800ull) + ((offset) & 15) * 8)
146 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
147 static inline uint64_t CVMX_CIU_EN2_PPX_IP3(unsigned long offset)
150 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
152 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
153 cvmx_warn("CVMX_CIU_EN2_PPX_IP3(%lu) is invalid on this chip\n", offset);
154 return CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8;
157 #define CVMX_CIU_EN2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x000107000000A200ull) + ((offset) & 15) * 8)
159 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
160 static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1C(unsigned long offset)
163 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
164 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
165 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
166 cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1C(%lu) is invalid on this chip\n", offset);
167 return CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8;
170 #define CVMX_CIU_EN2_PPX_IP3_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CA00ull) + ((offset) & 15) * 8)
172 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
173 static inline uint64_t CVMX_CIU_EN2_PPX_IP3_W1S(unsigned long offset)
176 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
177 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
178 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
179 cvmx_warn("CVMX_CIU_EN2_PPX_IP3_W1S(%lu) is invalid on this chip\n", offset);
180 return CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8;
183 #define CVMX_CIU_EN2_PPX_IP3_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AA00ull) + ((offset) & 15) * 8)
185 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
186 static inline uint64_t CVMX_CIU_EN2_PPX_IP4(unsigned long offset)
189 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
190 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
191 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
192 cvmx_warn("CVMX_CIU_EN2_PPX_IP4(%lu) is invalid on this chip\n", offset);
193 return CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8;
196 #define CVMX_CIU_EN2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x000107000000A400ull) + ((offset) & 15) * 8)
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
199 static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1C(unsigned long offset)
202 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
203 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
204 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
205 cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1C(%lu) is invalid on this chip\n", offset);
206 return CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8;
209 #define CVMX_CIU_EN2_PPX_IP4_W1C(offset) (CVMX_ADD_IO_SEG(0x000107000000CC00ull) + ((offset) & 15) * 8)
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 static inline uint64_t CVMX_CIU_EN2_PPX_IP4_W1S(unsigned long offset)
215 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
216 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
217 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
218 cvmx_warn("CVMX_CIU_EN2_PPX_IP4_W1S(%lu) is invalid on this chip\n", offset);
219 return CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8;
222 #define CVMX_CIU_EN2_PPX_IP4_W1S(offset) (CVMX_ADD_IO_SEG(0x000107000000AC00ull) + ((offset) & 15) * 8)
224 #define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull))
225 #define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull))
226 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
227 #define CVMX_CIU_INT33_SUM0 CVMX_CIU_INT33_SUM0_FUNC()
228 static inline uint64_t CVMX_CIU_INT33_SUM0_FUNC(void)
230 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
231 cvmx_warn("CVMX_CIU_INT33_SUM0 not supported on this chip\n");
232 return CVMX_ADD_IO_SEG(0x0001070000000110ull);
235 #define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull))
237 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
238 static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset)
241 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
242 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
243 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
244 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
245 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
246 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
247 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
248 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
249 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
250 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
251 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
252 cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
253 return CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16;
256 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16)
258 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
259 static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset)
262 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
265 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
266 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
267 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
268 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
269 cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset);
270 return CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16;
273 #define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16)
275 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
276 static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset)
279 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
280 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
281 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
282 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
283 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
284 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
285 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
286 cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset);
287 return CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16;
290 #define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16)
292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
293 static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset)
296 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
297 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
298 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
299 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
301 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
302 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
303 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
304 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
305 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
306 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
307 cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
308 return CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16;
311 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16)
313 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
314 static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset)
317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
318 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
319 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
320 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
321 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
322 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
323 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
324 cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset);
325 return CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16;
328 #define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16)
330 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
331 static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset)
334 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
335 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
336 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
337 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33)))) ||
338 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))) ||
339 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || ((offset >= 32) && (offset <= 33)))) ||
340 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || ((offset >= 32) && (offset <= 33))))))
341 cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset);
342 return CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16;
345 #define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16)
347 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
348 static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset)
351 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
352 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
353 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
354 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
355 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
357 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
358 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
359 cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset);
360 return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16;
363 #define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16)
365 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
366 static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset)
369 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
370 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
371 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
372 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
373 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
374 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
375 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
376 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset);
377 return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16;
380 #define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16)
382 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
383 static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset)
386 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
387 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
388 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
389 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
390 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
391 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
392 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
393 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset);
394 return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16;
397 #define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16)
399 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
400 static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset)
403 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
404 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
406 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
408 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
409 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
410 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
411 cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset);
412 return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16;
415 #define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16)
417 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
418 static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset)
421 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
422 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
423 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
424 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
425 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
426 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
427 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
428 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset);
429 return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16;
432 #define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16)
434 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
435 static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset)
438 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
439 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
440 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
441 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
442 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
443 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
444 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
445 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset);
446 return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16;
449 #define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16)
451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
452 static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset)
455 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) ||
456 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) ||
457 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) ||
458 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) ||
459 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) ||
460 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) ||
461 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) ||
462 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7) || (offset == 32))) ||
463 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32))) ||
464 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 19) || (offset == 32))) ||
465 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7) || (offset == 32)))))
466 cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset);
467 return CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8;
470 #define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8)
472 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
473 static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset)
476 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
477 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
478 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
479 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
480 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
481 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
482 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
483 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
484 cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset);
485 return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8;
488 #define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8)
490 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
491 #define CVMX_CIU_INT_DBG_SEL CVMX_CIU_INT_DBG_SEL_FUNC()
492 static inline uint64_t CVMX_CIU_INT_DBG_SEL_FUNC(void)
494 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
495 cvmx_warn("CVMX_CIU_INT_DBG_SEL not supported on this chip\n");
496 return CVMX_ADD_IO_SEG(0x00010700000007D0ull);
499 #define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull))
501 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
502 #define CVMX_CIU_INT_SUM1 CVMX_CIU_INT_SUM1_FUNC()
503 static inline uint64_t CVMX_CIU_INT_SUM1_FUNC(void)
505 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
506 cvmx_warn("CVMX_CIU_INT_SUM1 not supported on this chip\n");
507 return CVMX_ADD_IO_SEG(0x0001070000000108ull);
510 #define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull))
512 static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset)
514 switch(cvmx_get_octeon_family()) {
515 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
517 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 0) * 8;
519 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
520 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
521 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
523 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8;
525 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
526 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
528 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 1) * 8;
530 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
531 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
533 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
535 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
537 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
539 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
541 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8;
543 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
545 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 7) * 8;
547 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
549 return CVMX_ADD_IO_SEG(0x0001070100100600ull) + ((offset) & 31) * 8;
552 cvmx_warn("CVMX_CIU_MBOX_CLRX (offset = %lu) not supported on this chip\n", offset);
553 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 3) * 8;
555 static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset)
557 switch(cvmx_get_octeon_family()) {
558 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
560 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 0) * 8;
562 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
563 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
564 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
566 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8;
568 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
569 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
571 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 1) * 8;
573 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
574 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
576 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
578 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
580 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
582 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
584 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8;
586 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
588 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 7) * 8;
590 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
592 return CVMX_ADD_IO_SEG(0x0001070100100400ull) + ((offset) & 31) * 8;
595 cvmx_warn("CVMX_CIU_MBOX_SETX (offset = %lu) not supported on this chip\n", offset);
596 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 3) * 8;
598 #define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull))
599 #define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull))
600 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
601 #define CVMX_CIU_PP_BIST_STAT CVMX_CIU_PP_BIST_STAT_FUNC()
602 static inline uint64_t CVMX_CIU_PP_BIST_STAT_FUNC(void)
604 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
605 cvmx_warn("CVMX_CIU_PP_BIST_STAT not supported on this chip\n");
606 return CVMX_ADD_IO_SEG(0x00010700000007E0ull);
609 #define CVMX_CIU_PP_BIST_STAT (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
611 #define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull))
612 static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
614 switch(cvmx_get_octeon_family()) {
615 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
617 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 0) * 8;
619 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
620 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
621 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
623 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8;
625 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
626 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
628 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 1) * 8;
630 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
631 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
633 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
635 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
637 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
639 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
641 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8;
643 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
645 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 7) * 8;
647 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
649 return CVMX_ADD_IO_SEG(0x0001070100100200ull) + ((offset) & 31) * 8;
652 cvmx_warn("CVMX_CIU_PP_POKEX (offset = %lu) not supported on this chip\n", offset);
653 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 3) * 8;
655 #define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull))
656 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
657 #define CVMX_CIU_QLM0 CVMX_CIU_QLM0_FUNC()
658 static inline uint64_t CVMX_CIU_QLM0_FUNC(void)
660 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
661 cvmx_warn("CVMX_CIU_QLM0 not supported on this chip\n");
662 return CVMX_ADD_IO_SEG(0x0001070000000780ull);
665 #define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull))
667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
668 #define CVMX_CIU_QLM1 CVMX_CIU_QLM1_FUNC()
669 static inline uint64_t CVMX_CIU_QLM1_FUNC(void)
671 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
672 cvmx_warn("CVMX_CIU_QLM1 not supported on this chip\n");
673 return CVMX_ADD_IO_SEG(0x0001070000000788ull);
676 #define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull))
678 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
679 #define CVMX_CIU_QLM2 CVMX_CIU_QLM2_FUNC()
680 static inline uint64_t CVMX_CIU_QLM2_FUNC(void)
682 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
683 cvmx_warn("CVMX_CIU_QLM2 not supported on this chip\n");
684 return CVMX_ADD_IO_SEG(0x0001070000000790ull);
687 #define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull))
689 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
690 #define CVMX_CIU_QLM3 CVMX_CIU_QLM3_FUNC()
691 static inline uint64_t CVMX_CIU_QLM3_FUNC(void)
693 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
694 cvmx_warn("CVMX_CIU_QLM3 not supported on this chip\n");
695 return CVMX_ADD_IO_SEG(0x0001070000000798ull);
698 #define CVMX_CIU_QLM3 (CVMX_ADD_IO_SEG(0x0001070000000798ull))
700 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
701 #define CVMX_CIU_QLM4 CVMX_CIU_QLM4_FUNC()
702 static inline uint64_t CVMX_CIU_QLM4_FUNC(void)
704 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
705 cvmx_warn("CVMX_CIU_QLM4 not supported on this chip\n");
706 return CVMX_ADD_IO_SEG(0x00010700000007A0ull);
709 #define CVMX_CIU_QLM4 (CVMX_ADD_IO_SEG(0x00010700000007A0ull))
711 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
712 #define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC()
713 static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void)
715 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
716 cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n");
717 return CVMX_ADD_IO_SEG(0x0001070000000760ull);
720 #define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull))
722 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
723 #define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC()
724 static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void)
726 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
727 cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n");
728 return CVMX_ADD_IO_SEG(0x0001070000000768ull);
731 #define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull))
733 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
734 #define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC()
735 static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void)
737 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
738 cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n");
739 return CVMX_ADD_IO_SEG(0x0001070000000770ull);
742 #define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull))
744 #define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull))
745 #define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull))
746 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
747 #define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC()
748 static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void)
750 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
751 cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n");
752 return CVMX_ADD_IO_SEG(0x0001070000000758ull);
755 #define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull))
757 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
758 #define CVMX_CIU_SOFT_PRST2 CVMX_CIU_SOFT_PRST2_FUNC()
759 static inline uint64_t CVMX_CIU_SOFT_PRST2_FUNC(void)
761 if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
762 cvmx_warn("CVMX_CIU_SOFT_PRST2 not supported on this chip\n");
763 return CVMX_ADD_IO_SEG(0x00010700000007D8ull);
766 #define CVMX_CIU_SOFT_PRST2 (CVMX_ADD_IO_SEG(0x00010700000007D8ull))
768 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
769 #define CVMX_CIU_SOFT_PRST3 CVMX_CIU_SOFT_PRST3_FUNC()
770 static inline uint64_t CVMX_CIU_SOFT_PRST3_FUNC(void)
772 if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
773 cvmx_warn("CVMX_CIU_SOFT_PRST3 not supported on this chip\n");
774 return CVMX_ADD_IO_SEG(0x00010700000007E0ull);
777 #define CVMX_CIU_SOFT_PRST3 (CVMX_ADD_IO_SEG(0x00010700000007E0ull))
779 #define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull))
780 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
781 static inline uint64_t CVMX_CIU_SUM1_IOX_INT(unsigned long offset)
784 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
785 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
786 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
787 cvmx_warn("CVMX_CIU_SUM1_IOX_INT(%lu) is invalid on this chip\n", offset);
788 return CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8;
791 #define CVMX_CIU_SUM1_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008600ull) + ((offset) & 1) * 8)
793 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
794 static inline uint64_t CVMX_CIU_SUM1_PPX_IP2(unsigned long offset)
797 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
798 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
799 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
800 cvmx_warn("CVMX_CIU_SUM1_PPX_IP2(%lu) is invalid on this chip\n", offset);
801 return CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8;
804 #define CVMX_CIU_SUM1_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008000ull) + ((offset) & 15) * 8)
806 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
807 static inline uint64_t CVMX_CIU_SUM1_PPX_IP3(unsigned long offset)
810 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
811 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
812 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
813 cvmx_warn("CVMX_CIU_SUM1_PPX_IP3(%lu) is invalid on this chip\n", offset);
814 return CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8;
817 #define CVMX_CIU_SUM1_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008200ull) + ((offset) & 15) * 8)
819 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
820 static inline uint64_t CVMX_CIU_SUM1_PPX_IP4(unsigned long offset)
823 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
824 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
825 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
826 cvmx_warn("CVMX_CIU_SUM1_PPX_IP4(%lu) is invalid on this chip\n", offset);
827 return CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8;
830 #define CVMX_CIU_SUM1_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008400ull) + ((offset) & 15) * 8)
832 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
833 static inline uint64_t CVMX_CIU_SUM2_IOX_INT(unsigned long offset)
836 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
837 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
838 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
839 cvmx_warn("CVMX_CIU_SUM2_IOX_INT(%lu) is invalid on this chip\n", offset);
840 return CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8;
843 #define CVMX_CIU_SUM2_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070000008E00ull) + ((offset) & 1) * 8)
845 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
846 static inline uint64_t CVMX_CIU_SUM2_PPX_IP2(unsigned long offset)
849 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
850 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
851 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
852 cvmx_warn("CVMX_CIU_SUM2_PPX_IP2(%lu) is invalid on this chip\n", offset);
853 return CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8;
856 #define CVMX_CIU_SUM2_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070000008800ull) + ((offset) & 15) * 8)
858 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
859 static inline uint64_t CVMX_CIU_SUM2_PPX_IP3(unsigned long offset)
862 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
863 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
864 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
865 cvmx_warn("CVMX_CIU_SUM2_PPX_IP3(%lu) is invalid on this chip\n", offset);
866 return CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8;
869 #define CVMX_CIU_SUM2_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070000008A00ull) + ((offset) & 15) * 8)
871 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
872 static inline uint64_t CVMX_CIU_SUM2_PPX_IP4(unsigned long offset)
875 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
876 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
877 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
878 cvmx_warn("CVMX_CIU_SUM2_PPX_IP4(%lu) is invalid on this chip\n", offset);
879 return CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8;
882 #define CVMX_CIU_SUM2_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070000008C00ull) + ((offset) & 15) * 8)
884 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
885 static inline uint64_t CVMX_CIU_TIMX(unsigned long offset)
888 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) ||
889 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) ||
890 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) ||
891 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
892 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
893 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
894 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
895 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 9))) ||
896 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
897 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
898 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
899 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 9)))))
900 cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset);
901 return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8;
904 #define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 15) * 8)
906 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
907 #define CVMX_CIU_TIM_MULTI_CAST CVMX_CIU_TIM_MULTI_CAST_FUNC()
908 static inline uint64_t CVMX_CIU_TIM_MULTI_CAST_FUNC(void)
910 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
911 cvmx_warn("CVMX_CIU_TIM_MULTI_CAST not supported on this chip\n");
912 return CVMX_ADD_IO_SEG(0x000107000000C200ull);
915 #define CVMX_CIU_TIM_MULTI_CAST (CVMX_ADD_IO_SEG(0x000107000000C200ull))
917 static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
919 switch(cvmx_get_octeon_family()) {
920 case OCTEON_CN30XX & OCTEON_FAMILY_MASK:
922 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 0) * 8;
924 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
925 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
926 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
928 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8;
930 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
931 case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
933 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 1) * 8;
935 case OCTEON_CN38XX & OCTEON_FAMILY_MASK:
936 case OCTEON_CN58XX & OCTEON_FAMILY_MASK:
938 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
940 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
942 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
944 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
946 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8;
948 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
950 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 7) * 8;
952 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
954 return CVMX_ADD_IO_SEG(0x0001070100100000ull) + ((offset) & 31) * 8;
957 cvmx_warn("CVMX_CIU_WDOGX (offset = %lu) not supported on this chip\n", offset);
958 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 3) * 8;
964 union cvmx_ciu_bist {
966 struct cvmx_ciu_bist_s {
967 #ifdef __BIG_ENDIAN_BITFIELD
968 uint64_t reserved_7_63 : 57;
969 uint64_t bist : 7; /**< BIST Results.
970 HW sets a bit in BIST for for memory that fails
974 uint64_t reserved_7_63 : 57;
977 struct cvmx_ciu_bist_cn30xx {
978 #ifdef __BIG_ENDIAN_BITFIELD
979 uint64_t reserved_4_63 : 60;
980 uint64_t bist : 4; /**< BIST Results.
981 HW sets a bit in BIST for for memory that fails
985 uint64_t reserved_4_63 : 60;
988 struct cvmx_ciu_bist_cn30xx cn31xx;
989 struct cvmx_ciu_bist_cn30xx cn38xx;
990 struct cvmx_ciu_bist_cn30xx cn38xxp2;
991 struct cvmx_ciu_bist_cn50xx {
992 #ifdef __BIG_ENDIAN_BITFIELD
993 uint64_t reserved_2_63 : 62;
994 uint64_t bist : 2; /**< BIST Results.
995 HW sets a bit in BIST for for memory that fails
999 uint64_t reserved_2_63 : 62;
1002 struct cvmx_ciu_bist_cn52xx {
1003 #ifdef __BIG_ENDIAN_BITFIELD
1004 uint64_t reserved_3_63 : 61;
1005 uint64_t bist : 3; /**< BIST Results.
1006 HW sets a bit in BIST for for memory that fails
1010 uint64_t reserved_3_63 : 61;
1013 struct cvmx_ciu_bist_cn52xx cn52xxp1;
1014 struct cvmx_ciu_bist_cn30xx cn56xx;
1015 struct cvmx_ciu_bist_cn30xx cn56xxp1;
1016 struct cvmx_ciu_bist_cn30xx cn58xx;
1017 struct cvmx_ciu_bist_cn30xx cn58xxp1;
1018 struct cvmx_ciu_bist_cn61xx {
1019 #ifdef __BIG_ENDIAN_BITFIELD
1020 uint64_t reserved_6_63 : 58;
1021 uint64_t bist : 6; /**< BIST Results.
1022 HW sets a bit in BIST for for memory that fails
1026 uint64_t reserved_6_63 : 58;
1029 struct cvmx_ciu_bist_cn63xx {
1030 #ifdef __BIG_ENDIAN_BITFIELD
1031 uint64_t reserved_5_63 : 59;
1032 uint64_t bist : 5; /**< BIST Results.
1033 HW sets a bit in BIST for for memory that fails
1037 uint64_t reserved_5_63 : 59;
1040 struct cvmx_ciu_bist_cn63xx cn63xxp1;
1041 struct cvmx_ciu_bist_cn61xx cn66xx;
1042 struct cvmx_ciu_bist_s cn68xx;
1043 struct cvmx_ciu_bist_s cn68xxp1;
1044 struct cvmx_ciu_bist_cn61xx cnf71xx;
1046 typedef union cvmx_ciu_bist cvmx_ciu_bist_t;
1049 * cvmx_ciu_block_int
1051 * CIU_BLOCK_INT = CIU Blocks Interrupt
1053 * The interrupt lines from the various chip blocks.
1055 union cvmx_ciu_block_int {
1057 struct cvmx_ciu_block_int_s {
1058 #ifdef __BIG_ENDIAN_BITFIELD
1059 uint64_t reserved_62_63 : 2;
1060 uint64_t srio3 : 1; /**< SRIO3 interrupt
1061 See SRIO3_INT_REG, SRIO3_INT2_REG */
1062 uint64_t srio2 : 1; /**< SRIO2 interrupt
1063 See SRIO2_INT_REG, SRIO2_INT2_REG */
1064 uint64_t reserved_43_59 : 17;
1065 uint64_t ptp : 1; /**< PTP interrupt
1066 See CIU_INT_SUM1[PTP] */
1067 uint64_t dpi : 1; /**< DPI interrupt
1069 uint64_t dfm : 1; /**< DFM interrupt
1071 uint64_t reserved_34_39 : 6;
1072 uint64_t srio1 : 1; /**< SRIO1 interrupt
1073 See SRIO1_INT_REG */
1074 uint64_t srio0 : 1; /**< SRIO0 interrupt
1075 See SRIO0_INT_REG, SRIO0_INT2_REG */
1076 uint64_t reserved_31_31 : 1;
1077 uint64_t iob : 1; /**< IOB interrupt
1079 uint64_t reserved_29_29 : 1;
1080 uint64_t agl : 1; /**< AGL interrupt
1081 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
1082 uint64_t reserved_27_27 : 1;
1083 uint64_t pem1 : 1; /**< PEM1 interrupt
1084 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
1085 uint64_t pem0 : 1; /**< PEM0 interrupt
1086 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
1087 uint64_t reserved_24_24 : 1;
1088 uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */
1089 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
1090 uint64_t reserved_21_21 : 1;
1091 uint64_t pip : 1; /**< PIP interrupt
1093 uint64_t reserved_18_19 : 2;
1094 uint64_t lmc0 : 1; /**< LMC0 interrupt
1096 uint64_t l2c : 1; /**< L2C interrupt
1098 uint64_t reserved_15_15 : 1;
1099 uint64_t rad : 1; /**< RAD interrupt
1100 See RAD_REG_ERROR */
1101 uint64_t usb : 1; /**< USB UCTL0 interrupt
1102 See UCTL0_INT_REG */
1103 uint64_t pow : 1; /**< POW err interrupt
1105 uint64_t tim : 1; /**< TIM interrupt
1106 See TIM_REG_ERROR */
1107 uint64_t pko : 1; /**< PKO interrupt
1108 See PKO_REG_ERROR */
1109 uint64_t ipd : 1; /**< IPD interrupt
1111 uint64_t reserved_8_8 : 1;
1112 uint64_t zip : 1; /**< ZIP interrupt
1114 uint64_t dfa : 1; /**< DFA interrupt
1116 uint64_t fpa : 1; /**< FPA interrupt
1118 uint64_t key : 1; /**< KEY interrupt
1120 uint64_t sli : 1; /**< SLI interrupt
1121 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
1122 uint64_t gmx1 : 1; /**< GMX1 interrupt
1123 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
1124 uint64_t gmx0 : 1; /**< GMX0 interrupt
1125 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
1126 uint64_t mio : 1; /**< MIO boot interrupt
1137 uint64_t reserved_8_8 : 1;
1144 uint64_t reserved_15_15 : 1;
1147 uint64_t reserved_18_19 : 2;
1149 uint64_t reserved_21_21 : 1;
1150 uint64_t asxpcs0 : 1;
1151 uint64_t asxpcs1 : 1;
1152 uint64_t reserved_24_24 : 1;
1155 uint64_t reserved_27_27 : 1;
1157 uint64_t reserved_29_29 : 1;
1159 uint64_t reserved_31_31 : 1;
1162 uint64_t reserved_34_39 : 6;
1166 uint64_t reserved_43_59 : 17;
1169 uint64_t reserved_62_63 : 2;
1172 struct cvmx_ciu_block_int_cn61xx {
1173 #ifdef __BIG_ENDIAN_BITFIELD
1174 uint64_t reserved_43_63 : 21;
1175 uint64_t ptp : 1; /**< PTP interrupt
1176 See CIU_INT_SUM1[PTP] */
1177 uint64_t dpi : 1; /**< DPI interrupt
1179 uint64_t reserved_31_40 : 10;
1180 uint64_t iob : 1; /**< IOB interrupt
1182 uint64_t reserved_29_29 : 1;
1183 uint64_t agl : 1; /**< AGL interrupt
1184 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
1185 uint64_t reserved_27_27 : 1;
1186 uint64_t pem1 : 1; /**< PEM1 interrupt
1187 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
1188 uint64_t pem0 : 1; /**< PEM0 interrupt
1189 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
1190 uint64_t reserved_24_24 : 1;
1191 uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */
1192 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
1193 uint64_t reserved_21_21 : 1;
1194 uint64_t pip : 1; /**< PIP interrupt
1196 uint64_t reserved_18_19 : 2;
1197 uint64_t lmc0 : 1; /**< LMC0 interrupt
1199 uint64_t l2c : 1; /**< L2C interrupt
1201 uint64_t reserved_15_15 : 1;
1202 uint64_t rad : 1; /**< RAD interrupt
1203 See RAD_REG_ERROR */
1204 uint64_t usb : 1; /**< USB UCTL0 interrupt
1205 See UCTL0_INT_REG */
1206 uint64_t pow : 1; /**< POW err interrupt
1208 uint64_t tim : 1; /**< TIM interrupt
1209 See TIM_REG_ERROR */
1210 uint64_t pko : 1; /**< PKO interrupt
1211 See PKO_REG_ERROR */
1212 uint64_t ipd : 1; /**< IPD interrupt
1214 uint64_t reserved_8_8 : 1;
1215 uint64_t zip : 1; /**< ZIP interrupt
1217 uint64_t dfa : 1; /**< DFA interrupt
1219 uint64_t fpa : 1; /**< FPA interrupt
1221 uint64_t key : 1; /**< KEY interrupt
1223 uint64_t sli : 1; /**< SLI interrupt
1224 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
1225 uint64_t gmx1 : 1; /**< GMX1 interrupt
1226 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
1227 uint64_t gmx0 : 1; /**< GMX0 interrupt
1228 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
1229 uint64_t mio : 1; /**< MIO boot interrupt
1240 uint64_t reserved_8_8 : 1;
1247 uint64_t reserved_15_15 : 1;
1250 uint64_t reserved_18_19 : 2;
1252 uint64_t reserved_21_21 : 1;
1253 uint64_t asxpcs0 : 1;
1254 uint64_t asxpcs1 : 1;
1255 uint64_t reserved_24_24 : 1;
1258 uint64_t reserved_27_27 : 1;
1260 uint64_t reserved_29_29 : 1;
1262 uint64_t reserved_31_40 : 10;
1265 uint64_t reserved_43_63 : 21;
1268 struct cvmx_ciu_block_int_cn63xx {
1269 #ifdef __BIG_ENDIAN_BITFIELD
1270 uint64_t reserved_43_63 : 21;
1271 uint64_t ptp : 1; /**< PTP interrupt
1272 See CIU_INT_SUM1[PTP] */
1273 uint64_t dpi : 1; /**< DPI interrupt
1275 uint64_t dfm : 1; /**< DFM interrupt
1277 uint64_t reserved_34_39 : 6;
1278 uint64_t srio1 : 1; /**< SRIO1 interrupt
1279 See SRIO1_INT_REG, SRIO1_INT2_REG */
1280 uint64_t srio0 : 1; /**< SRIO0 interrupt
1281 See SRIO0_INT_REG, SRIO0_INT2_REG */
1282 uint64_t reserved_31_31 : 1;
1283 uint64_t iob : 1; /**< IOB interrupt
1285 uint64_t reserved_29_29 : 1;
1286 uint64_t agl : 1; /**< AGL interrupt
1287 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
1288 uint64_t reserved_27_27 : 1;
1289 uint64_t pem1 : 1; /**< PEM1 interrupt
1290 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
1291 uint64_t pem0 : 1; /**< PEM0 interrupt
1292 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
1293 uint64_t reserved_23_24 : 2;
1294 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
1295 uint64_t reserved_21_21 : 1;
1296 uint64_t pip : 1; /**< PIP interrupt
1298 uint64_t reserved_18_19 : 2;
1299 uint64_t lmc0 : 1; /**< LMC0 interrupt
1301 uint64_t l2c : 1; /**< L2C interrupt
1303 uint64_t reserved_15_15 : 1;
1304 uint64_t rad : 1; /**< RAD interrupt
1305 See RAD_REG_ERROR */
1306 uint64_t usb : 1; /**< USB UCTL0 interrupt
1307 See UCTL0_INT_REG */
1308 uint64_t pow : 1; /**< POW err interrupt
1310 uint64_t tim : 1; /**< TIM interrupt
1311 See TIM_REG_ERROR */
1312 uint64_t pko : 1; /**< PKO interrupt
1313 See PKO_REG_ERROR */
1314 uint64_t ipd : 1; /**< IPD interrupt
1316 uint64_t reserved_8_8 : 1;
1317 uint64_t zip : 1; /**< ZIP interrupt
1319 uint64_t dfa : 1; /**< DFA interrupt
1321 uint64_t fpa : 1; /**< FPA interrupt
1323 uint64_t key : 1; /**< KEY interrupt
1325 uint64_t sli : 1; /**< SLI interrupt
1326 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
1327 uint64_t reserved_2_2 : 1;
1328 uint64_t gmx0 : 1; /**< GMX0 interrupt
1329 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
1330 uint64_t mio : 1; /**< MIO boot interrupt
1335 uint64_t reserved_2_2 : 1;
1341 uint64_t reserved_8_8 : 1;
1348 uint64_t reserved_15_15 : 1;
1351 uint64_t reserved_18_19 : 2;
1353 uint64_t reserved_21_21 : 1;
1354 uint64_t asxpcs0 : 1;
1355 uint64_t reserved_23_24 : 2;
1358 uint64_t reserved_27_27 : 1;
1360 uint64_t reserved_29_29 : 1;
1362 uint64_t reserved_31_31 : 1;
1365 uint64_t reserved_34_39 : 6;
1369 uint64_t reserved_43_63 : 21;
1372 struct cvmx_ciu_block_int_cn63xx cn63xxp1;
1373 struct cvmx_ciu_block_int_cn66xx {
1374 #ifdef __BIG_ENDIAN_BITFIELD
1375 uint64_t reserved_62_63 : 2;
1376 uint64_t srio3 : 1; /**< SRIO3 interrupt
1377 See SRIO3_INT_REG, SRIO3_INT2_REG */
1378 uint64_t srio2 : 1; /**< SRIO2 interrupt
1379 See SRIO2_INT_REG, SRIO2_INT2_REG */
1380 uint64_t reserved_43_59 : 17;
1381 uint64_t ptp : 1; /**< PTP interrupt
1382 See CIU_INT_SUM1[PTP] */
1383 uint64_t dpi : 1; /**< DPI interrupt
1385 uint64_t dfm : 1; /**< DFM interrupt
1387 uint64_t reserved_33_39 : 7;
1388 uint64_t srio0 : 1; /**< SRIO0 interrupt
1389 See SRIO0_INT_REG, SRIO0_INT2_REG */
1390 uint64_t reserved_31_31 : 1;
1391 uint64_t iob : 1; /**< IOB interrupt
1393 uint64_t reserved_29_29 : 1;
1394 uint64_t agl : 1; /**< AGL interrupt
1395 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
1396 uint64_t reserved_27_27 : 1;
1397 uint64_t pem1 : 1; /**< PEM1 interrupt
1398 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
1399 uint64_t pem0 : 1; /**< PEM0 interrupt
1400 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
1401 uint64_t reserved_24_24 : 1;
1402 uint64_t asxpcs1 : 1; /**< See PCS1_INT*_REG, PCSX1_INT_REG */
1403 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
1404 uint64_t reserved_21_21 : 1;
1405 uint64_t pip : 1; /**< PIP interrupt
1407 uint64_t reserved_18_19 : 2;
1408 uint64_t lmc0 : 1; /**< LMC0 interrupt
1410 uint64_t l2c : 1; /**< L2C interrupt
1412 uint64_t reserved_15_15 : 1;
1413 uint64_t rad : 1; /**< RAD interrupt
1414 See RAD_REG_ERROR */
1415 uint64_t usb : 1; /**< USB UCTL0 interrupt
1416 See UCTL0_INT_REG */
1417 uint64_t pow : 1; /**< POW err interrupt
1419 uint64_t tim : 1; /**< TIM interrupt
1420 See TIM_REG_ERROR */
1421 uint64_t pko : 1; /**< PKO interrupt
1422 See PKO_REG_ERROR */
1423 uint64_t ipd : 1; /**< IPD interrupt
1425 uint64_t reserved_8_8 : 1;
1426 uint64_t zip : 1; /**< ZIP interrupt
1428 uint64_t dfa : 1; /**< DFA interrupt
1430 uint64_t fpa : 1; /**< FPA interrupt
1432 uint64_t key : 1; /**< KEY interrupt
1434 uint64_t sli : 1; /**< SLI interrupt
1435 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
1436 uint64_t gmx1 : 1; /**< GMX1 interrupt
1437 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG */
1438 uint64_t gmx0 : 1; /**< GMX0 interrupt
1439 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
1440 uint64_t mio : 1; /**< MIO boot interrupt
1451 uint64_t reserved_8_8 : 1;
1458 uint64_t reserved_15_15 : 1;
1461 uint64_t reserved_18_19 : 2;
1463 uint64_t reserved_21_21 : 1;
1464 uint64_t asxpcs0 : 1;
1465 uint64_t asxpcs1 : 1;
1466 uint64_t reserved_24_24 : 1;
1469 uint64_t reserved_27_27 : 1;
1471 uint64_t reserved_29_29 : 1;
1473 uint64_t reserved_31_31 : 1;
1475 uint64_t reserved_33_39 : 7;
1479 uint64_t reserved_43_59 : 17;
1482 uint64_t reserved_62_63 : 2;
1485 struct cvmx_ciu_block_int_cnf71xx {
1486 #ifdef __BIG_ENDIAN_BITFIELD
1487 uint64_t reserved_43_63 : 21;
1488 uint64_t ptp : 1; /**< PTP interrupt
1489 See CIU_INT_SUM1[PTP] */
1490 uint64_t dpi : 1; /**< DPI interrupt
1492 uint64_t reserved_31_40 : 10;
1493 uint64_t iob : 1; /**< IOB interrupt
1495 uint64_t reserved_27_29 : 3;
1496 uint64_t pem1 : 1; /**< PEM1 interrupt
1497 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
1498 uint64_t pem0 : 1; /**< PEM0 interrupt
1499 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
1500 uint64_t reserved_23_24 : 2;
1501 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */
1502 uint64_t reserved_21_21 : 1;
1503 uint64_t pip : 1; /**< PIP interrupt
1505 uint64_t reserved_18_19 : 2;
1506 uint64_t lmc0 : 1; /**< LMC0 interrupt
1508 uint64_t l2c : 1; /**< L2C interrupt
1510 uint64_t reserved_15_15 : 1;
1511 uint64_t rad : 1; /**< RAD interrupt
1512 See RAD_REG_ERROR */
1513 uint64_t usb : 1; /**< USB UCTL0 interrupt
1514 See UCTL0_INT_REG */
1515 uint64_t pow : 1; /**< POW err interrupt
1517 uint64_t tim : 1; /**< TIM interrupt
1518 See TIM_REG_ERROR */
1519 uint64_t pko : 1; /**< PKO interrupt
1520 See PKO_REG_ERROR */
1521 uint64_t ipd : 1; /**< IPD interrupt
1523 uint64_t reserved_6_8 : 3;
1524 uint64_t fpa : 1; /**< FPA interrupt
1526 uint64_t key : 1; /**< KEY interrupt
1528 uint64_t sli : 1; /**< SLI interrupt
1529 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
1530 uint64_t reserved_2_2 : 1;
1531 uint64_t gmx0 : 1; /**< GMX0 interrupt
1532 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */
1533 uint64_t mio : 1; /**< MIO boot interrupt
1538 uint64_t reserved_2_2 : 1;
1542 uint64_t reserved_6_8 : 3;
1549 uint64_t reserved_15_15 : 1;
1552 uint64_t reserved_18_19 : 2;
1554 uint64_t reserved_21_21 : 1;
1555 uint64_t asxpcs0 : 1;
1556 uint64_t reserved_23_24 : 2;
1559 uint64_t reserved_27_29 : 3;
1561 uint64_t reserved_31_40 : 10;
1564 uint64_t reserved_43_63 : 21;
1568 typedef union cvmx_ciu_block_int cvmx_ciu_block_int_t;
1573 union cvmx_ciu_dint {
1575 struct cvmx_ciu_dint_s {
1576 #ifdef __BIG_ENDIAN_BITFIELD
1577 uint64_t reserved_32_63 : 32;
1578 uint64_t dint : 32; /**< Send DINT pulse to PP vector */
1581 uint64_t reserved_32_63 : 32;
1584 struct cvmx_ciu_dint_cn30xx {
1585 #ifdef __BIG_ENDIAN_BITFIELD
1586 uint64_t reserved_1_63 : 63;
1587 uint64_t dint : 1; /**< Send DINT pulse to PP vector */
1590 uint64_t reserved_1_63 : 63;
1593 struct cvmx_ciu_dint_cn31xx {
1594 #ifdef __BIG_ENDIAN_BITFIELD
1595 uint64_t reserved_2_63 : 62;
1596 uint64_t dint : 2; /**< Send DINT pulse to PP vector */
1599 uint64_t reserved_2_63 : 62;
1602 struct cvmx_ciu_dint_cn38xx {
1603 #ifdef __BIG_ENDIAN_BITFIELD
1604 uint64_t reserved_16_63 : 48;
1605 uint64_t dint : 16; /**< Send DINT pulse to PP vector */
1608 uint64_t reserved_16_63 : 48;
1611 struct cvmx_ciu_dint_cn38xx cn38xxp2;
1612 struct cvmx_ciu_dint_cn31xx cn50xx;
1613 struct cvmx_ciu_dint_cn52xx {
1614 #ifdef __BIG_ENDIAN_BITFIELD
1615 uint64_t reserved_4_63 : 60;
1616 uint64_t dint : 4; /**< Send DINT pulse to PP vector */
1619 uint64_t reserved_4_63 : 60;
1622 struct cvmx_ciu_dint_cn52xx cn52xxp1;
1623 struct cvmx_ciu_dint_cn56xx {
1624 #ifdef __BIG_ENDIAN_BITFIELD
1625 uint64_t reserved_12_63 : 52;
1626 uint64_t dint : 12; /**< Send DINT pulse to PP vector */
1629 uint64_t reserved_12_63 : 52;
1632 struct cvmx_ciu_dint_cn56xx cn56xxp1;
1633 struct cvmx_ciu_dint_cn38xx cn58xx;
1634 struct cvmx_ciu_dint_cn38xx cn58xxp1;
1635 struct cvmx_ciu_dint_cn52xx cn61xx;
1636 struct cvmx_ciu_dint_cn63xx {
1637 #ifdef __BIG_ENDIAN_BITFIELD
1638 uint64_t reserved_6_63 : 58;
1639 uint64_t dint : 6; /**< Send DINT pulse to PP vector */
1642 uint64_t reserved_6_63 : 58;
1645 struct cvmx_ciu_dint_cn63xx cn63xxp1;
1646 struct cvmx_ciu_dint_cn66xx {
1647 #ifdef __BIG_ENDIAN_BITFIELD
1648 uint64_t reserved_10_63 : 54;
1649 uint64_t dint : 10; /**< Send DINT pulse to PP vector */
1652 uint64_t reserved_10_63 : 54;
1655 struct cvmx_ciu_dint_s cn68xx;
1656 struct cvmx_ciu_dint_s cn68xxp1;
1657 struct cvmx_ciu_dint_cn52xx cnf71xx;
1659 typedef union cvmx_ciu_dint cvmx_ciu_dint_t;
1662 * cvmx_ciu_en2_io#_int
1665 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
1668 union cvmx_ciu_en2_iox_int {
1670 struct cvmx_ciu_en2_iox_int_s {
1671 #ifdef __BIG_ENDIAN_BITFIELD
1672 uint64_t reserved_15_63 : 49;
1673 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
1674 uint64_t eoi : 1; /**< EOI rsl interrupt enable */
1675 uint64_t reserved_10_11 : 2;
1676 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
1677 uint64_t reserved_0_3 : 4;
1679 uint64_t reserved_0_3 : 4;
1681 uint64_t reserved_10_11 : 2;
1684 uint64_t reserved_15_63 : 49;
1687 struct cvmx_ciu_en2_iox_int_cn61xx {
1688 #ifdef __BIG_ENDIAN_BITFIELD
1689 uint64_t reserved_10_63 : 54;
1690 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
1691 uint64_t reserved_0_3 : 4;
1693 uint64_t reserved_0_3 : 4;
1695 uint64_t reserved_10_63 : 54;
1698 struct cvmx_ciu_en2_iox_int_cn61xx cn66xx;
1699 struct cvmx_ciu_en2_iox_int_s cnf71xx;
1701 typedef union cvmx_ciu_en2_iox_int cvmx_ciu_en2_iox_int_t;
1704 * cvmx_ciu_en2_io#_int_w1c
1707 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
1708 * CIU_EN2_PP(IO)X_IPx(INT) value.
1710 union cvmx_ciu_en2_iox_int_w1c {
1712 struct cvmx_ciu_en2_iox_int_w1c_s {
1713 #ifdef __BIG_ENDIAN_BITFIELD
1714 uint64_t reserved_15_63 : 49;
1715 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
1716 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
1717 uint64_t reserved_10_11 : 2;
1718 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
1719 uint64_t reserved_0_3 : 4;
1721 uint64_t reserved_0_3 : 4;
1723 uint64_t reserved_10_11 : 2;
1726 uint64_t reserved_15_63 : 49;
1729 struct cvmx_ciu_en2_iox_int_w1c_cn61xx {
1730 #ifdef __BIG_ENDIAN_BITFIELD
1731 uint64_t reserved_10_63 : 54;
1732 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
1733 uint64_t reserved_0_3 : 4;
1735 uint64_t reserved_0_3 : 4;
1737 uint64_t reserved_10_63 : 54;
1740 struct cvmx_ciu_en2_iox_int_w1c_cn61xx cn66xx;
1741 struct cvmx_ciu_en2_iox_int_w1c_s cnf71xx;
1743 typedef union cvmx_ciu_en2_iox_int_w1c cvmx_ciu_en2_iox_int_w1c_t;
1746 * cvmx_ciu_en2_io#_int_w1s
1749 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
1750 * CIU_EN2_PP(IO)X_IPx(INT) value.
1752 union cvmx_ciu_en2_iox_int_w1s {
1754 struct cvmx_ciu_en2_iox_int_w1s_s {
1755 #ifdef __BIG_ENDIAN_BITFIELD
1756 uint64_t reserved_15_63 : 49;
1757 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
1758 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
1759 uint64_t reserved_10_11 : 2;
1760 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
1761 uint64_t reserved_0_3 : 4;
1763 uint64_t reserved_0_3 : 4;
1765 uint64_t reserved_10_11 : 2;
1768 uint64_t reserved_15_63 : 49;
1771 struct cvmx_ciu_en2_iox_int_w1s_cn61xx {
1772 #ifdef __BIG_ENDIAN_BITFIELD
1773 uint64_t reserved_10_63 : 54;
1774 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
1775 uint64_t reserved_0_3 : 4;
1777 uint64_t reserved_0_3 : 4;
1779 uint64_t reserved_10_63 : 54;
1782 struct cvmx_ciu_en2_iox_int_w1s_cn61xx cn66xx;
1783 struct cvmx_ciu_en2_iox_int_w1s_s cnf71xx;
1785 typedef union cvmx_ciu_en2_iox_int_w1s cvmx_ciu_en2_iox_int_w1s_t;
1788 * cvmx_ciu_en2_pp#_ip2
1791 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
1794 union cvmx_ciu_en2_ppx_ip2 {
1796 struct cvmx_ciu_en2_ppx_ip2_s {
1797 #ifdef __BIG_ENDIAN_BITFIELD
1798 uint64_t reserved_15_63 : 49;
1799 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
1800 uint64_t eoi : 1; /**< EOI rsl interrupt enable */
1801 uint64_t reserved_10_11 : 2;
1802 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
1803 uint64_t reserved_0_3 : 4;
1805 uint64_t reserved_0_3 : 4;
1807 uint64_t reserved_10_11 : 2;
1810 uint64_t reserved_15_63 : 49;
1813 struct cvmx_ciu_en2_ppx_ip2_cn61xx {
1814 #ifdef __BIG_ENDIAN_BITFIELD
1815 uint64_t reserved_10_63 : 54;
1816 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
1817 uint64_t reserved_0_3 : 4;
1819 uint64_t reserved_0_3 : 4;
1821 uint64_t reserved_10_63 : 54;
1824 struct cvmx_ciu_en2_ppx_ip2_cn61xx cn66xx;
1825 struct cvmx_ciu_en2_ppx_ip2_s cnf71xx;
1827 typedef union cvmx_ciu_en2_ppx_ip2 cvmx_ciu_en2_ppx_ip2_t;
1830 * cvmx_ciu_en2_pp#_ip2_w1c
1833 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
1834 * CIU_EN2_PP(IO)X_IPx(INT) value.
1836 union cvmx_ciu_en2_ppx_ip2_w1c {
1838 struct cvmx_ciu_en2_ppx_ip2_w1c_s {
1839 #ifdef __BIG_ENDIAN_BITFIELD
1840 uint64_t reserved_15_63 : 49;
1841 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
1842 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
1843 uint64_t reserved_10_11 : 2;
1844 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
1845 uint64_t reserved_0_3 : 4;
1847 uint64_t reserved_0_3 : 4;
1849 uint64_t reserved_10_11 : 2;
1852 uint64_t reserved_15_63 : 49;
1855 struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx {
1856 #ifdef __BIG_ENDIAN_BITFIELD
1857 uint64_t reserved_10_63 : 54;
1858 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
1859 uint64_t reserved_0_3 : 4;
1861 uint64_t reserved_0_3 : 4;
1863 uint64_t reserved_10_63 : 54;
1866 struct cvmx_ciu_en2_ppx_ip2_w1c_cn61xx cn66xx;
1867 struct cvmx_ciu_en2_ppx_ip2_w1c_s cnf71xx;
1869 typedef union cvmx_ciu_en2_ppx_ip2_w1c cvmx_ciu_en2_ppx_ip2_w1c_t;
1872 * cvmx_ciu_en2_pp#_ip2_w1s
1875 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
1876 * CIU_EN2_PP(IO)X_IPx(INT) value.
1878 union cvmx_ciu_en2_ppx_ip2_w1s {
1880 struct cvmx_ciu_en2_ppx_ip2_w1s_s {
1881 #ifdef __BIG_ENDIAN_BITFIELD
1882 uint64_t reserved_15_63 : 49;
1883 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
1884 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
1885 uint64_t reserved_10_11 : 2;
1886 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
1887 uint64_t reserved_0_3 : 4;
1889 uint64_t reserved_0_3 : 4;
1891 uint64_t reserved_10_11 : 2;
1894 uint64_t reserved_15_63 : 49;
1897 struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx {
1898 #ifdef __BIG_ENDIAN_BITFIELD
1899 uint64_t reserved_10_63 : 54;
1900 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
1901 uint64_t reserved_0_3 : 4;
1903 uint64_t reserved_0_3 : 4;
1905 uint64_t reserved_10_63 : 54;
1908 struct cvmx_ciu_en2_ppx_ip2_w1s_cn61xx cn66xx;
1909 struct cvmx_ciu_en2_ppx_ip2_w1s_s cnf71xx;
1911 typedef union cvmx_ciu_en2_ppx_ip2_w1s cvmx_ciu_en2_ppx_ip2_w1s_t;
1914 * cvmx_ciu_en2_pp#_ip3
1917 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
1920 union cvmx_ciu_en2_ppx_ip3 {
1922 struct cvmx_ciu_en2_ppx_ip3_s {
1923 #ifdef __BIG_ENDIAN_BITFIELD
1924 uint64_t reserved_15_63 : 49;
1925 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
1926 uint64_t eoi : 1; /**< EOI rsl interrupt enable */
1927 uint64_t reserved_10_11 : 2;
1928 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
1929 uint64_t reserved_0_3 : 4;
1931 uint64_t reserved_0_3 : 4;
1933 uint64_t reserved_10_11 : 2;
1936 uint64_t reserved_15_63 : 49;
1939 struct cvmx_ciu_en2_ppx_ip3_cn61xx {
1940 #ifdef __BIG_ENDIAN_BITFIELD
1941 uint64_t reserved_10_63 : 54;
1942 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
1943 uint64_t reserved_0_3 : 4;
1945 uint64_t reserved_0_3 : 4;
1947 uint64_t reserved_10_63 : 54;
1950 struct cvmx_ciu_en2_ppx_ip3_cn61xx cn66xx;
1951 struct cvmx_ciu_en2_ppx_ip3_s cnf71xx;
1953 typedef union cvmx_ciu_en2_ppx_ip3 cvmx_ciu_en2_ppx_ip3_t;
1956 * cvmx_ciu_en2_pp#_ip3_w1c
1959 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
1960 * CIU_EN2_PP(IO)X_IPx(INT) value.
1962 union cvmx_ciu_en2_ppx_ip3_w1c {
1964 struct cvmx_ciu_en2_ppx_ip3_w1c_s {
1965 #ifdef __BIG_ENDIAN_BITFIELD
1966 uint64_t reserved_15_63 : 49;
1967 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
1968 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
1969 uint64_t reserved_10_11 : 2;
1970 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
1971 uint64_t reserved_0_3 : 4;
1973 uint64_t reserved_0_3 : 4;
1975 uint64_t reserved_10_11 : 2;
1978 uint64_t reserved_15_63 : 49;
1981 struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx {
1982 #ifdef __BIG_ENDIAN_BITFIELD
1983 uint64_t reserved_10_63 : 54;
1984 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
1985 uint64_t reserved_0_3 : 4;
1987 uint64_t reserved_0_3 : 4;
1989 uint64_t reserved_10_63 : 54;
1992 struct cvmx_ciu_en2_ppx_ip3_w1c_cn61xx cn66xx;
1993 struct cvmx_ciu_en2_ppx_ip3_w1c_s cnf71xx;
1995 typedef union cvmx_ciu_en2_ppx_ip3_w1c cvmx_ciu_en2_ppx_ip3_w1c_t;
1998 * cvmx_ciu_en2_pp#_ip3_w1s
2001 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
2002 * CIU_EN2_PP(IO)X_IPx(INT) value.
2004 union cvmx_ciu_en2_ppx_ip3_w1s {
2006 struct cvmx_ciu_en2_ppx_ip3_w1s_s {
2007 #ifdef __BIG_ENDIAN_BITFIELD
2008 uint64_t reserved_15_63 : 49;
2009 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
2010 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
2011 uint64_t reserved_10_11 : 2;
2012 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
2013 uint64_t reserved_0_3 : 4;
2015 uint64_t reserved_0_3 : 4;
2017 uint64_t reserved_10_11 : 2;
2020 uint64_t reserved_15_63 : 49;
2023 struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx {
2024 #ifdef __BIG_ENDIAN_BITFIELD
2025 uint64_t reserved_10_63 : 54;
2026 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
2027 uint64_t reserved_0_3 : 4;
2029 uint64_t reserved_0_3 : 4;
2031 uint64_t reserved_10_63 : 54;
2034 struct cvmx_ciu_en2_ppx_ip3_w1s_cn61xx cn66xx;
2035 struct cvmx_ciu_en2_ppx_ip3_w1s_s cnf71xx;
2037 typedef union cvmx_ciu_en2_ppx_ip3_w1s cvmx_ciu_en2_ppx_ip3_w1s_t;
2040 * cvmx_ciu_en2_pp#_ip4
2043 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
2046 union cvmx_ciu_en2_ppx_ip4 {
2048 struct cvmx_ciu_en2_ppx_ip4_s {
2049 #ifdef __BIG_ENDIAN_BITFIELD
2050 uint64_t reserved_15_63 : 49;
2051 uint64_t endor : 2; /**< ENDOR PHY interrupts enable */
2052 uint64_t eoi : 1; /**< EOI rsl interrupt enable */
2053 uint64_t reserved_10_11 : 2;
2054 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
2055 uint64_t reserved_0_3 : 4;
2057 uint64_t reserved_0_3 : 4;
2059 uint64_t reserved_10_11 : 2;
2062 uint64_t reserved_15_63 : 49;
2065 struct cvmx_ciu_en2_ppx_ip4_cn61xx {
2066 #ifdef __BIG_ENDIAN_BITFIELD
2067 uint64_t reserved_10_63 : 54;
2068 uint64_t timer : 6; /**< General timer 4-9 interrupt enable */
2069 uint64_t reserved_0_3 : 4;
2071 uint64_t reserved_0_3 : 4;
2073 uint64_t reserved_10_63 : 54;
2076 struct cvmx_ciu_en2_ppx_ip4_cn61xx cn66xx;
2077 struct cvmx_ciu_en2_ppx_ip4_s cnf71xx;
2079 typedef union cvmx_ciu_en2_ppx_ip4 cvmx_ciu_en2_ppx_ip4_t;
2082 * cvmx_ciu_en2_pp#_ip4_w1c
2085 * Write-1-to-clear version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
2086 * CIU_EN2_PP(IO)X_IPx(INT) value.
2088 union cvmx_ciu_en2_ppx_ip4_w1c {
2090 struct cvmx_ciu_en2_ppx_ip4_w1c_s {
2091 #ifdef __BIG_ENDIAN_BITFIELD
2092 uint64_t reserved_15_63 : 49;
2093 uint64_t endor : 2; /**< Write 1 to clear ENDOR PHY interrupts enable */
2094 uint64_t eoi : 1; /**< Write 1 to clear EOI rsl interrupt enable */
2095 uint64_t reserved_10_11 : 2;
2096 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
2097 uint64_t reserved_0_3 : 4;
2099 uint64_t reserved_0_3 : 4;
2101 uint64_t reserved_10_11 : 2;
2104 uint64_t reserved_15_63 : 49;
2107 struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx {
2108 #ifdef __BIG_ENDIAN_BITFIELD
2109 uint64_t reserved_10_63 : 54;
2110 uint64_t timer : 6; /**< Write 1 to clear General timer 4-9 interrupt enable */
2111 uint64_t reserved_0_3 : 4;
2113 uint64_t reserved_0_3 : 4;
2115 uint64_t reserved_10_63 : 54;
2118 struct cvmx_ciu_en2_ppx_ip4_w1c_cn61xx cn66xx;
2119 struct cvmx_ciu_en2_ppx_ip4_w1c_s cnf71xx;
2121 typedef union cvmx_ciu_en2_ppx_ip4_w1c cvmx_ciu_en2_ppx_ip4_w1c_t;
2124 * cvmx_ciu_en2_pp#_ip4_w1s
2127 * Write-1-to-set version of the CIU_EN2_PP(IO)X_IPx(INT) register, read back corresponding
2128 * CIU_EN2_PP(IO)X_IPx(INT) value.
2130 union cvmx_ciu_en2_ppx_ip4_w1s {
2132 struct cvmx_ciu_en2_ppx_ip4_w1s_s {
2133 #ifdef __BIG_ENDIAN_BITFIELD
2134 uint64_t reserved_15_63 : 49;
2135 uint64_t endor : 2; /**< Write 1 to set ENDOR PHY interrupts enable */
2136 uint64_t eoi : 1; /**< Write 1 to set EOI rsl interrupt enable */
2137 uint64_t reserved_10_11 : 2;
2138 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
2139 uint64_t reserved_0_3 : 4;
2141 uint64_t reserved_0_3 : 4;
2143 uint64_t reserved_10_11 : 2;
2146 uint64_t reserved_15_63 : 49;
2149 struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx {
2150 #ifdef __BIG_ENDIAN_BITFIELD
2151 uint64_t reserved_10_63 : 54;
2152 uint64_t timer : 6; /**< Write 1 to set General timer 4-9 interrupt enables */
2153 uint64_t reserved_0_3 : 4;
2155 uint64_t reserved_0_3 : 4;
2157 uint64_t reserved_10_63 : 54;
2160 struct cvmx_ciu_en2_ppx_ip4_w1s_cn61xx cn66xx;
2161 struct cvmx_ciu_en2_ppx_ip4_w1s_s cnf71xx;
2163 typedef union cvmx_ciu_en2_ppx_ip4_w1s cvmx_ciu_en2_ppx_ip4_w1s_t;
2168 union cvmx_ciu_fuse {
2170 struct cvmx_ciu_fuse_s {
2171 #ifdef __BIG_ENDIAN_BITFIELD
2172 uint64_t reserved_32_63 : 32;
2173 uint64_t fuse : 32; /**< Physical PP is present */
2176 uint64_t reserved_32_63 : 32;
2179 struct cvmx_ciu_fuse_cn30xx {
2180 #ifdef __BIG_ENDIAN_BITFIELD
2181 uint64_t reserved_1_63 : 63;
2182 uint64_t fuse : 1; /**< Physical PP is present */
2185 uint64_t reserved_1_63 : 63;
2188 struct cvmx_ciu_fuse_cn31xx {
2189 #ifdef __BIG_ENDIAN_BITFIELD
2190 uint64_t reserved_2_63 : 62;
2191 uint64_t fuse : 2; /**< Physical PP is present */
2194 uint64_t reserved_2_63 : 62;
2197 struct cvmx_ciu_fuse_cn38xx {
2198 #ifdef __BIG_ENDIAN_BITFIELD
2199 uint64_t reserved_16_63 : 48;
2200 uint64_t fuse : 16; /**< Physical PP is present */
2203 uint64_t reserved_16_63 : 48;
2206 struct cvmx_ciu_fuse_cn38xx cn38xxp2;
2207 struct cvmx_ciu_fuse_cn31xx cn50xx;
2208 struct cvmx_ciu_fuse_cn52xx {
2209 #ifdef __BIG_ENDIAN_BITFIELD
2210 uint64_t reserved_4_63 : 60;
2211 uint64_t fuse : 4; /**< Physical PP is present */
2214 uint64_t reserved_4_63 : 60;
2217 struct cvmx_ciu_fuse_cn52xx cn52xxp1;
2218 struct cvmx_ciu_fuse_cn56xx {
2219 #ifdef __BIG_ENDIAN_BITFIELD
2220 uint64_t reserved_12_63 : 52;
2221 uint64_t fuse : 12; /**< Physical PP is present */
2224 uint64_t reserved_12_63 : 52;
2227 struct cvmx_ciu_fuse_cn56xx cn56xxp1;
2228 struct cvmx_ciu_fuse_cn38xx cn58xx;
2229 struct cvmx_ciu_fuse_cn38xx cn58xxp1;
2230 struct cvmx_ciu_fuse_cn52xx cn61xx;
2231 struct cvmx_ciu_fuse_cn63xx {
2232 #ifdef __BIG_ENDIAN_BITFIELD
2233 uint64_t reserved_6_63 : 58;
2234 uint64_t fuse : 6; /**< Physical PP is present */
2237 uint64_t reserved_6_63 : 58;
2240 struct cvmx_ciu_fuse_cn63xx cn63xxp1;
2241 struct cvmx_ciu_fuse_cn66xx {
2242 #ifdef __BIG_ENDIAN_BITFIELD
2243 uint64_t reserved_10_63 : 54;
2244 uint64_t fuse : 10; /**< Physical PP is present */
2247 uint64_t reserved_10_63 : 54;
2250 struct cvmx_ciu_fuse_s cn68xx;
2251 struct cvmx_ciu_fuse_s cn68xxp1;
2252 struct cvmx_ciu_fuse_cn52xx cnf71xx;
2254 typedef union cvmx_ciu_fuse cvmx_ciu_fuse_t;
2259 union cvmx_ciu_gstop {
2261 struct cvmx_ciu_gstop_s {
2262 #ifdef __BIG_ENDIAN_BITFIELD
2263 uint64_t reserved_1_63 : 63;
2264 uint64_t gstop : 1; /**< GSTOP bit */
2267 uint64_t reserved_1_63 : 63;
2270 struct cvmx_ciu_gstop_s cn30xx;
2271 struct cvmx_ciu_gstop_s cn31xx;
2272 struct cvmx_ciu_gstop_s cn38xx;
2273 struct cvmx_ciu_gstop_s cn38xxp2;
2274 struct cvmx_ciu_gstop_s cn50xx;
2275 struct cvmx_ciu_gstop_s cn52xx;
2276 struct cvmx_ciu_gstop_s cn52xxp1;
2277 struct cvmx_ciu_gstop_s cn56xx;
2278 struct cvmx_ciu_gstop_s cn56xxp1;
2279 struct cvmx_ciu_gstop_s cn58xx;
2280 struct cvmx_ciu_gstop_s cn58xxp1;
2281 struct cvmx_ciu_gstop_s cn61xx;
2282 struct cvmx_ciu_gstop_s cn63xx;
2283 struct cvmx_ciu_gstop_s cn63xxp1;
2284 struct cvmx_ciu_gstop_s cn66xx;
2285 struct cvmx_ciu_gstop_s cn68xx;
2286 struct cvmx_ciu_gstop_s cn68xxp1;
2287 struct cvmx_ciu_gstop_s cnf71xx;
2289 typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t;
2295 * CIU_INT0_EN0: PP0/IP2
2296 * CIU_INT1_EN0: PP0/IP3
2297 * CIU_INT2_EN0: PP1/IP2
2298 * CIU_INT3_EN0: PP1/IP3
2299 * CIU_INT4_EN0: PP2/IP2
2300 * CIU_INT5_EN0: PP2/IP3
2301 * CIU_INT6_EN0: PP3/IP2
2302 * CIU_INT7_EN0: PP3/IP3
2306 * CIU_INT32_EN0: IO 0
2307 * CIU_INT33_EN0: IO 1
2309 union cvmx_ciu_intx_en0 {
2311 struct cvmx_ciu_intx_en0_s {
2312 #ifdef __BIG_ENDIAN_BITFIELD
2313 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
2314 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
2315 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
2316 uint64_t powiq : 1; /**< POW IQ interrupt enable */
2317 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
2318 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
2319 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
2320 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
2321 uint64_t timer : 4; /**< General timer interrupt enables */
2322 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
2323 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
2324 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
2325 uint64_t trace : 1; /**< Trace buffer interrupt enable */
2326 uint64_t rml : 1; /**< RML Interrupt enable */
2327 uint64_t twsi : 1; /**< TWSI Interrupt enable */
2328 uint64_t reserved_44_44 : 1;
2329 uint64_t pci_msi : 4; /**< PCIe MSI enables */
2330 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
2331 uint64_t uart : 2; /**< Two UART interrupt enables */
2332 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
2333 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
2334 uint64_t workq : 16; /**< 16 work queue interrupt enables */
2336 uint64_t workq : 16;
2340 uint64_t pci_int : 4;
2341 uint64_t pci_msi : 4;
2342 uint64_t reserved_44_44 : 1;
2346 uint64_t gmx_drp : 2;
2347 uint64_t ipd_drp : 1;
2348 uint64_t key_zero : 1;
2355 uint64_t ipdppthr : 1;
2357 uint64_t bootdma : 1;
2360 struct cvmx_ciu_intx_en0_cn30xx {
2361 #ifdef __BIG_ENDIAN_BITFIELD
2362 uint64_t reserved_59_63 : 5;
2363 uint64_t mpi : 1; /**< MPI/SPI interrupt */
2364 uint64_t pcm : 1; /**< PCM/TDM interrupt */
2365 uint64_t usb : 1; /**< USB interrupt */
2366 uint64_t timer : 4; /**< General timer interrupts */
2367 uint64_t reserved_51_51 : 1;
2368 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2369 uint64_t reserved_49_49 : 1;
2370 uint64_t gmx_drp : 1; /**< GMX packet drop */
2371 uint64_t reserved_47_47 : 1;
2372 uint64_t rml : 1; /**< RML Interrupt */
2373 uint64_t twsi : 1; /**< TWSI Interrupt */
2374 uint64_t reserved_44_44 : 1;
2375 uint64_t pci_msi : 4; /**< PCI MSI */
2376 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2377 uint64_t uart : 2; /**< Two UART interrupts */
2378 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2379 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2380 uint64_t workq : 16; /**< 16 work queue interrupts */
2382 uint64_t workq : 16;
2386 uint64_t pci_int : 4;
2387 uint64_t pci_msi : 4;
2388 uint64_t reserved_44_44 : 1;
2391 uint64_t reserved_47_47 : 1;
2392 uint64_t gmx_drp : 1;
2393 uint64_t reserved_49_49 : 1;
2394 uint64_t ipd_drp : 1;
2395 uint64_t reserved_51_51 : 1;
2400 uint64_t reserved_59_63 : 5;
2403 struct cvmx_ciu_intx_en0_cn31xx {
2404 #ifdef __BIG_ENDIAN_BITFIELD
2405 uint64_t reserved_59_63 : 5;
2406 uint64_t mpi : 1; /**< MPI/SPI interrupt */
2407 uint64_t pcm : 1; /**< PCM/TDM interrupt */
2408 uint64_t usb : 1; /**< USB interrupt */
2409 uint64_t timer : 4; /**< General timer interrupts */
2410 uint64_t reserved_51_51 : 1;
2411 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2412 uint64_t reserved_49_49 : 1;
2413 uint64_t gmx_drp : 1; /**< GMX packet drop */
2414 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
2415 uint64_t rml : 1; /**< RML Interrupt */
2416 uint64_t twsi : 1; /**< TWSI Interrupt */
2417 uint64_t reserved_44_44 : 1;
2418 uint64_t pci_msi : 4; /**< PCI MSI */
2419 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2420 uint64_t uart : 2; /**< Two UART interrupts */
2421 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2422 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2423 uint64_t workq : 16; /**< 16 work queue interrupts */
2425 uint64_t workq : 16;
2429 uint64_t pci_int : 4;
2430 uint64_t pci_msi : 4;
2431 uint64_t reserved_44_44 : 1;
2435 uint64_t gmx_drp : 1;
2436 uint64_t reserved_49_49 : 1;
2437 uint64_t ipd_drp : 1;
2438 uint64_t reserved_51_51 : 1;
2443 uint64_t reserved_59_63 : 5;
2446 struct cvmx_ciu_intx_en0_cn38xx {
2447 #ifdef __BIG_ENDIAN_BITFIELD
2448 uint64_t reserved_56_63 : 8;
2449 uint64_t timer : 4; /**< General timer interrupts */
2450 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
2451 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2452 uint64_t gmx_drp : 2; /**< GMX packet drop */
2453 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
2454 uint64_t rml : 1; /**< RML Interrupt */
2455 uint64_t twsi : 1; /**< TWSI Interrupt */
2456 uint64_t reserved_44_44 : 1;
2457 uint64_t pci_msi : 4; /**< PCI MSI */
2458 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2459 uint64_t uart : 2; /**< Two UART interrupts */
2460 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2461 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2462 uint64_t workq : 16; /**< 16 work queue interrupts */
2464 uint64_t workq : 16;
2468 uint64_t pci_int : 4;
2469 uint64_t pci_msi : 4;
2470 uint64_t reserved_44_44 : 1;
2474 uint64_t gmx_drp : 2;
2475 uint64_t ipd_drp : 1;
2476 uint64_t key_zero : 1;
2478 uint64_t reserved_56_63 : 8;
2481 struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
2482 struct cvmx_ciu_intx_en0_cn30xx cn50xx;
2483 struct cvmx_ciu_intx_en0_cn52xx {
2484 #ifdef __BIG_ENDIAN_BITFIELD
2485 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
2486 uint64_t mii : 1; /**< MII Interface Interrupt */
2487 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
2488 uint64_t powiq : 1; /**< POW IQ interrupt */
2489 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
2490 uint64_t reserved_57_58 : 2;
2491 uint64_t usb : 1; /**< USB Interrupt */
2492 uint64_t timer : 4; /**< General timer interrupts */
2493 uint64_t reserved_51_51 : 1;
2494 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2495 uint64_t reserved_49_49 : 1;
2496 uint64_t gmx_drp : 1; /**< GMX packet drop */
2497 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
2498 uint64_t rml : 1; /**< RML Interrupt */
2499 uint64_t twsi : 1; /**< TWSI Interrupt */
2500 uint64_t reserved_44_44 : 1;
2501 uint64_t pci_msi : 4; /**< PCI MSI */
2502 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2503 uint64_t uart : 2; /**< Two UART interrupts */
2504 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2505 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2506 uint64_t workq : 16; /**< 16 work queue interrupts */
2508 uint64_t workq : 16;
2512 uint64_t pci_int : 4;
2513 uint64_t pci_msi : 4;
2514 uint64_t reserved_44_44 : 1;
2518 uint64_t gmx_drp : 1;
2519 uint64_t reserved_49_49 : 1;
2520 uint64_t ipd_drp : 1;
2521 uint64_t reserved_51_51 : 1;
2524 uint64_t reserved_57_58 : 2;
2527 uint64_t ipdppthr : 1;
2529 uint64_t bootdma : 1;
2532 struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
2533 struct cvmx_ciu_intx_en0_cn56xx {
2534 #ifdef __BIG_ENDIAN_BITFIELD
2535 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
2536 uint64_t mii : 1; /**< MII Interface Interrupt */
2537 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
2538 uint64_t powiq : 1; /**< POW IQ interrupt */
2539 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
2540 uint64_t reserved_57_58 : 2;
2541 uint64_t usb : 1; /**< USB Interrupt */
2542 uint64_t timer : 4; /**< General timer interrupts */
2543 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
2544 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2545 uint64_t gmx_drp : 2; /**< GMX packet drop */
2546 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
2547 uint64_t rml : 1; /**< RML Interrupt */
2548 uint64_t twsi : 1; /**< TWSI Interrupt */
2549 uint64_t reserved_44_44 : 1;
2550 uint64_t pci_msi : 4; /**< PCI MSI */
2551 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2552 uint64_t uart : 2; /**< Two UART interrupts */
2553 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2554 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2555 uint64_t workq : 16; /**< 16 work queue interrupts */
2557 uint64_t workq : 16;
2561 uint64_t pci_int : 4;
2562 uint64_t pci_msi : 4;
2563 uint64_t reserved_44_44 : 1;
2567 uint64_t gmx_drp : 2;
2568 uint64_t ipd_drp : 1;
2569 uint64_t key_zero : 1;
2572 uint64_t reserved_57_58 : 2;
2575 uint64_t ipdppthr : 1;
2577 uint64_t bootdma : 1;
2580 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
2581 struct cvmx_ciu_intx_en0_cn38xx cn58xx;
2582 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
2583 struct cvmx_ciu_intx_en0_cn61xx {
2584 #ifdef __BIG_ENDIAN_BITFIELD
2585 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
2586 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */
2587 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
2588 uint64_t powiq : 1; /**< POW IQ interrupt enable */
2589 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
2590 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
2591 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
2592 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
2593 uint64_t timer : 4; /**< General timer interrupt enables */
2594 uint64_t reserved_51_51 : 1;
2595 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
2596 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
2597 uint64_t trace : 1; /**< Trace buffer interrupt enable */
2598 uint64_t rml : 1; /**< RML Interrupt enable */
2599 uint64_t twsi : 1; /**< TWSI Interrupt enable */
2600 uint64_t reserved_44_44 : 1;
2601 uint64_t pci_msi : 4; /**< PCIe MSI enables */
2602 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
2603 uint64_t uart : 2; /**< Two UART interrupt enables */
2604 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
2605 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
2606 uint64_t workq : 16; /**< 16 work queue interrupt enables */
2608 uint64_t workq : 16;
2612 uint64_t pci_int : 4;
2613 uint64_t pci_msi : 4;
2614 uint64_t reserved_44_44 : 1;
2618 uint64_t gmx_drp : 2;
2619 uint64_t ipd_drp : 1;
2620 uint64_t reserved_51_51 : 1;
2627 uint64_t ipdppthr : 1;
2629 uint64_t bootdma : 1;
2632 struct cvmx_ciu_intx_en0_cn52xx cn63xx;
2633 struct cvmx_ciu_intx_en0_cn52xx cn63xxp1;
2634 struct cvmx_ciu_intx_en0_cn66xx {
2635 #ifdef __BIG_ENDIAN_BITFIELD
2636 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
2637 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
2638 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
2639 uint64_t powiq : 1; /**< POW IQ interrupt enable */
2640 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
2641 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
2642 uint64_t reserved_57_57 : 1;
2643 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
2644 uint64_t timer : 4; /**< General timer interrupt enables */
2645 uint64_t reserved_51_51 : 1;
2646 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
2647 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
2648 uint64_t trace : 1; /**< Trace buffer interrupt enable */
2649 uint64_t rml : 1; /**< RML Interrupt enable */
2650 uint64_t twsi : 1; /**< TWSI Interrupt enable */
2651 uint64_t reserved_44_44 : 1;
2652 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */
2653 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
2654 uint64_t uart : 2; /**< Two UART interrupt enables */
2655 uint64_t mbox : 2; /**< Two mailbox/PCIe/sRIO interrupt enables */
2656 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
2657 uint64_t workq : 16; /**< 16 work queue interrupt enables */
2659 uint64_t workq : 16;
2663 uint64_t pci_int : 4;
2664 uint64_t pci_msi : 4;
2665 uint64_t reserved_44_44 : 1;
2669 uint64_t gmx_drp : 2;
2670 uint64_t ipd_drp : 1;
2671 uint64_t reserved_51_51 : 1;
2674 uint64_t reserved_57_57 : 1;
2678 uint64_t ipdppthr : 1;
2680 uint64_t bootdma : 1;
2683 struct cvmx_ciu_intx_en0_cnf71xx {
2684 #ifdef __BIG_ENDIAN_BITFIELD
2685 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
2686 uint64_t reserved_62_62 : 1;
2687 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
2688 uint64_t powiq : 1; /**< POW IQ interrupt enable */
2689 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
2690 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
2691 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
2692 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
2693 uint64_t timer : 4; /**< General timer interrupt enables */
2694 uint64_t reserved_51_51 : 1;
2695 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
2696 uint64_t reserved_49_49 : 1;
2697 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt enable */
2698 uint64_t trace : 1; /**< Trace buffer interrupt enable */
2699 uint64_t rml : 1; /**< RML Interrupt enable */
2700 uint64_t twsi : 1; /**< TWSI Interrupt enable */
2701 uint64_t reserved_44_44 : 1;
2702 uint64_t pci_msi : 4; /**< PCIe MSI enables */
2703 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
2704 uint64_t uart : 2; /**< Two UART interrupt enables */
2705 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
2706 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
2707 uint64_t workq : 16; /**< 16 work queue interrupt enables */
2709 uint64_t workq : 16;
2713 uint64_t pci_int : 4;
2714 uint64_t pci_msi : 4;
2715 uint64_t reserved_44_44 : 1;
2719 uint64_t gmx_drp : 1;
2720 uint64_t reserved_49_49 : 1;
2721 uint64_t ipd_drp : 1;
2722 uint64_t reserved_51_51 : 1;
2729 uint64_t ipdppthr : 1;
2730 uint64_t reserved_62_62 : 1;
2731 uint64_t bootdma : 1;
2735 typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t;
2738 * cvmx_ciu_int#_en0_w1c
2741 * Write-1-to-clear version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value.
2744 union cvmx_ciu_intx_en0_w1c {
2746 struct cvmx_ciu_intx_en0_w1c_s {
2747 #ifdef __BIG_ENDIAN_BITFIELD
2748 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
2750 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
2752 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
2754 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
2755 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
2756 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
2757 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
2758 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
2759 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
2760 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
2761 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
2763 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
2764 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
2765 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
2766 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
2767 uint64_t reserved_44_44 : 1;
2768 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
2769 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
2770 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
2771 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
2773 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
2774 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
2776 uint64_t workq : 16;
2780 uint64_t pci_int : 4;
2781 uint64_t pci_msi : 4;
2782 uint64_t reserved_44_44 : 1;
2786 uint64_t gmx_drp : 2;
2787 uint64_t ipd_drp : 1;
2788 uint64_t key_zero : 1;
2795 uint64_t ipdppthr : 1;
2797 uint64_t bootdma : 1;
2800 struct cvmx_ciu_intx_en0_w1c_cn52xx {
2801 #ifdef __BIG_ENDIAN_BITFIELD
2802 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
2803 uint64_t mii : 1; /**< MII Interface Interrupt */
2804 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
2805 uint64_t powiq : 1; /**< POW IQ interrupt */
2806 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
2807 uint64_t reserved_57_58 : 2;
2808 uint64_t usb : 1; /**< USB Interrupt */
2809 uint64_t timer : 4; /**< General timer interrupts */
2810 uint64_t reserved_51_51 : 1;
2811 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2812 uint64_t reserved_49_49 : 1;
2813 uint64_t gmx_drp : 1; /**< GMX packet drop */
2814 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
2815 uint64_t rml : 1; /**< RML Interrupt */
2816 uint64_t twsi : 1; /**< TWSI Interrupt */
2817 uint64_t reserved_44_44 : 1;
2818 uint64_t pci_msi : 4; /**< PCI MSI */
2819 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2820 uint64_t uart : 2; /**< Two UART interrupts */
2821 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2822 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2823 uint64_t workq : 16; /**< 16 work queue interrupts */
2825 uint64_t workq : 16;
2829 uint64_t pci_int : 4;
2830 uint64_t pci_msi : 4;
2831 uint64_t reserved_44_44 : 1;
2835 uint64_t gmx_drp : 1;
2836 uint64_t reserved_49_49 : 1;
2837 uint64_t ipd_drp : 1;
2838 uint64_t reserved_51_51 : 1;
2841 uint64_t reserved_57_58 : 2;
2844 uint64_t ipdppthr : 1;
2846 uint64_t bootdma : 1;
2849 struct cvmx_ciu_intx_en0_w1c_cn56xx {
2850 #ifdef __BIG_ENDIAN_BITFIELD
2851 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
2852 uint64_t mii : 1; /**< MII Interface Interrupt */
2853 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
2854 uint64_t powiq : 1; /**< POW IQ interrupt */
2855 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
2856 uint64_t reserved_57_58 : 2;
2857 uint64_t usb : 1; /**< USB Interrupt */
2858 uint64_t timer : 4; /**< General timer interrupts */
2859 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
2860 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2861 uint64_t gmx_drp : 2; /**< GMX packet drop */
2862 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
2863 uint64_t rml : 1; /**< RML Interrupt */
2864 uint64_t twsi : 1; /**< TWSI Interrupt */
2865 uint64_t reserved_44_44 : 1;
2866 uint64_t pci_msi : 4; /**< PCI MSI */
2867 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2868 uint64_t uart : 2; /**< Two UART interrupts */
2869 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2870 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2871 uint64_t workq : 16; /**< 16 work queue interrupts */
2873 uint64_t workq : 16;
2877 uint64_t pci_int : 4;
2878 uint64_t pci_msi : 4;
2879 uint64_t reserved_44_44 : 1;
2883 uint64_t gmx_drp : 2;
2884 uint64_t ipd_drp : 1;
2885 uint64_t key_zero : 1;
2888 uint64_t reserved_57_58 : 2;
2891 uint64_t ipdppthr : 1;
2893 uint64_t bootdma : 1;
2896 struct cvmx_ciu_intx_en0_w1c_cn58xx {
2897 #ifdef __BIG_ENDIAN_BITFIELD
2898 uint64_t reserved_56_63 : 8;
2899 uint64_t timer : 4; /**< General timer interrupts */
2900 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
2901 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
2902 uint64_t gmx_drp : 2; /**< GMX packet drop */
2903 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
2904 uint64_t rml : 1; /**< RML Interrupt */
2905 uint64_t twsi : 1; /**< TWSI Interrupt */
2906 uint64_t reserved_44_44 : 1;
2907 uint64_t pci_msi : 4; /**< PCI MSI */
2908 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
2909 uint64_t uart : 2; /**< Two UART interrupts */
2910 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2911 uint64_t gpio : 16; /**< 16 GPIO interrupts */
2912 uint64_t workq : 16; /**< 16 work queue interrupts */
2914 uint64_t workq : 16;
2918 uint64_t pci_int : 4;
2919 uint64_t pci_msi : 4;
2920 uint64_t reserved_44_44 : 1;
2924 uint64_t gmx_drp : 2;
2925 uint64_t ipd_drp : 1;
2926 uint64_t key_zero : 1;
2928 uint64_t reserved_56_63 : 8;
2931 struct cvmx_ciu_intx_en0_w1c_cn61xx {
2932 #ifdef __BIG_ENDIAN_BITFIELD
2933 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
2935 uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
2937 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
2939 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
2940 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
2941 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
2942 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
2943 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
2944 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
2945 uint64_t reserved_51_51 : 1;
2946 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
2948 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
2949 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
2950 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
2951 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
2952 uint64_t reserved_44_44 : 1;
2953 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
2954 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
2955 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
2956 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
2958 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
2959 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
2961 uint64_t workq : 16;
2965 uint64_t pci_int : 4;
2966 uint64_t pci_msi : 4;
2967 uint64_t reserved_44_44 : 1;
2971 uint64_t gmx_drp : 2;
2972 uint64_t ipd_drp : 1;
2973 uint64_t reserved_51_51 : 1;
2980 uint64_t ipdppthr : 1;
2982 uint64_t bootdma : 1;
2985 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx;
2986 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1;
2987 struct cvmx_ciu_intx_en0_w1c_cn66xx {
2988 #ifdef __BIG_ENDIAN_BITFIELD
2989 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
2991 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
2993 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
2995 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */
2996 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */
2997 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt */
2998 uint64_t reserved_57_57 : 1;
2999 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */
3000 uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */
3001 uint64_t reserved_51_51 : 1;
3002 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
3004 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
3005 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
3006 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
3007 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
3008 uint64_t reserved_44_44 : 1;
3009 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */
3010 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
3011 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
3012 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
3014 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
3015 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
3017 uint64_t workq : 16;
3021 uint64_t pci_int : 4;
3022 uint64_t pci_msi : 4;
3023 uint64_t reserved_44_44 : 1;
3027 uint64_t gmx_drp : 2;
3028 uint64_t ipd_drp : 1;
3029 uint64_t reserved_51_51 : 1;
3032 uint64_t reserved_57_57 : 1;
3036 uint64_t ipdppthr : 1;
3038 uint64_t bootdma : 1;
3041 struct cvmx_ciu_intx_en0_w1c_cnf71xx {
3042 #ifdef __BIG_ENDIAN_BITFIELD
3043 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
3045 uint64_t reserved_62_62 : 1;
3046 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
3048 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
3049 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
3050 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
3051 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
3052 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
3053 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
3054 uint64_t reserved_51_51 : 1;
3055 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
3057 uint64_t reserved_49_49 : 1;
3058 uint64_t gmx_drp : 1; /**< Write 1 to clear GMX packet drop interrupt enable */
3059 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
3060 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
3061 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
3062 uint64_t reserved_44_44 : 1;
3063 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
3064 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
3065 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
3066 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
3068 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
3069 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
3071 uint64_t workq : 16;
3075 uint64_t pci_int : 4;
3076 uint64_t pci_msi : 4;
3077 uint64_t reserved_44_44 : 1;
3081 uint64_t gmx_drp : 1;
3082 uint64_t reserved_49_49 : 1;
3083 uint64_t ipd_drp : 1;
3084 uint64_t reserved_51_51 : 1;
3091 uint64_t ipdppthr : 1;
3092 uint64_t reserved_62_62 : 1;
3093 uint64_t bootdma : 1;
3097 typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t;
3100 * cvmx_ciu_int#_en0_w1s
3103 * Write-1-to-set version of the CIU_INTx_EN0 register, read back corresponding CIU_INTx_EN0 value.
3106 union cvmx_ciu_intx_en0_w1s {
3108 struct cvmx_ciu_intx_en0_w1s_s {
3109 #ifdef __BIG_ENDIAN_BITFIELD
3110 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
3112 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
3114 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
3116 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
3117 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
3118 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
3119 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
3120 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
3121 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
3122 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
3123 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
3125 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
3126 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
3127 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
3128 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
3129 uint64_t reserved_44_44 : 1;
3130 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
3131 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
3132 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
3133 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
3135 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
3136 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
3138 uint64_t workq : 16;
3142 uint64_t pci_int : 4;
3143 uint64_t pci_msi : 4;
3144 uint64_t reserved_44_44 : 1;
3148 uint64_t gmx_drp : 2;
3149 uint64_t ipd_drp : 1;
3150 uint64_t key_zero : 1;
3157 uint64_t ipdppthr : 1;
3159 uint64_t bootdma : 1;
3162 struct cvmx_ciu_intx_en0_w1s_cn52xx {
3163 #ifdef __BIG_ENDIAN_BITFIELD
3164 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
3165 uint64_t mii : 1; /**< MII Interface Interrupt */
3166 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
3167 uint64_t powiq : 1; /**< POW IQ interrupt */
3168 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
3169 uint64_t reserved_57_58 : 2;
3170 uint64_t usb : 1; /**< USB Interrupt */
3171 uint64_t timer : 4; /**< General timer interrupts */
3172 uint64_t reserved_51_51 : 1;
3173 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
3174 uint64_t reserved_49_49 : 1;
3175 uint64_t gmx_drp : 1; /**< GMX packet drop */
3176 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
3177 uint64_t rml : 1; /**< RML Interrupt */
3178 uint64_t twsi : 1; /**< TWSI Interrupt */
3179 uint64_t reserved_44_44 : 1;
3180 uint64_t pci_msi : 4; /**< PCI MSI */
3181 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
3182 uint64_t uart : 2; /**< Two UART interrupts */
3183 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
3184 uint64_t gpio : 16; /**< 16 GPIO interrupts */
3185 uint64_t workq : 16; /**< 16 work queue interrupts */
3187 uint64_t workq : 16;
3191 uint64_t pci_int : 4;
3192 uint64_t pci_msi : 4;
3193 uint64_t reserved_44_44 : 1;
3197 uint64_t gmx_drp : 1;
3198 uint64_t reserved_49_49 : 1;
3199 uint64_t ipd_drp : 1;
3200 uint64_t reserved_51_51 : 1;
3203 uint64_t reserved_57_58 : 2;
3206 uint64_t ipdppthr : 1;
3208 uint64_t bootdma : 1;
3211 struct cvmx_ciu_intx_en0_w1s_cn56xx {
3212 #ifdef __BIG_ENDIAN_BITFIELD
3213 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
3214 uint64_t mii : 1; /**< MII Interface Interrupt */
3215 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
3216 uint64_t powiq : 1; /**< POW IQ interrupt */
3217 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
3218 uint64_t reserved_57_58 : 2;
3219 uint64_t usb : 1; /**< USB Interrupt */
3220 uint64_t timer : 4; /**< General timer interrupts */
3221 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
3222 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
3223 uint64_t gmx_drp : 2; /**< GMX packet drop */
3224 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
3225 uint64_t rml : 1; /**< RML Interrupt */
3226 uint64_t twsi : 1; /**< TWSI Interrupt */
3227 uint64_t reserved_44_44 : 1;
3228 uint64_t pci_msi : 4; /**< PCI MSI */
3229 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
3230 uint64_t uart : 2; /**< Two UART interrupts */
3231 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
3232 uint64_t gpio : 16; /**< 16 GPIO interrupts */
3233 uint64_t workq : 16; /**< 16 work queue interrupts */
3235 uint64_t workq : 16;
3239 uint64_t pci_int : 4;
3240 uint64_t pci_msi : 4;
3241 uint64_t reserved_44_44 : 1;
3245 uint64_t gmx_drp : 2;
3246 uint64_t ipd_drp : 1;
3247 uint64_t key_zero : 1;
3250 uint64_t reserved_57_58 : 2;
3253 uint64_t ipdppthr : 1;
3255 uint64_t bootdma : 1;
3258 struct cvmx_ciu_intx_en0_w1s_cn58xx {
3259 #ifdef __BIG_ENDIAN_BITFIELD
3260 uint64_t reserved_56_63 : 8;
3261 uint64_t timer : 4; /**< General timer interrupts */
3262 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
3263 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
3264 uint64_t gmx_drp : 2; /**< GMX packet drop */
3265 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
3266 uint64_t rml : 1; /**< RML Interrupt */
3267 uint64_t twsi : 1; /**< TWSI Interrupt */
3268 uint64_t reserved_44_44 : 1;
3269 uint64_t pci_msi : 4; /**< PCI MSI */
3270 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
3271 uint64_t uart : 2; /**< Two UART interrupts */
3272 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
3273 uint64_t gpio : 16; /**< 16 GPIO interrupts */
3274 uint64_t workq : 16; /**< 16 work queue interrupts */
3276 uint64_t workq : 16;
3280 uint64_t pci_int : 4;
3281 uint64_t pci_msi : 4;
3282 uint64_t reserved_44_44 : 1;
3286 uint64_t gmx_drp : 2;
3287 uint64_t ipd_drp : 1;
3288 uint64_t key_zero : 1;
3290 uint64_t reserved_56_63 : 8;
3293 struct cvmx_ciu_intx_en0_w1s_cn61xx {
3294 #ifdef __BIG_ENDIAN_BITFIELD
3295 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
3297 uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
3299 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
3301 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
3302 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
3303 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
3304 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
3305 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
3306 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
3307 uint64_t reserved_51_51 : 1;
3308 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
3310 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
3311 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
3312 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
3313 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
3314 uint64_t reserved_44_44 : 1;
3315 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
3316 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
3317 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
3318 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
3320 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
3321 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
3323 uint64_t workq : 16;
3327 uint64_t pci_int : 4;
3328 uint64_t pci_msi : 4;
3329 uint64_t reserved_44_44 : 1;
3333 uint64_t gmx_drp : 2;
3334 uint64_t ipd_drp : 1;
3335 uint64_t reserved_51_51 : 1;
3342 uint64_t ipdppthr : 1;
3344 uint64_t bootdma : 1;
3347 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx;
3348 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1;
3349 struct cvmx_ciu_intx_en0_w1s_cn66xx {
3350 #ifdef __BIG_ENDIAN_BITFIELD
3351 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
3353 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
3355 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
3357 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */
3358 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */
3359 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt */
3360 uint64_t reserved_57_57 : 1;
3361 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */
3362 uint64_t timer : 4; /**< Write 1 to set General timer interrupts */
3363 uint64_t reserved_51_51 : 1;
3364 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
3366 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
3367 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
3368 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
3369 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
3370 uint64_t reserved_44_44 : 1;
3371 uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */
3372 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
3373 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
3374 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe/sRIO interrupt
3376 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
3377 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
3379 uint64_t workq : 16;
3383 uint64_t pci_int : 4;
3384 uint64_t pci_msi : 4;
3385 uint64_t reserved_44_44 : 1;
3389 uint64_t gmx_drp : 2;
3390 uint64_t ipd_drp : 1;
3391 uint64_t reserved_51_51 : 1;
3394 uint64_t reserved_57_57 : 1;
3398 uint64_t ipdppthr : 1;
3400 uint64_t bootdma : 1;
3403 struct cvmx_ciu_intx_en0_w1s_cnf71xx {
3404 #ifdef __BIG_ENDIAN_BITFIELD
3405 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
3407 uint64_t reserved_62_62 : 1;
3408 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
3410 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
3411 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
3412 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
3413 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
3414 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
3415 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
3416 uint64_t reserved_51_51 : 1;
3417 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
3419 uint64_t reserved_49_49 : 1;
3420 uint64_t gmx_drp : 1; /**< Write 1 to set GMX packet drop interrupt enable */
3421 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
3422 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
3423 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
3424 uint64_t reserved_44_44 : 1;
3425 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
3426 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
3427 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
3428 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
3430 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
3431 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
3433 uint64_t workq : 16;
3437 uint64_t pci_int : 4;
3438 uint64_t pci_msi : 4;
3439 uint64_t reserved_44_44 : 1;
3443 uint64_t gmx_drp : 1;
3444 uint64_t reserved_49_49 : 1;
3445 uint64_t ipd_drp : 1;
3446 uint64_t reserved_51_51 : 1;
3453 uint64_t ipdppthr : 1;
3454 uint64_t reserved_62_62 : 1;
3455 uint64_t bootdma : 1;
3459 typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t;
3465 * Enables for CIU_SUM1_PPX_IPx or CIU_SUM1_IOX_INT
3466 * CIU_INT0_EN1: PP0/IP2
3467 * CIU_INT1_EN1: PP0/IP3
3468 * CIU_INT2_EN1: PP1/IP2
3469 * CIU_INT3_EN1: PP1/IP3
3470 * CIU_INT4_EN1: PP2/IP2
3471 * CIU_INT5_EN1: PP2/IP3
3472 * CIU_INT6_EN1: PP3/IP2
3473 * CIU_INT7_EN1: PP3/IP3
3477 * CIU_INT32_EN1: IO0
3478 * CIU_INT33_EN1: IO1
3481 * PPx/IP2 will be raised when...
3484 * PPx/IP2 = |([CIU_SUM2_PPx_IP2,CIU_SUM1_PPx_IP2, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP2,CIU_INTn_EN1, CIU_INTn_EN0])
3486 * PPx/IP3 will be raised when...
3489 * PPx/IP3 = |([CIU_SUM2_PPx_IP3,CIU_SUM1_PPx_IP3, CIU_INTn_SUM0] & [CIU_EN2_PPx_IP3,CIU_INTn_EN1, CIU_INTn_EN0])
3491 * PCI/INT will be raised when...
3493 * PCI/INT = |([CIU_SUM2_IO0_INT,CIU_SUM1_IO0_INT, CIU_INT32_SUM0] & [CIU_EN2_IO0_INT,CIU_INT32_EN1, CIU_INT32_EN0])
3494 * PCI/INT = |([CIU_SUM2_IO1_INT,CIU_SUM1_IO1_INT, CIU_INT33_SUM0] & [CIU_EN2_IO1_INT,CIU_INT33_EN1, CIU_INT33_EN0])
3497 union cvmx_ciu_intx_en1 {
3499 struct cvmx_ciu_intx_en1_s {
3500 #ifdef __BIG_ENDIAN_BITFIELD
3501 uint64_t rst : 1; /**< MIO RST interrupt enable */
3502 uint64_t reserved_62_62 : 1;
3503 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
3504 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
3505 uint64_t reserved_57_59 : 3;
3506 uint64_t dfm : 1; /**< DFM interrupt enable */
3507 uint64_t reserved_53_55 : 3;
3508 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
3509 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */
3510 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
3511 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
3512 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
3513 uint64_t ptp : 1; /**< PTP interrupt enable */
3514 uint64_t agl : 1; /**< AGL interrupt enable */
3515 uint64_t reserved_41_45 : 5;
3516 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
3517 uint64_t reserved_38_39 : 2;
3518 uint64_t agx1 : 1; /**< GMX1 interrupt enable */
3519 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
3520 uint64_t dpi : 1; /**< DPI interrupt enable */
3521 uint64_t sli : 1; /**< SLI interrupt enable */
3522 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
3523 uint64_t dfa : 1; /**< DFA interrupt enable */
3524 uint64_t key : 1; /**< KEY interrupt enable */
3525 uint64_t rad : 1; /**< RAD interrupt enable */
3526 uint64_t tim : 1; /**< TIM interrupt enable */
3527 uint64_t zip : 1; /**< ZIP interrupt enable */
3528 uint64_t pko : 1; /**< PKO interrupt enable */
3529 uint64_t pip : 1; /**< PIP interrupt enable */
3530 uint64_t ipd : 1; /**< IPD interrupt enable */
3531 uint64_t l2c : 1; /**< L2C interrupt enable */
3532 uint64_t pow : 1; /**< POW err interrupt enable */
3533 uint64_t fpa : 1; /**< FPA interrupt enable */
3534 uint64_t iob : 1; /**< IOB interrupt enable */
3535 uint64_t mio : 1; /**< MIO boot interrupt enable */
3536 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
3537 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
3538 uint64_t usb1 : 1; /**< Second USB Interrupt */
3539 uint64_t uart2 : 1; /**< Third UART interrupt */
3540 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vector */
3565 uint64_t reserved_38_39 : 2;
3566 uint64_t dpi_dma : 1;
3567 uint64_t reserved_41_45 : 5;
3575 uint64_t reserved_53_55 : 3;
3577 uint64_t reserved_57_59 : 3;
3580 uint64_t reserved_62_62 : 1;
3584 struct cvmx_ciu_intx_en1_cn30xx {
3585 #ifdef __BIG_ENDIAN_BITFIELD
3586 uint64_t reserved_1_63 : 63;
3587 uint64_t wdog : 1; /**< Watchdog summary interrupt enable vector */
3590 uint64_t reserved_1_63 : 63;
3593 struct cvmx_ciu_intx_en1_cn31xx {
3594 #ifdef __BIG_ENDIAN_BITFIELD
3595 uint64_t reserved_2_63 : 62;
3596 uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */
3599 uint64_t reserved_2_63 : 62;
3602 struct cvmx_ciu_intx_en1_cn38xx {
3603 #ifdef __BIG_ENDIAN_BITFIELD
3604 uint64_t reserved_16_63 : 48;
3605 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
3608 uint64_t reserved_16_63 : 48;
3611 struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
3612 struct cvmx_ciu_intx_en1_cn31xx cn50xx;
3613 struct cvmx_ciu_intx_en1_cn52xx {
3614 #ifdef __BIG_ENDIAN_BITFIELD
3615 uint64_t reserved_20_63 : 44;
3616 uint64_t nand : 1; /**< NAND Flash Controller */
3617 uint64_t mii1 : 1; /**< Second MII Interrupt */
3618 uint64_t usb1 : 1; /**< Second USB Interrupt */
3619 uint64_t uart2 : 1; /**< Third UART interrupt */
3620 uint64_t reserved_4_15 : 12;
3621 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
3624 uint64_t reserved_4_15 : 12;
3629 uint64_t reserved_20_63 : 44;
3632 struct cvmx_ciu_intx_en1_cn52xxp1 {
3633 #ifdef __BIG_ENDIAN_BITFIELD
3634 uint64_t reserved_19_63 : 45;
3635 uint64_t mii1 : 1; /**< Second MII Interrupt */
3636 uint64_t usb1 : 1; /**< Second USB Interrupt */
3637 uint64_t uart2 : 1; /**< Third UART interrupt */
3638 uint64_t reserved_4_15 : 12;
3639 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
3642 uint64_t reserved_4_15 : 12;
3646 uint64_t reserved_19_63 : 45;
3649 struct cvmx_ciu_intx_en1_cn56xx {
3650 #ifdef __BIG_ENDIAN_BITFIELD
3651 uint64_t reserved_12_63 : 52;
3652 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
3655 uint64_t reserved_12_63 : 52;
3658 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
3659 struct cvmx_ciu_intx_en1_cn38xx cn58xx;
3660 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
3661 struct cvmx_ciu_intx_en1_cn61xx {
3662 #ifdef __BIG_ENDIAN_BITFIELD
3663 uint64_t rst : 1; /**< MIO RST interrupt enable */
3664 uint64_t reserved_53_62 : 10;
3665 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
3666 uint64_t reserved_50_51 : 2;
3667 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
3668 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
3669 uint64_t ptp : 1; /**< PTP interrupt enable */
3670 uint64_t agl : 1; /**< AGL interrupt enable */
3671 uint64_t reserved_41_45 : 5;
3672 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
3673 uint64_t reserved_38_39 : 2;
3674 uint64_t agx1 : 1; /**< GMX1 interrupt enable */
3675 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
3676 uint64_t dpi : 1; /**< DPI interrupt enable */
3677 uint64_t sli : 1; /**< SLI interrupt enable */
3678 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
3679 uint64_t dfa : 1; /**< DFA interrupt enable */
3680 uint64_t key : 1; /**< KEY interrupt enable */
3681 uint64_t rad : 1; /**< RAD interrupt enable */
3682 uint64_t tim : 1; /**< TIM interrupt enable */
3683 uint64_t zip : 1; /**< ZIP interrupt enable */
3684 uint64_t pko : 1; /**< PKO interrupt enable */
3685 uint64_t pip : 1; /**< PIP interrupt enable */
3686 uint64_t ipd : 1; /**< IPD interrupt enable */
3687 uint64_t l2c : 1; /**< L2C interrupt enable */
3688 uint64_t pow : 1; /**< POW err interrupt enable */
3689 uint64_t fpa : 1; /**< FPA interrupt enable */
3690 uint64_t iob : 1; /**< IOB interrupt enable */
3691 uint64_t mio : 1; /**< MIO boot interrupt enable */
3692 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
3693 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt enable */
3694 uint64_t reserved_4_17 : 14;
3695 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
3698 uint64_t reserved_4_17 : 14;
3719 uint64_t reserved_38_39 : 2;
3720 uint64_t dpi_dma : 1;
3721 uint64_t reserved_41_45 : 5;
3726 uint64_t reserved_50_51 : 2;
3728 uint64_t reserved_53_62 : 10;
3732 struct cvmx_ciu_intx_en1_cn63xx {
3733 #ifdef __BIG_ENDIAN_BITFIELD
3734 uint64_t rst : 1; /**< MIO RST interrupt enable */
3735 uint64_t reserved_57_62 : 6;
3736 uint64_t dfm : 1; /**< DFM interrupt enable */
3737 uint64_t reserved_53_55 : 3;
3738 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
3739 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */
3740 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
3741 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
3742 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
3743 uint64_t ptp : 1; /**< PTP interrupt enable */
3744 uint64_t agl : 1; /**< AGL interrupt enable */
3745 uint64_t reserved_37_45 : 9;
3746 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
3747 uint64_t dpi : 1; /**< DPI interrupt enable */
3748 uint64_t sli : 1; /**< SLI interrupt enable */
3749 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
3750 uint64_t dfa : 1; /**< DFA interrupt enable */
3751 uint64_t key : 1; /**< KEY interrupt enable */
3752 uint64_t rad : 1; /**< RAD interrupt enable */
3753 uint64_t tim : 1; /**< TIM interrupt enable */
3754 uint64_t zip : 1; /**< ZIP interrupt enable */
3755 uint64_t pko : 1; /**< PKO interrupt enable */
3756 uint64_t pip : 1; /**< PIP interrupt enable */
3757 uint64_t ipd : 1; /**< IPD interrupt enable */
3758 uint64_t l2c : 1; /**< L2C interrupt enable */
3759 uint64_t pow : 1; /**< POW err interrupt enable */
3760 uint64_t fpa : 1; /**< FPA interrupt enable */
3761 uint64_t iob : 1; /**< IOB interrupt enable */
3762 uint64_t mio : 1; /**< MIO boot interrupt enable */
3763 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
3764 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
3765 uint64_t reserved_6_17 : 12;
3766 uint64_t wdog : 6; /**< Watchdog summary interrupt enable vector */
3769 uint64_t reserved_6_17 : 12;
3789 uint64_t reserved_37_45 : 9;
3797 uint64_t reserved_53_55 : 3;
3799 uint64_t reserved_57_62 : 6;
3803 struct cvmx_ciu_intx_en1_cn63xx cn63xxp1;
3804 struct cvmx_ciu_intx_en1_cn66xx {
3805 #ifdef __BIG_ENDIAN_BITFIELD
3806 uint64_t rst : 1; /**< MIO RST interrupt enable */
3807 uint64_t reserved_62_62 : 1;
3808 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
3809 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
3810 uint64_t reserved_57_59 : 3;
3811 uint64_t dfm : 1; /**< DFM interrupt enable */
3812 uint64_t reserved_53_55 : 3;
3813 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
3814 uint64_t reserved_51_51 : 1;
3815 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
3816 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
3817 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
3818 uint64_t ptp : 1; /**< PTP interrupt enable */
3819 uint64_t agl : 1; /**< AGL interrupt enable */
3820 uint64_t reserved_38_45 : 8;
3821 uint64_t agx1 : 1; /**< GMX1 interrupt enable */
3822 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
3823 uint64_t dpi : 1; /**< DPI interrupt enable */
3824 uint64_t sli : 1; /**< SLI interrupt enable */
3825 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
3826 uint64_t dfa : 1; /**< DFA interrupt enable */
3827 uint64_t key : 1; /**< KEY interrupt enable */
3828 uint64_t rad : 1; /**< RAD interrupt enable */
3829 uint64_t tim : 1; /**< TIM interrupt enable */
3830 uint64_t zip : 1; /**< ZIP interrupt enable */
3831 uint64_t pko : 1; /**< PKO interrupt enable */
3832 uint64_t pip : 1; /**< PIP interrupt enable */
3833 uint64_t ipd : 1; /**< IPD interrupt enable */
3834 uint64_t l2c : 1; /**< L2C interrupt enable */
3835 uint64_t pow : 1; /**< POW err interrupt enable */
3836 uint64_t fpa : 1; /**< FPA interrupt enable */
3837 uint64_t iob : 1; /**< IOB interrupt enable */
3838 uint64_t mio : 1; /**< MIO boot interrupt enable */
3839 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
3840 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
3841 uint64_t reserved_10_17 : 8;
3842 uint64_t wdog : 10; /**< Watchdog summary interrupt enable vector */
3845 uint64_t reserved_10_17 : 8;
3866 uint64_t reserved_38_45 : 8;
3872 uint64_t reserved_51_51 : 1;
3874 uint64_t reserved_53_55 : 3;
3876 uint64_t reserved_57_59 : 3;
3879 uint64_t reserved_62_62 : 1;
3883 struct cvmx_ciu_intx_en1_cnf71xx {
3884 #ifdef __BIG_ENDIAN_BITFIELD
3885 uint64_t rst : 1; /**< MIO RST interrupt enable */
3886 uint64_t reserved_53_62 : 10;
3887 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
3888 uint64_t reserved_50_51 : 2;
3889 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
3890 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
3891 uint64_t ptp : 1; /**< PTP interrupt enable */
3892 uint64_t reserved_41_46 : 6;
3893 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
3894 uint64_t reserved_37_39 : 3;
3895 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
3896 uint64_t dpi : 1; /**< DPI interrupt enable */
3897 uint64_t sli : 1; /**< SLI interrupt enable */
3898 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
3899 uint64_t reserved_32_32 : 1;
3900 uint64_t key : 1; /**< KEY interrupt enable */
3901 uint64_t rad : 1; /**< RAD interrupt enable */
3902 uint64_t tim : 1; /**< TIM interrupt enable */
3903 uint64_t reserved_28_28 : 1;
3904 uint64_t pko : 1; /**< PKO interrupt enable */
3905 uint64_t pip : 1; /**< PIP interrupt enable */
3906 uint64_t ipd : 1; /**< IPD interrupt enable */
3907 uint64_t l2c : 1; /**< L2C interrupt enable */
3908 uint64_t pow : 1; /**< POW err interrupt enable */
3909 uint64_t fpa : 1; /**< FPA interrupt enable */
3910 uint64_t iob : 1; /**< IOB interrupt enable */
3911 uint64_t mio : 1; /**< MIO boot interrupt enable */
3912 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
3913 uint64_t reserved_4_18 : 15;
3914 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
3917 uint64_t reserved_4_18 : 15;
3927 uint64_t reserved_28_28 : 1;
3931 uint64_t reserved_32_32 : 1;
3936 uint64_t reserved_37_39 : 3;
3937 uint64_t dpi_dma : 1;
3938 uint64_t reserved_41_46 : 6;
3942 uint64_t reserved_50_51 : 2;
3944 uint64_t reserved_53_62 : 10;
3949 typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t;
3952 * cvmx_ciu_int#_en1_w1c
3955 * Write-1-to-clear version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value.
3958 union cvmx_ciu_intx_en1_w1c {
3960 struct cvmx_ciu_intx_en1_w1c_s {
3961 #ifdef __BIG_ENDIAN_BITFIELD
3962 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
3963 uint64_t reserved_62_62 : 1;
3964 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
3965 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
3966 uint64_t reserved_57_59 : 3;
3967 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
3968 uint64_t reserved_53_55 : 3;
3969 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
3970 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */
3971 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
3972 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
3973 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
3974 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
3975 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
3976 uint64_t reserved_41_45 : 5;
3977 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
3978 uint64_t reserved_38_39 : 2;
3979 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
3980 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
3981 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
3982 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
3983 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
3984 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
3985 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
3986 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
3987 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
3988 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
3989 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
3990 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
3991 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
3992 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
3993 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
3994 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
3995 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
3996 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
3997 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
3999 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
4001 uint64_t usb1 : 1; /**< Second USB Interrupt */
4002 uint64_t uart2 : 1; /**< Third UART interrupt */
4003 uint64_t wdog : 16; /**< Write 1s to clear Watchdog summary interrupt enable */
4028 uint64_t reserved_38_39 : 2;
4029 uint64_t dpi_dma : 1;
4030 uint64_t reserved_41_45 : 5;
4038 uint64_t reserved_53_55 : 3;
4040 uint64_t reserved_57_59 : 3;
4043 uint64_t reserved_62_62 : 1;
4047 struct cvmx_ciu_intx_en1_w1c_cn52xx {
4048 #ifdef __BIG_ENDIAN_BITFIELD
4049 uint64_t reserved_20_63 : 44;
4050 uint64_t nand : 1; /**< NAND Flash Controller */
4051 uint64_t mii1 : 1; /**< Second MII Interrupt */
4052 uint64_t usb1 : 1; /**< Second USB Interrupt */
4053 uint64_t uart2 : 1; /**< Third UART interrupt */
4054 uint64_t reserved_4_15 : 12;
4055 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
4058 uint64_t reserved_4_15 : 12;
4063 uint64_t reserved_20_63 : 44;
4066 struct cvmx_ciu_intx_en1_w1c_cn56xx {
4067 #ifdef __BIG_ENDIAN_BITFIELD
4068 uint64_t reserved_12_63 : 52;
4069 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
4072 uint64_t reserved_12_63 : 52;
4075 struct cvmx_ciu_intx_en1_w1c_cn58xx {
4076 #ifdef __BIG_ENDIAN_BITFIELD
4077 uint64_t reserved_16_63 : 48;
4078 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
4081 uint64_t reserved_16_63 : 48;
4084 struct cvmx_ciu_intx_en1_w1c_cn61xx {
4085 #ifdef __BIG_ENDIAN_BITFIELD
4086 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
4087 uint64_t reserved_53_62 : 10;
4088 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
4089 uint64_t reserved_50_51 : 2;
4090 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
4091 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
4092 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
4093 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
4094 uint64_t reserved_41_45 : 5;
4095 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
4096 uint64_t reserved_38_39 : 2;
4097 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
4098 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
4099 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
4100 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
4101 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
4102 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
4103 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
4104 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
4105 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
4106 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
4107 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
4108 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
4109 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
4110 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
4111 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
4112 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
4113 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
4114 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
4115 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
4117 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MIX Interface 1
4119 uint64_t reserved_4_17 : 14;
4120 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
4123 uint64_t reserved_4_17 : 14;
4144 uint64_t reserved_38_39 : 2;
4145 uint64_t dpi_dma : 1;
4146 uint64_t reserved_41_45 : 5;
4151 uint64_t reserved_50_51 : 2;
4153 uint64_t reserved_53_62 : 10;
4157 struct cvmx_ciu_intx_en1_w1c_cn63xx {
4158 #ifdef __BIG_ENDIAN_BITFIELD
4159 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
4160 uint64_t reserved_57_62 : 6;
4161 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
4162 uint64_t reserved_53_55 : 3;
4163 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
4164 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */
4165 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
4166 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
4167 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
4168 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
4169 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
4170 uint64_t reserved_37_45 : 9;
4171 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
4172 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
4173 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
4174 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
4175 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
4176 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
4177 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
4178 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
4179 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
4180 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
4181 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
4182 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
4183 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
4184 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
4185 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
4186 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
4187 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
4188 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
4190 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
4192 uint64_t reserved_6_17 : 12;
4193 uint64_t wdog : 6; /**< Write 1s to clear Watchdog summary interrupt enable */
4196 uint64_t reserved_6_17 : 12;
4216 uint64_t reserved_37_45 : 9;
4224 uint64_t reserved_53_55 : 3;
4226 uint64_t reserved_57_62 : 6;
4230 struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1;
4231 struct cvmx_ciu_intx_en1_w1c_cn66xx {
4232 #ifdef __BIG_ENDIAN_BITFIELD
4233 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
4234 uint64_t reserved_62_62 : 1;
4235 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
4236 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
4237 uint64_t reserved_57_59 : 3;
4238 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
4239 uint64_t reserved_53_55 : 3;
4240 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
4241 uint64_t reserved_51_51 : 1;
4242 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
4243 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
4244 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
4245 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
4246 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
4247 uint64_t reserved_38_45 : 8;
4248 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
4249 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
4250 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
4251 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
4252 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
4253 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
4254 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
4255 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
4256 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
4257 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
4258 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
4259 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
4260 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
4261 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
4262 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
4263 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
4264 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
4265 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
4266 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
4268 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
4270 uint64_t reserved_10_17 : 8;
4271 uint64_t wdog : 10; /**< Write 1s to clear Watchdog summary interrupt enable */
4274 uint64_t reserved_10_17 : 8;
4295 uint64_t reserved_38_45 : 8;
4301 uint64_t reserved_51_51 : 1;
4303 uint64_t reserved_53_55 : 3;
4305 uint64_t reserved_57_59 : 3;
4308 uint64_t reserved_62_62 : 1;
4312 struct cvmx_ciu_intx_en1_w1c_cnf71xx {
4313 #ifdef __BIG_ENDIAN_BITFIELD
4314 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
4315 uint64_t reserved_53_62 : 10;
4316 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
4317 uint64_t reserved_50_51 : 2;
4318 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
4319 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
4320 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
4321 uint64_t reserved_41_46 : 6;
4322 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
4323 uint64_t reserved_37_39 : 3;
4324 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
4325 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
4326 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
4327 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
4328 uint64_t reserved_32_32 : 1;
4329 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
4330 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
4331 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
4332 uint64_t reserved_28_28 : 1;
4333 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
4334 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
4335 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
4336 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
4337 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
4338 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
4339 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
4340 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
4341 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
4343 uint64_t reserved_4_18 : 15;
4344 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
4347 uint64_t reserved_4_18 : 15;
4357 uint64_t reserved_28_28 : 1;
4361 uint64_t reserved_32_32 : 1;
4366 uint64_t reserved_37_39 : 3;
4367 uint64_t dpi_dma : 1;
4368 uint64_t reserved_41_46 : 6;
4372 uint64_t reserved_50_51 : 2;
4374 uint64_t reserved_53_62 : 10;
4379 typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t;
4382 * cvmx_ciu_int#_en1_w1s
4385 * Write-1-to-set version of the CIU_INTX_EN1 register, read back corresponding CIU_INTX_EN1 value.
4388 union cvmx_ciu_intx_en1_w1s {
4390 struct cvmx_ciu_intx_en1_w1s_s {
4391 #ifdef __BIG_ENDIAN_BITFIELD
4392 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
4393 uint64_t reserved_62_62 : 1;
4394 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
4395 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
4396 uint64_t reserved_57_59 : 3;
4397 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
4398 uint64_t reserved_53_55 : 3;
4399 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
4400 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */
4401 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
4402 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
4403 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
4404 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
4405 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
4406 uint64_t reserved_41_45 : 5;
4407 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
4408 uint64_t reserved_38_39 : 2;
4409 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
4410 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
4411 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
4412 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
4413 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
4414 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
4415 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
4416 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
4417 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
4418 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
4419 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
4420 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
4421 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
4422 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
4423 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
4424 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
4425 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
4426 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
4427 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
4429 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
4431 uint64_t usb1 : 1; /**< Second USB Interrupt */
4432 uint64_t uart2 : 1; /**< Third UART interrupt */
4433 uint64_t wdog : 16; /**< Write 1s to set Watchdog summary interrupt enable */
4458 uint64_t reserved_38_39 : 2;
4459 uint64_t dpi_dma : 1;
4460 uint64_t reserved_41_45 : 5;
4468 uint64_t reserved_53_55 : 3;
4470 uint64_t reserved_57_59 : 3;
4473 uint64_t reserved_62_62 : 1;
4477 struct cvmx_ciu_intx_en1_w1s_cn52xx {
4478 #ifdef __BIG_ENDIAN_BITFIELD
4479 uint64_t reserved_20_63 : 44;
4480 uint64_t nand : 1; /**< NAND Flash Controller */
4481 uint64_t mii1 : 1; /**< Second MII Interrupt */
4482 uint64_t usb1 : 1; /**< Second USB Interrupt */
4483 uint64_t uart2 : 1; /**< Third UART interrupt */
4484 uint64_t reserved_4_15 : 12;
4485 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
4488 uint64_t reserved_4_15 : 12;
4493 uint64_t reserved_20_63 : 44;
4496 struct cvmx_ciu_intx_en1_w1s_cn56xx {
4497 #ifdef __BIG_ENDIAN_BITFIELD
4498 uint64_t reserved_12_63 : 52;
4499 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
4502 uint64_t reserved_12_63 : 52;
4505 struct cvmx_ciu_intx_en1_w1s_cn58xx {
4506 #ifdef __BIG_ENDIAN_BITFIELD
4507 uint64_t reserved_16_63 : 48;
4508 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
4511 uint64_t reserved_16_63 : 48;
4514 struct cvmx_ciu_intx_en1_w1s_cn61xx {
4515 #ifdef __BIG_ENDIAN_BITFIELD
4516 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
4517 uint64_t reserved_53_62 : 10;
4518 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
4519 uint64_t reserved_50_51 : 2;
4520 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
4521 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
4522 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
4523 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
4524 uint64_t reserved_41_45 : 5;
4525 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
4526 uint64_t reserved_38_39 : 2;
4527 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
4528 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
4529 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
4530 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
4531 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
4532 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
4533 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
4534 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
4535 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
4536 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
4537 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
4538 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
4539 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
4540 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
4541 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
4542 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
4543 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
4544 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
4545 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
4547 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MIX Interface 1 Interrupt
4549 uint64_t reserved_4_17 : 14;
4550 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
4553 uint64_t reserved_4_17 : 14;
4574 uint64_t reserved_38_39 : 2;
4575 uint64_t dpi_dma : 1;
4576 uint64_t reserved_41_45 : 5;
4581 uint64_t reserved_50_51 : 2;
4583 uint64_t reserved_53_62 : 10;
4587 struct cvmx_ciu_intx_en1_w1s_cn63xx {
4588 #ifdef __BIG_ENDIAN_BITFIELD
4589 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
4590 uint64_t reserved_57_62 : 6;
4591 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
4592 uint64_t reserved_53_55 : 3;
4593 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
4594 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */
4595 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
4596 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
4597 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
4598 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
4599 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
4600 uint64_t reserved_37_45 : 9;
4601 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
4602 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
4603 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
4604 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
4605 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
4606 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
4607 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
4608 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
4609 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
4610 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
4611 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
4612 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
4613 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
4614 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
4615 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
4616 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
4617 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
4618 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
4620 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
4622 uint64_t reserved_6_17 : 12;
4623 uint64_t wdog : 6; /**< Write 1s to set Watchdog summary interrupt enable */
4626 uint64_t reserved_6_17 : 12;
4646 uint64_t reserved_37_45 : 9;
4654 uint64_t reserved_53_55 : 3;
4656 uint64_t reserved_57_62 : 6;
4660 struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1;
4661 struct cvmx_ciu_intx_en1_w1s_cn66xx {
4662 #ifdef __BIG_ENDIAN_BITFIELD
4663 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
4664 uint64_t reserved_62_62 : 1;
4665 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
4666 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
4667 uint64_t reserved_57_59 : 3;
4668 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
4669 uint64_t reserved_53_55 : 3;
4670 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
4671 uint64_t reserved_51_51 : 1;
4672 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
4673 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
4674 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
4675 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
4676 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
4677 uint64_t reserved_38_45 : 8;
4678 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
4679 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
4680 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
4681 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
4682 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
4683 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
4684 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
4685 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
4686 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
4687 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
4688 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
4689 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
4690 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
4691 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
4692 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
4693 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
4694 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
4695 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
4696 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
4698 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
4700 uint64_t reserved_10_17 : 8;
4701 uint64_t wdog : 10; /**< Write 1s to set Watchdog summary interrupt enable */
4704 uint64_t reserved_10_17 : 8;
4725 uint64_t reserved_38_45 : 8;
4731 uint64_t reserved_51_51 : 1;
4733 uint64_t reserved_53_55 : 3;
4735 uint64_t reserved_57_59 : 3;
4738 uint64_t reserved_62_62 : 1;
4742 struct cvmx_ciu_intx_en1_w1s_cnf71xx {
4743 #ifdef __BIG_ENDIAN_BITFIELD
4744 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
4745 uint64_t reserved_53_62 : 10;
4746 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
4747 uint64_t reserved_50_51 : 2;
4748 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
4749 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
4750 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
4751 uint64_t reserved_41_46 : 6;
4752 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
4753 uint64_t reserved_37_39 : 3;
4754 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
4755 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
4756 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
4757 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
4758 uint64_t reserved_32_32 : 1;
4759 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
4760 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
4761 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
4762 uint64_t reserved_28_28 : 1;
4763 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
4764 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
4765 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
4766 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
4767 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
4768 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
4769 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
4770 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
4771 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
4773 uint64_t reserved_4_18 : 15;
4774 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
4777 uint64_t reserved_4_18 : 15;
4787 uint64_t reserved_28_28 : 1;
4791 uint64_t reserved_32_32 : 1;
4796 uint64_t reserved_37_39 : 3;
4797 uint64_t dpi_dma : 1;
4798 uint64_t reserved_41_46 : 6;
4802 uint64_t reserved_50_51 : 2;
4804 uint64_t reserved_53_62 : 10;
4809 typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t;
4812 * cvmx_ciu_int#_en4_0
4815 * CIU_INT0_EN4_0: PP0 /IP4
4816 * CIU_INT1_EN4_0: PP1 /IP4
4818 * CIU_INT3_EN4_0: PP3 /IP4
4820 union cvmx_ciu_intx_en4_0 {
4822 struct cvmx_ciu_intx_en4_0_s {
4823 #ifdef __BIG_ENDIAN_BITFIELD
4824 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
4825 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
4826 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
4827 uint64_t powiq : 1; /**< POW IQ interrupt enable */
4828 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
4829 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
4830 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
4831 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
4832 uint64_t timer : 4; /**< General timer interrupt enables */
4833 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
4834 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
4835 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
4836 uint64_t trace : 1; /**< Trace buffer interrupt enable */
4837 uint64_t rml : 1; /**< RML Interrupt enable */
4838 uint64_t twsi : 1; /**< TWSI Interrupt enable */
4839 uint64_t reserved_44_44 : 1;
4840 uint64_t pci_msi : 4; /**< PCIe MSI enables */
4841 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
4842 uint64_t uart : 2; /**< Two UART interrupt enables */
4843 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
4844 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
4845 uint64_t workq : 16; /**< 16 work queue interrupt enables */
4847 uint64_t workq : 16;
4851 uint64_t pci_int : 4;
4852 uint64_t pci_msi : 4;
4853 uint64_t reserved_44_44 : 1;
4857 uint64_t gmx_drp : 2;
4858 uint64_t ipd_drp : 1;
4859 uint64_t key_zero : 1;
4866 uint64_t ipdppthr : 1;
4868 uint64_t bootdma : 1;
4871 struct cvmx_ciu_intx_en4_0_cn50xx {
4872 #ifdef __BIG_ENDIAN_BITFIELD
4873 uint64_t reserved_59_63 : 5;
4874 uint64_t mpi : 1; /**< MPI/SPI interrupt */
4875 uint64_t pcm : 1; /**< PCM/TDM interrupt */
4876 uint64_t usb : 1; /**< USB interrupt */
4877 uint64_t timer : 4; /**< General timer interrupts */
4878 uint64_t reserved_51_51 : 1;
4879 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
4880 uint64_t reserved_49_49 : 1;
4881 uint64_t gmx_drp : 1; /**< GMX packet drop */
4882 uint64_t reserved_47_47 : 1;
4883 uint64_t rml : 1; /**< RML Interrupt */
4884 uint64_t twsi : 1; /**< TWSI Interrupt */
4885 uint64_t reserved_44_44 : 1;
4886 uint64_t pci_msi : 4; /**< PCI MSI */
4887 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
4888 uint64_t uart : 2; /**< Two UART interrupts */
4889 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
4890 uint64_t gpio : 16; /**< 16 GPIO interrupts */
4891 uint64_t workq : 16; /**< 16 work queue interrupts */
4893 uint64_t workq : 16;
4897 uint64_t pci_int : 4;
4898 uint64_t pci_msi : 4;
4899 uint64_t reserved_44_44 : 1;
4902 uint64_t reserved_47_47 : 1;
4903 uint64_t gmx_drp : 1;
4904 uint64_t reserved_49_49 : 1;
4905 uint64_t ipd_drp : 1;
4906 uint64_t reserved_51_51 : 1;
4911 uint64_t reserved_59_63 : 5;
4914 struct cvmx_ciu_intx_en4_0_cn52xx {
4915 #ifdef __BIG_ENDIAN_BITFIELD
4916 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
4917 uint64_t mii : 1; /**< MII Interface Interrupt */
4918 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
4919 uint64_t powiq : 1; /**< POW IQ interrupt */
4920 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
4921 uint64_t reserved_57_58 : 2;
4922 uint64_t usb : 1; /**< USB Interrupt */
4923 uint64_t timer : 4; /**< General timer interrupts */
4924 uint64_t reserved_51_51 : 1;
4925 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
4926 uint64_t reserved_49_49 : 1;
4927 uint64_t gmx_drp : 1; /**< GMX packet drop */
4928 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
4929 uint64_t rml : 1; /**< RML Interrupt */
4930 uint64_t twsi : 1; /**< TWSI Interrupt */
4931 uint64_t reserved_44_44 : 1;
4932 uint64_t pci_msi : 4; /**< PCI MSI */
4933 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
4934 uint64_t uart : 2; /**< Two UART interrupts */
4935 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
4936 uint64_t gpio : 16; /**< 16 GPIO interrupts */
4937 uint64_t workq : 16; /**< 16 work queue interrupts */
4939 uint64_t workq : 16;
4943 uint64_t pci_int : 4;
4944 uint64_t pci_msi : 4;
4945 uint64_t reserved_44_44 : 1;
4949 uint64_t gmx_drp : 1;
4950 uint64_t reserved_49_49 : 1;
4951 uint64_t ipd_drp : 1;
4952 uint64_t reserved_51_51 : 1;
4955 uint64_t reserved_57_58 : 2;
4958 uint64_t ipdppthr : 1;
4960 uint64_t bootdma : 1;
4963 struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
4964 struct cvmx_ciu_intx_en4_0_cn56xx {
4965 #ifdef __BIG_ENDIAN_BITFIELD
4966 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
4967 uint64_t mii : 1; /**< MII Interface Interrupt */
4968 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
4969 uint64_t powiq : 1; /**< POW IQ interrupt */
4970 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
4971 uint64_t reserved_57_58 : 2;
4972 uint64_t usb : 1; /**< USB Interrupt */
4973 uint64_t timer : 4; /**< General timer interrupts */
4974 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
4975 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
4976 uint64_t gmx_drp : 2; /**< GMX packet drop */
4977 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
4978 uint64_t rml : 1; /**< RML Interrupt */
4979 uint64_t twsi : 1; /**< TWSI Interrupt */
4980 uint64_t reserved_44_44 : 1;
4981 uint64_t pci_msi : 4; /**< PCI MSI */
4982 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
4983 uint64_t uart : 2; /**< Two UART interrupts */
4984 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
4985 uint64_t gpio : 16; /**< 16 GPIO interrupts */
4986 uint64_t workq : 16; /**< 16 work queue interrupts */
4988 uint64_t workq : 16;
4992 uint64_t pci_int : 4;
4993 uint64_t pci_msi : 4;
4994 uint64_t reserved_44_44 : 1;
4998 uint64_t gmx_drp : 2;
4999 uint64_t ipd_drp : 1;
5000 uint64_t key_zero : 1;
5003 uint64_t reserved_57_58 : 2;
5006 uint64_t ipdppthr : 1;
5008 uint64_t bootdma : 1;
5011 struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
5012 struct cvmx_ciu_intx_en4_0_cn58xx {
5013 #ifdef __BIG_ENDIAN_BITFIELD
5014 uint64_t reserved_56_63 : 8;
5015 uint64_t timer : 4; /**< General timer interrupts */
5016 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
5017 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
5018 uint64_t gmx_drp : 2; /**< GMX packet drop */
5019 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
5020 uint64_t rml : 1; /**< RML Interrupt */
5021 uint64_t twsi : 1; /**< TWSI Interrupt */
5022 uint64_t reserved_44_44 : 1;
5023 uint64_t pci_msi : 4; /**< PCI MSI */
5024 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
5025 uint64_t uart : 2; /**< Two UART interrupts */
5026 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5027 uint64_t gpio : 16; /**< 16 GPIO interrupts */
5028 uint64_t workq : 16; /**< 16 work queue interrupts */
5030 uint64_t workq : 16;
5034 uint64_t pci_int : 4;
5035 uint64_t pci_msi : 4;
5036 uint64_t reserved_44_44 : 1;
5040 uint64_t gmx_drp : 2;
5041 uint64_t ipd_drp : 1;
5042 uint64_t key_zero : 1;
5044 uint64_t reserved_56_63 : 8;
5047 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
5048 struct cvmx_ciu_intx_en4_0_cn61xx {
5049 #ifdef __BIG_ENDIAN_BITFIELD
5050 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
5051 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt enable */
5052 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
5053 uint64_t powiq : 1; /**< POW IQ interrupt enable */
5054 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
5055 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
5056 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
5057 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
5058 uint64_t timer : 4; /**< General timer interrupt enables */
5059 uint64_t reserved_51_51 : 1;
5060 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
5061 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
5062 uint64_t trace : 1; /**< Trace buffer interrupt enable */
5063 uint64_t rml : 1; /**< RML Interrupt enable */
5064 uint64_t twsi : 1; /**< TWSI Interrupt enable */
5065 uint64_t reserved_44_44 : 1;
5066 uint64_t pci_msi : 4; /**< PCIe MSI enables */
5067 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
5068 uint64_t uart : 2; /**< Two UART interrupt enables */
5069 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
5070 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
5071 uint64_t workq : 16; /**< 16 work queue interrupt enables */
5073 uint64_t workq : 16;
5077 uint64_t pci_int : 4;
5078 uint64_t pci_msi : 4;
5079 uint64_t reserved_44_44 : 1;
5083 uint64_t gmx_drp : 2;
5084 uint64_t ipd_drp : 1;
5085 uint64_t reserved_51_51 : 1;
5092 uint64_t ipdppthr : 1;
5094 uint64_t bootdma : 1;
5097 struct cvmx_ciu_intx_en4_0_cn52xx cn63xx;
5098 struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1;
5099 struct cvmx_ciu_intx_en4_0_cn66xx {
5100 #ifdef __BIG_ENDIAN_BITFIELD
5101 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
5102 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */
5103 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
5104 uint64_t powiq : 1; /**< POW IQ interrupt enable */
5105 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
5106 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
5107 uint64_t reserved_57_57 : 1;
5108 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
5109 uint64_t timer : 4; /**< General timer interrupt enables */
5110 uint64_t reserved_51_51 : 1;
5111 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
5112 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */
5113 uint64_t trace : 1; /**< Trace buffer interrupt enable */
5114 uint64_t rml : 1; /**< RML Interrupt enable */
5115 uint64_t twsi : 1; /**< TWSI Interrupt enable */
5116 uint64_t reserved_44_44 : 1;
5117 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */
5118 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
5119 uint64_t uart : 2; /**< Two UART interrupt enables */
5120 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
5121 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
5122 uint64_t workq : 16; /**< 16 work queue interrupt enables */
5124 uint64_t workq : 16;
5128 uint64_t pci_int : 4;
5129 uint64_t pci_msi : 4;
5130 uint64_t reserved_44_44 : 1;
5134 uint64_t gmx_drp : 2;
5135 uint64_t ipd_drp : 1;
5136 uint64_t reserved_51_51 : 1;
5139 uint64_t reserved_57_57 : 1;
5143 uint64_t ipdppthr : 1;
5145 uint64_t bootdma : 1;
5148 struct cvmx_ciu_intx_en4_0_cnf71xx {
5149 #ifdef __BIG_ENDIAN_BITFIELD
5150 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */
5151 uint64_t reserved_62_62 : 1;
5152 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */
5153 uint64_t powiq : 1; /**< POW IQ interrupt enable */
5154 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */
5155 uint64_t mpi : 1; /**< MPI/SPI interrupt enable */
5156 uint64_t pcm : 1; /**< PCM/TDM interrupt enable */
5157 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */
5158 uint64_t timer : 4; /**< General timer interrupt enables */
5159 uint64_t reserved_51_51 : 1;
5160 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */
5161 uint64_t reserved_49_49 : 1;
5162 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt enable */
5163 uint64_t trace : 1; /**< Trace buffer interrupt enable */
5164 uint64_t rml : 1; /**< RML Interrupt enable */
5165 uint64_t twsi : 1; /**< TWSI Interrupt enable */
5166 uint64_t reserved_44_44 : 1;
5167 uint64_t pci_msi : 4; /**< PCIe MSI enables */
5168 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */
5169 uint64_t uart : 2; /**< Two UART interrupt enables */
5170 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
5171 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */
5172 uint64_t workq : 16; /**< 16 work queue interrupt enables */
5174 uint64_t workq : 16;
5178 uint64_t pci_int : 4;
5179 uint64_t pci_msi : 4;
5180 uint64_t reserved_44_44 : 1;
5184 uint64_t gmx_drp : 1;
5185 uint64_t reserved_49_49 : 1;
5186 uint64_t ipd_drp : 1;
5187 uint64_t reserved_51_51 : 1;
5194 uint64_t ipdppthr : 1;
5195 uint64_t reserved_62_62 : 1;
5196 uint64_t bootdma : 1;
5200 typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t;
5203 * cvmx_ciu_int#_en4_0_w1c
5206 * Write-1-to-clear version of the CIU_INTx_EN4_0 register, read back corresponding CIU_INTx_EN4_0 value.
5209 union cvmx_ciu_intx_en4_0_w1c {
5211 struct cvmx_ciu_intx_en4_0_w1c_s {
5212 #ifdef __BIG_ENDIAN_BITFIELD
5213 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
5215 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
5217 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
5219 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
5220 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
5221 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
5222 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
5223 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
5224 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
5225 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
5226 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
5228 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
5229 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
5230 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
5231 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
5232 uint64_t reserved_44_44 : 1;
5233 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
5234 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
5235 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
5236 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5237 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
5238 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
5240 uint64_t workq : 16;
5244 uint64_t pci_int : 4;
5245 uint64_t pci_msi : 4;
5246 uint64_t reserved_44_44 : 1;
5250 uint64_t gmx_drp : 2;
5251 uint64_t ipd_drp : 1;
5252 uint64_t key_zero : 1;
5259 uint64_t ipdppthr : 1;
5261 uint64_t bootdma : 1;
5264 struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
5265 #ifdef __BIG_ENDIAN_BITFIELD
5266 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
5267 uint64_t mii : 1; /**< MII Interface Interrupt */
5268 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
5269 uint64_t powiq : 1; /**< POW IQ interrupt */
5270 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
5271 uint64_t reserved_57_58 : 2;
5272 uint64_t usb : 1; /**< USB Interrupt */
5273 uint64_t timer : 4; /**< General timer interrupts */
5274 uint64_t reserved_51_51 : 1;
5275 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
5276 uint64_t reserved_49_49 : 1;
5277 uint64_t gmx_drp : 1; /**< GMX packet drop */
5278 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
5279 uint64_t rml : 1; /**< RML Interrupt */
5280 uint64_t twsi : 1; /**< TWSI Interrupt */
5281 uint64_t reserved_44_44 : 1;
5282 uint64_t pci_msi : 4; /**< PCI MSI */
5283 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
5284 uint64_t uart : 2; /**< Two UART interrupts */
5285 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5286 uint64_t gpio : 16; /**< 16 GPIO interrupts */
5287 uint64_t workq : 16; /**< 16 work queue interrupts */
5289 uint64_t workq : 16;
5293 uint64_t pci_int : 4;
5294 uint64_t pci_msi : 4;
5295 uint64_t reserved_44_44 : 1;
5299 uint64_t gmx_drp : 1;
5300 uint64_t reserved_49_49 : 1;
5301 uint64_t ipd_drp : 1;
5302 uint64_t reserved_51_51 : 1;
5305 uint64_t reserved_57_58 : 2;
5308 uint64_t ipdppthr : 1;
5310 uint64_t bootdma : 1;
5313 struct cvmx_ciu_intx_en4_0_w1c_cn56xx {
5314 #ifdef __BIG_ENDIAN_BITFIELD
5315 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
5316 uint64_t mii : 1; /**< MII Interface Interrupt */
5317 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
5318 uint64_t powiq : 1; /**< POW IQ interrupt */
5319 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
5320 uint64_t reserved_57_58 : 2;
5321 uint64_t usb : 1; /**< USB Interrupt */
5322 uint64_t timer : 4; /**< General timer interrupts */
5323 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
5324 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
5325 uint64_t gmx_drp : 2; /**< GMX packet drop */
5326 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
5327 uint64_t rml : 1; /**< RML Interrupt */
5328 uint64_t twsi : 1; /**< TWSI Interrupt */
5329 uint64_t reserved_44_44 : 1;
5330 uint64_t pci_msi : 4; /**< PCI MSI */
5331 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
5332 uint64_t uart : 2; /**< Two UART interrupts */
5333 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5334 uint64_t gpio : 16; /**< 16 GPIO interrupts */
5335 uint64_t workq : 16; /**< 16 work queue interrupts */
5337 uint64_t workq : 16;
5341 uint64_t pci_int : 4;
5342 uint64_t pci_msi : 4;
5343 uint64_t reserved_44_44 : 1;
5347 uint64_t gmx_drp : 2;
5348 uint64_t ipd_drp : 1;
5349 uint64_t key_zero : 1;
5352 uint64_t reserved_57_58 : 2;
5355 uint64_t ipdppthr : 1;
5357 uint64_t bootdma : 1;
5360 struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
5361 #ifdef __BIG_ENDIAN_BITFIELD
5362 uint64_t reserved_56_63 : 8;
5363 uint64_t timer : 4; /**< General timer interrupts */
5364 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
5365 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
5366 uint64_t gmx_drp : 2; /**< GMX packet drop */
5367 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
5368 uint64_t rml : 1; /**< RML Interrupt */
5369 uint64_t twsi : 1; /**< TWSI Interrupt */
5370 uint64_t reserved_44_44 : 1;
5371 uint64_t pci_msi : 4; /**< PCI MSI */
5372 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
5373 uint64_t uart : 2; /**< Two UART interrupts */
5374 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5375 uint64_t gpio : 16; /**< 16 GPIO interrupts */
5376 uint64_t workq : 16; /**< 16 work queue interrupts */
5378 uint64_t workq : 16;
5382 uint64_t pci_int : 4;
5383 uint64_t pci_msi : 4;
5384 uint64_t reserved_44_44 : 1;
5388 uint64_t gmx_drp : 2;
5389 uint64_t ipd_drp : 1;
5390 uint64_t key_zero : 1;
5392 uint64_t reserved_56_63 : 8;
5395 struct cvmx_ciu_intx_en4_0_w1c_cn61xx {
5396 #ifdef __BIG_ENDIAN_BITFIELD
5397 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
5399 uint64_t mii : 1; /**< Write 1 to clr RGMII/MIX Interface 0 Interrupt
5401 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
5403 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
5404 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
5405 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
5406 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
5407 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
5408 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
5409 uint64_t reserved_51_51 : 1;
5410 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
5412 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
5413 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
5414 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
5415 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
5416 uint64_t reserved_44_44 : 1;
5417 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
5418 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
5419 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
5420 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5421 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
5422 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
5424 uint64_t workq : 16;
5428 uint64_t pci_int : 4;
5429 uint64_t pci_msi : 4;
5430 uint64_t reserved_44_44 : 1;
5434 uint64_t gmx_drp : 2;
5435 uint64_t ipd_drp : 1;
5436 uint64_t reserved_51_51 : 1;
5443 uint64_t ipdppthr : 1;
5445 uint64_t bootdma : 1;
5448 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx;
5449 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1;
5450 struct cvmx_ciu_intx_en4_0_w1c_cn66xx {
5451 #ifdef __BIG_ENDIAN_BITFIELD
5452 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
5454 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt
5456 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
5458 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */
5459 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */
5460 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt */
5461 uint64_t reserved_57_57 : 1;
5462 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */
5463 uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */
5464 uint64_t reserved_51_51 : 1;
5465 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
5467 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */
5468 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
5469 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
5470 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
5471 uint64_t reserved_44_44 : 1;
5472 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */
5473 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
5474 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
5475 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5476 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
5477 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
5479 uint64_t workq : 16;
5483 uint64_t pci_int : 4;
5484 uint64_t pci_msi : 4;
5485 uint64_t reserved_44_44 : 1;
5489 uint64_t gmx_drp : 2;
5490 uint64_t ipd_drp : 1;
5491 uint64_t reserved_51_51 : 1;
5494 uint64_t reserved_57_57 : 1;
5498 uint64_t ipdppthr : 1;
5500 uint64_t bootdma : 1;
5503 struct cvmx_ciu_intx_en4_0_w1c_cnf71xx {
5504 #ifdef __BIG_ENDIAN_BITFIELD
5505 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt
5507 uint64_t reserved_62_62 : 1;
5508 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold
5510 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt enable */
5511 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt enable */
5512 uint64_t mpi : 1; /**< Write 1 to clear MPI/SPI interrupt enable */
5513 uint64_t pcm : 1; /**< Write 1 to clear PCM/TDM interrupt enable */
5514 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt enable */
5515 uint64_t timer : 4; /**< Write 1 to clear General timer interrupt enables */
5516 uint64_t reserved_51_51 : 1;
5517 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt
5519 uint64_t reserved_49_49 : 1;
5520 uint64_t gmx_drp : 1; /**< Write 1 to clear GMX packet drop interrupt enable */
5521 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */
5522 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */
5523 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */
5524 uint64_t reserved_44_44 : 1;
5525 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe MSI enables */
5526 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */
5527 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */
5528 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5529 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */
5530 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */
5532 uint64_t workq : 16;
5536 uint64_t pci_int : 4;
5537 uint64_t pci_msi : 4;
5538 uint64_t reserved_44_44 : 1;
5542 uint64_t gmx_drp : 1;
5543 uint64_t reserved_49_49 : 1;
5544 uint64_t ipd_drp : 1;
5545 uint64_t reserved_51_51 : 1;
5552 uint64_t ipdppthr : 1;
5553 uint64_t reserved_62_62 : 1;
5554 uint64_t bootdma : 1;
5558 typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t;
5561 * cvmx_ciu_int#_en4_0_w1s
5564 * Write-1-to-set version of the CIU_INTX_EN4_0 register, read back corresponding CIU_INTX_EN4_0 value.
5567 union cvmx_ciu_intx_en4_0_w1s {
5569 struct cvmx_ciu_intx_en4_0_w1s_s {
5570 #ifdef __BIG_ENDIAN_BITFIELD
5571 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
5573 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
5575 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
5577 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
5578 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
5579 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
5580 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
5581 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
5582 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
5583 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
5584 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
5586 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
5587 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
5588 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
5589 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
5590 uint64_t reserved_44_44 : 1;
5591 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
5592 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
5593 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
5594 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5595 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
5596 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
5598 uint64_t workq : 16;
5602 uint64_t pci_int : 4;
5603 uint64_t pci_msi : 4;
5604 uint64_t reserved_44_44 : 1;
5608 uint64_t gmx_drp : 2;
5609 uint64_t ipd_drp : 1;
5610 uint64_t key_zero : 1;
5617 uint64_t ipdppthr : 1;
5619 uint64_t bootdma : 1;
5622 struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
5623 #ifdef __BIG_ENDIAN_BITFIELD
5624 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
5625 uint64_t mii : 1; /**< MII Interface Interrupt */
5626 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
5627 uint64_t powiq : 1; /**< POW IQ interrupt */
5628 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
5629 uint64_t reserved_57_58 : 2;
5630 uint64_t usb : 1; /**< USB Interrupt */
5631 uint64_t timer : 4; /**< General timer interrupts */
5632 uint64_t reserved_51_51 : 1;
5633 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
5634 uint64_t reserved_49_49 : 1;
5635 uint64_t gmx_drp : 1; /**< GMX packet drop */
5636 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
5637 uint64_t rml : 1; /**< RML Interrupt */
5638 uint64_t twsi : 1; /**< TWSI Interrupt */
5639 uint64_t reserved_44_44 : 1;
5640 uint64_t pci_msi : 4; /**< PCI MSI */
5641 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
5642 uint64_t uart : 2; /**< Two UART interrupts */
5643 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5644 uint64_t gpio : 16; /**< 16 GPIO interrupts */
5645 uint64_t workq : 16; /**< 16 work queue interrupts */
5647 uint64_t workq : 16;
5651 uint64_t pci_int : 4;
5652 uint64_t pci_msi : 4;
5653 uint64_t reserved_44_44 : 1;
5657 uint64_t gmx_drp : 1;
5658 uint64_t reserved_49_49 : 1;
5659 uint64_t ipd_drp : 1;
5660 uint64_t reserved_51_51 : 1;
5663 uint64_t reserved_57_58 : 2;
5666 uint64_t ipdppthr : 1;
5668 uint64_t bootdma : 1;
5671 struct cvmx_ciu_intx_en4_0_w1s_cn56xx {
5672 #ifdef __BIG_ENDIAN_BITFIELD
5673 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
5674 uint64_t mii : 1; /**< MII Interface Interrupt */
5675 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
5676 uint64_t powiq : 1; /**< POW IQ interrupt */
5677 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
5678 uint64_t reserved_57_58 : 2;
5679 uint64_t usb : 1; /**< USB Interrupt */
5680 uint64_t timer : 4; /**< General timer interrupts */
5681 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
5682 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
5683 uint64_t gmx_drp : 2; /**< GMX packet drop */
5684 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
5685 uint64_t rml : 1; /**< RML Interrupt */
5686 uint64_t twsi : 1; /**< TWSI Interrupt */
5687 uint64_t reserved_44_44 : 1;
5688 uint64_t pci_msi : 4; /**< PCI MSI */
5689 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
5690 uint64_t uart : 2; /**< Two UART interrupts */
5691 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5692 uint64_t gpio : 16; /**< 16 GPIO interrupts */
5693 uint64_t workq : 16; /**< 16 work queue interrupts */
5695 uint64_t workq : 16;
5699 uint64_t pci_int : 4;
5700 uint64_t pci_msi : 4;
5701 uint64_t reserved_44_44 : 1;
5705 uint64_t gmx_drp : 2;
5706 uint64_t ipd_drp : 1;
5707 uint64_t key_zero : 1;
5710 uint64_t reserved_57_58 : 2;
5713 uint64_t ipdppthr : 1;
5715 uint64_t bootdma : 1;
5718 struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
5719 #ifdef __BIG_ENDIAN_BITFIELD
5720 uint64_t reserved_56_63 : 8;
5721 uint64_t timer : 4; /**< General timer interrupts */
5722 uint64_t key_zero : 1; /**< Key Zeroization interrupt */
5723 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
5724 uint64_t gmx_drp : 2; /**< GMX packet drop */
5725 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
5726 uint64_t rml : 1; /**< RML Interrupt */
5727 uint64_t twsi : 1; /**< TWSI Interrupt */
5728 uint64_t reserved_44_44 : 1;
5729 uint64_t pci_msi : 4; /**< PCI MSI */
5730 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
5731 uint64_t uart : 2; /**< Two UART interrupts */
5732 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5733 uint64_t gpio : 16; /**< 16 GPIO interrupts */
5734 uint64_t workq : 16; /**< 16 work queue interrupts */
5736 uint64_t workq : 16;
5740 uint64_t pci_int : 4;
5741 uint64_t pci_msi : 4;
5742 uint64_t reserved_44_44 : 1;
5746 uint64_t gmx_drp : 2;
5747 uint64_t ipd_drp : 1;
5748 uint64_t key_zero : 1;
5750 uint64_t reserved_56_63 : 8;
5753 struct cvmx_ciu_intx_en4_0_w1s_cn61xx {
5754 #ifdef __BIG_ENDIAN_BITFIELD
5755 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
5757 uint64_t mii : 1; /**< Write 1 to set RGMII/MIX Interface 0 Interrupt
5759 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
5761 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
5762 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
5763 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
5764 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
5765 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
5766 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
5767 uint64_t reserved_51_51 : 1;
5768 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
5770 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
5771 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
5772 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
5773 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
5774 uint64_t reserved_44_44 : 1;
5775 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
5776 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
5777 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
5778 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5779 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
5780 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
5782 uint64_t workq : 16;
5786 uint64_t pci_int : 4;
5787 uint64_t pci_msi : 4;
5788 uint64_t reserved_44_44 : 1;
5792 uint64_t gmx_drp : 2;
5793 uint64_t ipd_drp : 1;
5794 uint64_t reserved_51_51 : 1;
5801 uint64_t ipdppthr : 1;
5803 uint64_t bootdma : 1;
5806 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx;
5807 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1;
5808 struct cvmx_ciu_intx_en4_0_w1s_cn66xx {
5809 #ifdef __BIG_ENDIAN_BITFIELD
5810 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
5812 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt
5814 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
5816 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */
5817 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */
5818 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt */
5819 uint64_t reserved_57_57 : 1;
5820 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */
5821 uint64_t timer : 4; /**< Write 1 to set General timer interrupts */
5822 uint64_t reserved_51_51 : 1;
5823 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
5825 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */
5826 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
5827 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
5828 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
5829 uint64_t reserved_44_44 : 1;
5830 uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */
5831 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
5832 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
5833 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5834 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
5835 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
5837 uint64_t workq : 16;
5841 uint64_t pci_int : 4;
5842 uint64_t pci_msi : 4;
5843 uint64_t reserved_44_44 : 1;
5847 uint64_t gmx_drp : 2;
5848 uint64_t ipd_drp : 1;
5849 uint64_t reserved_51_51 : 1;
5852 uint64_t reserved_57_57 : 1;
5856 uint64_t ipdppthr : 1;
5858 uint64_t bootdma : 1;
5861 struct cvmx_ciu_intx_en4_0_w1s_cnf71xx {
5862 #ifdef __BIG_ENDIAN_BITFIELD
5863 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt
5865 uint64_t reserved_62_62 : 1;
5866 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold
5868 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt enable */
5869 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt enable */
5870 uint64_t mpi : 1; /**< Write 1 to set MPI/SPI interrupt enable */
5871 uint64_t pcm : 1; /**< Write 1 to set PCM/TDM interrupt enable */
5872 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt enable */
5873 uint64_t timer : 4; /**< Write 1 to set General timer interrupt enables */
5874 uint64_t reserved_51_51 : 1;
5875 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt
5877 uint64_t reserved_49_49 : 1;
5878 uint64_t gmx_drp : 1; /**< Write 1 to set GMX packet drop interrupt enable */
5879 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */
5880 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */
5881 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */
5882 uint64_t reserved_44_44 : 1;
5883 uint64_t pci_msi : 4; /**< Write 1s to set PCIe MSI enables */
5884 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */
5885 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */
5886 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5887 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */
5888 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */
5890 uint64_t workq : 16;
5894 uint64_t pci_int : 4;
5895 uint64_t pci_msi : 4;
5896 uint64_t reserved_44_44 : 1;
5900 uint64_t gmx_drp : 1;
5901 uint64_t reserved_49_49 : 1;
5902 uint64_t ipd_drp : 1;
5903 uint64_t reserved_51_51 : 1;
5910 uint64_t ipdppthr : 1;
5911 uint64_t reserved_62_62 : 1;
5912 uint64_t bootdma : 1;
5916 typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t;
5919 * cvmx_ciu_int#_en4_1
5922 * PPx/IP4 will be raised when...
5923 * PPx/IP4 = |([CIU_SUM1_PPx_IP4, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0])
5925 union cvmx_ciu_intx_en4_1 {
5927 struct cvmx_ciu_intx_en4_1_s {
5928 #ifdef __BIG_ENDIAN_BITFIELD
5929 uint64_t rst : 1; /**< MIO RST interrupt enable */
5930 uint64_t reserved_62_62 : 1;
5931 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
5932 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
5933 uint64_t reserved_57_59 : 3;
5934 uint64_t dfm : 1; /**< DFM interrupt enable */
5935 uint64_t reserved_53_55 : 3;
5936 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
5937 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */
5938 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
5939 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
5940 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
5941 uint64_t ptp : 1; /**< PTP interrupt enable */
5942 uint64_t agl : 1; /**< AGL interrupt enable */
5943 uint64_t reserved_41_45 : 5;
5944 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
5945 uint64_t reserved_38_39 : 2;
5946 uint64_t agx1 : 1; /**< GMX1 interrupt enable */
5947 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
5948 uint64_t dpi : 1; /**< DPI interrupt enable */
5949 uint64_t sli : 1; /**< SLI interrupt enable */
5950 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
5951 uint64_t dfa : 1; /**< DFA interrupt enable */
5952 uint64_t key : 1; /**< KEY interrupt enable */
5953 uint64_t rad : 1; /**< RAD interrupt enable */
5954 uint64_t tim : 1; /**< TIM interrupt enable */
5955 uint64_t zip : 1; /**< ZIP interrupt enable */
5956 uint64_t pko : 1; /**< PKO interrupt enable */
5957 uint64_t pip : 1; /**< PIP interrupt enable */
5958 uint64_t ipd : 1; /**< IPD interrupt enable */
5959 uint64_t l2c : 1; /**< L2C interrupt enable */
5960 uint64_t pow : 1; /**< POW err interrupt enable */
5961 uint64_t fpa : 1; /**< FPA interrupt enable */
5962 uint64_t iob : 1; /**< IOB interrupt enable */
5963 uint64_t mio : 1; /**< MIO boot interrupt enable */
5964 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
5965 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
5966 uint64_t usb1 : 1; /**< Second USB Interrupt */
5967 uint64_t uart2 : 1; /**< Third UART interrupt */
5968 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vector */
5993 uint64_t reserved_38_39 : 2;
5994 uint64_t dpi_dma : 1;
5995 uint64_t reserved_41_45 : 5;
6003 uint64_t reserved_53_55 : 3;
6005 uint64_t reserved_57_59 : 3;
6008 uint64_t reserved_62_62 : 1;
6012 struct cvmx_ciu_intx_en4_1_cn50xx {
6013 #ifdef __BIG_ENDIAN_BITFIELD
6014 uint64_t reserved_2_63 : 62;
6015 uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */
6018 uint64_t reserved_2_63 : 62;
6021 struct cvmx_ciu_intx_en4_1_cn52xx {
6022 #ifdef __BIG_ENDIAN_BITFIELD
6023 uint64_t reserved_20_63 : 44;
6024 uint64_t nand : 1; /**< NAND Flash Controller */
6025 uint64_t mii1 : 1; /**< Second MII Interrupt */
6026 uint64_t usb1 : 1; /**< Second USB Interrupt */
6027 uint64_t uart2 : 1; /**< Third UART interrupt */
6028 uint64_t reserved_4_15 : 12;
6029 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
6032 uint64_t reserved_4_15 : 12;
6037 uint64_t reserved_20_63 : 44;
6040 struct cvmx_ciu_intx_en4_1_cn52xxp1 {
6041 #ifdef __BIG_ENDIAN_BITFIELD
6042 uint64_t reserved_19_63 : 45;
6043 uint64_t mii1 : 1; /**< Second MII Interrupt */
6044 uint64_t usb1 : 1; /**< Second USB Interrupt */
6045 uint64_t uart2 : 1; /**< Third UART interrupt */
6046 uint64_t reserved_4_15 : 12;
6047 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
6050 uint64_t reserved_4_15 : 12;
6054 uint64_t reserved_19_63 : 45;
6057 struct cvmx_ciu_intx_en4_1_cn56xx {
6058 #ifdef __BIG_ENDIAN_BITFIELD
6059 uint64_t reserved_12_63 : 52;
6060 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
6063 uint64_t reserved_12_63 : 52;
6066 struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
6067 struct cvmx_ciu_intx_en4_1_cn58xx {
6068 #ifdef __BIG_ENDIAN_BITFIELD
6069 uint64_t reserved_16_63 : 48;
6070 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
6073 uint64_t reserved_16_63 : 48;
6076 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
6077 struct cvmx_ciu_intx_en4_1_cn61xx {
6078 #ifdef __BIG_ENDIAN_BITFIELD
6079 uint64_t rst : 1; /**< MIO RST interrupt enable */
6080 uint64_t reserved_53_62 : 10;
6081 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
6082 uint64_t reserved_50_51 : 2;
6083 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
6084 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
6085 uint64_t ptp : 1; /**< PTP interrupt enable */
6086 uint64_t agl : 1; /**< AGL interrupt enable */
6087 uint64_t reserved_41_45 : 5;
6088 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
6089 uint64_t reserved_38_39 : 2;
6090 uint64_t agx1 : 1; /**< GMX1 interrupt enable */
6091 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
6092 uint64_t dpi : 1; /**< DPI interrupt enable */
6093 uint64_t sli : 1; /**< SLI interrupt enable */
6094 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
6095 uint64_t dfa : 1; /**< DFA interrupt enable */
6096 uint64_t key : 1; /**< KEY interrupt enable */
6097 uint64_t rad : 1; /**< RAD interrupt enable */
6098 uint64_t tim : 1; /**< TIM interrupt enable */
6099 uint64_t zip : 1; /**< ZIP interrupt enable */
6100 uint64_t pko : 1; /**< PKO interrupt enable */
6101 uint64_t pip : 1; /**< PIP interrupt enable */
6102 uint64_t ipd : 1; /**< IPD interrupt enable */
6103 uint64_t l2c : 1; /**< L2C interrupt enable */
6104 uint64_t pow : 1; /**< POW err interrupt enable */
6105 uint64_t fpa : 1; /**< FPA interrupt enable */
6106 uint64_t iob : 1; /**< IOB interrupt enable */
6107 uint64_t mio : 1; /**< MIO boot interrupt enable */
6108 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
6109 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt enable */
6110 uint64_t reserved_4_17 : 14;
6111 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
6114 uint64_t reserved_4_17 : 14;
6135 uint64_t reserved_38_39 : 2;
6136 uint64_t dpi_dma : 1;
6137 uint64_t reserved_41_45 : 5;
6142 uint64_t reserved_50_51 : 2;
6144 uint64_t reserved_53_62 : 10;
6148 struct cvmx_ciu_intx_en4_1_cn63xx {
6149 #ifdef __BIG_ENDIAN_BITFIELD
6150 uint64_t rst : 1; /**< MIO RST interrupt enable */
6151 uint64_t reserved_57_62 : 6;
6152 uint64_t dfm : 1; /**< DFM interrupt enable */
6153 uint64_t reserved_53_55 : 3;
6154 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
6155 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */
6156 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
6157 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
6158 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
6159 uint64_t ptp : 1; /**< PTP interrupt enable */
6160 uint64_t agl : 1; /**< AGL interrupt enable */
6161 uint64_t reserved_37_45 : 9;
6162 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
6163 uint64_t dpi : 1; /**< DPI interrupt enable */
6164 uint64_t sli : 1; /**< SLI interrupt enable */
6165 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
6166 uint64_t dfa : 1; /**< DFA interrupt enable */
6167 uint64_t key : 1; /**< KEY interrupt enable */
6168 uint64_t rad : 1; /**< RAD interrupt enable */
6169 uint64_t tim : 1; /**< TIM interrupt enable */
6170 uint64_t zip : 1; /**< ZIP interrupt enable */
6171 uint64_t pko : 1; /**< PKO interrupt enable */
6172 uint64_t pip : 1; /**< PIP interrupt enable */
6173 uint64_t ipd : 1; /**< IPD interrupt enable */
6174 uint64_t l2c : 1; /**< L2C interrupt enable */
6175 uint64_t pow : 1; /**< POW err interrupt enable */
6176 uint64_t fpa : 1; /**< FPA interrupt enable */
6177 uint64_t iob : 1; /**< IOB interrupt enable */
6178 uint64_t mio : 1; /**< MIO boot interrupt enable */
6179 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
6180 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
6181 uint64_t reserved_6_17 : 12;
6182 uint64_t wdog : 6; /**< Watchdog summary interrupt enable vector */
6185 uint64_t reserved_6_17 : 12;
6205 uint64_t reserved_37_45 : 9;
6213 uint64_t reserved_53_55 : 3;
6215 uint64_t reserved_57_62 : 6;
6219 struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1;
6220 struct cvmx_ciu_intx_en4_1_cn66xx {
6221 #ifdef __BIG_ENDIAN_BITFIELD
6222 uint64_t rst : 1; /**< MIO RST interrupt enable */
6223 uint64_t reserved_62_62 : 1;
6224 uint64_t srio3 : 1; /**< SRIO3 interrupt enable */
6225 uint64_t srio2 : 1; /**< SRIO2 interrupt enable */
6226 uint64_t reserved_57_59 : 3;
6227 uint64_t dfm : 1; /**< DFM interrupt enable */
6228 uint64_t reserved_53_55 : 3;
6229 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
6230 uint64_t reserved_51_51 : 1;
6231 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */
6232 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
6233 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
6234 uint64_t ptp : 1; /**< PTP interrupt enable */
6235 uint64_t agl : 1; /**< AGL interrupt enable */
6236 uint64_t reserved_38_45 : 8;
6237 uint64_t agx1 : 1; /**< GMX1 interrupt enable */
6238 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
6239 uint64_t dpi : 1; /**< DPI interrupt enable */
6240 uint64_t sli : 1; /**< SLI interrupt enable */
6241 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
6242 uint64_t dfa : 1; /**< DFA interrupt enable */
6243 uint64_t key : 1; /**< KEY interrupt enable */
6244 uint64_t rad : 1; /**< RAD interrupt enable */
6245 uint64_t tim : 1; /**< TIM interrupt enable */
6246 uint64_t zip : 1; /**< ZIP interrupt enable */
6247 uint64_t pko : 1; /**< PKO interrupt enable */
6248 uint64_t pip : 1; /**< PIP interrupt enable */
6249 uint64_t ipd : 1; /**< IPD interrupt enable */
6250 uint64_t l2c : 1; /**< L2C interrupt enable */
6251 uint64_t pow : 1; /**< POW err interrupt enable */
6252 uint64_t fpa : 1; /**< FPA interrupt enable */
6253 uint64_t iob : 1; /**< IOB interrupt enable */
6254 uint64_t mio : 1; /**< MIO boot interrupt enable */
6255 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */
6256 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */
6257 uint64_t reserved_10_17 : 8;
6258 uint64_t wdog : 10; /**< Watchdog summary interrupt enable vector */
6261 uint64_t reserved_10_17 : 8;
6282 uint64_t reserved_38_45 : 8;
6288 uint64_t reserved_51_51 : 1;
6290 uint64_t reserved_53_55 : 3;
6292 uint64_t reserved_57_59 : 3;
6295 uint64_t reserved_62_62 : 1;
6299 struct cvmx_ciu_intx_en4_1_cnf71xx {
6300 #ifdef __BIG_ENDIAN_BITFIELD
6301 uint64_t rst : 1; /**< MIO RST interrupt enable */
6302 uint64_t reserved_53_62 : 10;
6303 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */
6304 uint64_t reserved_50_51 : 2;
6305 uint64_t pem1 : 1; /**< PEM1 interrupt enable */
6306 uint64_t pem0 : 1; /**< PEM0 interrupt enable */
6307 uint64_t ptp : 1; /**< PTP interrupt enable */
6308 uint64_t reserved_41_46 : 6;
6309 uint64_t dpi_dma : 1; /**< DPI_DMA interrupt enable */
6310 uint64_t reserved_37_39 : 3;
6311 uint64_t agx0 : 1; /**< GMX0 interrupt enable */
6312 uint64_t dpi : 1; /**< DPI interrupt enable */
6313 uint64_t sli : 1; /**< SLI interrupt enable */
6314 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */
6315 uint64_t reserved_32_32 : 1;
6316 uint64_t key : 1; /**< KEY interrupt enable */
6317 uint64_t rad : 1; /**< RAD interrupt enable */
6318 uint64_t tim : 1; /**< TIM interrupt enable */
6319 uint64_t reserved_28_28 : 1;
6320 uint64_t pko : 1; /**< PKO interrupt enable */
6321 uint64_t pip : 1; /**< PIP interrupt enable */
6322 uint64_t ipd : 1; /**< IPD interrupt enable */
6323 uint64_t l2c : 1; /**< L2C interrupt enable */
6324 uint64_t pow : 1; /**< POW err interrupt enable */
6325 uint64_t fpa : 1; /**< FPA interrupt enable */
6326 uint64_t iob : 1; /**< IOB interrupt enable */
6327 uint64_t mio : 1; /**< MIO boot interrupt enable */
6328 uint64_t nand : 1; /**< EMMC Flash Controller interrupt enable */
6329 uint64_t reserved_4_18 : 15;
6330 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
6333 uint64_t reserved_4_18 : 15;
6343 uint64_t reserved_28_28 : 1;
6347 uint64_t reserved_32_32 : 1;
6352 uint64_t reserved_37_39 : 3;
6353 uint64_t dpi_dma : 1;
6354 uint64_t reserved_41_46 : 6;
6358 uint64_t reserved_50_51 : 2;
6360 uint64_t reserved_53_62 : 10;
6365 typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t;
6368 * cvmx_ciu_int#_en4_1_w1c
6371 * Write-1-to-clear version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value.
6374 union cvmx_ciu_intx_en4_1_w1c {
6376 struct cvmx_ciu_intx_en4_1_w1c_s {
6377 #ifdef __BIG_ENDIAN_BITFIELD
6378 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
6379 uint64_t reserved_62_62 : 1;
6380 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
6381 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
6382 uint64_t reserved_57_59 : 3;
6383 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
6384 uint64_t reserved_53_55 : 3;
6385 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
6386 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */
6387 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
6388 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
6389 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
6390 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
6391 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
6392 uint64_t reserved_41_45 : 5;
6393 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
6394 uint64_t reserved_38_39 : 2;
6395 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
6396 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
6397 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
6398 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
6399 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
6400 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
6401 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
6402 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
6403 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
6404 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
6405 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
6406 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
6407 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
6408 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
6409 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
6410 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
6411 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
6412 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
6413 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
6415 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
6417 uint64_t usb1 : 1; /**< Second USB Interrupt */
6418 uint64_t uart2 : 1; /**< Third UART interrupt */
6419 uint64_t wdog : 16; /**< Write 1s to clear Watchdog summary interrupt enable */
6444 uint64_t reserved_38_39 : 2;
6445 uint64_t dpi_dma : 1;
6446 uint64_t reserved_41_45 : 5;
6454 uint64_t reserved_53_55 : 3;
6456 uint64_t reserved_57_59 : 3;
6459 uint64_t reserved_62_62 : 1;
6463 struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
6464 #ifdef __BIG_ENDIAN_BITFIELD
6465 uint64_t reserved_20_63 : 44;
6466 uint64_t nand : 1; /**< NAND Flash Controller */
6467 uint64_t mii1 : 1; /**< Second MII Interrupt */
6468 uint64_t usb1 : 1; /**< Second USB Interrupt */
6469 uint64_t uart2 : 1; /**< Third UART interrupt */
6470 uint64_t reserved_4_15 : 12;
6471 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
6474 uint64_t reserved_4_15 : 12;
6479 uint64_t reserved_20_63 : 44;
6482 struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
6483 #ifdef __BIG_ENDIAN_BITFIELD
6484 uint64_t reserved_12_63 : 52;
6485 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
6488 uint64_t reserved_12_63 : 52;
6491 struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
6492 #ifdef __BIG_ENDIAN_BITFIELD
6493 uint64_t reserved_16_63 : 48;
6494 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
6497 uint64_t reserved_16_63 : 48;
6500 struct cvmx_ciu_intx_en4_1_w1c_cn61xx {
6501 #ifdef __BIG_ENDIAN_BITFIELD
6502 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
6503 uint64_t reserved_53_62 : 10;
6504 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
6505 uint64_t reserved_50_51 : 2;
6506 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
6507 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
6508 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
6509 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
6510 uint64_t reserved_41_45 : 5;
6511 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
6512 uint64_t reserved_38_39 : 2;
6513 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
6514 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
6515 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
6516 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
6517 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
6518 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
6519 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
6520 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
6521 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
6522 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
6523 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
6524 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
6525 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
6526 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
6527 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
6528 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
6529 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
6530 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
6531 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
6533 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MIX Interface 1
6535 uint64_t reserved_4_17 : 14;
6536 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
6539 uint64_t reserved_4_17 : 14;
6560 uint64_t reserved_38_39 : 2;
6561 uint64_t dpi_dma : 1;
6562 uint64_t reserved_41_45 : 5;
6567 uint64_t reserved_50_51 : 2;
6569 uint64_t reserved_53_62 : 10;
6573 struct cvmx_ciu_intx_en4_1_w1c_cn63xx {
6574 #ifdef __BIG_ENDIAN_BITFIELD
6575 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
6576 uint64_t reserved_57_62 : 6;
6577 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
6578 uint64_t reserved_53_55 : 3;
6579 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
6580 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */
6581 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
6582 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
6583 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
6584 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
6585 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
6586 uint64_t reserved_37_45 : 9;
6587 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
6588 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
6589 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
6590 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
6591 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
6592 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
6593 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
6594 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
6595 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
6596 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
6597 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
6598 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
6599 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
6600 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
6601 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
6602 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
6603 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
6604 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
6606 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
6608 uint64_t reserved_6_17 : 12;
6609 uint64_t wdog : 6; /**< Write 1s to clear Watchdog summary interrupt enable */
6612 uint64_t reserved_6_17 : 12;
6632 uint64_t reserved_37_45 : 9;
6640 uint64_t reserved_53_55 : 3;
6642 uint64_t reserved_57_62 : 6;
6646 struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1;
6647 struct cvmx_ciu_intx_en4_1_w1c_cn66xx {
6648 #ifdef __BIG_ENDIAN_BITFIELD
6649 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
6650 uint64_t reserved_62_62 : 1;
6651 uint64_t srio3 : 1; /**< Write 1 to clear SRIO3 interrupt enable */
6652 uint64_t srio2 : 1; /**< Write 1 to clear SRIO2 interrupt enable */
6653 uint64_t reserved_57_59 : 3;
6654 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */
6655 uint64_t reserved_53_55 : 3;
6656 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
6657 uint64_t reserved_51_51 : 1;
6658 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */
6659 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
6660 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
6661 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
6662 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */
6663 uint64_t reserved_38_45 : 8;
6664 uint64_t agx1 : 1; /**< Write 1 to clear GMX1 interrupt enable */
6665 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
6666 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
6667 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
6668 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
6669 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */
6670 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
6671 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
6672 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
6673 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */
6674 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
6675 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
6676 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
6677 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
6678 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
6679 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
6680 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
6681 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
6682 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt
6684 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1
6686 uint64_t reserved_10_17 : 8;
6687 uint64_t wdog : 10; /**< Write 1s to clear Watchdog summary interrupt enable */
6690 uint64_t reserved_10_17 : 8;
6711 uint64_t reserved_38_45 : 8;
6717 uint64_t reserved_51_51 : 1;
6719 uint64_t reserved_53_55 : 3;
6721 uint64_t reserved_57_59 : 3;
6724 uint64_t reserved_62_62 : 1;
6728 struct cvmx_ciu_intx_en4_1_w1c_cnf71xx {
6729 #ifdef __BIG_ENDIAN_BITFIELD
6730 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */
6731 uint64_t reserved_53_62 : 10;
6732 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */
6733 uint64_t reserved_50_51 : 2;
6734 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */
6735 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */
6736 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */
6737 uint64_t reserved_41_46 : 6;
6738 uint64_t dpi_dma : 1; /**< Write 1 to clear DPI_DMA interrupt enable */
6739 uint64_t reserved_37_39 : 3;
6740 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */
6741 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */
6742 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */
6743 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */
6744 uint64_t reserved_32_32 : 1;
6745 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */
6746 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */
6747 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */
6748 uint64_t reserved_28_28 : 1;
6749 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */
6750 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */
6751 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */
6752 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */
6753 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */
6754 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */
6755 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */
6756 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */
6757 uint64_t nand : 1; /**< Write 1 to clear EMMC Flash Controller interrupt
6759 uint64_t reserved_4_18 : 15;
6760 uint64_t wdog : 4; /**< Write 1s to clear Watchdog summary interrupt enable */
6763 uint64_t reserved_4_18 : 15;
6773 uint64_t reserved_28_28 : 1;
6777 uint64_t reserved_32_32 : 1;
6782 uint64_t reserved_37_39 : 3;
6783 uint64_t dpi_dma : 1;
6784 uint64_t reserved_41_46 : 6;
6788 uint64_t reserved_50_51 : 2;
6790 uint64_t reserved_53_62 : 10;
6795 typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t;
6798 * cvmx_ciu_int#_en4_1_w1s
6801 * Write-1-to-set version of the CIU_INTX_EN4_1 register, read back corresponding CIU_INTX_EN4_1 value.
6804 union cvmx_ciu_intx_en4_1_w1s {
6806 struct cvmx_ciu_intx_en4_1_w1s_s {
6807 #ifdef __BIG_ENDIAN_BITFIELD
6808 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
6809 uint64_t reserved_62_62 : 1;
6810 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
6811 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
6812 uint64_t reserved_57_59 : 3;
6813 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
6814 uint64_t reserved_53_55 : 3;
6815 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
6816 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */
6817 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
6818 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
6819 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
6820 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
6821 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
6822 uint64_t reserved_41_45 : 5;
6823 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
6824 uint64_t reserved_38_39 : 2;
6825 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
6826 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
6827 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
6828 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
6829 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
6830 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
6831 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
6832 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
6833 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
6834 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
6835 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
6836 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
6837 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
6838 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
6839 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
6840 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
6841 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
6842 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
6843 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
6845 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
6847 uint64_t usb1 : 1; /**< Second USB Interrupt */
6848 uint64_t uart2 : 1; /**< Third UART interrupt */
6849 uint64_t wdog : 16; /**< Write 1s to set Watchdog summary interrupt enable */
6874 uint64_t reserved_38_39 : 2;
6875 uint64_t dpi_dma : 1;
6876 uint64_t reserved_41_45 : 5;
6884 uint64_t reserved_53_55 : 3;
6886 uint64_t reserved_57_59 : 3;
6889 uint64_t reserved_62_62 : 1;
6893 struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
6894 #ifdef __BIG_ENDIAN_BITFIELD
6895 uint64_t reserved_20_63 : 44;
6896 uint64_t nand : 1; /**< NAND Flash Controller */
6897 uint64_t mii1 : 1; /**< Second MII Interrupt */
6898 uint64_t usb1 : 1; /**< Second USB Interrupt */
6899 uint64_t uart2 : 1; /**< Third UART interrupt */
6900 uint64_t reserved_4_15 : 12;
6901 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */
6904 uint64_t reserved_4_15 : 12;
6909 uint64_t reserved_20_63 : 44;
6912 struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
6913 #ifdef __BIG_ENDIAN_BITFIELD
6914 uint64_t reserved_12_63 : 52;
6915 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */
6918 uint64_t reserved_12_63 : 52;
6921 struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
6922 #ifdef __BIG_ENDIAN_BITFIELD
6923 uint64_t reserved_16_63 : 48;
6924 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */
6927 uint64_t reserved_16_63 : 48;
6930 struct cvmx_ciu_intx_en4_1_w1s_cn61xx {
6931 #ifdef __BIG_ENDIAN_BITFIELD
6932 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
6933 uint64_t reserved_53_62 : 10;
6934 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
6935 uint64_t reserved_50_51 : 2;
6936 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
6937 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
6938 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
6939 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
6940 uint64_t reserved_41_45 : 5;
6941 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
6942 uint64_t reserved_38_39 : 2;
6943 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
6944 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
6945 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
6946 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
6947 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
6948 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
6949 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
6950 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
6951 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
6952 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
6953 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
6954 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
6955 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
6956 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
6957 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
6958 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
6959 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
6960 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
6961 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
6963 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MIX Interface 1 Interrupt
6965 uint64_t reserved_4_17 : 14;
6966 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
6969 uint64_t reserved_4_17 : 14;
6990 uint64_t reserved_38_39 : 2;
6991 uint64_t dpi_dma : 1;
6992 uint64_t reserved_41_45 : 5;
6997 uint64_t reserved_50_51 : 2;
6999 uint64_t reserved_53_62 : 10;
7003 struct cvmx_ciu_intx_en4_1_w1s_cn63xx {
7004 #ifdef __BIG_ENDIAN_BITFIELD
7005 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
7006 uint64_t reserved_57_62 : 6;
7007 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
7008 uint64_t reserved_53_55 : 3;
7009 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
7010 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */
7011 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
7012 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
7013 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
7014 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
7015 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
7016 uint64_t reserved_37_45 : 9;
7017 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
7018 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
7019 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
7020 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
7021 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
7022 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
7023 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
7024 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
7025 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
7026 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
7027 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
7028 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
7029 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
7030 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
7031 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
7032 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
7033 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
7034 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
7036 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
7038 uint64_t reserved_6_17 : 12;
7039 uint64_t wdog : 6; /**< Write 1s to set Watchdog summary interrupt enable */
7042 uint64_t reserved_6_17 : 12;
7062 uint64_t reserved_37_45 : 9;
7070 uint64_t reserved_53_55 : 3;
7072 uint64_t reserved_57_62 : 6;
7076 struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1;
7077 struct cvmx_ciu_intx_en4_1_w1s_cn66xx {
7078 #ifdef __BIG_ENDIAN_BITFIELD
7079 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
7080 uint64_t reserved_62_62 : 1;
7081 uint64_t srio3 : 1; /**< Write 1 to set SRIO3 interrupt enable */
7082 uint64_t srio2 : 1; /**< Write 1 to set SRIO2 interrupt enable */
7083 uint64_t reserved_57_59 : 3;
7084 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */
7085 uint64_t reserved_53_55 : 3;
7086 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
7087 uint64_t reserved_51_51 : 1;
7088 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */
7089 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
7090 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
7091 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
7092 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */
7093 uint64_t reserved_38_45 : 8;
7094 uint64_t agx1 : 1; /**< Write 1 to set GMX1 interrupt enable */
7095 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
7096 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
7097 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
7098 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
7099 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */
7100 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
7101 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
7102 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
7103 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */
7104 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
7105 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
7106 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
7107 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
7108 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
7109 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
7110 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
7111 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
7112 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt
7114 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt
7116 uint64_t reserved_10_17 : 8;
7117 uint64_t wdog : 10; /**< Write 1s to set Watchdog summary interrupt enable */
7120 uint64_t reserved_10_17 : 8;
7141 uint64_t reserved_38_45 : 8;
7147 uint64_t reserved_51_51 : 1;
7149 uint64_t reserved_53_55 : 3;
7151 uint64_t reserved_57_59 : 3;
7154 uint64_t reserved_62_62 : 1;
7158 struct cvmx_ciu_intx_en4_1_w1s_cnf71xx {
7159 #ifdef __BIG_ENDIAN_BITFIELD
7160 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */
7161 uint64_t reserved_53_62 : 10;
7162 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */
7163 uint64_t reserved_50_51 : 2;
7164 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */
7165 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */
7166 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */
7167 uint64_t reserved_41_46 : 6;
7168 uint64_t dpi_dma : 1; /**< Write 1 to set DPI_DMA interrupt enable */
7169 uint64_t reserved_37_39 : 3;
7170 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */
7171 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */
7172 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */
7173 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */
7174 uint64_t reserved_32_32 : 1;
7175 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */
7176 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */
7177 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */
7178 uint64_t reserved_28_28 : 1;
7179 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */
7180 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */
7181 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */
7182 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */
7183 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */
7184 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */
7185 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */
7186 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */
7187 uint64_t nand : 1; /**< Write 1 to set EMMC Flash Controller interrupt
7189 uint64_t reserved_4_18 : 15;
7190 uint64_t wdog : 4; /**< Write 1s to set Watchdog summary interrupt enable */
7193 uint64_t reserved_4_18 : 15;
7203 uint64_t reserved_28_28 : 1;
7207 uint64_t reserved_32_32 : 1;
7212 uint64_t reserved_37_39 : 3;
7213 uint64_t dpi_dma : 1;
7214 uint64_t reserved_41_46 : 6;
7218 uint64_t reserved_50_51 : 2;
7220 uint64_t reserved_53_62 : 10;
7225 typedef union cvmx_ciu_intx_en4_1_w1s cvmx_ciu_intx_en4_1_w1s_t;
7228 * cvmx_ciu_int#_sum0
7230 union cvmx_ciu_intx_sum0 {
7232 struct cvmx_ciu_intx_sum0_s {
7233 #ifdef __BIG_ENDIAN_BITFIELD
7234 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7235 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7236 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
7238 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7239 See IPD_PORT_QOS_INT* */
7240 uint64_t powiq : 1; /**< POW IQ interrupt
7242 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
7244 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction
7245 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
7246 uint64_t pcm : 1; /**< PCM/TDM interrupt */
7247 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
7248 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7249 uint64_t timer : 4; /**< General timer 0-3 interrupts.
7250 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
7251 common for all PP/IRQs, writing '1' to any PP/IRQ
7252 will clear all TIMERx(x=0..9) interrupts.
7253 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
7254 are set at the same time, but clearing are based on
7255 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
7256 The combination of this field and the
7257 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
7259 uint64_t reserved_51_51 : 1;
7260 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7261 Set any time PIP/IPD drops a packet */
7262 uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt
7263 Set any time corresponding GMX0/1 drops a packet */
7264 uint64_t trace : 1; /**< Trace buffer interrupt
7265 See TRA_INT_STATUS */
7266 uint64_t rml : 1; /**< RML Interrupt
7267 This interrupt will assert if any bit within
7268 CIU_BLOCK_INT is asserted. */
7269 uint64_t twsi : 1; /**< TWSI Interrupt
7271 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
7272 This read-only bit reads as a one whenever any
7273 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
7274 and corresponding enable bit in CIU_INTx_EN is set
7275 PPs use CIU_INTx_SUM0 where x=0-7
7276 PCIe uses the CIU_INTx_SUM0 where x=32-33.
7277 Note that WDOG_SUM only summarizes the SUM1/EN1
7278 result and does not have a corresponding enable
7279 bit, so does not directly contribute to
7281 uint64_t pci_msi : 4; /**< PCIe MSI
7282 See SLI_MSI_RCVn for bit <40+n> */
7283 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
7284 Refer to "Receiving Emulated INTA/INTB/
7285 INTC/INTD" in the SLI chapter of the spec
7289 PCI_INT<0> = INTA */
7290 uint64_t uart : 2; /**< Two UART interrupts
7291 See MIO_UARTn_IIR[IID] for bit <34+n> */
7292 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7293 [33] is the or of <31:16>
7294 [32] is the or of <15:0>
7295 Two PCIe internal interrupts for entries 32-33
7296 which equal CIU_PCI_INTA[INT] */
7297 uint64_t gpio : 16; /**< 16 GPIO interrupts
7298 When GPIO_MULTI_CAST[EN] == 1
7299 Write 1 to clear either the per PP or common GPIO
7300 edge-triggered interrupts,depending on mode.
7301 See GPIO_MULTI_CAST for all details.
7302 When GPIO_MULTI_CAST[EN] == 0
7303 Read Only, retain the same behavior as o63. */
7304 uint64_t workq : 16; /**< 16 work queue interrupts
7305 See POW_WQ_INT[WQ_INT]
7306 1 bit/group. A copy of the R/W1C bit in the POW. */
7308 uint64_t workq : 16;
7312 uint64_t pci_int : 4;
7313 uint64_t pci_msi : 4;
7314 uint64_t wdog_sum : 1;
7318 uint64_t gmx_drp : 2;
7319 uint64_t ipd_drp : 1;
7320 uint64_t reserved_51_51 : 1;
7327 uint64_t ipdppthr : 1;
7329 uint64_t bootdma : 1;
7332 struct cvmx_ciu_intx_sum0_cn30xx {
7333 #ifdef __BIG_ENDIAN_BITFIELD
7334 uint64_t reserved_59_63 : 5;
7335 uint64_t mpi : 1; /**< MPI/SPI interrupt */
7336 uint64_t pcm : 1; /**< PCM/TDM interrupt */
7337 uint64_t usb : 1; /**< USB interrupt */
7338 uint64_t timer : 4; /**< General timer interrupts */
7339 uint64_t reserved_51_51 : 1;
7340 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
7341 uint64_t reserved_49_49 : 1;
7342 uint64_t gmx_drp : 1; /**< GMX packet drop */
7343 uint64_t reserved_47_47 : 1;
7344 uint64_t rml : 1; /**< RML Interrupt */
7345 uint64_t twsi : 1; /**< TWSI Interrupt */
7346 uint64_t wdog_sum : 1; /**< Watchdog summary
7347 PPs use CIU_INTx_SUM0 where x=0-1.
7348 PCI uses the CIU_INTx_SUM0 where x=32.
7349 Even INTx registers report WDOG to IP2
7350 Odd INTx registers report WDOG to IP3 */
7351 uint64_t pci_msi : 4; /**< PCI MSI
7352 [43] is the or of <63:48>
7353 [42] is the or of <47:32>
7354 [41] is the or of <31:16>
7355 [40] is the or of <15:0> */
7356 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
7357 uint64_t uart : 2; /**< Two UART interrupts */
7358 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
7359 [33] is the or of <31:16>
7360 [32] is the or of <15:0>
7361 Two PCI internal interrupts for entry 32
7363 uint64_t gpio : 16; /**< 16 GPIO interrupts */
7364 uint64_t workq : 16; /**< 16 work queue interrupts
7365 1 bit/group. A copy of the R/W1C bit in the POW. */
7367 uint64_t workq : 16;
7371 uint64_t pci_int : 4;
7372 uint64_t pci_msi : 4;
7373 uint64_t wdog_sum : 1;
7376 uint64_t reserved_47_47 : 1;
7377 uint64_t gmx_drp : 1;
7378 uint64_t reserved_49_49 : 1;
7379 uint64_t ipd_drp : 1;
7380 uint64_t reserved_51_51 : 1;
7385 uint64_t reserved_59_63 : 5;
7388 struct cvmx_ciu_intx_sum0_cn31xx {
7389 #ifdef __BIG_ENDIAN_BITFIELD
7390 uint64_t reserved_59_63 : 5;
7391 uint64_t mpi : 1; /**< MPI/SPI interrupt */
7392 uint64_t pcm : 1; /**< PCM/TDM interrupt */
7393 uint64_t usb : 1; /**< USB interrupt */
7394 uint64_t timer : 4; /**< General timer interrupts */
7395 uint64_t reserved_51_51 : 1;
7396 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
7397 uint64_t reserved_49_49 : 1;
7398 uint64_t gmx_drp : 1; /**< GMX packet drop */
7399 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
7400 uint64_t rml : 1; /**< RML Interrupt */
7401 uint64_t twsi : 1; /**< TWSI Interrupt */
7402 uint64_t wdog_sum : 1; /**< Watchdog summary
7403 PPs use CIU_INTx_SUM0 where x=0-3.
7404 PCI uses the CIU_INTx_SUM0 where x=32.
7405 Even INTx registers report WDOG to IP2
7406 Odd INTx registers report WDOG to IP3 */
7407 uint64_t pci_msi : 4; /**< PCI MSI
7408 [43] is the or of <63:48>
7409 [42] is the or of <47:32>
7410 [41] is the or of <31:16>
7411 [40] is the or of <15:0> */
7412 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
7413 uint64_t uart : 2; /**< Two UART interrupts */
7414 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
7415 [33] is the or of <31:16>
7416 [32] is the or of <15:0>
7417 Two PCI internal interrupts for entry 32
7419 uint64_t gpio : 16; /**< 16 GPIO interrupts */
7420 uint64_t workq : 16; /**< 16 work queue interrupts
7421 1 bit/group. A copy of the R/W1C bit in the POW. */
7423 uint64_t workq : 16;
7427 uint64_t pci_int : 4;
7428 uint64_t pci_msi : 4;
7429 uint64_t wdog_sum : 1;
7433 uint64_t gmx_drp : 1;
7434 uint64_t reserved_49_49 : 1;
7435 uint64_t ipd_drp : 1;
7436 uint64_t reserved_51_51 : 1;
7441 uint64_t reserved_59_63 : 5;
7444 struct cvmx_ciu_intx_sum0_cn38xx {
7445 #ifdef __BIG_ENDIAN_BITFIELD
7446 uint64_t reserved_56_63 : 8;
7447 uint64_t timer : 4; /**< General timer interrupts */
7448 uint64_t key_zero : 1; /**< Key Zeroization interrupt
7449 KEY_ZERO will be set when the external ZERO_KEYS
7450 pin is sampled high. KEY_ZERO is cleared by SW */
7451 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
7452 uint64_t gmx_drp : 2; /**< GMX packet drop */
7453 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
7454 uint64_t rml : 1; /**< RML Interrupt */
7455 uint64_t twsi : 1; /**< TWSI Interrupt */
7456 uint64_t wdog_sum : 1; /**< Watchdog summary
7457 PPs use CIU_INTx_SUM0 where x=0-31.
7458 PCI uses the CIU_INTx_SUM0 where x=32.
7459 Even INTx registers report WDOG to IP2
7460 Odd INTx registers report WDOG to IP3 */
7461 uint64_t pci_msi : 4; /**< PCI MSI
7462 [43] is the or of <63:48>
7463 [42] is the or of <47:32>
7464 [41] is the or of <31:16>
7465 [40] is the or of <15:0> */
7466 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
7467 uint64_t uart : 2; /**< Two UART interrupts */
7468 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
7469 [33] is the or of <31:16>
7470 [32] is the or of <15:0>
7471 Two PCI internal interrupts for entry 32
7473 uint64_t gpio : 16; /**< 16 GPIO interrupts */
7474 uint64_t workq : 16; /**< 16 work queue interrupts
7475 1 bit/group. A copy of the R/W1C bit in the POW. */
7477 uint64_t workq : 16;
7481 uint64_t pci_int : 4;
7482 uint64_t pci_msi : 4;
7483 uint64_t wdog_sum : 1;
7487 uint64_t gmx_drp : 2;
7488 uint64_t ipd_drp : 1;
7489 uint64_t key_zero : 1;
7491 uint64_t reserved_56_63 : 8;
7494 struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
7495 struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
7496 struct cvmx_ciu_intx_sum0_cn52xx {
7497 #ifdef __BIG_ENDIAN_BITFIELD
7498 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
7499 uint64_t mii : 1; /**< MII Interface Interrupt */
7500 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
7501 uint64_t powiq : 1; /**< POW IQ interrupt */
7502 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
7503 uint64_t reserved_57_58 : 2;
7504 uint64_t usb : 1; /**< USB Interrupt */
7505 uint64_t timer : 4; /**< General timer interrupts */
7506 uint64_t reserved_51_51 : 1;
7507 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
7508 uint64_t reserved_49_49 : 1;
7509 uint64_t gmx_drp : 1; /**< GMX packet drop */
7510 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
7511 uint64_t rml : 1; /**< RML Interrupt */
7512 uint64_t twsi : 1; /**< TWSI Interrupt */
7513 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
7514 This read-only bit reads as a one whenever any
7515 CIU_INT_SUM1 bit is set and corresponding
7516 enable bit in CIU_INTx_EN is set, where x
7517 is the same as x in this CIU_INTx_SUM0.
7518 PPs use CIU_INTx_SUM0 where x=0-7.
7519 PCI uses the CIU_INTx_SUM0 where x=32.
7520 Even INTx registers report WDOG to IP2
7521 Odd INTx registers report WDOG to IP3
7522 Note that WDOG_SUM only summarizes the SUM/EN1
7523 result and does not have a corresponding enable
7524 bit, so does not directly contribute to
7526 uint64_t pci_msi : 4; /**< PCI MSI
7527 Refer to "Receiving Message-Signalled
7528 Interrupts" in the PCIe chapter of the spec */
7529 uint64_t pci_int : 4; /**< PCI INTA/B/C/D
7530 Refer to "Receiving Emulated INTA/INTB/
7531 INTC/INTD" in the PCIe chapter of the spec */
7532 uint64_t uart : 2; /**< Two UART interrupts */
7533 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-7
7534 [33] is the or of <31:16>
7535 [32] is the or of <15:0>
7536 Two PCI internal interrupts for entry 32
7538 uint64_t gpio : 16; /**< 16 GPIO interrupts */
7539 uint64_t workq : 16; /**< 16 work queue interrupts
7540 1 bit/group. A copy of the R/W1C bit in the POW. */
7542 uint64_t workq : 16;
7546 uint64_t pci_int : 4;
7547 uint64_t pci_msi : 4;
7548 uint64_t wdog_sum : 1;
7552 uint64_t gmx_drp : 1;
7553 uint64_t reserved_49_49 : 1;
7554 uint64_t ipd_drp : 1;
7555 uint64_t reserved_51_51 : 1;
7558 uint64_t reserved_57_58 : 2;
7561 uint64_t ipdppthr : 1;
7563 uint64_t bootdma : 1;
7566 struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
7567 struct cvmx_ciu_intx_sum0_cn56xx {
7568 #ifdef __BIG_ENDIAN_BITFIELD
7569 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
7570 uint64_t mii : 1; /**< MII Interface Interrupt */
7571 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
7572 uint64_t powiq : 1; /**< POW IQ interrupt */
7573 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
7574 uint64_t reserved_57_58 : 2;
7575 uint64_t usb : 1; /**< USB Interrupt */
7576 uint64_t timer : 4; /**< General timer interrupts */
7577 uint64_t key_zero : 1; /**< Key Zeroization interrupt
7578 KEY_ZERO will be set when the external ZERO_KEYS
7579 pin is sampled high. KEY_ZERO is cleared by SW */
7580 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
7581 uint64_t gmx_drp : 2; /**< GMX packet drop */
7582 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
7583 uint64_t rml : 1; /**< RML Interrupt */
7584 uint64_t twsi : 1; /**< TWSI Interrupt */
7585 uint64_t wdog_sum : 1; /**< Watchdog summary
7586 PPs use CIU_INTx_SUM0 where x=0-23.
7587 PCI uses the CIU_INTx_SUM0 where x=32.
7588 Even INTx registers report WDOG to IP2
7589 Odd INTx registers report WDOG to IP3 */
7590 uint64_t pci_msi : 4; /**< PCI MSI
7591 Refer to "Receiving Message-Signalled
7592 Interrupts" in the PCIe chapter of the spec */
7593 uint64_t pci_int : 4; /**< PCI INTA/B/C/D
7594 Refer to "Receiving Emulated INTA/INTB/
7595 INTC/INTD" in the PCIe chapter of the spec */
7596 uint64_t uart : 2; /**< Two UART interrupts */
7597 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-23
7598 [33] is the or of <31:16>
7599 [32] is the or of <15:0>
7600 Two PCI internal interrupts for entry 32
7602 uint64_t gpio : 16; /**< 16 GPIO interrupts */
7603 uint64_t workq : 16; /**< 16 work queue interrupts
7604 1 bit/group. A copy of the R/W1C bit in the POW. */
7606 uint64_t workq : 16;
7610 uint64_t pci_int : 4;
7611 uint64_t pci_msi : 4;
7612 uint64_t wdog_sum : 1;
7616 uint64_t gmx_drp : 2;
7617 uint64_t ipd_drp : 1;
7618 uint64_t key_zero : 1;
7621 uint64_t reserved_57_58 : 2;
7624 uint64_t ipdppthr : 1;
7626 uint64_t bootdma : 1;
7629 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
7630 struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
7631 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
7632 struct cvmx_ciu_intx_sum0_cn61xx {
7633 #ifdef __BIG_ENDIAN_BITFIELD
7634 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7635 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7636 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt
7638 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7639 See IPD_PORT_QOS_INT* */
7640 uint64_t powiq : 1; /**< POW IQ interrupt
7642 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
7644 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction
7645 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
7646 uint64_t pcm : 1; /**< PCM/TDM interrupt */
7647 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
7648 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7649 uint64_t timer : 4; /**< General timer 0-3 interrupts.
7650 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
7651 common for all PP/IRQs, writing '1' to any PP/IRQ
7652 will clear all TIMERx(x=0..9) interrupts.
7653 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
7654 are set at the same time, but clearing are based on
7655 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
7656 The combination of this field and the
7657 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
7659 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
7660 This read-only bit reads as a one whenever any
7661 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
7662 and corresponding enable bit in CIU_EN2_PPX_IPx
7663 (CIU_EN2_IOX_INT) is set.
7664 Note that SUM2 only summarizes the SUM2/EN2
7665 result and does not have a corresponding enable
7666 bit, so does not directly contribute to
7668 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7669 Set any time PIP/IPD drops a packet */
7670 uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt
7671 Set any time corresponding GMX0/1 drops a packet */
7672 uint64_t trace : 1; /**< Trace buffer interrupt
7673 See TRA_INT_STATUS */
7674 uint64_t rml : 1; /**< RML Interrupt
7675 This interrupt will assert if any bit within
7676 CIU_BLOCK_INT is asserted. */
7677 uint64_t twsi : 1; /**< TWSI Interrupt
7679 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
7680 This read-only bit reads as a one whenever any
7681 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
7682 and corresponding enable bit in CIU_INTx_EN is set
7683 PPs use CIU_INTx_SUM0 where x=0-7
7684 PCIe uses the CIU_INTx_SUM0 where x=32-33.
7685 Note that WDOG_SUM only summarizes the SUM1/EN1
7686 result and does not have a corresponding enable
7687 bit, so does not directly contribute to
7689 uint64_t pci_msi : 4; /**< PCIe MSI
7690 See SLI_MSI_RCVn for bit <40+n> */
7691 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
7692 Refer to "Receiving Emulated INTA/INTB/
7693 INTC/INTD" in the SLI chapter of the spec
7697 PCI_INT<0> = INTA */
7698 uint64_t uart : 2; /**< Two UART interrupts
7699 See MIO_UARTn_IIR[IID] for bit <34+n> */
7700 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7701 [33] is the or of <31:16>
7702 [32] is the or of <15:0>
7703 Two PCIe internal interrupts for entries 32-33
7704 which equal CIU_PCI_INTA[INT] */
7705 uint64_t gpio : 16; /**< 16 GPIO interrupts
7706 When GPIO_MULTI_CAST[EN] == 1
7707 Write 1 to clear either the per PP or common GPIO
7708 edge-triggered interrupts,depending on mode.
7709 See GPIO_MULTI_CAST for all details.
7710 When GPIO_MULTI_CAST[EN] == 0
7711 Read Only, retain the same behavior as o63. */
7712 uint64_t workq : 16; /**< 16 work queue interrupts
7713 See POW_WQ_INT[WQ_INT]
7714 1 bit/group. A copy of the R/W1C bit in the POW. */
7716 uint64_t workq : 16;
7720 uint64_t pci_int : 4;
7721 uint64_t pci_msi : 4;
7722 uint64_t wdog_sum : 1;
7726 uint64_t gmx_drp : 2;
7727 uint64_t ipd_drp : 1;
7735 uint64_t ipdppthr : 1;
7737 uint64_t bootdma : 1;
7740 struct cvmx_ciu_intx_sum0_cn52xx cn63xx;
7741 struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1;
7742 struct cvmx_ciu_intx_sum0_cn66xx {
7743 #ifdef __BIG_ENDIAN_BITFIELD
7744 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7745 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7746 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
7748 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7749 See IPD_PORT_QOS_INT* */
7750 uint64_t powiq : 1; /**< POW IQ interrupt
7752 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
7754 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction
7755 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
7756 uint64_t reserved_57_57 : 1;
7757 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
7758 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7759 uint64_t timer : 4; /**< General timer 0-3 interrupts.
7760 Prior to pass 1.2 or
7761 when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is
7762 common for all PP/IRQs, writing '1' to any PP/IRQ
7763 will clear all TIMERx(x=0..9) interrupts.
7764 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
7765 are set at the same time, but clearing is per
7766 cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
7767 The combination of this field and the
7768 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
7770 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
7771 In pass 1.2 and subsequent passes,
7772 this read-only bit reads as a one whenever any
7773 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
7774 and corresponding enable bit in CIU_EN2_PPX_IPx
7775 (CIU_EN2_IOX_INT) is set.
7776 Note that SUM2 only summarizes the SUM2/EN2
7777 result and does not have a corresponding enable
7778 bit, so does not directly contribute to
7780 Prior to pass 1.2, SUM2 did not exist and this
7781 bit reads as zero. */
7782 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7783 Set any time PIP/IPD drops a packet */
7784 uint64_t gmx_drp : 2; /**< GMX0/1 packet drop interrupt
7785 Set any time corresponding GMX0/1 drops a packet */
7786 uint64_t trace : 1; /**< Trace buffer interrupt
7787 See TRA_INT_STATUS */
7788 uint64_t rml : 1; /**< RML Interrupt
7789 This interrupt will assert if any bit within
7790 CIU_BLOCK_INT is asserted. */
7791 uint64_t twsi : 1; /**< TWSI Interrupt
7793 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
7794 This read-only bit reads as a one whenever any
7795 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
7796 and corresponding enable bit in CIU_INTx_EN is set
7797 PPs use CIU_INTx_SUM0 where x=0-19
7798 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
7799 Note that WDOG_SUM only summarizes the SUM1/EN1
7800 result and does not have a corresponding enable
7801 bit, so does not directly contribute to
7803 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
7804 See SLI_MSI_RCVn for bit <40+n> */
7805 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
7806 Refer to "Receiving Emulated INTA/INTB/
7807 INTC/INTD" in the SLI chapter of the spec
7811 PCI_INT<0> = INTA */
7812 uint64_t uart : 2; /**< Two UART interrupts
7813 See MIO_UARTn_IIR[IID] for bit <34+n> */
7814 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7815 [33] is the or of <31:16>
7816 [32] is the or of <15:0>
7817 Two PCIe/sRIO internal interrupts for entries 32-33
7818 which equal CIU_PCI_INTA[INT] */
7819 uint64_t gpio : 16; /**< 16 GPIO interrupts */
7820 uint64_t workq : 16; /**< 16 work queue interrupts
7821 See POW_WQ_INT[WQ_INT]
7822 1 bit/group. A copy of the R/W1C bit in the POW. */
7824 uint64_t workq : 16;
7828 uint64_t pci_int : 4;
7829 uint64_t pci_msi : 4;
7830 uint64_t wdog_sum : 1;
7834 uint64_t gmx_drp : 2;
7835 uint64_t ipd_drp : 1;
7839 uint64_t reserved_57_57 : 1;
7843 uint64_t ipdppthr : 1;
7845 uint64_t bootdma : 1;
7848 struct cvmx_ciu_intx_sum0_cnf71xx {
7849 #ifdef __BIG_ENDIAN_BITFIELD
7850 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7851 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7852 uint64_t reserved_62_62 : 1;
7853 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7854 See IPD_PORT_QOS_INT* */
7855 uint64_t powiq : 1; /**< POW IQ interrupt
7857 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
7859 uint64_t mpi : 1; /**< MPI/SPI interrupt, Set when MPI transaction
7860 finished, see MPI_CFG[INT_ENA] and MPI_STS[BUSY] */
7861 uint64_t pcm : 1; /**< PCM/TDM interrupt */
7862 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
7863 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7864 uint64_t timer : 4; /**< General timer 0-3 interrupts.
7865 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
7866 common for all PP/IRQs, writing '1' to any PP/IRQ
7867 will clear all TIMERx(x=0..9) interrupts.
7868 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
7869 are set at the same time, but clearing are based on
7870 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
7871 The combination of this field and the
7872 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
7874 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
7875 This read-only bit reads as a one whenever any
7876 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
7877 and corresponding enable bit in CIU_EN2_PPX_IPx
7878 (CIU_EN2_IOX_INT) is set.
7879 Note that SUM2 only summarizes the SUM2/EN2
7880 result and does not have a corresponding enable
7881 bit, so does not directly contribute to
7883 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7884 Set any time PIP/IPD drops a packet */
7885 uint64_t reserved_49_49 : 1;
7886 uint64_t gmx_drp : 1; /**< GMX0/1 packet drop interrupt
7887 Set any time corresponding GMX0/1 drops a packet */
7888 uint64_t trace : 1; /**< Trace buffer interrupt
7889 See TRA_INT_STATUS */
7890 uint64_t rml : 1; /**< RML Interrupt
7891 This interrupt will assert if any bit within
7892 CIU_BLOCK_INT is asserted. */
7893 uint64_t twsi : 1; /**< TWSI Interrupt
7895 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
7896 This read-only bit reads as a one whenever any
7897 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
7898 and corresponding enable bit in CIU_INTx_EN is set
7899 PPs use CIU_INTx_SUM0 where x=0-7
7900 PCIe uses the CIU_INTx_SUM0 where x=32-33.
7901 Note that WDOG_SUM only summarizes the SUM1/EN1
7902 result and does not have a corresponding enable
7903 bit, so does not directly contribute to
7905 uint64_t pci_msi : 4; /**< PCIe MSI
7906 See SLI_MSI_RCVn for bit <40+n> */
7907 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
7908 Refer to "Receiving Emulated INTA/INTB/
7909 INTC/INTD" in the SLI chapter of the spec
7913 PCI_INT<0> = INTA */
7914 uint64_t uart : 2; /**< Two UART interrupts
7915 See MIO_UARTn_IIR[IID] for bit <34+n> */
7916 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7917 [33] is the or of <31:16>
7918 [32] is the or of <15:0>
7919 Two PCIe internal interrupts for entries 32-33
7920 which equal CIU_PCI_INTA[INT] */
7921 uint64_t gpio : 16; /**< 16 GPIO interrupts
7922 When GPIO_MULTI_CAST[EN] == 1
7923 Write 1 to clear either the per PP or common GPIO
7924 edge-triggered interrupts,depending on mode.
7925 See GPIO_MULTI_CAST for all details.
7926 When GPIO_MULTI_CAST[EN] == 0
7927 Read Only, retain the same behavior as o63. */
7928 uint64_t workq : 16; /**< 16 work queue interrupts
7929 See POW_WQ_INT[WQ_INT]
7930 1 bit/group. A copy of the R/W1C bit in the POW. */
7932 uint64_t workq : 16;
7936 uint64_t pci_int : 4;
7937 uint64_t pci_msi : 4;
7938 uint64_t wdog_sum : 1;
7942 uint64_t gmx_drp : 1;
7943 uint64_t reserved_49_49 : 1;
7944 uint64_t ipd_drp : 1;
7952 uint64_t ipdppthr : 1;
7953 uint64_t reserved_62_62 : 1;
7954 uint64_t bootdma : 1;
7958 typedef union cvmx_ciu_intx_sum0 cvmx_ciu_intx_sum0_t;
7961 * cvmx_ciu_int#_sum4
7963 union cvmx_ciu_intx_sum4 {
7965 struct cvmx_ciu_intx_sum4_s {
7966 #ifdef __BIG_ENDIAN_BITFIELD
7967 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7968 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7969 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
7971 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7972 See IPD_PORT_QOS_INT* */
7973 uint64_t powiq : 1; /**< POW IQ interrupt
7975 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
7977 uint64_t mpi : 1; /**< MPI/SPI interrupt */
7978 uint64_t pcm : 1; /**< PCM/TDM interrupt */
7979 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
7980 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7981 uint64_t timer : 4; /**< General timer 0-3 interrupts
7982 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
7983 common for all PP/IRQs, writing '1' to any PP/IRQ
7984 will clear all TIMERx(x=0..9) interrupts.
7985 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
7986 are set at the same time, but clearing are based on
7987 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
7988 The combination of this field and the
7989 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
7991 uint64_t reserved_51_51 : 1;
7992 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7993 Set any time PIP/IPD drops a packet */
7994 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt
7995 Set any time corresponding GMX drops a packet */
7996 uint64_t trace : 1; /**< Trace buffer interrupt
7997 See TRA_INT_STATUS */
7998 uint64_t rml : 1; /**< RML Interrupt
7999 This bit is set when any bit is set in
8001 uint64_t twsi : 1; /**< TWSI Interrupt
8003 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8004 This read-only bit reads as a one whenever any
8005 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
8006 and corresponding enable bit in CIU_INTx_EN is set
8007 PPs use CIU_INTx_SUM0 where x=0-19
8008 PCIe uses the CIU_INTx_SUM0 where x=32-33.
8009 Note that WDOG_SUM only summarizes the SUM1/EN1
8010 result and does not have a corresponding enable
8011 bit, so does not directly contribute to
8013 uint64_t pci_msi : 4; /**< PCIe MSI
8014 See SLI_MSI_RCVn for bit <40+n> */
8015 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8016 Refer to "Receiving Emulated INTA/INTB/
8017 INTC/INTD" in the SLI chapter of the spec
8021 PCI_INT<0> = INTA */
8022 uint64_t uart : 2; /**< Two UART interrupts
8023 See MIO_UARTn_IIR[IID] for bit <34+n> */
8024 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8025 [33] is the or of <31:16>
8026 [32] is the or of <15:0> */
8027 uint64_t gpio : 16; /**< 16 GPIO interrupts
8028 When GPIO_MULTI_CAST[EN] == 1
8029 Write 1 to clear either the per PP interrupt or
8030 common GPIO interrupt for all PP/IOs,depending
8031 on mode setting. This will apply to all 16 GPIOs.
8032 See GPIO_MULTI_CAST for all details
8033 When GPIO_MULTI_CAST[EN] == 0
8034 Read Only, retain the same behavior as o63. */
8035 uint64_t workq : 16; /**< 16 work queue interrupts
8036 See POW_WQ_INT[WQ_INT]
8037 1 bit/group. A copy of the R/W1C bit in the POW. */
8039 uint64_t workq : 16;
8043 uint64_t pci_int : 4;
8044 uint64_t pci_msi : 4;
8045 uint64_t wdog_sum : 1;
8049 uint64_t gmx_drp : 2;
8050 uint64_t ipd_drp : 1;
8051 uint64_t reserved_51_51 : 1;
8058 uint64_t ipdppthr : 1;
8060 uint64_t bootdma : 1;
8063 struct cvmx_ciu_intx_sum4_cn50xx {
8064 #ifdef __BIG_ENDIAN_BITFIELD
8065 uint64_t reserved_59_63 : 5;
8066 uint64_t mpi : 1; /**< MPI/SPI interrupt */
8067 uint64_t pcm : 1; /**< PCM/TDM interrupt */
8068 uint64_t usb : 1; /**< USB interrupt */
8069 uint64_t timer : 4; /**< General timer interrupts */
8070 uint64_t reserved_51_51 : 1;
8071 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
8072 uint64_t reserved_49_49 : 1;
8073 uint64_t gmx_drp : 1; /**< GMX packet drop */
8074 uint64_t reserved_47_47 : 1;
8075 uint64_t rml : 1; /**< RML Interrupt */
8076 uint64_t twsi : 1; /**< TWSI Interrupt */
8077 uint64_t wdog_sum : 1; /**< Watchdog summary
8078 PPs use CIU_INTx_SUM4 where x=0-1. */
8079 uint64_t pci_msi : 4; /**< PCI MSI
8080 [43] is the or of <63:48>
8081 [42] is the or of <47:32>
8082 [41] is the or of <31:16>
8083 [40] is the or of <15:0> */
8084 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
8085 uint64_t uart : 2; /**< Two UART interrupts */
8086 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
8087 [33] is the or of <31:16>
8088 [32] is the or of <15:0>
8089 Two PCI internal interrupts for entry 32
8091 uint64_t gpio : 16; /**< 16 GPIO interrupts */
8092 uint64_t workq : 16; /**< 16 work queue interrupts
8093 1 bit/group. A copy of the R/W1C bit in the POW. */
8095 uint64_t workq : 16;
8099 uint64_t pci_int : 4;
8100 uint64_t pci_msi : 4;
8101 uint64_t wdog_sum : 1;
8104 uint64_t reserved_47_47 : 1;
8105 uint64_t gmx_drp : 1;
8106 uint64_t reserved_49_49 : 1;
8107 uint64_t ipd_drp : 1;
8108 uint64_t reserved_51_51 : 1;
8113 uint64_t reserved_59_63 : 5;
8116 struct cvmx_ciu_intx_sum4_cn52xx {
8117 #ifdef __BIG_ENDIAN_BITFIELD
8118 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
8119 uint64_t mii : 1; /**< MII Interface Interrupt */
8120 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
8121 uint64_t powiq : 1; /**< POW IQ interrupt */
8122 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
8123 uint64_t reserved_57_58 : 2;
8124 uint64_t usb : 1; /**< USB Interrupt */
8125 uint64_t timer : 4; /**< General timer interrupts */
8126 uint64_t reserved_51_51 : 1;
8127 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
8128 uint64_t reserved_49_49 : 1;
8129 uint64_t gmx_drp : 1; /**< GMX packet drop */
8130 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
8131 uint64_t rml : 1; /**< RML Interrupt */
8132 uint64_t twsi : 1; /**< TWSI Interrupt */
8133 uint64_t wdog_sum : 1; /**< SUM1&EN4_1 summary bit
8134 This read-only bit reads as a one whenever any
8135 CIU_INT_SUM1 bit is set and corresponding
8136 enable bit in CIU_INTx_EN4_1 is set, where x
8137 is the same as x in this CIU_INTx_SUM4.
8138 PPs use CIU_INTx_SUM4 for IP4, where x=PPid.
8139 Note that WDOG_SUM only summarizes the SUM/EN4_1
8140 result and does not have a corresponding enable
8141 bit, so does not directly contribute to
8143 uint64_t pci_msi : 4; /**< PCI MSI
8144 Refer to "Receiving Message-Signalled
8145 Interrupts" in the PCIe chapter of the spec */
8146 uint64_t pci_int : 4; /**< PCI INTA/B/C/D
8147 Refer to "Receiving Emulated INTA/INTB/
8148 INTC/INTD" in the PCIe chapter of the spec */
8149 uint64_t uart : 2; /**< Two UART interrupts */
8150 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-3
8151 [33] is the or of <31:16>
8152 [32] is the or of <15:0> */
8153 uint64_t gpio : 16; /**< 16 GPIO interrupts */
8154 uint64_t workq : 16; /**< 16 work queue interrupts
8155 1 bit/group. A copy of the R/W1C bit in the POW. */
8157 uint64_t workq : 16;
8161 uint64_t pci_int : 4;
8162 uint64_t pci_msi : 4;
8163 uint64_t wdog_sum : 1;
8167 uint64_t gmx_drp : 1;
8168 uint64_t reserved_49_49 : 1;
8169 uint64_t ipd_drp : 1;
8170 uint64_t reserved_51_51 : 1;
8173 uint64_t reserved_57_58 : 2;
8176 uint64_t ipdppthr : 1;
8178 uint64_t bootdma : 1;
8181 struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
8182 struct cvmx_ciu_intx_sum4_cn56xx {
8183 #ifdef __BIG_ENDIAN_BITFIELD
8184 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */
8185 uint64_t mii : 1; /**< MII Interface Interrupt */
8186 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */
8187 uint64_t powiq : 1; /**< POW IQ interrupt */
8188 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */
8189 uint64_t reserved_57_58 : 2;
8190 uint64_t usb : 1; /**< USB Interrupt */
8191 uint64_t timer : 4; /**< General timer interrupts */
8192 uint64_t key_zero : 1; /**< Key Zeroization interrupt
8193 KEY_ZERO will be set when the external ZERO_KEYS
8194 pin is sampled high. KEY_ZERO is cleared by SW */
8195 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
8196 uint64_t gmx_drp : 2; /**< GMX packet drop */
8197 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
8198 uint64_t rml : 1; /**< RML Interrupt */
8199 uint64_t twsi : 1; /**< TWSI Interrupt */
8200 uint64_t wdog_sum : 1; /**< Watchdog summary
8201 These registers report WDOG to IP4 */
8202 uint64_t pci_msi : 4; /**< PCI MSI
8203 Refer to "Receiving Message-Signalled
8204 Interrupts" in the PCIe chapter of the spec */
8205 uint64_t pci_int : 4; /**< PCI INTA/B/C/D
8206 Refer to "Receiving Emulated INTA/INTB/
8207 INTC/INTD" in the PCIe chapter of the spec */
8208 uint64_t uart : 2; /**< Two UART interrupts */
8209 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
8210 [33] is the or of <31:16>
8211 [32] is the or of <15:0> */
8212 uint64_t gpio : 16; /**< 16 GPIO interrupts */
8213 uint64_t workq : 16; /**< 16 work queue interrupts
8214 1 bit/group. A copy of the R/W1C bit in the POW. */
8216 uint64_t workq : 16;
8220 uint64_t pci_int : 4;
8221 uint64_t pci_msi : 4;
8222 uint64_t wdog_sum : 1;
8226 uint64_t gmx_drp : 2;
8227 uint64_t ipd_drp : 1;
8228 uint64_t key_zero : 1;
8231 uint64_t reserved_57_58 : 2;
8234 uint64_t ipdppthr : 1;
8236 uint64_t bootdma : 1;
8239 struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
8240 struct cvmx_ciu_intx_sum4_cn58xx {
8241 #ifdef __BIG_ENDIAN_BITFIELD
8242 uint64_t reserved_56_63 : 8;
8243 uint64_t timer : 4; /**< General timer interrupts */
8244 uint64_t key_zero : 1; /**< Key Zeroization interrupt
8245 KEY_ZERO will be set when the external ZERO_KEYS
8246 pin is sampled high. KEY_ZERO is cleared by SW */
8247 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */
8248 uint64_t gmx_drp : 2; /**< GMX packet drop */
8249 uint64_t trace : 1; /**< L2C has the CMB trace buffer */
8250 uint64_t rml : 1; /**< RML Interrupt */
8251 uint64_t twsi : 1; /**< TWSI Interrupt */
8252 uint64_t wdog_sum : 1; /**< Watchdog summary
8253 These registers report WDOG to IP4 */
8254 uint64_t pci_msi : 4; /**< PCI MSI
8255 [43] is the or of <63:48>
8256 [42] is the or of <47:32>
8257 [41] is the or of <31:16>
8258 [40] is the or of <15:0> */
8259 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */
8260 uint64_t uart : 2; /**< Two UART interrupts */
8261 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
8262 [33] is the or of <31:16>
8263 [32] is the or of <15:0>
8264 Two PCI internal interrupts for entry 32
8266 uint64_t gpio : 16; /**< 16 GPIO interrupts */
8267 uint64_t workq : 16; /**< 16 work queue interrupts
8268 1 bit/group. A copy of the R/W1C bit in the POW. */
8270 uint64_t workq : 16;
8274 uint64_t pci_int : 4;
8275 uint64_t pci_msi : 4;
8276 uint64_t wdog_sum : 1;
8280 uint64_t gmx_drp : 2;
8281 uint64_t ipd_drp : 1;
8282 uint64_t key_zero : 1;
8284 uint64_t reserved_56_63 : 8;
8287 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
8288 struct cvmx_ciu_intx_sum4_cn61xx {
8289 #ifdef __BIG_ENDIAN_BITFIELD
8290 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8291 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8292 uint64_t mii : 1; /**< RGMII/MIX Interface 0 Interrupt
8294 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8295 See IPD_PORT_QOS_INT* */
8296 uint64_t powiq : 1; /**< POW IQ interrupt
8298 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
8300 uint64_t mpi : 1; /**< MPI/SPI interrupt */
8301 uint64_t pcm : 1; /**< PCM/TDM interrupt */
8302 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
8303 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8304 uint64_t timer : 4; /**< General timer 0-3 interrupts
8305 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
8306 common for all PP/IRQs, writing '1' to any PP/IRQ
8307 will clear all TIMERx(x=0..9) interrupts.
8308 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
8309 are set at the same time, but clearing are based on
8310 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
8311 The combination of this field and the
8312 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
8314 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
8315 This read-only bit reads as a one whenever any
8316 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
8317 and corresponding enable bit in CIU_EN2_PPX_IPx
8318 (CIU_EN2_IOX_INT) is set.
8319 Note that WDOG_SUM only summarizes the SUM2/EN2
8320 result and does not have a corresponding enable
8321 bit, so does not directly contribute to
8323 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8324 Set any time PIP/IPD drops a packet */
8325 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt
8326 Set any time corresponding GMX drops a packet */
8327 uint64_t trace : 1; /**< Trace buffer interrupt
8328 See TRA_INT_STATUS */
8329 uint64_t rml : 1; /**< RML Interrupt
8330 This bit is set when any bit is set in
8332 uint64_t twsi : 1; /**< TWSI Interrupt
8334 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8335 This read-only bit reads as a one whenever any
8336 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
8337 and corresponding enable bit in CIU_INTx_EN is set
8338 PPs use CIU_INTx_SUM0 where x=0-19
8339 PCIe uses the CIU_INTx_SUM0 where x=32-33.
8340 Note that WDOG_SUM only summarizes the SUM1/EN1
8341 result and does not have a corresponding enable
8342 bit, so does not directly contribute to
8344 uint64_t pci_msi : 4; /**< PCIe MSI
8345 See SLI_MSI_RCVn for bit <40+n> */
8346 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8347 Refer to "Receiving Emulated INTA/INTB/
8348 INTC/INTD" in the SLI chapter of the spec
8352 PCI_INT<0> = INTA */
8353 uint64_t uart : 2; /**< Two UART interrupts
8354 See MIO_UARTn_IIR[IID] for bit <34+n> */
8355 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8356 [33] is the or of <31:16>
8357 [32] is the or of <15:0> */
8358 uint64_t gpio : 16; /**< 16 GPIO interrupts
8359 When GPIO_MULTI_CAST[EN] == 1
8360 Write 1 to clear either the per PP interrupt or
8361 common GPIO interrupt for all PP/IOs,depending
8362 on mode setting. This will apply to all 16 GPIOs.
8363 See GPIO_MULTI_CAST for all details
8364 When GPIO_MULTI_CAST[EN] == 0
8365 Read Only, retain the same behavior as o63. */
8366 uint64_t workq : 16; /**< 16 work queue interrupts
8367 See POW_WQ_INT[WQ_INT]
8368 1 bit/group. A copy of the R/W1C bit in the POW. */
8370 uint64_t workq : 16;
8374 uint64_t pci_int : 4;
8375 uint64_t pci_msi : 4;
8376 uint64_t wdog_sum : 1;
8380 uint64_t gmx_drp : 2;
8381 uint64_t ipd_drp : 1;
8389 uint64_t ipdppthr : 1;
8391 uint64_t bootdma : 1;
8394 struct cvmx_ciu_intx_sum4_cn52xx cn63xx;
8395 struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1;
8396 struct cvmx_ciu_intx_sum4_cn66xx {
8397 #ifdef __BIG_ENDIAN_BITFIELD
8398 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8399 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8400 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8402 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8403 See IPD_PORT_QOS_INT* */
8404 uint64_t powiq : 1; /**< POW IQ interrupt
8406 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
8408 uint64_t mpi : 1; /**< MPI/SPI interrupt */
8409 uint64_t reserved_57_57 : 1;
8410 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
8411 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8412 uint64_t timer : 4; /**< General timer 0-3 interrupts.
8413 Prior to pass 1.2 or
8414 when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is
8415 common for all PP/IRQs, writing '1' to any PP/IRQ
8416 will clear all TIMERx(x=0..9) interrupts.
8417 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
8418 are set at the same time, but clearing is per
8419 cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
8420 The combination of this field and the
8421 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
8423 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
8424 In pass 1.2 and subsequent passes,
8425 this read-only bit reads as a one whenever any
8426 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
8427 and corresponding enable bit in CIU_EN2_PPX_IPx
8428 (CIU_EN2_IOX_INT) is set.
8429 Note that WDOG_SUM only summarizes the SUM2/EN2
8430 result and does not have a corresponding enable
8431 bit, so does not directly contribute to
8433 Prior to pass 1.2, SUM2 did not exist and this
8434 bit reads as zero. */
8435 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8436 Set any time PIP/IPD drops a packet */
8437 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt
8438 Set any time corresponding GMX drops a packet */
8439 uint64_t trace : 1; /**< Trace buffer interrupt
8440 See TRA_INT_STATUS */
8441 uint64_t rml : 1; /**< RML Interrupt
8442 This bit is set when any bit is set in
8444 uint64_t twsi : 1; /**< TWSI Interrupt
8446 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8447 This read-only bit reads as a one whenever any
8448 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
8449 and corresponding enable bit in CIU_INTx_EN is set
8450 PPs use CIU_INTx_SUM0 where x=0-19
8451 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
8452 Note that WDOG_SUM only summarizes the SUM1/EN1
8453 result and does not have a corresponding enable
8454 bit, so does not directly contribute to
8456 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
8457 See SLI_MSI_RCVn for bit <40+n> */
8458 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8459 Refer to "Receiving Emulated INTA/INTB/
8460 INTC/INTD" in the SLI chapter of the spec
8464 PCI_INT<0> = INTA */
8465 uint64_t uart : 2; /**< Two UART interrupts
8466 See MIO_UARTn_IIR[IID] for bit <34+n> */
8467 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8468 [33] is the or of <31:16>
8469 [32] is the or of <15:0> */
8470 uint64_t gpio : 16; /**< 16 GPIO interrupts */
8471 uint64_t workq : 16; /**< 16 work queue interrupts
8472 See POW_WQ_INT[WQ_INT]
8473 1 bit/group. A copy of the R/W1C bit in the POW. */
8475 uint64_t workq : 16;
8479 uint64_t pci_int : 4;
8480 uint64_t pci_msi : 4;
8481 uint64_t wdog_sum : 1;
8485 uint64_t gmx_drp : 2;
8486 uint64_t ipd_drp : 1;
8490 uint64_t reserved_57_57 : 1;
8494 uint64_t ipdppthr : 1;
8496 uint64_t bootdma : 1;
8499 struct cvmx_ciu_intx_sum4_cnf71xx {
8500 #ifdef __BIG_ENDIAN_BITFIELD
8501 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8502 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8503 uint64_t reserved_62_62 : 1;
8504 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8505 See IPD_PORT_QOS_INT* */
8506 uint64_t powiq : 1; /**< POW IQ interrupt
8508 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
8510 uint64_t mpi : 1; /**< MPI/SPI interrupt */
8511 uint64_t pcm : 1; /**< PCM/TDM interrupt */
8512 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
8513 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8514 uint64_t timer : 4; /**< General timer 0-3 interrupts
8515 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
8516 common for all PP/IRQs, writing '1' to any PP/IRQ
8517 will clear all TIMERx(x=0..9) interrupts.
8518 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
8519 are set at the same time, but clearing are based on
8520 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
8521 The combination of this field and the
8522 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
8524 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
8525 This read-only bit reads as a one whenever any
8526 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
8527 and corresponding enable bit in CIU_EN2_PPX_IPx
8528 (CIU_EN2_IOX_INT) is set.
8529 Note that WDOG_SUM only summarizes the SUM2/EN2
8530 result and does not have a corresponding enable
8531 bit, so does not directly contribute to
8533 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8534 Set any time PIP/IPD drops a packet */
8535 uint64_t reserved_49_49 : 1;
8536 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt
8537 Set any time corresponding GMX drops a packet */
8538 uint64_t trace : 1; /**< Trace buffer interrupt
8539 See TRA_INT_STATUS */
8540 uint64_t rml : 1; /**< RML Interrupt
8541 This bit is set when any bit is set in
8543 uint64_t twsi : 1; /**< TWSI Interrupt
8545 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8546 This read-only bit reads as a one whenever any
8547 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
8548 and corresponding enable bit in CIU_INTx_EN is set
8549 PPs use CIU_INTx_SUM0 where x=0-19
8550 PCIe uses the CIU_INTx_SUM0 where x=32-33.
8551 Note that WDOG_SUM only summarizes the SUM1/EN1
8552 result and does not have a corresponding enable
8553 bit, so does not directly contribute to
8555 uint64_t pci_msi : 4; /**< PCIe MSI
8556 See SLI_MSI_RCVn for bit <40+n> */
8557 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8558 Refer to "Receiving Emulated INTA/INTB/
8559 INTC/INTD" in the SLI chapter of the spec
8563 PCI_INT<0> = INTA */
8564 uint64_t uart : 2; /**< Two UART interrupts
8565 See MIO_UARTn_IIR[IID] for bit <34+n> */
8566 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8567 [33] is the or of <31:16>
8568 [32] is the or of <15:0> */
8569 uint64_t gpio : 16; /**< 16 GPIO interrupts
8570 When GPIO_MULTI_CAST[EN] == 1
8571 Write 1 to clear either the per PP interrupt or
8572 common GPIO interrupt for all PP/IOs,depending
8573 on mode setting. This will apply to all 16 GPIOs.
8574 See GPIO_MULTI_CAST for all details
8575 When GPIO_MULTI_CAST[EN] == 0
8576 Read Only, retain the same behavior as o63. */
8577 uint64_t workq : 16; /**< 16 work queue interrupts
8578 See POW_WQ_INT[WQ_INT]
8579 1 bit/group. A copy of the R/W1C bit in the POW. */
8581 uint64_t workq : 16;
8585 uint64_t pci_int : 4;
8586 uint64_t pci_msi : 4;
8587 uint64_t wdog_sum : 1;
8591 uint64_t gmx_drp : 1;
8592 uint64_t reserved_49_49 : 1;
8593 uint64_t ipd_drp : 1;
8601 uint64_t ipdppthr : 1;
8602 uint64_t reserved_62_62 : 1;
8603 uint64_t bootdma : 1;
8607 typedef union cvmx_ciu_intx_sum4 cvmx_ciu_intx_sum4_t;
8610 * cvmx_ciu_int33_sum0
8612 union cvmx_ciu_int33_sum0 {
8614 struct cvmx_ciu_int33_sum0_s {
8615 #ifdef __BIG_ENDIAN_BITFIELD
8616 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8617 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8618 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8620 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8621 See IPD_PORT_QOS_INT* */
8622 uint64_t powiq : 1; /**< POW IQ interrupt
8624 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
8626 uint64_t mpi : 1; /**< MPI/SPI interrupt */
8627 uint64_t pcm : 1; /**< PCM/TDM interrupt */
8628 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
8629 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8630 uint64_t timer : 4; /**< General timer 0-3 interrupts.
8631 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
8632 common for all PP/IRQs, writing '1' to any PP/IRQ
8633 will clear all TIMERx(x=0..9) interrupts.
8634 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
8635 are set at the same time, but clearing are based on
8636 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
8637 The combination of this field and the
8638 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
8640 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
8641 This read-only bit reads as a one whenever any
8642 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
8643 and corresponding enable bit in CIU_EN2_PPX_IPx
8644 (CIU_EN2_IOX_INT) is set.
8645 Note that SUM2 only summarizes the SUM2/EN2
8646 result and does not have a corresponding enable
8647 bit, so does not directly contribute to
8649 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8650 Set any time PIP/IPD drops a packet */
8651 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt
8652 Set any time corresponding GMX drops a packet */
8653 uint64_t trace : 1; /**< Trace buffer interrupt
8654 See TRA_INT_STATUS */
8655 uint64_t rml : 1; /**< RML Interrupt
8656 This interrupt will assert if any bit within
8657 CIU_BLOCK_INT is asserted. */
8658 uint64_t twsi : 1; /**< TWSI Interrupt
8660 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8661 This read-only bit reads as a one whenever any
8662 CIU_SUM1_PPX_IPx bit is set and corresponding
8663 enable bit in CIU_INTx_EN is set, where x
8664 is the same as x in this CIU_INTx_SUM0.
8665 PPs use CIU_INTx_SUM0 where x=0-7.
8666 PCIe uses the CIU_INTx_SUM0 where x=32-33.
8667 Note that WDOG_SUM only summarizes the SUM1/EN1
8668 result and does not have a corresponding enable
8669 bit, so does not directly contribute to
8671 uint64_t pci_msi : 4; /**< PCIe MSI
8672 See SLI_MSI_RCVn for bit <40+n> */
8673 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8674 Refer to "Receiving Emulated INTA/INTB/
8675 INTC/INTD" in the SLI chapter of the spec
8679 PCI_INT<0> = INTA */
8680 uint64_t uart : 2; /**< Two UART interrupts
8681 See MIO_UARTn_IIR[IID] for bit <34+n> */
8682 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8683 uint64_t gpio : 16; /**< 16 GPIO interrupts
8684 When GPIO_MULTI_CAST[EN] == 1
8685 Write 1 to clear either the per PP or common GPIO
8686 edge-triggered interrupts,depending on mode.
8687 See GPIO_MULTI_CAST for all details.
8688 When GPIO_MULTI_CAST[EN] == 0
8689 Read Only, retain the same behavior as o63. */
8690 uint64_t workq : 16; /**< 16 work queue interrupts
8691 See POW_WQ_INT[WQ_INT]
8692 1 bit/group. A copy of the R/W1C bit in the POW. */
8694 uint64_t workq : 16;
8698 uint64_t pci_int : 4;
8699 uint64_t pci_msi : 4;
8700 uint64_t wdog_sum : 1;
8704 uint64_t gmx_drp : 2;
8705 uint64_t ipd_drp : 1;
8713 uint64_t ipdppthr : 1;
8715 uint64_t bootdma : 1;
8718 struct cvmx_ciu_int33_sum0_s cn61xx;
8719 struct cvmx_ciu_int33_sum0_cn63xx {
8720 #ifdef __BIG_ENDIAN_BITFIELD
8721 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8722 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8723 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8725 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8726 See IPD_PORT_QOS_INT* */
8727 uint64_t powiq : 1; /**< POW IQ interrupt
8729 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
8731 uint64_t reserved_57_58 : 2;
8732 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
8733 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8734 uint64_t timer : 4; /**< General timer interrupts
8735 Set any time the corresponding CIU timer expires */
8736 uint64_t reserved_51_51 : 1;
8737 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8738 Set any time PIP/IPD drops a packet */
8739 uint64_t reserved_49_49 : 1;
8740 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt
8741 Set any time corresponding GMX drops a packet */
8742 uint64_t trace : 1; /**< Trace buffer interrupt
8743 See TRA_INT_STATUS */
8744 uint64_t rml : 1; /**< RML Interrupt
8745 This interrupt will assert if any bit within
8746 CIU_BLOCK_INT is asserted. */
8747 uint64_t twsi : 1; /**< TWSI Interrupt
8749 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8750 This read-only bit reads as a one whenever any
8751 CIU_INT_SUM1 bit is set and corresponding
8752 enable bit in CIU_INTx_EN is set, where x
8753 is the same as x in this CIU_INTx_SUM0.
8754 PPs use CIU_INTx_SUM0 where x=0-11.
8755 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
8756 Even INTx registers report WDOG to IP2
8757 Odd INTx registers report WDOG to IP3
8758 Note that WDOG_SUM only summarizes the SUM/EN1
8759 result and does not have a corresponding enable
8760 bit, so does not directly contribute to
8762 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
8763 See SLI_MSI_RCVn for bit <40+n> */
8764 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8765 Refer to "Receiving Emulated INTA/INTB/
8766 INTC/INTD" in the SLI chapter of the spec
8770 PCI_INT<0> = INTA */
8771 uint64_t uart : 2; /**< Two UART interrupts
8772 See MIO_UARTn_IIR[IID] for bit <34+n> */
8773 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8774 uint64_t gpio : 16; /**< 16 GPIO interrupts */
8775 uint64_t workq : 16; /**< 16 work queue interrupts
8776 See POW_WQ_INT[WQ_INT]
8777 1 bit/group. A copy of the R/W1C bit in the POW. */
8779 uint64_t workq : 16;
8783 uint64_t pci_int : 4;
8784 uint64_t pci_msi : 4;
8785 uint64_t wdog_sum : 1;
8789 uint64_t gmx_drp : 1;
8790 uint64_t reserved_49_49 : 1;
8791 uint64_t ipd_drp : 1;
8792 uint64_t reserved_51_51 : 1;
8795 uint64_t reserved_57_58 : 2;
8798 uint64_t ipdppthr : 1;
8800 uint64_t bootdma : 1;
8803 struct cvmx_ciu_int33_sum0_cn63xx cn63xxp1;
8804 struct cvmx_ciu_int33_sum0_cn66xx {
8805 #ifdef __BIG_ENDIAN_BITFIELD
8806 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8807 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8808 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt
8810 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8811 See IPD_PORT_QOS_INT* */
8812 uint64_t powiq : 1; /**< POW IQ interrupt
8814 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
8816 uint64_t mpi : 1; /**< MPI/SPI interrupt */
8817 uint64_t reserved_57_57 : 1;
8818 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
8819 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8820 uint64_t timer : 4; /**< General timer 0-3 interrupts.
8821 Prior to pass 1.2 or
8822 when CIU_TIM_MULTI_CAST[EN]==0, this interrupt is
8823 common for all PP/IRQs, writing '1' to any PP/IRQ
8824 will clear all TIMERx(x=0..9) interrupts.
8825 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
8826 are set at the same time, but clearing is per
8827 cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
8828 The combination of this field and the
8829 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
8831 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
8832 In pass 1.2 and subsequent passes,
8833 this read-only bit reads as a one whenever any
8834 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
8835 and corresponding enable bit in CIU_EN2_PPX_IPx
8836 (CIU_EN2_IOX_INT) is set.
8837 Note that SUM2 only summarizes the SUM2/EN2
8838 result and does not have a corresponding enable
8839 bit, so does not directly contribute to
8841 Prior to pass 1.2, SUM2 did not exist and this
8842 bit reads as zero. */
8843 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8844 Set any time PIP/IPD drops a packet */
8845 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt
8846 Set any time corresponding GMX drops a packet */
8847 uint64_t trace : 1; /**< Trace buffer interrupt
8848 See TRA_INT_STATUS */
8849 uint64_t rml : 1; /**< RML Interrupt
8850 This interrupt will assert if any bit within
8851 CIU_BLOCK_INT is asserted. */
8852 uint64_t twsi : 1; /**< TWSI Interrupt
8854 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8855 This read-only bit reads as a one whenever any
8856 CIU_SUM1_PPX_IPx (CIU_SUM1_IOX_INT) bit is set
8857 and corresponding enable bit in CIU_INTx_EN is set
8858 PPs use CIU_INTx_SUM0 where x=0-19
8859 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33.
8860 Note that WDOG_SUM only summarizes the SUM1/EN1
8861 result and does not have a corresponding enable
8862 bit, so does not directly contribute to
8864 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
8865 See SLI_MSI_RCVn for bit <40+n> */
8866 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8867 Refer to "Receiving Emulated INTA/INTB/
8868 INTC/INTD" in the SLI chapter of the spec
8872 PCI_INT<0> = INTA */
8873 uint64_t uart : 2; /**< Two UART interrupts
8874 See MIO_UARTn_IIR[IID] for bit <34+n> */
8875 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8876 uint64_t gpio : 16; /**< 16 GPIO interrupts */
8877 uint64_t workq : 16; /**< 16 work queue interrupts
8878 See POW_WQ_INT[WQ_INT]
8879 1 bit/group. A copy of the R/W1C bit in the POW. */
8881 uint64_t workq : 16;
8885 uint64_t pci_int : 4;
8886 uint64_t pci_msi : 4;
8887 uint64_t wdog_sum : 1;
8891 uint64_t gmx_drp : 2;
8892 uint64_t ipd_drp : 1;
8896 uint64_t reserved_57_57 : 1;
8900 uint64_t ipdppthr : 1;
8902 uint64_t bootdma : 1;
8905 struct cvmx_ciu_int33_sum0_cnf71xx {
8906 #ifdef __BIG_ENDIAN_BITFIELD
8907 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8908 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8909 uint64_t reserved_62_62 : 1;
8910 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8911 See IPD_PORT_QOS_INT* */
8912 uint64_t powiq : 1; /**< POW IQ interrupt
8914 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt
8916 uint64_t mpi : 1; /**< MPI/SPI interrupt */
8917 uint64_t pcm : 1; /**< PCM/TDM interrupt */
8918 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt
8919 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8920 uint64_t timer : 4; /**< General timer 0-3 interrupts.
8921 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
8922 common for all PP/IRQs, writing '1' to any PP/IRQ
8923 will clear all TIMERx(x=0..9) interrupts.
8924 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
8925 are set at the same time, but clearing are based on
8926 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
8927 The combination of this field and the
8928 CIU_SUM2_*[TIMER] field implement all 10 CIU_TIM*
8930 uint64_t sum2 : 1; /**< SUM2&EN2 SUMMARY bit
8931 This read-only bit reads as a one whenever any
8932 CIU_SUM2_PPX_IPx (CIU_SUM2_IOX_INT) bit is set
8933 and corresponding enable bit in CIU_EN2_PPX_IPx
8934 (CIU_EN2_IOX_INT) is set.
8935 Note that SUM2 only summarizes the SUM2/EN2
8936 result and does not have a corresponding enable
8937 bit, so does not directly contribute to
8939 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8940 Set any time PIP/IPD drops a packet */
8941 uint64_t reserved_49_49 : 1;
8942 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt
8943 Set any time corresponding GMX drops a packet */
8944 uint64_t trace : 1; /**< Trace buffer interrupt
8945 See TRA_INT_STATUS */
8946 uint64_t rml : 1; /**< RML Interrupt
8947 This interrupt will assert if any bit within
8948 CIU_BLOCK_INT is asserted. */
8949 uint64_t twsi : 1; /**< TWSI Interrupt
8951 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit
8952 This read-only bit reads as a one whenever any
8953 CIU_SUM1_PPX_IPx bit is set and corresponding
8954 enable bit in CIU_INTx_EN is set, where x
8955 is the same as x in this CIU_INTx_SUM0.
8956 PPs use CIU_INTx_SUM0 where x=0-7.
8957 PCIe uses the CIU_INTx_SUM0 where x=32-33.
8958 Note that WDOG_SUM only summarizes the SUM1/EN1
8959 result and does not have a corresponding enable
8960 bit, so does not directly contribute to
8962 uint64_t pci_msi : 4; /**< PCIe MSI
8963 See SLI_MSI_RCVn for bit <40+n> */
8964 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D
8965 Refer to "Receiving Emulated INTA/INTB/
8966 INTC/INTD" in the SLI chapter of the spec
8970 PCI_INT<0> = INTA */
8971 uint64_t uart : 2; /**< Two UART interrupts
8972 See MIO_UARTn_IIR[IID] for bit <34+n> */
8973 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8974 uint64_t gpio : 16; /**< 16 GPIO interrupts
8975 When GPIO_MULTI_CAST[EN] == 1
8976 Write 1 to clear either the per PP or common GPIO
8977 edge-triggered interrupts,depending on mode.
8978 See GPIO_MULTI_CAST for all details.
8979 When GPIO_MULTI_CAST[EN] == 0
8980 Read Only, retain the same behavior as o63. */
8981 uint64_t workq : 16; /**< 16 work queue interrupts
8982 See POW_WQ_INT[WQ_INT]
8983 1 bit/group. A copy of the R/W1C bit in the POW. */
8985 uint64_t workq : 16;
8989 uint64_t pci_int : 4;
8990 uint64_t pci_msi : 4;
8991 uint64_t wdog_sum : 1;
8995 uint64_t gmx_drp : 1;
8996 uint64_t reserved_49_49 : 1;
8997 uint64_t ipd_drp : 1;
9005 uint64_t ipdppthr : 1;
9006 uint64_t reserved_62_62 : 1;
9007 uint64_t bootdma : 1;
9011 typedef union cvmx_ciu_int33_sum0 cvmx_ciu_int33_sum0_t;
9014 * cvmx_ciu_int_dbg_sel
9016 union cvmx_ciu_int_dbg_sel {
9018 struct cvmx_ciu_int_dbg_sel_s {
9019 #ifdef __BIG_ENDIAN_BITFIELD
9020 uint64_t reserved_19_63 : 45;
9021 uint64_t sel : 3; /**< Selects if all or the specific interrupt is
9022 presented on the debug port.
9025 2=toggle at sclk/2 freq
9026 3=All PP interrupt bits are ORed together
9027 4=Only the selected virtual PP/IRQ is selected */
9028 uint64_t reserved_10_15 : 6;
9029 uint64_t irq : 2; /**< Which IRQ to select
9033 uint64_t reserved_5_7 : 3;
9034 uint64_t pp : 5; /**< Which PP to select */
9037 uint64_t reserved_5_7 : 3;
9039 uint64_t reserved_10_15 : 6;
9041 uint64_t reserved_19_63 : 45;
9044 struct cvmx_ciu_int_dbg_sel_cn61xx {
9045 #ifdef __BIG_ENDIAN_BITFIELD
9046 uint64_t reserved_19_63 : 45;
9047 uint64_t sel : 3; /**< Selects if all or the specific interrupt is
9048 presented on the debug port.
9051 2=toggle at sclk/2 freq
9052 3=All PP interrupt bits are ORed together
9053 4=Only the selected virtual PP/IRQ is selected */
9054 uint64_t reserved_10_15 : 6;
9055 uint64_t irq : 2; /**< Which IRQ to select
9059 uint64_t reserved_4_7 : 4;
9060 uint64_t pp : 4; /**< Which PP to select */
9063 uint64_t reserved_4_7 : 4;
9065 uint64_t reserved_10_15 : 6;
9067 uint64_t reserved_19_63 : 45;
9070 struct cvmx_ciu_int_dbg_sel_cn63xx {
9071 #ifdef __BIG_ENDIAN_BITFIELD
9072 uint64_t reserved_19_63 : 45;
9073 uint64_t sel : 3; /**< Selects if all or the specific interrupt is
9074 presented on the debug port.
9077 2=toggle at sclk/2 freq
9078 3=All PP interrupt bits are ORed together
9079 4=Only the selected physical PP/IRQ is selected */
9080 uint64_t reserved_10_15 : 6;
9081 uint64_t irq : 2; /**< Which IRQ to select
9085 uint64_t reserved_3_7 : 5;
9086 uint64_t pp : 3; /**< Which PP to select */
9089 uint64_t reserved_3_7 : 5;
9091 uint64_t reserved_10_15 : 6;
9093 uint64_t reserved_19_63 : 45;
9096 struct cvmx_ciu_int_dbg_sel_cn61xx cn66xx;
9097 struct cvmx_ciu_int_dbg_sel_s cn68xx;
9098 struct cvmx_ciu_int_dbg_sel_s cn68xxp1;
9099 struct cvmx_ciu_int_dbg_sel_cn61xx cnf71xx;
9101 typedef union cvmx_ciu_int_dbg_sel cvmx_ciu_int_dbg_sel_t;
9106 union cvmx_ciu_int_sum1 {
9108 struct cvmx_ciu_int_sum1_s {
9109 #ifdef __BIG_ENDIAN_BITFIELD
9110 uint64_t rst : 1; /**< MIO RST interrupt
9112 uint64_t reserved_62_62 : 1;
9113 uint64_t srio3 : 1; /**< SRIO3 interrupt
9114 See SRIO3_INT_REG, SRIO3_INT2_REG */
9115 uint64_t srio2 : 1; /**< SRIO2 interrupt
9116 See SRIO2_INT_REG, SRIO2_INT2_REG */
9117 uint64_t reserved_57_59 : 3;
9118 uint64_t dfm : 1; /**< DFM Interrupt
9120 uint64_t reserved_53_55 : 3;
9121 uint64_t lmc0 : 1; /**< LMC0 interrupt
9123 uint64_t srio1 : 1; /**< SRIO1 interrupt
9124 See SRIO1_INT_REG */
9125 uint64_t srio0 : 1; /**< SRIO0 interrupt
9126 See SRIO0_INT_REG, SRIO0_INT2_REG */
9127 uint64_t pem1 : 1; /**< PEM1 interrupt
9128 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
9129 uint64_t pem0 : 1; /**< PEM0 interrupt
9130 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
9131 uint64_t ptp : 1; /**< PTP interrupt
9132 Set when HW decrements MIO_PTP_EVT_CNT to zero */
9133 uint64_t agl : 1; /**< AGL interrupt
9134 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
9135 uint64_t reserved_38_45 : 8;
9136 uint64_t agx1 : 1; /**< GMX1 interrupt
9137 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
9138 PCS1_INT*_REG, PCSX1_INT_REG */
9139 uint64_t agx0 : 1; /**< GMX0 interrupt
9140 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
9141 PCS0_INT*_REG, PCSX0_INT_REG */
9142 uint64_t dpi : 1; /**< DPI interrupt
9144 uint64_t sli : 1; /**< SLI interrupt
9145 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
9146 uint64_t usb : 1; /**< USB UCTL0 interrupt
9147 See UCTL0_INT_REG */
9148 uint64_t dfa : 1; /**< DFA interrupt
9150 uint64_t key : 1; /**< KEY interrupt
9152 uint64_t rad : 1; /**< RAD interrupt
9153 See RAD_REG_ERROR */
9154 uint64_t tim : 1; /**< TIM interrupt
9155 See TIM_REG_ERROR */
9156 uint64_t zip : 1; /**< ZIP interrupt
9158 uint64_t pko : 1; /**< PKO interrupt
9159 See PKO_REG_ERROR */
9160 uint64_t pip : 1; /**< PIP interrupt
9162 uint64_t ipd : 1; /**< IPD interrupt
9164 uint64_t l2c : 1; /**< L2C interrupt
9166 uint64_t pow : 1; /**< POW err interrupt
9168 uint64_t fpa : 1; /**< FPA interrupt
9170 uint64_t iob : 1; /**< IOB interrupt
9172 uint64_t mio : 1; /**< MIO boot interrupt
9174 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
9175 See EMMC interrupt */
9176 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
9178 uint64_t usb1 : 1; /**< Second USB Interrupt */
9179 uint64_t uart2 : 1; /**< Third UART interrupt */
9180 uint64_t wdog : 16; /**< Per PP watchdog interrupts */
9205 uint64_t reserved_38_45 : 8;
9213 uint64_t reserved_53_55 : 3;
9215 uint64_t reserved_57_59 : 3;
9218 uint64_t reserved_62_62 : 1;
9222 struct cvmx_ciu_int_sum1_cn30xx {
9223 #ifdef __BIG_ENDIAN_BITFIELD
9224 uint64_t reserved_1_63 : 63;
9225 uint64_t wdog : 1; /**< 1 watchdog interrupt */
9228 uint64_t reserved_1_63 : 63;
9231 struct cvmx_ciu_int_sum1_cn31xx {
9232 #ifdef __BIG_ENDIAN_BITFIELD
9233 uint64_t reserved_2_63 : 62;
9234 uint64_t wdog : 2; /**< 2 watchdog interrupts */
9237 uint64_t reserved_2_63 : 62;
9240 struct cvmx_ciu_int_sum1_cn38xx {
9241 #ifdef __BIG_ENDIAN_BITFIELD
9242 uint64_t reserved_16_63 : 48;
9243 uint64_t wdog : 16; /**< 16 watchdog interrupts */
9246 uint64_t reserved_16_63 : 48;
9249 struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
9250 struct cvmx_ciu_int_sum1_cn31xx cn50xx;
9251 struct cvmx_ciu_int_sum1_cn52xx {
9252 #ifdef __BIG_ENDIAN_BITFIELD
9253 uint64_t reserved_20_63 : 44;
9254 uint64_t nand : 1; /**< NAND Flash Controller */
9255 uint64_t mii1 : 1; /**< Second MII Interrupt */
9256 uint64_t usb1 : 1; /**< Second USB Interrupt */
9257 uint64_t uart2 : 1; /**< Third UART interrupt */
9258 uint64_t reserved_4_15 : 12;
9259 uint64_t wdog : 4; /**< 4 watchdog interrupts */
9262 uint64_t reserved_4_15 : 12;
9267 uint64_t reserved_20_63 : 44;
9270 struct cvmx_ciu_int_sum1_cn52xxp1 {
9271 #ifdef __BIG_ENDIAN_BITFIELD
9272 uint64_t reserved_19_63 : 45;
9273 uint64_t mii1 : 1; /**< Second MII Interrupt */
9274 uint64_t usb1 : 1; /**< Second USB Interrupt */
9275 uint64_t uart2 : 1; /**< Third UART interrupt */
9276 uint64_t reserved_4_15 : 12;
9277 uint64_t wdog : 4; /**< 4 watchdog interrupts */
9280 uint64_t reserved_4_15 : 12;
9284 uint64_t reserved_19_63 : 45;
9287 struct cvmx_ciu_int_sum1_cn56xx {
9288 #ifdef __BIG_ENDIAN_BITFIELD
9289 uint64_t reserved_12_63 : 52;
9290 uint64_t wdog : 12; /**< 12 watchdog interrupts */
9293 uint64_t reserved_12_63 : 52;
9296 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
9297 struct cvmx_ciu_int_sum1_cn38xx cn58xx;
9298 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
9299 struct cvmx_ciu_int_sum1_cn61xx {
9300 #ifdef __BIG_ENDIAN_BITFIELD
9301 uint64_t rst : 1; /**< MIO RST interrupt
9303 uint64_t reserved_53_62 : 10;
9304 uint64_t lmc0 : 1; /**< LMC0 interrupt
9306 uint64_t reserved_50_51 : 2;
9307 uint64_t pem1 : 1; /**< PEM1 interrupt
9308 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
9309 uint64_t pem0 : 1; /**< PEM0 interrupt
9310 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
9311 uint64_t ptp : 1; /**< PTP interrupt
9312 Set when HW decrements MIO_PTP_EVT_CNT to zero */
9313 uint64_t agl : 1; /**< AGL interrupt
9314 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
9315 uint64_t reserved_38_45 : 8;
9316 uint64_t agx1 : 1; /**< GMX1 interrupt
9317 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
9318 PCS1_INT*_REG, PCSX1_INT_REG */
9319 uint64_t agx0 : 1; /**< GMX0 interrupt
9320 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
9321 PCS0_INT*_REG, PCSX0_INT_REG */
9322 uint64_t dpi : 1; /**< DPI interrupt
9324 uint64_t sli : 1; /**< SLI interrupt
9325 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
9326 uint64_t usb : 1; /**< USB UCTL0 interrupt
9327 See UCTL0_INT_REG */
9328 uint64_t dfa : 1; /**< DFA interrupt
9330 uint64_t key : 1; /**< KEY interrupt
9332 uint64_t rad : 1; /**< RAD interrupt
9333 See RAD_REG_ERROR */
9334 uint64_t tim : 1; /**< TIM interrupt
9335 See TIM_REG_ERROR */
9336 uint64_t zip : 1; /**< ZIP interrupt
9338 uint64_t pko : 1; /**< PKO interrupt
9339 See PKO_REG_ERROR */
9340 uint64_t pip : 1; /**< PIP interrupt
9342 uint64_t ipd : 1; /**< IPD interrupt
9344 uint64_t l2c : 1; /**< L2C interrupt
9346 uint64_t pow : 1; /**< POW err interrupt
9348 uint64_t fpa : 1; /**< FPA interrupt
9350 uint64_t iob : 1; /**< IOB interrupt
9352 uint64_t mio : 1; /**< MIO boot interrupt
9354 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
9355 See EMMC interrupt */
9356 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt
9358 uint64_t reserved_4_17 : 14;
9359 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
9362 uint64_t reserved_4_17 : 14;
9383 uint64_t reserved_38_45 : 8;
9388 uint64_t reserved_50_51 : 2;
9390 uint64_t reserved_53_62 : 10;
9394 struct cvmx_ciu_int_sum1_cn63xx {
9395 #ifdef __BIG_ENDIAN_BITFIELD
9396 uint64_t rst : 1; /**< MIO RST interrupt
9398 uint64_t reserved_57_62 : 6;
9399 uint64_t dfm : 1; /**< DFM Interrupt
9401 uint64_t reserved_53_55 : 3;
9402 uint64_t lmc0 : 1; /**< LMC0 interrupt
9404 uint64_t srio1 : 1; /**< SRIO1 interrupt
9405 See SRIO1_INT_REG, SRIO1_INT2_REG */
9406 uint64_t srio0 : 1; /**< SRIO0 interrupt
9407 See SRIO0_INT_REG, SRIO0_INT2_REG */
9408 uint64_t pem1 : 1; /**< PEM1 interrupt
9409 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
9410 uint64_t pem0 : 1; /**< PEM0 interrupt
9411 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
9412 uint64_t ptp : 1; /**< PTP interrupt
9413 Set when HW decrements MIO_PTP_EVT_CNT to zero */
9414 uint64_t agl : 1; /**< AGL interrupt
9415 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
9416 uint64_t reserved_37_45 : 9;
9417 uint64_t agx0 : 1; /**< GMX0 interrupt
9418 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
9419 PCS0_INT*_REG, PCSX0_INT_REG */
9420 uint64_t dpi : 1; /**< DPI interrupt
9422 uint64_t sli : 1; /**< SLI interrupt
9423 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
9424 uint64_t usb : 1; /**< USB UCTL0 interrupt
9425 See UCTL0_INT_REG */
9426 uint64_t dfa : 1; /**< DFA interrupt
9428 uint64_t key : 1; /**< KEY interrupt
9430 uint64_t rad : 1; /**< RAD interrupt
9431 See RAD_REG_ERROR */
9432 uint64_t tim : 1; /**< TIM interrupt
9433 See TIM_REG_ERROR */
9434 uint64_t zip : 1; /**< ZIP interrupt
9436 uint64_t pko : 1; /**< PKO interrupt
9437 See PKO_REG_ERROR */
9438 uint64_t pip : 1; /**< PIP interrupt
9440 uint64_t ipd : 1; /**< IPD interrupt
9442 uint64_t l2c : 1; /**< L2C interrupt
9444 uint64_t pow : 1; /**< POW err interrupt
9446 uint64_t fpa : 1; /**< FPA interrupt
9448 uint64_t iob : 1; /**< IOB interrupt
9450 uint64_t mio : 1; /**< MIO boot interrupt
9452 uint64_t nand : 1; /**< NAND Flash Controller interrupt
9454 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
9456 uint64_t reserved_6_17 : 12;
9457 uint64_t wdog : 6; /**< 6 watchdog interrupts */
9460 uint64_t reserved_6_17 : 12;
9480 uint64_t reserved_37_45 : 9;
9488 uint64_t reserved_53_55 : 3;
9490 uint64_t reserved_57_62 : 6;
9494 struct cvmx_ciu_int_sum1_cn63xx cn63xxp1;
9495 struct cvmx_ciu_int_sum1_cn66xx {
9496 #ifdef __BIG_ENDIAN_BITFIELD
9497 uint64_t rst : 1; /**< MIO RST interrupt
9499 uint64_t reserved_62_62 : 1;
9500 uint64_t srio3 : 1; /**< SRIO3 interrupt
9501 See SRIO3_INT_REG, SRIO3_INT2_REG */
9502 uint64_t srio2 : 1; /**< SRIO2 interrupt
9503 See SRIO2_INT_REG, SRIO2_INT2_REG */
9504 uint64_t reserved_57_59 : 3;
9505 uint64_t dfm : 1; /**< DFM Interrupt
9507 uint64_t reserved_53_55 : 3;
9508 uint64_t lmc0 : 1; /**< LMC0 interrupt
9510 uint64_t reserved_51_51 : 1;
9511 uint64_t srio0 : 1; /**< SRIO0 interrupt
9512 See SRIO0_INT_REG, SRIO0_INT2_REG */
9513 uint64_t pem1 : 1; /**< PEM1 interrupt
9514 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
9515 uint64_t pem0 : 1; /**< PEM0 interrupt
9516 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
9517 uint64_t ptp : 1; /**< PTP interrupt
9518 Set when HW decrements MIO_PTP_EVT_CNT to zero */
9519 uint64_t agl : 1; /**< AGL interrupt
9520 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
9521 uint64_t reserved_38_45 : 8;
9522 uint64_t agx1 : 1; /**< GMX1 interrupt
9523 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
9524 PCS1_INT*_REG, PCSX1_INT_REG */
9525 uint64_t agx0 : 1; /**< GMX0 interrupt
9526 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
9527 PCS0_INT*_REG, PCSX0_INT_REG */
9528 uint64_t dpi : 1; /**< DPI interrupt
9530 uint64_t sli : 1; /**< SLI interrupt
9531 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
9532 uint64_t usb : 1; /**< USB UCTL0 interrupt
9533 See UCTL0_INT_REG */
9534 uint64_t dfa : 1; /**< DFA interrupt
9536 uint64_t key : 1; /**< KEY interrupt
9538 uint64_t rad : 1; /**< RAD interrupt
9539 See RAD_REG_ERROR */
9540 uint64_t tim : 1; /**< TIM interrupt
9541 See TIM_REG_ERROR */
9542 uint64_t zip : 1; /**< ZIP interrupt
9544 uint64_t pko : 1; /**< PKO interrupt
9545 See PKO_REG_ERROR */
9546 uint64_t pip : 1; /**< PIP interrupt
9548 uint64_t ipd : 1; /**< IPD interrupt
9550 uint64_t l2c : 1; /**< L2C interrupt
9552 uint64_t pow : 1; /**< POW err interrupt
9554 uint64_t fpa : 1; /**< FPA interrupt
9556 uint64_t iob : 1; /**< IOB interrupt
9558 uint64_t mio : 1; /**< MIO boot interrupt
9560 uint64_t nand : 1; /**< NAND Flash Controller interrupt
9562 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
9564 uint64_t reserved_10_17 : 8;
9565 uint64_t wdog : 10; /**< 10 watchdog interrupts */
9568 uint64_t reserved_10_17 : 8;
9589 uint64_t reserved_38_45 : 8;
9595 uint64_t reserved_51_51 : 1;
9597 uint64_t reserved_53_55 : 3;
9599 uint64_t reserved_57_59 : 3;
9602 uint64_t reserved_62_62 : 1;
9606 struct cvmx_ciu_int_sum1_cnf71xx {
9607 #ifdef __BIG_ENDIAN_BITFIELD
9608 uint64_t rst : 1; /**< MIO RST interrupt
9610 uint64_t reserved_53_62 : 10;
9611 uint64_t lmc0 : 1; /**< LMC0 interrupt
9613 uint64_t reserved_50_51 : 2;
9614 uint64_t pem1 : 1; /**< PEM1 interrupt
9615 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
9616 uint64_t pem0 : 1; /**< PEM0 interrupt
9617 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
9618 uint64_t ptp : 1; /**< PTP interrupt
9619 Set when HW decrements MIO_PTP_EVT_CNT to zero */
9620 uint64_t reserved_37_46 : 10;
9621 uint64_t agx0 : 1; /**< GMX0 interrupt
9622 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
9623 PCS0_INT*_REG, PCSX0_INT_REG */
9624 uint64_t dpi : 1; /**< DPI interrupt
9626 uint64_t sli : 1; /**< SLI interrupt
9627 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
9628 uint64_t usb : 1; /**< USB UCTL0 interrupt
9629 See UCTL0_INT_REG */
9630 uint64_t reserved_32_32 : 1;
9631 uint64_t key : 1; /**< KEY interrupt
9633 uint64_t rad : 1; /**< RAD interrupt
9634 See RAD_REG_ERROR */
9635 uint64_t tim : 1; /**< TIM interrupt
9636 See TIM_REG_ERROR */
9637 uint64_t reserved_28_28 : 1;
9638 uint64_t pko : 1; /**< PKO interrupt
9639 See PKO_REG_ERROR */
9640 uint64_t pip : 1; /**< PIP interrupt
9642 uint64_t ipd : 1; /**< IPD interrupt
9644 uint64_t l2c : 1; /**< L2C interrupt
9646 uint64_t pow : 1; /**< POW err interrupt
9648 uint64_t fpa : 1; /**< FPA interrupt
9650 uint64_t iob : 1; /**< IOB interrupt
9652 uint64_t mio : 1; /**< MIO boot interrupt
9654 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
9655 See EMMC interrupt */
9656 uint64_t reserved_4_18 : 15;
9657 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
9660 uint64_t reserved_4_18 : 15;
9670 uint64_t reserved_28_28 : 1;
9674 uint64_t reserved_32_32 : 1;
9679 uint64_t reserved_37_46 : 10;
9683 uint64_t reserved_50_51 : 2;
9685 uint64_t reserved_53_62 : 10;
9690 typedef union cvmx_ciu_int_sum1 cvmx_ciu_int_sum1_t;
9693 * cvmx_ciu_mbox_clr#
9695 union cvmx_ciu_mbox_clrx {
9697 struct cvmx_ciu_mbox_clrx_s {
9698 #ifdef __BIG_ENDIAN_BITFIELD
9699 uint64_t reserved_32_63 : 32;
9700 uint64_t bits : 32; /**< On writes, clr corresponding bit in MBOX register
9701 on reads, return the MBOX register */
9704 uint64_t reserved_32_63 : 32;
9707 struct cvmx_ciu_mbox_clrx_s cn30xx;
9708 struct cvmx_ciu_mbox_clrx_s cn31xx;
9709 struct cvmx_ciu_mbox_clrx_s cn38xx;
9710 struct cvmx_ciu_mbox_clrx_s cn38xxp2;
9711 struct cvmx_ciu_mbox_clrx_s cn50xx;
9712 struct cvmx_ciu_mbox_clrx_s cn52xx;
9713 struct cvmx_ciu_mbox_clrx_s cn52xxp1;
9714 struct cvmx_ciu_mbox_clrx_s cn56xx;
9715 struct cvmx_ciu_mbox_clrx_s cn56xxp1;
9716 struct cvmx_ciu_mbox_clrx_s cn58xx;
9717 struct cvmx_ciu_mbox_clrx_s cn58xxp1;
9718 struct cvmx_ciu_mbox_clrx_s cn61xx;
9719 struct cvmx_ciu_mbox_clrx_s cn63xx;
9720 struct cvmx_ciu_mbox_clrx_s cn63xxp1;
9721 struct cvmx_ciu_mbox_clrx_s cn66xx;
9722 struct cvmx_ciu_mbox_clrx_s cn68xx;
9723 struct cvmx_ciu_mbox_clrx_s cn68xxp1;
9724 struct cvmx_ciu_mbox_clrx_s cnf71xx;
9726 typedef union cvmx_ciu_mbox_clrx cvmx_ciu_mbox_clrx_t;
9729 * cvmx_ciu_mbox_set#
9731 union cvmx_ciu_mbox_setx {
9733 struct cvmx_ciu_mbox_setx_s {
9734 #ifdef __BIG_ENDIAN_BITFIELD
9735 uint64_t reserved_32_63 : 32;
9736 uint64_t bits : 32; /**< On writes, set corresponding bit in MBOX register
9737 on reads, return the MBOX register */
9740 uint64_t reserved_32_63 : 32;
9743 struct cvmx_ciu_mbox_setx_s cn30xx;
9744 struct cvmx_ciu_mbox_setx_s cn31xx;
9745 struct cvmx_ciu_mbox_setx_s cn38xx;
9746 struct cvmx_ciu_mbox_setx_s cn38xxp2;
9747 struct cvmx_ciu_mbox_setx_s cn50xx;
9748 struct cvmx_ciu_mbox_setx_s cn52xx;
9749 struct cvmx_ciu_mbox_setx_s cn52xxp1;
9750 struct cvmx_ciu_mbox_setx_s cn56xx;
9751 struct cvmx_ciu_mbox_setx_s cn56xxp1;
9752 struct cvmx_ciu_mbox_setx_s cn58xx;
9753 struct cvmx_ciu_mbox_setx_s cn58xxp1;
9754 struct cvmx_ciu_mbox_setx_s cn61xx;
9755 struct cvmx_ciu_mbox_setx_s cn63xx;
9756 struct cvmx_ciu_mbox_setx_s cn63xxp1;
9757 struct cvmx_ciu_mbox_setx_s cn66xx;
9758 struct cvmx_ciu_mbox_setx_s cn68xx;
9759 struct cvmx_ciu_mbox_setx_s cn68xxp1;
9760 struct cvmx_ciu_mbox_setx_s cnf71xx;
9762 typedef union cvmx_ciu_mbox_setx cvmx_ciu_mbox_setx_t;
9767 union cvmx_ciu_nmi {
9769 struct cvmx_ciu_nmi_s {
9770 #ifdef __BIG_ENDIAN_BITFIELD
9771 uint64_t reserved_32_63 : 32;
9772 uint64_t nmi : 32; /**< Send NMI pulse to PP vector */
9775 uint64_t reserved_32_63 : 32;
9778 struct cvmx_ciu_nmi_cn30xx {
9779 #ifdef __BIG_ENDIAN_BITFIELD
9780 uint64_t reserved_1_63 : 63;
9781 uint64_t nmi : 1; /**< Send NMI pulse to PP vector */
9784 uint64_t reserved_1_63 : 63;
9787 struct cvmx_ciu_nmi_cn31xx {
9788 #ifdef __BIG_ENDIAN_BITFIELD
9789 uint64_t reserved_2_63 : 62;
9790 uint64_t nmi : 2; /**< Send NMI pulse to PP vector */
9793 uint64_t reserved_2_63 : 62;
9796 struct cvmx_ciu_nmi_cn38xx {
9797 #ifdef __BIG_ENDIAN_BITFIELD
9798 uint64_t reserved_16_63 : 48;
9799 uint64_t nmi : 16; /**< Send NMI pulse to PP vector */
9802 uint64_t reserved_16_63 : 48;
9805 struct cvmx_ciu_nmi_cn38xx cn38xxp2;
9806 struct cvmx_ciu_nmi_cn31xx cn50xx;
9807 struct cvmx_ciu_nmi_cn52xx {
9808 #ifdef __BIG_ENDIAN_BITFIELD
9809 uint64_t reserved_4_63 : 60;
9810 uint64_t nmi : 4; /**< Send NMI pulse to PP vector */
9813 uint64_t reserved_4_63 : 60;
9816 struct cvmx_ciu_nmi_cn52xx cn52xxp1;
9817 struct cvmx_ciu_nmi_cn56xx {
9818 #ifdef __BIG_ENDIAN_BITFIELD
9819 uint64_t reserved_12_63 : 52;
9820 uint64_t nmi : 12; /**< Send NMI pulse to PP vector */
9823 uint64_t reserved_12_63 : 52;
9826 struct cvmx_ciu_nmi_cn56xx cn56xxp1;
9827 struct cvmx_ciu_nmi_cn38xx cn58xx;
9828 struct cvmx_ciu_nmi_cn38xx cn58xxp1;
9829 struct cvmx_ciu_nmi_cn52xx cn61xx;
9830 struct cvmx_ciu_nmi_cn63xx {
9831 #ifdef __BIG_ENDIAN_BITFIELD
9832 uint64_t reserved_6_63 : 58;
9833 uint64_t nmi : 6; /**< Send NMI pulse to PP vector */
9836 uint64_t reserved_6_63 : 58;
9839 struct cvmx_ciu_nmi_cn63xx cn63xxp1;
9840 struct cvmx_ciu_nmi_cn66xx {
9841 #ifdef __BIG_ENDIAN_BITFIELD
9842 uint64_t reserved_10_63 : 54;
9843 uint64_t nmi : 10; /**< Send NMI pulse to PP vector */
9846 uint64_t reserved_10_63 : 54;
9849 struct cvmx_ciu_nmi_s cn68xx;
9850 struct cvmx_ciu_nmi_s cn68xxp1;
9851 struct cvmx_ciu_nmi_cn52xx cnf71xx;
9853 typedef union cvmx_ciu_nmi cvmx_ciu_nmi_t;
9858 union cvmx_ciu_pci_inta {
9860 struct cvmx_ciu_pci_inta_s {
9861 #ifdef __BIG_ENDIAN_BITFIELD
9862 uint64_t reserved_2_63 : 62;
9863 uint64_t intr : 2; /**< PCIe interrupt
9864 These bits are observed in CIU_INTX_SUM0<33:32>
9868 uint64_t reserved_2_63 : 62;
9871 struct cvmx_ciu_pci_inta_s cn30xx;
9872 struct cvmx_ciu_pci_inta_s cn31xx;
9873 struct cvmx_ciu_pci_inta_s cn38xx;
9874 struct cvmx_ciu_pci_inta_s cn38xxp2;
9875 struct cvmx_ciu_pci_inta_s cn50xx;
9876 struct cvmx_ciu_pci_inta_s cn52xx;
9877 struct cvmx_ciu_pci_inta_s cn52xxp1;
9878 struct cvmx_ciu_pci_inta_s cn56xx;
9879 struct cvmx_ciu_pci_inta_s cn56xxp1;
9880 struct cvmx_ciu_pci_inta_s cn58xx;
9881 struct cvmx_ciu_pci_inta_s cn58xxp1;
9882 struct cvmx_ciu_pci_inta_s cn61xx;
9883 struct cvmx_ciu_pci_inta_s cn63xx;
9884 struct cvmx_ciu_pci_inta_s cn63xxp1;
9885 struct cvmx_ciu_pci_inta_s cn66xx;
9886 struct cvmx_ciu_pci_inta_s cn68xx;
9887 struct cvmx_ciu_pci_inta_s cn68xxp1;
9888 struct cvmx_ciu_pci_inta_s cnf71xx;
9890 typedef union cvmx_ciu_pci_inta cvmx_ciu_pci_inta_t;
9893 * cvmx_ciu_pp_bist_stat
9895 union cvmx_ciu_pp_bist_stat {
9897 struct cvmx_ciu_pp_bist_stat_s {
9898 #ifdef __BIG_ENDIAN_BITFIELD
9899 uint64_t reserved_32_63 : 32;
9900 uint64_t pp_bist : 32; /**< Physical PP BIST status */
9902 uint64_t pp_bist : 32;
9903 uint64_t reserved_32_63 : 32;
9906 struct cvmx_ciu_pp_bist_stat_s cn68xx;
9907 struct cvmx_ciu_pp_bist_stat_s cn68xxp1;
9909 typedef union cvmx_ciu_pp_bist_stat cvmx_ciu_pp_bist_stat_t;
9914 union cvmx_ciu_pp_dbg {
9916 struct cvmx_ciu_pp_dbg_s {
9917 #ifdef __BIG_ENDIAN_BITFIELD
9918 uint64_t reserved_32_63 : 32;
9919 uint64_t ppdbg : 32; /**< Debug[DM] value for each PP
9920 whether the PP's are in debug mode or not */
9922 uint64_t ppdbg : 32;
9923 uint64_t reserved_32_63 : 32;
9926 struct cvmx_ciu_pp_dbg_cn30xx {
9927 #ifdef __BIG_ENDIAN_BITFIELD
9928 uint64_t reserved_1_63 : 63;
9929 uint64_t ppdbg : 1; /**< Debug[DM] value for each PP
9930 whether the PP's are in debug mode or not */
9933 uint64_t reserved_1_63 : 63;
9936 struct cvmx_ciu_pp_dbg_cn31xx {
9937 #ifdef __BIG_ENDIAN_BITFIELD
9938 uint64_t reserved_2_63 : 62;
9939 uint64_t ppdbg : 2; /**< Debug[DM] value for each PP
9940 whether the PP's are in debug mode or not */
9943 uint64_t reserved_2_63 : 62;
9946 struct cvmx_ciu_pp_dbg_cn38xx {
9947 #ifdef __BIG_ENDIAN_BITFIELD
9948 uint64_t reserved_16_63 : 48;
9949 uint64_t ppdbg : 16; /**< Debug[DM] value for each PP
9950 whether the PP's are in debug mode or not */
9952 uint64_t ppdbg : 16;
9953 uint64_t reserved_16_63 : 48;
9956 struct cvmx_ciu_pp_dbg_cn38xx cn38xxp2;
9957 struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
9958 struct cvmx_ciu_pp_dbg_cn52xx {
9959 #ifdef __BIG_ENDIAN_BITFIELD
9960 uint64_t reserved_4_63 : 60;
9961 uint64_t ppdbg : 4; /**< Debug[DM] value for each PP
9962 whether the PP's are in debug mode or not */
9965 uint64_t reserved_4_63 : 60;
9968 struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
9969 struct cvmx_ciu_pp_dbg_cn56xx {
9970 #ifdef __BIG_ENDIAN_BITFIELD
9971 uint64_t reserved_12_63 : 52;
9972 uint64_t ppdbg : 12; /**< Debug[DM] value for each PP
9973 whether the PP's are in debug mode or not */
9975 uint64_t ppdbg : 12;
9976 uint64_t reserved_12_63 : 52;
9979 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
9980 struct cvmx_ciu_pp_dbg_cn38xx cn58xx;
9981 struct cvmx_ciu_pp_dbg_cn38xx cn58xxp1;
9982 struct cvmx_ciu_pp_dbg_cn52xx cn61xx;
9983 struct cvmx_ciu_pp_dbg_cn63xx {
9984 #ifdef __BIG_ENDIAN_BITFIELD
9985 uint64_t reserved_6_63 : 58;
9986 uint64_t ppdbg : 6; /**< Debug[DM] value for each PP
9987 whether the PP's are in debug mode or not */
9990 uint64_t reserved_6_63 : 58;
9993 struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1;
9994 struct cvmx_ciu_pp_dbg_cn66xx {
9995 #ifdef __BIG_ENDIAN_BITFIELD
9996 uint64_t reserved_10_63 : 54;
9997 uint64_t ppdbg : 10; /**< Debug[DM] value for each PP
9998 whether the PP's are in debug mode or not */
10000 uint64_t ppdbg : 10;
10001 uint64_t reserved_10_63 : 54;
10004 struct cvmx_ciu_pp_dbg_s cn68xx;
10005 struct cvmx_ciu_pp_dbg_s cn68xxp1;
10006 struct cvmx_ciu_pp_dbg_cn52xx cnf71xx;
10008 typedef union cvmx_ciu_pp_dbg cvmx_ciu_pp_dbg_t;
10011 * cvmx_ciu_pp_poke#
10014 * Any write to a CIU_PP_POKE register clears any pending interrupt generated
10015 * by the associated watchdog, resets the CIU_WDOG[STATE] field, and set
10016 * CIU_WDOG[CNT] to be (CIU_WDOG[LEN] << 8).
10018 * Reads to this register will return the associated CIU_WDOG register.
10020 union cvmx_ciu_pp_pokex {
10022 struct cvmx_ciu_pp_pokex_s {
10023 #ifdef __BIG_ENDIAN_BITFIELD
10024 uint64_t poke : 64; /**< Reserved */
10026 uint64_t poke : 64;
10029 struct cvmx_ciu_pp_pokex_s cn30xx;
10030 struct cvmx_ciu_pp_pokex_s cn31xx;
10031 struct cvmx_ciu_pp_pokex_s cn38xx;
10032 struct cvmx_ciu_pp_pokex_s cn38xxp2;
10033 struct cvmx_ciu_pp_pokex_s cn50xx;
10034 struct cvmx_ciu_pp_pokex_s cn52xx;
10035 struct cvmx_ciu_pp_pokex_s cn52xxp1;
10036 struct cvmx_ciu_pp_pokex_s cn56xx;
10037 struct cvmx_ciu_pp_pokex_s cn56xxp1;
10038 struct cvmx_ciu_pp_pokex_s cn58xx;
10039 struct cvmx_ciu_pp_pokex_s cn58xxp1;
10040 struct cvmx_ciu_pp_pokex_s cn61xx;
10041 struct cvmx_ciu_pp_pokex_s cn63xx;
10042 struct cvmx_ciu_pp_pokex_s cn63xxp1;
10043 struct cvmx_ciu_pp_pokex_s cn66xx;
10044 struct cvmx_ciu_pp_pokex_s cn68xx;
10045 struct cvmx_ciu_pp_pokex_s cn68xxp1;
10046 struct cvmx_ciu_pp_pokex_s cnf71xx;
10048 typedef union cvmx_ciu_pp_pokex cvmx_ciu_pp_pokex_t;
10053 * Contains the reset control for each PP. Value of '1' will hold a PP in reset, '0' will release.
10054 * Resets to 0xf when PCI boot is enabled, 0xe otherwise.
10056 union cvmx_ciu_pp_rst {
10058 struct cvmx_ciu_pp_rst_s {
10059 #ifdef __BIG_ENDIAN_BITFIELD
10060 uint64_t reserved_32_63 : 32;
10061 uint64_t rst : 31; /**< PP Rst for PP's 3-1 */
10062 uint64_t rst0 : 1; /**< PP Rst for PP0
10063 depends on standalone mode */
10067 uint64_t reserved_32_63 : 32;
10070 struct cvmx_ciu_pp_rst_cn30xx {
10071 #ifdef __BIG_ENDIAN_BITFIELD
10072 uint64_t reserved_1_63 : 63;
10073 uint64_t rst0 : 1; /**< PP Rst for PP0
10074 depends on standalone mode */
10077 uint64_t reserved_1_63 : 63;
10080 struct cvmx_ciu_pp_rst_cn31xx {
10081 #ifdef __BIG_ENDIAN_BITFIELD
10082 uint64_t reserved_2_63 : 62;
10083 uint64_t rst : 1; /**< PP Rst for PP1 */
10084 uint64_t rst0 : 1; /**< PP Rst for PP0
10085 depends on standalone mode */
10089 uint64_t reserved_2_63 : 62;
10092 struct cvmx_ciu_pp_rst_cn38xx {
10093 #ifdef __BIG_ENDIAN_BITFIELD
10094 uint64_t reserved_16_63 : 48;
10095 uint64_t rst : 15; /**< PP Rst for PP's 15-1 */
10096 uint64_t rst0 : 1; /**< PP Rst for PP0
10097 depends on standalone mode */
10101 uint64_t reserved_16_63 : 48;
10104 struct cvmx_ciu_pp_rst_cn38xx cn38xxp2;
10105 struct cvmx_ciu_pp_rst_cn31xx cn50xx;
10106 struct cvmx_ciu_pp_rst_cn52xx {
10107 #ifdef __BIG_ENDIAN_BITFIELD
10108 uint64_t reserved_4_63 : 60;
10109 uint64_t rst : 3; /**< PP Rst for PP's 11-1 */
10110 uint64_t rst0 : 1; /**< PP Rst for PP0
10111 depends on standalone mode */
10115 uint64_t reserved_4_63 : 60;
10118 struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
10119 struct cvmx_ciu_pp_rst_cn56xx {
10120 #ifdef __BIG_ENDIAN_BITFIELD
10121 uint64_t reserved_12_63 : 52;
10122 uint64_t rst : 11; /**< PP Rst for PP's 11-1 */
10123 uint64_t rst0 : 1; /**< PP Rst for PP0
10124 depends on standalone mode */
10128 uint64_t reserved_12_63 : 52;
10131 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
10132 struct cvmx_ciu_pp_rst_cn38xx cn58xx;
10133 struct cvmx_ciu_pp_rst_cn38xx cn58xxp1;
10134 struct cvmx_ciu_pp_rst_cn52xx cn61xx;
10135 struct cvmx_ciu_pp_rst_cn63xx {
10136 #ifdef __BIG_ENDIAN_BITFIELD
10137 uint64_t reserved_6_63 : 58;
10138 uint64_t rst : 5; /**< PP Rst for PP's 5-1 */
10139 uint64_t rst0 : 1; /**< PP Rst for PP0
10140 depends on standalone mode */
10144 uint64_t reserved_6_63 : 58;
10147 struct cvmx_ciu_pp_rst_cn63xx cn63xxp1;
10148 struct cvmx_ciu_pp_rst_cn66xx {
10149 #ifdef __BIG_ENDIAN_BITFIELD
10150 uint64_t reserved_10_63 : 54;
10151 uint64_t rst : 9; /**< PP Rst for PP's 9-1 */
10152 uint64_t rst0 : 1; /**< PP Rst for PP0
10153 depends on standalone mode */
10157 uint64_t reserved_10_63 : 54;
10160 struct cvmx_ciu_pp_rst_s cn68xx;
10161 struct cvmx_ciu_pp_rst_s cn68xxp1;
10162 struct cvmx_ciu_pp_rst_cn52xx cnf71xx;
10164 typedef union cvmx_ciu_pp_rst cvmx_ciu_pp_rst_t;
10170 * This register is only reset by cold reset.
10173 union cvmx_ciu_qlm0 {
10175 struct cvmx_ciu_qlm0_s {
10176 #ifdef __BIG_ENDIAN_BITFIELD
10177 uint64_t g2bypass : 1; /**< QLM0 PCIE Gen2 tx bypass enable */
10178 uint64_t reserved_53_62 : 10;
10179 uint64_t g2deemph : 5; /**< QLM0 PCIE Gen2 tx bypass de-emphasis value */
10180 uint64_t reserved_45_47 : 3;
10181 uint64_t g2margin : 5; /**< QLM0 PCIE Gen2 tx bypass margin (amplitude) value */
10182 uint64_t reserved_32_39 : 8;
10183 uint64_t txbypass : 1; /**< QLM0 transmitter bypass enable */
10184 uint64_t reserved_21_30 : 10;
10185 uint64_t txdeemph : 5; /**< QLM0 transmitter bypass de-emphasis value */
10186 uint64_t reserved_13_15 : 3;
10187 uint64_t txmargin : 5; /**< QLM0 transmitter bypass margin (amplitude) value */
10188 uint64_t reserved_4_7 : 4;
10189 uint64_t lane_en : 4; /**< QLM0 lane enable mask */
10191 uint64_t lane_en : 4;
10192 uint64_t reserved_4_7 : 4;
10193 uint64_t txmargin : 5;
10194 uint64_t reserved_13_15 : 3;
10195 uint64_t txdeemph : 5;
10196 uint64_t reserved_21_30 : 10;
10197 uint64_t txbypass : 1;
10198 uint64_t reserved_32_39 : 8;
10199 uint64_t g2margin : 5;
10200 uint64_t reserved_45_47 : 3;
10201 uint64_t g2deemph : 5;
10202 uint64_t reserved_53_62 : 10;
10203 uint64_t g2bypass : 1;
10206 struct cvmx_ciu_qlm0_s cn61xx;
10207 struct cvmx_ciu_qlm0_s cn63xx;
10208 struct cvmx_ciu_qlm0_cn63xxp1 {
10209 #ifdef __BIG_ENDIAN_BITFIELD
10210 uint64_t reserved_32_63 : 32;
10211 uint64_t txbypass : 1; /**< QLM0 transmitter bypass enable */
10212 uint64_t reserved_20_30 : 11;
10213 uint64_t txdeemph : 4; /**< QLM0 transmitter bypass de-emphasis value */
10214 uint64_t reserved_13_15 : 3;
10215 uint64_t txmargin : 5; /**< QLM0 transmitter bypass margin (amplitude) value */
10216 uint64_t reserved_4_7 : 4;
10217 uint64_t lane_en : 4; /**< QLM0 lane enable mask */
10219 uint64_t lane_en : 4;
10220 uint64_t reserved_4_7 : 4;
10221 uint64_t txmargin : 5;
10222 uint64_t reserved_13_15 : 3;
10223 uint64_t txdeemph : 4;
10224 uint64_t reserved_20_30 : 11;
10225 uint64_t txbypass : 1;
10226 uint64_t reserved_32_63 : 32;
10229 struct cvmx_ciu_qlm0_s cn66xx;
10230 struct cvmx_ciu_qlm0_cn68xx {
10231 #ifdef __BIG_ENDIAN_BITFIELD
10232 uint64_t reserved_32_63 : 32;
10233 uint64_t txbypass : 1; /**< QLMx transmitter bypass enable */
10234 uint64_t reserved_21_30 : 10;
10235 uint64_t txdeemph : 5; /**< QLMx transmitter bypass de-emphasis value */
10236 uint64_t reserved_13_15 : 3;
10237 uint64_t txmargin : 5; /**< QLMx transmitter bypass margin (amplitude) value */
10238 uint64_t reserved_4_7 : 4;
10239 uint64_t lane_en : 4; /**< QLMx lane enable mask */
10241 uint64_t lane_en : 4;
10242 uint64_t reserved_4_7 : 4;
10243 uint64_t txmargin : 5;
10244 uint64_t reserved_13_15 : 3;
10245 uint64_t txdeemph : 5;
10246 uint64_t reserved_21_30 : 10;
10247 uint64_t txbypass : 1;
10248 uint64_t reserved_32_63 : 32;
10251 struct cvmx_ciu_qlm0_cn68xx cn68xxp1;
10252 struct cvmx_ciu_qlm0_s cnf71xx;
10254 typedef union cvmx_ciu_qlm0 cvmx_ciu_qlm0_t;
10260 * This register is only reset by cold reset.
10263 union cvmx_ciu_qlm1 {
10265 struct cvmx_ciu_qlm1_s {
10266 #ifdef __BIG_ENDIAN_BITFIELD
10267 uint64_t g2bypass : 1; /**< QLM1 PCIE Gen2 tx bypass enable */
10268 uint64_t reserved_53_62 : 10;
10269 uint64_t g2deemph : 5; /**< QLM1 PCIE Gen2 tx bypass de-emphasis value */
10270 uint64_t reserved_45_47 : 3;
10271 uint64_t g2margin : 5; /**< QLM1 PCIE Gen2 tx bypass margin (amplitude) value */
10272 uint64_t reserved_32_39 : 8;
10273 uint64_t txbypass : 1; /**< QLM1 transmitter bypass enable */
10274 uint64_t reserved_21_30 : 10;
10275 uint64_t txdeemph : 5; /**< QLM1 transmitter bypass de-emphasis value */
10276 uint64_t reserved_13_15 : 3;
10277 uint64_t txmargin : 5; /**< QLM1 transmitter bypass margin (amplitude) value */
10278 uint64_t reserved_4_7 : 4;
10279 uint64_t lane_en : 4; /**< QLM1 lane enable mask */
10281 uint64_t lane_en : 4;
10282 uint64_t reserved_4_7 : 4;
10283 uint64_t txmargin : 5;
10284 uint64_t reserved_13_15 : 3;
10285 uint64_t txdeemph : 5;
10286 uint64_t reserved_21_30 : 10;
10287 uint64_t txbypass : 1;
10288 uint64_t reserved_32_39 : 8;
10289 uint64_t g2margin : 5;
10290 uint64_t reserved_45_47 : 3;
10291 uint64_t g2deemph : 5;
10292 uint64_t reserved_53_62 : 10;
10293 uint64_t g2bypass : 1;
10296 struct cvmx_ciu_qlm1_s cn61xx;
10297 struct cvmx_ciu_qlm1_s cn63xx;
10298 struct cvmx_ciu_qlm1_cn63xxp1 {
10299 #ifdef __BIG_ENDIAN_BITFIELD
10300 uint64_t reserved_32_63 : 32;
10301 uint64_t txbypass : 1; /**< QLM1 transmitter bypass enable */
10302 uint64_t reserved_20_30 : 11;
10303 uint64_t txdeemph : 4; /**< QLM1 transmitter bypass de-emphasis value */
10304 uint64_t reserved_13_15 : 3;
10305 uint64_t txmargin : 5; /**< QLM1 transmitter bypass margin (amplitude) value */
10306 uint64_t reserved_4_7 : 4;
10307 uint64_t lane_en : 4; /**< QLM1 lane enable mask */
10309 uint64_t lane_en : 4;
10310 uint64_t reserved_4_7 : 4;
10311 uint64_t txmargin : 5;
10312 uint64_t reserved_13_15 : 3;
10313 uint64_t txdeemph : 4;
10314 uint64_t reserved_20_30 : 11;
10315 uint64_t txbypass : 1;
10316 uint64_t reserved_32_63 : 32;
10319 struct cvmx_ciu_qlm1_s cn66xx;
10320 struct cvmx_ciu_qlm1_s cn68xx;
10321 struct cvmx_ciu_qlm1_s cn68xxp1;
10322 struct cvmx_ciu_qlm1_s cnf71xx;
10324 typedef union cvmx_ciu_qlm1 cvmx_ciu_qlm1_t;
10330 * This register is only reset by cold reset.
10333 union cvmx_ciu_qlm2 {
10335 struct cvmx_ciu_qlm2_s {
10336 #ifdef __BIG_ENDIAN_BITFIELD
10337 uint64_t g2bypass : 1; /**< QLMx PCIE Gen2 tx bypass enable */
10338 uint64_t reserved_53_62 : 10;
10339 uint64_t g2deemph : 5; /**< QLMx PCIE Gen2 tx bypass de-emphasis value */
10340 uint64_t reserved_45_47 : 3;
10341 uint64_t g2margin : 5; /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */
10342 uint64_t reserved_32_39 : 8;
10343 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */
10344 uint64_t reserved_21_30 : 10;
10345 uint64_t txdeemph : 5; /**< QLM2 transmitter bypass de-emphasis value */
10346 uint64_t reserved_13_15 : 3;
10347 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */
10348 uint64_t reserved_4_7 : 4;
10349 uint64_t lane_en : 4; /**< QLM2 lane enable mask */
10351 uint64_t lane_en : 4;
10352 uint64_t reserved_4_7 : 4;
10353 uint64_t txmargin : 5;
10354 uint64_t reserved_13_15 : 3;
10355 uint64_t txdeemph : 5;
10356 uint64_t reserved_21_30 : 10;
10357 uint64_t txbypass : 1;
10358 uint64_t reserved_32_39 : 8;
10359 uint64_t g2margin : 5;
10360 uint64_t reserved_45_47 : 3;
10361 uint64_t g2deemph : 5;
10362 uint64_t reserved_53_62 : 10;
10363 uint64_t g2bypass : 1;
10366 struct cvmx_ciu_qlm2_cn61xx {
10367 #ifdef __BIG_ENDIAN_BITFIELD
10368 uint64_t reserved_32_63 : 32;
10369 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */
10370 uint64_t reserved_21_30 : 10;
10371 uint64_t txdeemph : 5; /**< QLM2 transmitter bypass de-emphasis value */
10372 uint64_t reserved_13_15 : 3;
10373 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */
10374 uint64_t reserved_4_7 : 4;
10375 uint64_t lane_en : 4; /**< QLM2 lane enable mask */
10377 uint64_t lane_en : 4;
10378 uint64_t reserved_4_7 : 4;
10379 uint64_t txmargin : 5;
10380 uint64_t reserved_13_15 : 3;
10381 uint64_t txdeemph : 5;
10382 uint64_t reserved_21_30 : 10;
10383 uint64_t txbypass : 1;
10384 uint64_t reserved_32_63 : 32;
10387 struct cvmx_ciu_qlm2_cn61xx cn63xx;
10388 struct cvmx_ciu_qlm2_cn63xxp1 {
10389 #ifdef __BIG_ENDIAN_BITFIELD
10390 uint64_t reserved_32_63 : 32;
10391 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */
10392 uint64_t reserved_20_30 : 11;
10393 uint64_t txdeemph : 4; /**< QLM2 transmitter bypass de-emphasis value */
10394 uint64_t reserved_13_15 : 3;
10395 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */
10396 uint64_t reserved_4_7 : 4;
10397 uint64_t lane_en : 4; /**< QLM2 lane enable mask */
10399 uint64_t lane_en : 4;
10400 uint64_t reserved_4_7 : 4;
10401 uint64_t txmargin : 5;
10402 uint64_t reserved_13_15 : 3;
10403 uint64_t txdeemph : 4;
10404 uint64_t reserved_20_30 : 11;
10405 uint64_t txbypass : 1;
10406 uint64_t reserved_32_63 : 32;
10409 struct cvmx_ciu_qlm2_cn61xx cn66xx;
10410 struct cvmx_ciu_qlm2_s cn68xx;
10411 struct cvmx_ciu_qlm2_s cn68xxp1;
10412 struct cvmx_ciu_qlm2_cn61xx cnf71xx;
10414 typedef union cvmx_ciu_qlm2 cvmx_ciu_qlm2_t;
10420 * This register is only reset by cold reset.
10423 union cvmx_ciu_qlm3 {
10425 struct cvmx_ciu_qlm3_s {
10426 #ifdef __BIG_ENDIAN_BITFIELD
10427 uint64_t g2bypass : 1; /**< QLMx PCIE Gen2 tx bypass enable */
10428 uint64_t reserved_53_62 : 10;
10429 uint64_t g2deemph : 5; /**< QLMx PCIE Gen2 tx bypass de-emphasis value */
10430 uint64_t reserved_45_47 : 3;
10431 uint64_t g2margin : 5; /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */
10432 uint64_t reserved_32_39 : 8;
10433 uint64_t txbypass : 1; /**< QLMx transmitter bypass enable */
10434 uint64_t reserved_21_30 : 10;
10435 uint64_t txdeemph : 5; /**< QLMx transmitter bypass de-emphasis value */
10436 uint64_t reserved_13_15 : 3;
10437 uint64_t txmargin : 5; /**< QLMx transmitter bypass margin (amplitude) value */
10438 uint64_t reserved_4_7 : 4;
10439 uint64_t lane_en : 4; /**< QLMx lane enable mask */
10441 uint64_t lane_en : 4;
10442 uint64_t reserved_4_7 : 4;
10443 uint64_t txmargin : 5;
10444 uint64_t reserved_13_15 : 3;
10445 uint64_t txdeemph : 5;
10446 uint64_t reserved_21_30 : 10;
10447 uint64_t txbypass : 1;
10448 uint64_t reserved_32_39 : 8;
10449 uint64_t g2margin : 5;
10450 uint64_t reserved_45_47 : 3;
10451 uint64_t g2deemph : 5;
10452 uint64_t reserved_53_62 : 10;
10453 uint64_t g2bypass : 1;
10456 struct cvmx_ciu_qlm3_s cn68xx;
10457 struct cvmx_ciu_qlm3_s cn68xxp1;
10459 typedef union cvmx_ciu_qlm3 cvmx_ciu_qlm3_t;
10465 * This register is only reset by cold reset.
10468 union cvmx_ciu_qlm4 {
10470 struct cvmx_ciu_qlm4_s {
10471 #ifdef __BIG_ENDIAN_BITFIELD
10472 uint64_t g2bypass : 1; /**< QLMx PCIE Gen2 tx bypass enable */
10473 uint64_t reserved_53_62 : 10;
10474 uint64_t g2deemph : 5; /**< QLMx PCIE Gen2 tx bypass de-emphasis value */
10475 uint64_t reserved_45_47 : 3;
10476 uint64_t g2margin : 5; /**< QLMx PCIE Gen2 tx bypass margin (amplitude) value */
10477 uint64_t reserved_32_39 : 8;
10478 uint64_t txbypass : 1; /**< QLMx transmitter bypass enable */
10479 uint64_t reserved_21_30 : 10;
10480 uint64_t txdeemph : 5; /**< QLMx transmitter bypass de-emphasis value */
10481 uint64_t reserved_13_15 : 3;
10482 uint64_t txmargin : 5; /**< QLMx transmitter bypass margin (amplitude) value */
10483 uint64_t reserved_4_7 : 4;
10484 uint64_t lane_en : 4; /**< QLMx lane enable mask */
10486 uint64_t lane_en : 4;
10487 uint64_t reserved_4_7 : 4;
10488 uint64_t txmargin : 5;
10489 uint64_t reserved_13_15 : 3;
10490 uint64_t txdeemph : 5;
10491 uint64_t reserved_21_30 : 10;
10492 uint64_t txbypass : 1;
10493 uint64_t reserved_32_39 : 8;
10494 uint64_t g2margin : 5;
10495 uint64_t reserved_45_47 : 3;
10496 uint64_t g2deemph : 5;
10497 uint64_t reserved_53_62 : 10;
10498 uint64_t g2bypass : 1;
10501 struct cvmx_ciu_qlm4_s cn68xx;
10502 struct cvmx_ciu_qlm4_s cn68xxp1;
10504 typedef union cvmx_ciu_qlm4 cvmx_ciu_qlm4_t;
10507 * cvmx_ciu_qlm_dcok
10509 union cvmx_ciu_qlm_dcok {
10511 struct cvmx_ciu_qlm_dcok_s {
10512 #ifdef __BIG_ENDIAN_BITFIELD
10513 uint64_t reserved_4_63 : 60;
10514 uint64_t qlm_dcok : 4; /**< Re-assert dcok for each QLM. The value in this
10515 field is "anded" with the pll_dcok pin and then
10516 sent to each QLM (0..3). */
10518 uint64_t qlm_dcok : 4;
10519 uint64_t reserved_4_63 : 60;
10522 struct cvmx_ciu_qlm_dcok_cn52xx {
10523 #ifdef __BIG_ENDIAN_BITFIELD
10524 uint64_t reserved_2_63 : 62;
10525 uint64_t qlm_dcok : 2; /**< Re-assert dcok for each QLM. The value in this
10526 field is "anded" with the pll_dcok pin and then
10527 sent to each QLM (0..3). */
10529 uint64_t qlm_dcok : 2;
10530 uint64_t reserved_2_63 : 62;
10533 struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
10534 struct cvmx_ciu_qlm_dcok_s cn56xx;
10535 struct cvmx_ciu_qlm_dcok_s cn56xxp1;
10537 typedef union cvmx_ciu_qlm_dcok cvmx_ciu_qlm_dcok_t;
10540 * cvmx_ciu_qlm_jtgc
10542 union cvmx_ciu_qlm_jtgc {
10544 struct cvmx_ciu_qlm_jtgc_s {
10545 #ifdef __BIG_ENDIAN_BITFIELD
10546 uint64_t reserved_17_63 : 47;
10547 uint64_t bypass_ext : 1; /**< BYPASS Field extension to select QLM 4
10548 Selects which QLM JTAG shift chains are bypassed
10549 by the QLM JTAG data register (CIU_QLM_JTGD) (one
10551 uint64_t reserved_11_15 : 5;
10552 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is
10553 divided by 2^(CLK_DIV + 2) */
10554 uint64_t reserved_7_7 : 1;
10555 uint64_t mux_sel : 3; /**< Selects which QLM JTAG shift out is shifted into
10556 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
10557 uint64_t bypass : 4; /**< Selects which QLM JTAG shift chains are bypassed
10558 by the QLM JTAG data register (CIU_QLM_JTGD) (one
10561 uint64_t bypass : 4;
10562 uint64_t mux_sel : 3;
10563 uint64_t reserved_7_7 : 1;
10564 uint64_t clk_div : 3;
10565 uint64_t reserved_11_15 : 5;
10566 uint64_t bypass_ext : 1;
10567 uint64_t reserved_17_63 : 47;
10570 struct cvmx_ciu_qlm_jtgc_cn52xx {
10571 #ifdef __BIG_ENDIAN_BITFIELD
10572 uint64_t reserved_11_63 : 53;
10573 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is
10574 divided by 2^(CLK_DIV + 2) */
10575 uint64_t reserved_5_7 : 3;
10576 uint64_t mux_sel : 1; /**< Selects which QLM JTAG shift out is shifted into
10577 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
10578 uint64_t reserved_2_3 : 2;
10579 uint64_t bypass : 2; /**< Selects which QLM JTAG shift chains are bypassed
10580 by the QLM JTAG data register (CIU_QLM_JTGD) (one
10583 uint64_t bypass : 2;
10584 uint64_t reserved_2_3 : 2;
10585 uint64_t mux_sel : 1;
10586 uint64_t reserved_5_7 : 3;
10587 uint64_t clk_div : 3;
10588 uint64_t reserved_11_63 : 53;
10591 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
10592 struct cvmx_ciu_qlm_jtgc_cn56xx {
10593 #ifdef __BIG_ENDIAN_BITFIELD
10594 uint64_t reserved_11_63 : 53;
10595 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is
10596 divided by 2^(CLK_DIV + 2) */
10597 uint64_t reserved_6_7 : 2;
10598 uint64_t mux_sel : 2; /**< Selects which QLM JTAG shift out is shifted into
10599 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
10600 uint64_t bypass : 4; /**< Selects which QLM JTAG shift chains are bypassed
10601 by the QLM JTAG data register (CIU_QLM_JTGD) (one
10604 uint64_t bypass : 4;
10605 uint64_t mux_sel : 2;
10606 uint64_t reserved_6_7 : 2;
10607 uint64_t clk_div : 3;
10608 uint64_t reserved_11_63 : 53;
10611 struct cvmx_ciu_qlm_jtgc_cn56xx cn56xxp1;
10612 struct cvmx_ciu_qlm_jtgc_cn61xx {
10613 #ifdef __BIG_ENDIAN_BITFIELD
10614 uint64_t reserved_11_63 : 53;
10615 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is
10616 divided by 2^(CLK_DIV + 2) */
10617 uint64_t reserved_6_7 : 2;
10618 uint64_t mux_sel : 2; /**< Selects which QLM JTAG shift out is shifted into
10619 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */
10620 uint64_t reserved_3_3 : 1;
10621 uint64_t bypass : 3; /**< Selects which QLM JTAG shift chains are bypassed
10622 by the QLM JTAG data register (CIU_QLM_JTGD) (one
10625 uint64_t bypass : 3;
10626 uint64_t reserved_3_3 : 1;
10627 uint64_t mux_sel : 2;
10628 uint64_t reserved_6_7 : 2;
10629 uint64_t clk_div : 3;
10630 uint64_t reserved_11_63 : 53;
10633 struct cvmx_ciu_qlm_jtgc_cn61xx cn63xx;
10634 struct cvmx_ciu_qlm_jtgc_cn61xx cn63xxp1;
10635 struct cvmx_ciu_qlm_jtgc_cn61xx cn66xx;
10636 struct cvmx_ciu_qlm_jtgc_s cn68xx;
10637 struct cvmx_ciu_qlm_jtgc_s cn68xxp1;
10638 struct cvmx_ciu_qlm_jtgc_cn61xx cnf71xx;
10640 typedef union cvmx_ciu_qlm_jtgc cvmx_ciu_qlm_jtgc_t;
10643 * cvmx_ciu_qlm_jtgd
10645 union cvmx_ciu_qlm_jtgd {
10647 struct cvmx_ciu_qlm_jtgd_s {
10648 #ifdef __BIG_ENDIAN_BITFIELD
10649 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when
10651 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when
10653 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when
10655 uint64_t reserved_45_60 : 16;
10656 uint64_t select : 5; /**< Selects which QLM JTAG shift chains the JTAG
10657 operations are performed on */
10658 uint64_t reserved_37_39 : 3;
10659 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */
10660 uint64_t shft_reg : 32; /**< QLM JTAG shift register */
10662 uint64_t shft_reg : 32;
10663 uint64_t shft_cnt : 5;
10664 uint64_t reserved_37_39 : 3;
10665 uint64_t select : 5;
10666 uint64_t reserved_45_60 : 16;
10667 uint64_t update : 1;
10668 uint64_t shift : 1;
10669 uint64_t capture : 1;
10672 struct cvmx_ciu_qlm_jtgd_cn52xx {
10673 #ifdef __BIG_ENDIAN_BITFIELD
10674 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when
10676 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when
10678 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when
10680 uint64_t reserved_42_60 : 19;
10681 uint64_t select : 2; /**< Selects which QLM JTAG shift chains the JTAG
10682 operations are performed on */
10683 uint64_t reserved_37_39 : 3;
10684 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */
10685 uint64_t shft_reg : 32; /**< QLM JTAG shift register */
10687 uint64_t shft_reg : 32;
10688 uint64_t shft_cnt : 5;
10689 uint64_t reserved_37_39 : 3;
10690 uint64_t select : 2;
10691 uint64_t reserved_42_60 : 19;
10692 uint64_t update : 1;
10693 uint64_t shift : 1;
10694 uint64_t capture : 1;
10697 struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
10698 struct cvmx_ciu_qlm_jtgd_cn56xx {
10699 #ifdef __BIG_ENDIAN_BITFIELD
10700 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when
10702 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when
10704 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when
10706 uint64_t reserved_44_60 : 17;
10707 uint64_t select : 4; /**< Selects which QLM JTAG shift chains the JTAG
10708 operations are performed on */
10709 uint64_t reserved_37_39 : 3;
10710 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */
10711 uint64_t shft_reg : 32; /**< QLM JTAG shift register */
10713 uint64_t shft_reg : 32;
10714 uint64_t shft_cnt : 5;
10715 uint64_t reserved_37_39 : 3;
10716 uint64_t select : 4;
10717 uint64_t reserved_44_60 : 17;
10718 uint64_t update : 1;
10719 uint64_t shift : 1;
10720 uint64_t capture : 1;
10723 struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
10724 #ifdef __BIG_ENDIAN_BITFIELD
10725 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when
10727 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when
10729 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when
10731 uint64_t reserved_37_60 : 24;
10732 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */
10733 uint64_t shft_reg : 32; /**< QLM JTAG shift register */
10735 uint64_t shft_reg : 32;
10736 uint64_t shft_cnt : 5;
10737 uint64_t reserved_37_60 : 24;
10738 uint64_t update : 1;
10739 uint64_t shift : 1;
10740 uint64_t capture : 1;
10743 struct cvmx_ciu_qlm_jtgd_cn61xx {
10744 #ifdef __BIG_ENDIAN_BITFIELD
10745 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when
10747 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when
10749 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when
10751 uint64_t reserved_43_60 : 18;
10752 uint64_t select : 3; /**< Selects which QLM JTAG shift chains the JTAG
10753 operations are performed on */
10754 uint64_t reserved_37_39 : 3;
10755 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */
10756 uint64_t shft_reg : 32; /**< QLM JTAG shift register */
10758 uint64_t shft_reg : 32;
10759 uint64_t shft_cnt : 5;
10760 uint64_t reserved_37_39 : 3;
10761 uint64_t select : 3;
10762 uint64_t reserved_43_60 : 18;
10763 uint64_t update : 1;
10764 uint64_t shift : 1;
10765 uint64_t capture : 1;
10768 struct cvmx_ciu_qlm_jtgd_cn61xx cn63xx;
10769 struct cvmx_ciu_qlm_jtgd_cn61xx cn63xxp1;
10770 struct cvmx_ciu_qlm_jtgd_cn61xx cn66xx;
10771 struct cvmx_ciu_qlm_jtgd_s cn68xx;
10772 struct cvmx_ciu_qlm_jtgd_s cn68xxp1;
10773 struct cvmx_ciu_qlm_jtgd_cn61xx cnf71xx;
10775 typedef union cvmx_ciu_qlm_jtgd cvmx_ciu_qlm_jtgd_t;
10778 * cvmx_ciu_soft_bist
10780 union cvmx_ciu_soft_bist {
10782 struct cvmx_ciu_soft_bist_s {
10783 #ifdef __BIG_ENDIAN_BITFIELD
10784 uint64_t reserved_1_63 : 63;
10785 uint64_t soft_bist : 1; /**< Reserved */
10787 uint64_t soft_bist : 1;
10788 uint64_t reserved_1_63 : 63;
10791 struct cvmx_ciu_soft_bist_s cn30xx;
10792 struct cvmx_ciu_soft_bist_s cn31xx;
10793 struct cvmx_ciu_soft_bist_s cn38xx;
10794 struct cvmx_ciu_soft_bist_s cn38xxp2;
10795 struct cvmx_ciu_soft_bist_s cn50xx;
10796 struct cvmx_ciu_soft_bist_s cn52xx;
10797 struct cvmx_ciu_soft_bist_s cn52xxp1;
10798 struct cvmx_ciu_soft_bist_s cn56xx;
10799 struct cvmx_ciu_soft_bist_s cn56xxp1;
10800 struct cvmx_ciu_soft_bist_s cn58xx;
10801 struct cvmx_ciu_soft_bist_s cn58xxp1;
10802 struct cvmx_ciu_soft_bist_s cn61xx;
10803 struct cvmx_ciu_soft_bist_s cn63xx;
10804 struct cvmx_ciu_soft_bist_s cn63xxp1;
10805 struct cvmx_ciu_soft_bist_s cn66xx;
10806 struct cvmx_ciu_soft_bist_s cn68xx;
10807 struct cvmx_ciu_soft_bist_s cn68xxp1;
10808 struct cvmx_ciu_soft_bist_s cnf71xx;
10810 typedef union cvmx_ciu_soft_bist cvmx_ciu_soft_bist_t;
10813 * cvmx_ciu_soft_prst
10815 union cvmx_ciu_soft_prst {
10817 struct cvmx_ciu_soft_prst_s {
10818 #ifdef __BIG_ENDIAN_BITFIELD
10819 uint64_t reserved_3_63 : 61;
10820 uint64_t host64 : 1; /**< PCX Host Mode Device Capability (0=32b/1=64b) */
10821 uint64_t npi : 1; /**< When PCI soft reset is asserted, also reset the
10822 NPI and PNI logic */
10823 uint64_t soft_prst : 1; /**< Resets the PCIe logic in all modes, not just
10824 RC mode. The reset value is based on the
10825 corresponding MIO_RST_CTL[PRTMODE] CSR field:
10826 If PRTMODE == 0, then SOFT_PRST resets to 0
10827 If PRTMODE != 0, then SOFT_PRST resets to 1
10828 When OCTEON is configured to drive the PERST*_L
10829 chip pin (ie. MIO_RST_CTL0[RST_DRV] is set), this
10830 controls the PERST*_L chip pin. */
10832 uint64_t soft_prst : 1;
10834 uint64_t host64 : 1;
10835 uint64_t reserved_3_63 : 61;
10838 struct cvmx_ciu_soft_prst_s cn30xx;
10839 struct cvmx_ciu_soft_prst_s cn31xx;
10840 struct cvmx_ciu_soft_prst_s cn38xx;
10841 struct cvmx_ciu_soft_prst_s cn38xxp2;
10842 struct cvmx_ciu_soft_prst_s cn50xx;
10843 struct cvmx_ciu_soft_prst_cn52xx {
10844 #ifdef __BIG_ENDIAN_BITFIELD
10845 uint64_t reserved_1_63 : 63;
10846 uint64_t soft_prst : 1; /**< Reset the PCI bus. Only works when Octane is
10847 configured as a HOST. When OCTEON is a PCI host
10848 (i.e. when PCI_HOST_MODE = 1), This controls
10849 PCI_RST_L. Refer to section 10.11.1. */
10851 uint64_t soft_prst : 1;
10852 uint64_t reserved_1_63 : 63;
10855 struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
10856 struct cvmx_ciu_soft_prst_cn52xx cn56xx;
10857 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
10858 struct cvmx_ciu_soft_prst_s cn58xx;
10859 struct cvmx_ciu_soft_prst_s cn58xxp1;
10860 struct cvmx_ciu_soft_prst_cn52xx cn61xx;
10861 struct cvmx_ciu_soft_prst_cn52xx cn63xx;
10862 struct cvmx_ciu_soft_prst_cn52xx cn63xxp1;
10863 struct cvmx_ciu_soft_prst_cn52xx cn66xx;
10864 struct cvmx_ciu_soft_prst_cn52xx cn68xx;
10865 struct cvmx_ciu_soft_prst_cn52xx cn68xxp1;
10866 struct cvmx_ciu_soft_prst_cn52xx cnf71xx;
10868 typedef union cvmx_ciu_soft_prst cvmx_ciu_soft_prst_t;
10871 * cvmx_ciu_soft_prst1
10873 union cvmx_ciu_soft_prst1 {
10875 struct cvmx_ciu_soft_prst1_s {
10876 #ifdef __BIG_ENDIAN_BITFIELD
10877 uint64_t reserved_1_63 : 63;
10878 uint64_t soft_prst : 1; /**< Resets the PCIe logic in all modes, not just
10879 RC mode. The reset value is based on the
10880 corresponding MIO_RST_CTL[PRTMODE] CSR field:
10881 If PRTMODE == 0, then SOFT_PRST resets to 0
10882 If PRTMODE != 0, then SOFT_PRST resets to 1
10883 In o61, this PRST initial value is always '1' as
10884 PEM1 always running on host mode. */
10886 uint64_t soft_prst : 1;
10887 uint64_t reserved_1_63 : 63;
10890 struct cvmx_ciu_soft_prst1_s cn52xx;
10891 struct cvmx_ciu_soft_prst1_s cn52xxp1;
10892 struct cvmx_ciu_soft_prst1_s cn56xx;
10893 struct cvmx_ciu_soft_prst1_s cn56xxp1;
10894 struct cvmx_ciu_soft_prst1_s cn61xx;
10895 struct cvmx_ciu_soft_prst1_s cn63xx;
10896 struct cvmx_ciu_soft_prst1_s cn63xxp1;
10897 struct cvmx_ciu_soft_prst1_s cn66xx;
10898 struct cvmx_ciu_soft_prst1_s cn68xx;
10899 struct cvmx_ciu_soft_prst1_s cn68xxp1;
10900 struct cvmx_ciu_soft_prst1_s cnf71xx;
10902 typedef union cvmx_ciu_soft_prst1 cvmx_ciu_soft_prst1_t;
10905 * cvmx_ciu_soft_prst2
10907 union cvmx_ciu_soft_prst2 {
10909 struct cvmx_ciu_soft_prst2_s {
10910 #ifdef __BIG_ENDIAN_BITFIELD
10911 uint64_t reserved_1_63 : 63;
10912 uint64_t soft_prst : 1; /**< Resets the sRIO logic in all modes, not just
10913 RC mode. The reset value is based on the
10914 corresponding MIO_RST_CNTL[PRTMODE] CSR field:
10915 If PRTMODE == 0, then SOFT_PRST resets to 0
10916 If PRTMODE != 0, then SOFT_PRST resets to 1 */
10918 uint64_t soft_prst : 1;
10919 uint64_t reserved_1_63 : 63;
10922 struct cvmx_ciu_soft_prst2_s cn66xx;
10924 typedef union cvmx_ciu_soft_prst2 cvmx_ciu_soft_prst2_t;
10927 * cvmx_ciu_soft_prst3
10929 union cvmx_ciu_soft_prst3 {
10931 struct cvmx_ciu_soft_prst3_s {
10932 #ifdef __BIG_ENDIAN_BITFIELD
10933 uint64_t reserved_1_63 : 63;
10934 uint64_t soft_prst : 1; /**< Resets the sRIO logic in all modes, not just
10935 RC mode. The reset value is based on the
10936 corresponding MIO_RST_CNTL[PRTMODE] CSR field:
10937 If PRTMODE == 0, then SOFT_PRST resets to 0
10938 If PRTMODE != 0, then SOFT_PRST resets to 1 */
10940 uint64_t soft_prst : 1;
10941 uint64_t reserved_1_63 : 63;
10944 struct cvmx_ciu_soft_prst3_s cn66xx;
10946 typedef union cvmx_ciu_soft_prst3 cvmx_ciu_soft_prst3_t;
10949 * cvmx_ciu_soft_rst
10951 union cvmx_ciu_soft_rst {
10953 struct cvmx_ciu_soft_rst_s {
10954 #ifdef __BIG_ENDIAN_BITFIELD
10955 uint64_t reserved_1_63 : 63;
10956 uint64_t soft_rst : 1; /**< Resets Octeon
10957 When soft reseting Octeon from a remote PCIe
10958 host, always read CIU_SOFT_RST (and wait for
10959 result) before writing SOFT_RST to '1'. */
10961 uint64_t soft_rst : 1;
10962 uint64_t reserved_1_63 : 63;
10965 struct cvmx_ciu_soft_rst_s cn30xx;
10966 struct cvmx_ciu_soft_rst_s cn31xx;
10967 struct cvmx_ciu_soft_rst_s cn38xx;
10968 struct cvmx_ciu_soft_rst_s cn38xxp2;
10969 struct cvmx_ciu_soft_rst_s cn50xx;
10970 struct cvmx_ciu_soft_rst_s cn52xx;
10971 struct cvmx_ciu_soft_rst_s cn52xxp1;
10972 struct cvmx_ciu_soft_rst_s cn56xx;
10973 struct cvmx_ciu_soft_rst_s cn56xxp1;
10974 struct cvmx_ciu_soft_rst_s cn58xx;
10975 struct cvmx_ciu_soft_rst_s cn58xxp1;
10976 struct cvmx_ciu_soft_rst_s cn61xx;
10977 struct cvmx_ciu_soft_rst_s cn63xx;
10978 struct cvmx_ciu_soft_rst_s cn63xxp1;
10979 struct cvmx_ciu_soft_rst_s cn66xx;
10980 struct cvmx_ciu_soft_rst_s cn68xx;
10981 struct cvmx_ciu_soft_rst_s cn68xxp1;
10982 struct cvmx_ciu_soft_rst_s cnf71xx;
10984 typedef union cvmx_ciu_soft_rst cvmx_ciu_soft_rst_t;
10987 * cvmx_ciu_sum1_io#_int
10990 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
10991 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
10992 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for
10993 * different PPs, same value as $CIU_INT_SUM1.
10994 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
10996 union cvmx_ciu_sum1_iox_int {
10998 struct cvmx_ciu_sum1_iox_int_s {
10999 #ifdef __BIG_ENDIAN_BITFIELD
11000 uint64_t rst : 1; /**< MIO RST interrupt
11002 uint64_t reserved_62_62 : 1;
11003 uint64_t srio3 : 1; /**< SRIO3 interrupt
11004 See SRIO3_INT_REG, SRIO3_INT2_REG */
11005 uint64_t srio2 : 1; /**< SRIO2 interrupt
11006 See SRIO2_INT_REG, SRIO2_INT2_REG */
11007 uint64_t reserved_57_59 : 3;
11008 uint64_t dfm : 1; /**< DFM Interrupt
11009 See DFM_FNT_STAT */
11010 uint64_t reserved_53_55 : 3;
11011 uint64_t lmc0 : 1; /**< LMC0 interrupt
11013 uint64_t reserved_51_51 : 1;
11014 uint64_t srio0 : 1; /**< SRIO0 interrupt
11015 See SRIO0_INT_REG, SRIO0_INT2_REG */
11016 uint64_t pem1 : 1; /**< PEM1 interrupt
11017 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11018 uint64_t pem0 : 1; /**< PEM0 interrupt
11019 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11020 uint64_t ptp : 1; /**< PTP interrupt
11021 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11022 uint64_t agl : 1; /**< AGL interrupt
11023 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11024 uint64_t reserved_41_45 : 5;
11025 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11026 TBD, See DPI DMA instruction completion */
11027 uint64_t reserved_38_39 : 2;
11028 uint64_t agx1 : 1; /**< GMX1 interrupt
11029 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11030 PCS1_INT*_REG, PCSX1_INT_REG */
11031 uint64_t agx0 : 1; /**< GMX0 interrupt
11032 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11033 PCS0_INT*_REG, PCSX0_INT_REG */
11034 uint64_t dpi : 1; /**< DPI interrupt
11036 uint64_t sli : 1; /**< SLI interrupt
11037 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11038 uint64_t usb : 1; /**< USB UCTL0 interrupt
11039 See UCTL0_INT_REG */
11040 uint64_t dfa : 1; /**< DFA interrupt
11042 uint64_t key : 1; /**< KEY interrupt
11044 uint64_t rad : 1; /**< RAD interrupt
11045 See RAD_REG_ERROR */
11046 uint64_t tim : 1; /**< TIM interrupt
11047 See TIM_REG_ERROR */
11048 uint64_t zip : 1; /**< ZIP interrupt
11050 uint64_t pko : 1; /**< PKO interrupt
11051 See PKO_REG_ERROR */
11052 uint64_t pip : 1; /**< PIP interrupt
11054 uint64_t ipd : 1; /**< IPD interrupt
11056 uint64_t l2c : 1; /**< L2C interrupt
11058 uint64_t pow : 1; /**< POW err interrupt
11060 uint64_t fpa : 1; /**< FPA interrupt
11062 uint64_t iob : 1; /**< IOB interrupt
11064 uint64_t mio : 1; /**< MIO boot interrupt
11065 See MIO_BOOT_ERR */
11066 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
11067 See EMMC interrupt */
11068 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
11070 uint64_t reserved_10_17 : 8;
11071 uint64_t wdog : 10; /**< Per PP watchdog interrupts */
11073 uint64_t wdog : 10;
11074 uint64_t reserved_10_17 : 8;
11095 uint64_t reserved_38_39 : 2;
11096 uint64_t dpi_dma : 1;
11097 uint64_t reserved_41_45 : 5;
11102 uint64_t srio0 : 1;
11103 uint64_t reserved_51_51 : 1;
11105 uint64_t reserved_53_55 : 3;
11107 uint64_t reserved_57_59 : 3;
11108 uint64_t srio2 : 1;
11109 uint64_t srio3 : 1;
11110 uint64_t reserved_62_62 : 1;
11114 struct cvmx_ciu_sum1_iox_int_cn61xx {
11115 #ifdef __BIG_ENDIAN_BITFIELD
11116 uint64_t rst : 1; /**< MIO RST interrupt
11118 uint64_t reserved_53_62 : 10;
11119 uint64_t lmc0 : 1; /**< LMC0 interrupt
11121 uint64_t reserved_50_51 : 2;
11122 uint64_t pem1 : 1; /**< PEM1 interrupt
11123 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11124 uint64_t pem0 : 1; /**< PEM0 interrupt
11125 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11126 uint64_t ptp : 1; /**< PTP interrupt
11127 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11128 uint64_t agl : 1; /**< AGL interrupt
11129 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11130 uint64_t reserved_41_45 : 5;
11131 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11132 TBD, See DPI DMA instruction completion */
11133 uint64_t reserved_38_39 : 2;
11134 uint64_t agx1 : 1; /**< GMX1 interrupt
11135 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11136 PCS1_INT*_REG, PCSX1_INT_REG */
11137 uint64_t agx0 : 1; /**< GMX0 interrupt
11138 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11139 PCS0_INT*_REG, PCSX0_INT_REG */
11140 uint64_t dpi : 1; /**< DPI interrupt
11142 uint64_t sli : 1; /**< SLI interrupt
11143 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11144 uint64_t usb : 1; /**< USB UCTL0 interrupt
11145 See UCTL0_INT_REG */
11146 uint64_t dfa : 1; /**< DFA interrupt
11148 uint64_t key : 1; /**< KEY interrupt
11150 uint64_t rad : 1; /**< RAD interrupt
11151 See RAD_REG_ERROR */
11152 uint64_t tim : 1; /**< TIM interrupt
11153 See TIM_REG_ERROR */
11154 uint64_t zip : 1; /**< ZIP interrupt
11156 uint64_t pko : 1; /**< PKO interrupt
11157 See PKO_REG_ERROR */
11158 uint64_t pip : 1; /**< PIP interrupt
11160 uint64_t ipd : 1; /**< IPD interrupt
11162 uint64_t l2c : 1; /**< L2C interrupt
11164 uint64_t pow : 1; /**< POW err interrupt
11166 uint64_t fpa : 1; /**< FPA interrupt
11168 uint64_t iob : 1; /**< IOB interrupt
11170 uint64_t mio : 1; /**< MIO boot interrupt
11171 See MIO_BOOT_ERR */
11172 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
11173 See EMMC interrupt */
11174 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt
11176 uint64_t reserved_4_17 : 14;
11177 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
11180 uint64_t reserved_4_17 : 14;
11201 uint64_t reserved_38_39 : 2;
11202 uint64_t dpi_dma : 1;
11203 uint64_t reserved_41_45 : 5;
11208 uint64_t reserved_50_51 : 2;
11210 uint64_t reserved_53_62 : 10;
11214 struct cvmx_ciu_sum1_iox_int_cn66xx {
11215 #ifdef __BIG_ENDIAN_BITFIELD
11216 uint64_t rst : 1; /**< MIO RST interrupt
11218 uint64_t reserved_62_62 : 1;
11219 uint64_t srio3 : 1; /**< SRIO3 interrupt
11220 See SRIO3_INT_REG, SRIO3_INT2_REG */
11221 uint64_t srio2 : 1; /**< SRIO2 interrupt
11222 See SRIO2_INT_REG, SRIO2_INT2_REG */
11223 uint64_t reserved_57_59 : 3;
11224 uint64_t dfm : 1; /**< DFM Interrupt
11225 See DFM_FNT_STAT */
11226 uint64_t reserved_53_55 : 3;
11227 uint64_t lmc0 : 1; /**< LMC0 interrupt
11229 uint64_t reserved_51_51 : 1;
11230 uint64_t srio0 : 1; /**< SRIO0 interrupt
11231 See SRIO0_INT_REG, SRIO0_INT2_REG */
11232 uint64_t pem1 : 1; /**< PEM1 interrupt
11233 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11234 uint64_t pem0 : 1; /**< PEM0 interrupt
11235 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11236 uint64_t ptp : 1; /**< PTP interrupt
11237 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11238 uint64_t agl : 1; /**< AGL interrupt
11239 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11240 uint64_t reserved_38_45 : 8;
11241 uint64_t agx1 : 1; /**< GMX1 interrupt
11242 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11243 PCS1_INT*_REG, PCSX1_INT_REG */
11244 uint64_t agx0 : 1; /**< GMX0 interrupt
11245 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11246 PCS0_INT*_REG, PCSX0_INT_REG */
11247 uint64_t dpi : 1; /**< DPI interrupt
11249 uint64_t sli : 1; /**< SLI interrupt
11250 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11251 uint64_t usb : 1; /**< USB UCTL0 interrupt
11252 See UCTL0_INT_REG */
11253 uint64_t dfa : 1; /**< DFA interrupt
11255 uint64_t key : 1; /**< KEY interrupt
11257 uint64_t rad : 1; /**< RAD interrupt
11258 See RAD_REG_ERROR */
11259 uint64_t tim : 1; /**< TIM interrupt
11260 See TIM_REG_ERROR */
11261 uint64_t zip : 1; /**< ZIP interrupt
11263 uint64_t pko : 1; /**< PKO interrupt
11264 See PKO_REG_ERROR */
11265 uint64_t pip : 1; /**< PIP interrupt
11267 uint64_t ipd : 1; /**< IPD interrupt
11269 uint64_t l2c : 1; /**< L2C interrupt
11271 uint64_t pow : 1; /**< POW err interrupt
11273 uint64_t fpa : 1; /**< FPA interrupt
11275 uint64_t iob : 1; /**< IOB interrupt
11277 uint64_t mio : 1; /**< MIO boot interrupt
11278 See MIO_BOOT_ERR */
11279 uint64_t nand : 1; /**< NAND Flash Controller interrupt
11281 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
11283 uint64_t reserved_10_17 : 8;
11284 uint64_t wdog : 10; /**< 10 watchdog interrupts */
11286 uint64_t wdog : 10;
11287 uint64_t reserved_10_17 : 8;
11308 uint64_t reserved_38_45 : 8;
11313 uint64_t srio0 : 1;
11314 uint64_t reserved_51_51 : 1;
11316 uint64_t reserved_53_55 : 3;
11318 uint64_t reserved_57_59 : 3;
11319 uint64_t srio2 : 1;
11320 uint64_t srio3 : 1;
11321 uint64_t reserved_62_62 : 1;
11325 struct cvmx_ciu_sum1_iox_int_cnf71xx {
11326 #ifdef __BIG_ENDIAN_BITFIELD
11327 uint64_t rst : 1; /**< MIO RST interrupt
11329 uint64_t reserved_53_62 : 10;
11330 uint64_t lmc0 : 1; /**< LMC0 interrupt
11332 uint64_t reserved_50_51 : 2;
11333 uint64_t pem1 : 1; /**< PEM1 interrupt
11334 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11335 uint64_t pem0 : 1; /**< PEM0 interrupt
11336 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11337 uint64_t ptp : 1; /**< PTP interrupt
11338 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11339 uint64_t reserved_41_46 : 6;
11340 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11341 TBD, See DPI DMA instruction completion */
11342 uint64_t reserved_37_39 : 3;
11343 uint64_t agx0 : 1; /**< GMX0 interrupt
11344 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11345 PCS0_INT*_REG, PCSX0_INT_REG */
11346 uint64_t dpi : 1; /**< DPI interrupt
11348 uint64_t sli : 1; /**< SLI interrupt
11349 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11350 uint64_t usb : 1; /**< USB UCTL0 interrupt
11351 See UCTL0_INT_REG */
11352 uint64_t reserved_32_32 : 1;
11353 uint64_t key : 1; /**< KEY interrupt
11355 uint64_t rad : 1; /**< RAD interrupt
11356 See RAD_REG_ERROR */
11357 uint64_t tim : 1; /**< TIM interrupt
11358 See TIM_REG_ERROR */
11359 uint64_t reserved_28_28 : 1;
11360 uint64_t pko : 1; /**< PKO interrupt
11361 See PKO_REG_ERROR */
11362 uint64_t pip : 1; /**< PIP interrupt
11364 uint64_t ipd : 1; /**< IPD interrupt
11366 uint64_t l2c : 1; /**< L2C interrupt
11368 uint64_t pow : 1; /**< POW err interrupt
11370 uint64_t fpa : 1; /**< FPA interrupt
11372 uint64_t iob : 1; /**< IOB interrupt
11374 uint64_t mio : 1; /**< MIO boot interrupt
11375 See MIO_BOOT_ERR */
11376 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
11377 See EMMC interrupt */
11378 uint64_t reserved_4_18 : 15;
11379 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
11382 uint64_t reserved_4_18 : 15;
11392 uint64_t reserved_28_28 : 1;
11396 uint64_t reserved_32_32 : 1;
11401 uint64_t reserved_37_39 : 3;
11402 uint64_t dpi_dma : 1;
11403 uint64_t reserved_41_46 : 6;
11407 uint64_t reserved_50_51 : 2;
11409 uint64_t reserved_53_62 : 10;
11414 typedef union cvmx_ciu_sum1_iox_int cvmx_ciu_sum1_iox_int_t;
11417 * cvmx_ciu_sum1_pp#_ip2
11420 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
11421 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
11422 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for
11423 * different PPs, same value as $CIU_INT_SUM1.
11424 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
11426 union cvmx_ciu_sum1_ppx_ip2 {
11428 struct cvmx_ciu_sum1_ppx_ip2_s {
11429 #ifdef __BIG_ENDIAN_BITFIELD
11430 uint64_t rst : 1; /**< MIO RST interrupt
11432 uint64_t reserved_62_62 : 1;
11433 uint64_t srio3 : 1; /**< SRIO3 interrupt
11434 See SRIO3_INT_REG, SRIO3_INT2_REG */
11435 uint64_t srio2 : 1; /**< SRIO2 interrupt
11436 See SRIO2_INT_REG, SRIO2_INT2_REG */
11437 uint64_t reserved_57_59 : 3;
11438 uint64_t dfm : 1; /**< DFM Interrupt
11439 See DFM_FNT_STAT */
11440 uint64_t reserved_53_55 : 3;
11441 uint64_t lmc0 : 1; /**< LMC0 interrupt
11443 uint64_t reserved_51_51 : 1;
11444 uint64_t srio0 : 1; /**< SRIO0 interrupt
11445 See SRIO0_INT_REG, SRIO0_INT2_REG */
11446 uint64_t pem1 : 1; /**< PEM1 interrupt
11447 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11448 uint64_t pem0 : 1; /**< PEM0 interrupt
11449 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11450 uint64_t ptp : 1; /**< PTP interrupt
11451 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11452 uint64_t agl : 1; /**< AGL interrupt
11453 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11454 uint64_t reserved_41_45 : 5;
11455 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11456 TBD, See DPI DMA instruction completion */
11457 uint64_t reserved_38_39 : 2;
11458 uint64_t agx1 : 1; /**< GMX1 interrupt
11459 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11460 PCS1_INT*_REG, PCSX1_INT_REG */
11461 uint64_t agx0 : 1; /**< GMX0 interrupt
11462 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11463 PCS0_INT*_REG, PCSX0_INT_REG */
11464 uint64_t dpi : 1; /**< DPI interrupt
11466 uint64_t sli : 1; /**< SLI interrupt
11467 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11468 uint64_t usb : 1; /**< USB UCTL0 interrupt
11469 See UCTL0_INT_REG */
11470 uint64_t dfa : 1; /**< DFA interrupt
11472 uint64_t key : 1; /**< KEY interrupt
11474 uint64_t rad : 1; /**< RAD interrupt
11475 See RAD_REG_ERROR */
11476 uint64_t tim : 1; /**< TIM interrupt
11477 See TIM_REG_ERROR */
11478 uint64_t zip : 1; /**< ZIP interrupt
11480 uint64_t pko : 1; /**< PKO interrupt
11481 See PKO_REG_ERROR */
11482 uint64_t pip : 1; /**< PIP interrupt
11484 uint64_t ipd : 1; /**< IPD interrupt
11486 uint64_t l2c : 1; /**< L2C interrupt
11488 uint64_t pow : 1; /**< POW err interrupt
11490 uint64_t fpa : 1; /**< FPA interrupt
11492 uint64_t iob : 1; /**< IOB interrupt
11494 uint64_t mio : 1; /**< MIO boot interrupt
11495 See MIO_BOOT_ERR */
11496 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
11497 See EMMC interrupt */
11498 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
11500 uint64_t reserved_10_17 : 8;
11501 uint64_t wdog : 10; /**< Per PP watchdog interrupts */
11503 uint64_t wdog : 10;
11504 uint64_t reserved_10_17 : 8;
11525 uint64_t reserved_38_39 : 2;
11526 uint64_t dpi_dma : 1;
11527 uint64_t reserved_41_45 : 5;
11532 uint64_t srio0 : 1;
11533 uint64_t reserved_51_51 : 1;
11535 uint64_t reserved_53_55 : 3;
11537 uint64_t reserved_57_59 : 3;
11538 uint64_t srio2 : 1;
11539 uint64_t srio3 : 1;
11540 uint64_t reserved_62_62 : 1;
11544 struct cvmx_ciu_sum1_ppx_ip2_cn61xx {
11545 #ifdef __BIG_ENDIAN_BITFIELD
11546 uint64_t rst : 1; /**< MIO RST interrupt
11548 uint64_t reserved_53_62 : 10;
11549 uint64_t lmc0 : 1; /**< LMC0 interrupt
11551 uint64_t reserved_50_51 : 2;
11552 uint64_t pem1 : 1; /**< PEM1 interrupt
11553 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11554 uint64_t pem0 : 1; /**< PEM0 interrupt
11555 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11556 uint64_t ptp : 1; /**< PTP interrupt
11557 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11558 uint64_t agl : 1; /**< AGL interrupt
11559 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11560 uint64_t reserved_41_45 : 5;
11561 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11562 TBD, See DPI DMA instruction completion */
11563 uint64_t reserved_38_39 : 2;
11564 uint64_t agx1 : 1; /**< GMX1 interrupt
11565 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11566 PCS1_INT*_REG, PCSX1_INT_REG */
11567 uint64_t agx0 : 1; /**< GMX0 interrupt
11568 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11569 PCS0_INT*_REG, PCSX0_INT_REG */
11570 uint64_t dpi : 1; /**< DPI interrupt
11572 uint64_t sli : 1; /**< SLI interrupt
11573 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11574 uint64_t usb : 1; /**< USB UCTL0 interrupt
11575 See UCTL0_INT_REG */
11576 uint64_t dfa : 1; /**< DFA interrupt
11578 uint64_t key : 1; /**< KEY interrupt
11580 uint64_t rad : 1; /**< RAD interrupt
11581 See RAD_REG_ERROR */
11582 uint64_t tim : 1; /**< TIM interrupt
11583 See TIM_REG_ERROR */
11584 uint64_t zip : 1; /**< ZIP interrupt
11586 uint64_t pko : 1; /**< PKO interrupt
11587 See PKO_REG_ERROR */
11588 uint64_t pip : 1; /**< PIP interrupt
11590 uint64_t ipd : 1; /**< IPD interrupt
11592 uint64_t l2c : 1; /**< L2C interrupt
11594 uint64_t pow : 1; /**< POW err interrupt
11596 uint64_t fpa : 1; /**< FPA interrupt
11598 uint64_t iob : 1; /**< IOB interrupt
11600 uint64_t mio : 1; /**< MIO boot interrupt
11601 See MIO_BOOT_ERR */
11602 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
11603 See EMMC interrupt */
11604 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt
11606 uint64_t reserved_4_17 : 14;
11607 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
11610 uint64_t reserved_4_17 : 14;
11631 uint64_t reserved_38_39 : 2;
11632 uint64_t dpi_dma : 1;
11633 uint64_t reserved_41_45 : 5;
11638 uint64_t reserved_50_51 : 2;
11640 uint64_t reserved_53_62 : 10;
11644 struct cvmx_ciu_sum1_ppx_ip2_cn66xx {
11645 #ifdef __BIG_ENDIAN_BITFIELD
11646 uint64_t rst : 1; /**< MIO RST interrupt
11648 uint64_t reserved_62_62 : 1;
11649 uint64_t srio3 : 1; /**< SRIO3 interrupt
11650 See SRIO3_INT_REG, SRIO3_INT2_REG */
11651 uint64_t srio2 : 1; /**< SRIO2 interrupt
11652 See SRIO2_INT_REG, SRIO2_INT2_REG */
11653 uint64_t reserved_57_59 : 3;
11654 uint64_t dfm : 1; /**< DFM Interrupt
11655 See DFM_FNT_STAT */
11656 uint64_t reserved_53_55 : 3;
11657 uint64_t lmc0 : 1; /**< LMC0 interrupt
11659 uint64_t reserved_51_51 : 1;
11660 uint64_t srio0 : 1; /**< SRIO0 interrupt
11661 See SRIO0_INT_REG, SRIO0_INT2_REG */
11662 uint64_t pem1 : 1; /**< PEM1 interrupt
11663 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11664 uint64_t pem0 : 1; /**< PEM0 interrupt
11665 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11666 uint64_t ptp : 1; /**< PTP interrupt
11667 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11668 uint64_t agl : 1; /**< AGL interrupt
11669 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11670 uint64_t reserved_38_45 : 8;
11671 uint64_t agx1 : 1; /**< GMX1 interrupt
11672 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11673 PCS1_INT*_REG, PCSX1_INT_REG */
11674 uint64_t agx0 : 1; /**< GMX0 interrupt
11675 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11676 PCS0_INT*_REG, PCSX0_INT_REG */
11677 uint64_t dpi : 1; /**< DPI interrupt
11679 uint64_t sli : 1; /**< SLI interrupt
11680 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11681 uint64_t usb : 1; /**< USB UCTL0 interrupt
11682 See UCTL0_INT_REG */
11683 uint64_t dfa : 1; /**< DFA interrupt
11685 uint64_t key : 1; /**< KEY interrupt
11687 uint64_t rad : 1; /**< RAD interrupt
11688 See RAD_REG_ERROR */
11689 uint64_t tim : 1; /**< TIM interrupt
11690 See TIM_REG_ERROR */
11691 uint64_t zip : 1; /**< ZIP interrupt
11693 uint64_t pko : 1; /**< PKO interrupt
11694 See PKO_REG_ERROR */
11695 uint64_t pip : 1; /**< PIP interrupt
11697 uint64_t ipd : 1; /**< IPD interrupt
11699 uint64_t l2c : 1; /**< L2C interrupt
11701 uint64_t pow : 1; /**< POW err interrupt
11703 uint64_t fpa : 1; /**< FPA interrupt
11705 uint64_t iob : 1; /**< IOB interrupt
11707 uint64_t mio : 1; /**< MIO boot interrupt
11708 See MIO_BOOT_ERR */
11709 uint64_t nand : 1; /**< NAND Flash Controller interrupt
11711 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
11713 uint64_t reserved_10_17 : 8;
11714 uint64_t wdog : 10; /**< 10 watchdog interrupts */
11716 uint64_t wdog : 10;
11717 uint64_t reserved_10_17 : 8;
11738 uint64_t reserved_38_45 : 8;
11743 uint64_t srio0 : 1;
11744 uint64_t reserved_51_51 : 1;
11746 uint64_t reserved_53_55 : 3;
11748 uint64_t reserved_57_59 : 3;
11749 uint64_t srio2 : 1;
11750 uint64_t srio3 : 1;
11751 uint64_t reserved_62_62 : 1;
11755 struct cvmx_ciu_sum1_ppx_ip2_cnf71xx {
11756 #ifdef __BIG_ENDIAN_BITFIELD
11757 uint64_t rst : 1; /**< MIO RST interrupt
11759 uint64_t reserved_53_62 : 10;
11760 uint64_t lmc0 : 1; /**< LMC0 interrupt
11762 uint64_t reserved_50_51 : 2;
11763 uint64_t pem1 : 1; /**< PEM1 interrupt
11764 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11765 uint64_t pem0 : 1; /**< PEM0 interrupt
11766 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11767 uint64_t ptp : 1; /**< PTP interrupt
11768 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11769 uint64_t reserved_41_46 : 6;
11770 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11771 TBD, See DPI DMA instruction completion */
11772 uint64_t reserved_37_39 : 3;
11773 uint64_t agx0 : 1; /**< GMX0 interrupt
11774 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11775 PCS0_INT*_REG, PCSX0_INT_REG */
11776 uint64_t dpi : 1; /**< DPI interrupt
11778 uint64_t sli : 1; /**< SLI interrupt
11779 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11780 uint64_t usb : 1; /**< USB UCTL0 interrupt
11781 See UCTL0_INT_REG */
11782 uint64_t reserved_32_32 : 1;
11783 uint64_t key : 1; /**< KEY interrupt
11785 uint64_t rad : 1; /**< RAD interrupt
11786 See RAD_REG_ERROR */
11787 uint64_t tim : 1; /**< TIM interrupt
11788 See TIM_REG_ERROR */
11789 uint64_t reserved_28_28 : 1;
11790 uint64_t pko : 1; /**< PKO interrupt
11791 See PKO_REG_ERROR */
11792 uint64_t pip : 1; /**< PIP interrupt
11794 uint64_t ipd : 1; /**< IPD interrupt
11796 uint64_t l2c : 1; /**< L2C interrupt
11798 uint64_t pow : 1; /**< POW err interrupt
11800 uint64_t fpa : 1; /**< FPA interrupt
11802 uint64_t iob : 1; /**< IOB interrupt
11804 uint64_t mio : 1; /**< MIO boot interrupt
11805 See MIO_BOOT_ERR */
11806 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
11807 See EMMC interrupt */
11808 uint64_t reserved_4_18 : 15;
11809 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
11812 uint64_t reserved_4_18 : 15;
11822 uint64_t reserved_28_28 : 1;
11826 uint64_t reserved_32_32 : 1;
11831 uint64_t reserved_37_39 : 3;
11832 uint64_t dpi_dma : 1;
11833 uint64_t reserved_41_46 : 6;
11837 uint64_t reserved_50_51 : 2;
11839 uint64_t reserved_53_62 : 10;
11844 typedef union cvmx_ciu_sum1_ppx_ip2 cvmx_ciu_sum1_ppx_ip2_t;
11847 * cvmx_ciu_sum1_pp#_ip3
11850 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
11851 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
11852 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for
11853 * different PPs, same value as $CIU_INT_SUM1.
11854 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
11856 union cvmx_ciu_sum1_ppx_ip3 {
11858 struct cvmx_ciu_sum1_ppx_ip3_s {
11859 #ifdef __BIG_ENDIAN_BITFIELD
11860 uint64_t rst : 1; /**< MIO RST interrupt
11862 uint64_t reserved_62_62 : 1;
11863 uint64_t srio3 : 1; /**< SRIO3 interrupt
11864 See SRIO3_INT_REG, SRIO3_INT2_REG */
11865 uint64_t srio2 : 1; /**< SRIO2 interrupt
11866 See SRIO2_INT_REG, SRIO2_INT2_REG */
11867 uint64_t reserved_57_59 : 3;
11868 uint64_t dfm : 1; /**< DFM Interrupt
11869 See DFM_FNT_STAT */
11870 uint64_t reserved_53_55 : 3;
11871 uint64_t lmc0 : 1; /**< LMC0 interrupt
11873 uint64_t reserved_51_51 : 1;
11874 uint64_t srio0 : 1; /**< SRIO0 interrupt
11875 See SRIO0_INT_REG, SRIO0_INT2_REG */
11876 uint64_t pem1 : 1; /**< PEM1 interrupt
11877 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11878 uint64_t pem0 : 1; /**< PEM0 interrupt
11879 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11880 uint64_t ptp : 1; /**< PTP interrupt
11881 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11882 uint64_t agl : 1; /**< AGL interrupt
11883 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11884 uint64_t reserved_41_45 : 5;
11885 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11886 TBD, See DPI DMA instruction completion */
11887 uint64_t reserved_38_39 : 2;
11888 uint64_t agx1 : 1; /**< GMX1 interrupt
11889 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11890 PCS1_INT*_REG, PCSX1_INT_REG */
11891 uint64_t agx0 : 1; /**< GMX0 interrupt
11892 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11893 PCS0_INT*_REG, PCSX0_INT_REG */
11894 uint64_t dpi : 1; /**< DPI interrupt
11896 uint64_t sli : 1; /**< SLI interrupt
11897 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
11898 uint64_t usb : 1; /**< USB UCTL0 interrupt
11899 See UCTL0_INT_REG */
11900 uint64_t dfa : 1; /**< DFA interrupt
11902 uint64_t key : 1; /**< KEY interrupt
11904 uint64_t rad : 1; /**< RAD interrupt
11905 See RAD_REG_ERROR */
11906 uint64_t tim : 1; /**< TIM interrupt
11907 See TIM_REG_ERROR */
11908 uint64_t zip : 1; /**< ZIP interrupt
11910 uint64_t pko : 1; /**< PKO interrupt
11911 See PKO_REG_ERROR */
11912 uint64_t pip : 1; /**< PIP interrupt
11914 uint64_t ipd : 1; /**< IPD interrupt
11916 uint64_t l2c : 1; /**< L2C interrupt
11918 uint64_t pow : 1; /**< POW err interrupt
11920 uint64_t fpa : 1; /**< FPA interrupt
11922 uint64_t iob : 1; /**< IOB interrupt
11924 uint64_t mio : 1; /**< MIO boot interrupt
11925 See MIO_BOOT_ERR */
11926 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
11927 See EMMC interrupt */
11928 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
11930 uint64_t reserved_10_17 : 8;
11931 uint64_t wdog : 10; /**< Per PP watchdog interrupts */
11933 uint64_t wdog : 10;
11934 uint64_t reserved_10_17 : 8;
11955 uint64_t reserved_38_39 : 2;
11956 uint64_t dpi_dma : 1;
11957 uint64_t reserved_41_45 : 5;
11962 uint64_t srio0 : 1;
11963 uint64_t reserved_51_51 : 1;
11965 uint64_t reserved_53_55 : 3;
11967 uint64_t reserved_57_59 : 3;
11968 uint64_t srio2 : 1;
11969 uint64_t srio3 : 1;
11970 uint64_t reserved_62_62 : 1;
11974 struct cvmx_ciu_sum1_ppx_ip3_cn61xx {
11975 #ifdef __BIG_ENDIAN_BITFIELD
11976 uint64_t rst : 1; /**< MIO RST interrupt
11978 uint64_t reserved_53_62 : 10;
11979 uint64_t lmc0 : 1; /**< LMC0 interrupt
11981 uint64_t reserved_50_51 : 2;
11982 uint64_t pem1 : 1; /**< PEM1 interrupt
11983 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
11984 uint64_t pem0 : 1; /**< PEM0 interrupt
11985 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
11986 uint64_t ptp : 1; /**< PTP interrupt
11987 Set when HW decrements MIO_PTP_EVT_CNT to zero */
11988 uint64_t agl : 1; /**< AGL interrupt
11989 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
11990 uint64_t reserved_41_45 : 5;
11991 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
11992 TBD, See DPI DMA instruction completion */
11993 uint64_t reserved_38_39 : 2;
11994 uint64_t agx1 : 1; /**< GMX1 interrupt
11995 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
11996 PCS1_INT*_REG, PCSX1_INT_REG */
11997 uint64_t agx0 : 1; /**< GMX0 interrupt
11998 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
11999 PCS0_INT*_REG, PCSX0_INT_REG */
12000 uint64_t dpi : 1; /**< DPI interrupt
12002 uint64_t sli : 1; /**< SLI interrupt
12003 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
12004 uint64_t usb : 1; /**< USB UCTL0 interrupt
12005 See UCTL0_INT_REG */
12006 uint64_t dfa : 1; /**< DFA interrupt
12008 uint64_t key : 1; /**< KEY interrupt
12010 uint64_t rad : 1; /**< RAD interrupt
12011 See RAD_REG_ERROR */
12012 uint64_t tim : 1; /**< TIM interrupt
12013 See TIM_REG_ERROR */
12014 uint64_t zip : 1; /**< ZIP interrupt
12016 uint64_t pko : 1; /**< PKO interrupt
12017 See PKO_REG_ERROR */
12018 uint64_t pip : 1; /**< PIP interrupt
12020 uint64_t ipd : 1; /**< IPD interrupt
12022 uint64_t l2c : 1; /**< L2C interrupt
12024 uint64_t pow : 1; /**< POW err interrupt
12026 uint64_t fpa : 1; /**< FPA interrupt
12028 uint64_t iob : 1; /**< IOB interrupt
12030 uint64_t mio : 1; /**< MIO boot interrupt
12031 See MIO_BOOT_ERR */
12032 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
12033 See EMMC interrupt */
12034 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt
12036 uint64_t reserved_4_17 : 14;
12037 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
12040 uint64_t reserved_4_17 : 14;
12061 uint64_t reserved_38_39 : 2;
12062 uint64_t dpi_dma : 1;
12063 uint64_t reserved_41_45 : 5;
12068 uint64_t reserved_50_51 : 2;
12070 uint64_t reserved_53_62 : 10;
12074 struct cvmx_ciu_sum1_ppx_ip3_cn66xx {
12075 #ifdef __BIG_ENDIAN_BITFIELD
12076 uint64_t rst : 1; /**< MIO RST interrupt
12078 uint64_t reserved_62_62 : 1;
12079 uint64_t srio3 : 1; /**< SRIO3 interrupt
12080 See SRIO3_INT_REG, SRIO3_INT2_REG */
12081 uint64_t srio2 : 1; /**< SRIO2 interrupt
12082 See SRIO2_INT_REG, SRIO2_INT2_REG */
12083 uint64_t reserved_57_59 : 3;
12084 uint64_t dfm : 1; /**< DFM Interrupt
12085 See DFM_FNT_STAT */
12086 uint64_t reserved_53_55 : 3;
12087 uint64_t lmc0 : 1; /**< LMC0 interrupt
12089 uint64_t reserved_51_51 : 1;
12090 uint64_t srio0 : 1; /**< SRIO0 interrupt
12091 See SRIO0_INT_REG, SRIO0_INT2_REG */
12092 uint64_t pem1 : 1; /**< PEM1 interrupt
12093 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
12094 uint64_t pem0 : 1; /**< PEM0 interrupt
12095 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
12096 uint64_t ptp : 1; /**< PTP interrupt
12097 Set when HW decrements MIO_PTP_EVT_CNT to zero */
12098 uint64_t agl : 1; /**< AGL interrupt
12099 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
12100 uint64_t reserved_38_45 : 8;
12101 uint64_t agx1 : 1; /**< GMX1 interrupt
12102 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
12103 PCS1_INT*_REG, PCSX1_INT_REG */
12104 uint64_t agx0 : 1; /**< GMX0 interrupt
12105 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
12106 PCS0_INT*_REG, PCSX0_INT_REG */
12107 uint64_t dpi : 1; /**< DPI interrupt
12109 uint64_t sli : 1; /**< SLI interrupt
12110 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
12111 uint64_t usb : 1; /**< USB UCTL0 interrupt
12112 See UCTL0_INT_REG */
12113 uint64_t dfa : 1; /**< DFA interrupt
12115 uint64_t key : 1; /**< KEY interrupt
12117 uint64_t rad : 1; /**< RAD interrupt
12118 See RAD_REG_ERROR */
12119 uint64_t tim : 1; /**< TIM interrupt
12120 See TIM_REG_ERROR */
12121 uint64_t zip : 1; /**< ZIP interrupt
12123 uint64_t pko : 1; /**< PKO interrupt
12124 See PKO_REG_ERROR */
12125 uint64_t pip : 1; /**< PIP interrupt
12127 uint64_t ipd : 1; /**< IPD interrupt
12129 uint64_t l2c : 1; /**< L2C interrupt
12131 uint64_t pow : 1; /**< POW err interrupt
12133 uint64_t fpa : 1; /**< FPA interrupt
12135 uint64_t iob : 1; /**< IOB interrupt
12137 uint64_t mio : 1; /**< MIO boot interrupt
12138 See MIO_BOOT_ERR */
12139 uint64_t nand : 1; /**< NAND Flash Controller interrupt
12141 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
12143 uint64_t reserved_10_17 : 8;
12144 uint64_t wdog : 10; /**< 10 watchdog interrupts */
12146 uint64_t wdog : 10;
12147 uint64_t reserved_10_17 : 8;
12168 uint64_t reserved_38_45 : 8;
12173 uint64_t srio0 : 1;
12174 uint64_t reserved_51_51 : 1;
12176 uint64_t reserved_53_55 : 3;
12178 uint64_t reserved_57_59 : 3;
12179 uint64_t srio2 : 1;
12180 uint64_t srio3 : 1;
12181 uint64_t reserved_62_62 : 1;
12185 struct cvmx_ciu_sum1_ppx_ip3_cnf71xx {
12186 #ifdef __BIG_ENDIAN_BITFIELD
12187 uint64_t rst : 1; /**< MIO RST interrupt
12189 uint64_t reserved_53_62 : 10;
12190 uint64_t lmc0 : 1; /**< LMC0 interrupt
12192 uint64_t reserved_50_51 : 2;
12193 uint64_t pem1 : 1; /**< PEM1 interrupt
12194 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
12195 uint64_t pem0 : 1; /**< PEM0 interrupt
12196 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
12197 uint64_t ptp : 1; /**< PTP interrupt
12198 Set when HW decrements MIO_PTP_EVT_CNT to zero */
12199 uint64_t reserved_41_46 : 6;
12200 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
12201 TBD, See DPI DMA instruction completion */
12202 uint64_t reserved_37_39 : 3;
12203 uint64_t agx0 : 1; /**< GMX0 interrupt
12204 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
12205 PCS0_INT*_REG, PCSX0_INT_REG */
12206 uint64_t dpi : 1; /**< DPI interrupt
12208 uint64_t sli : 1; /**< SLI interrupt
12209 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
12210 uint64_t usb : 1; /**< USB UCTL0 interrupt
12211 See UCTL0_INT_REG */
12212 uint64_t reserved_32_32 : 1;
12213 uint64_t key : 1; /**< KEY interrupt
12215 uint64_t rad : 1; /**< RAD interrupt
12216 See RAD_REG_ERROR */
12217 uint64_t tim : 1; /**< TIM interrupt
12218 See TIM_REG_ERROR */
12219 uint64_t reserved_28_28 : 1;
12220 uint64_t pko : 1; /**< PKO interrupt
12221 See PKO_REG_ERROR */
12222 uint64_t pip : 1; /**< PIP interrupt
12224 uint64_t ipd : 1; /**< IPD interrupt
12226 uint64_t l2c : 1; /**< L2C interrupt
12228 uint64_t pow : 1; /**< POW err interrupt
12230 uint64_t fpa : 1; /**< FPA interrupt
12232 uint64_t iob : 1; /**< IOB interrupt
12234 uint64_t mio : 1; /**< MIO boot interrupt
12235 See MIO_BOOT_ERR */
12236 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
12237 See EMMC interrupt */
12238 uint64_t reserved_4_18 : 15;
12239 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
12242 uint64_t reserved_4_18 : 15;
12252 uint64_t reserved_28_28 : 1;
12256 uint64_t reserved_32_32 : 1;
12261 uint64_t reserved_37_39 : 3;
12262 uint64_t dpi_dma : 1;
12263 uint64_t reserved_41_46 : 6;
12267 uint64_t reserved_50_51 : 2;
12269 uint64_t reserved_53_62 : 10;
12274 typedef union cvmx_ciu_sum1_ppx_ip3 cvmx_ciu_sum1_ppx_ip3_t;
12277 * cvmx_ciu_sum1_pp#_ip4
12280 * SUM1 becomes per IPx in o65/6 and afterwards. Only Field <40> DPI_DMA will have
12281 * different value per PP(IP) for $CIU_SUM1_PPx_IPy, and <40> DPI_DMA will always
12282 * be zero for $CIU_SUM1_IOX_INT. All other fields ([63:41] and [39:0]) values are idential for
12283 * different PPs, same value as $CIU_INT_SUM1.
12284 * Write to any IRQ's PTP fields will clear PTP for all IRQ's PTP field.
12286 union cvmx_ciu_sum1_ppx_ip4 {
12288 struct cvmx_ciu_sum1_ppx_ip4_s {
12289 #ifdef __BIG_ENDIAN_BITFIELD
12290 uint64_t rst : 1; /**< MIO RST interrupt
12292 uint64_t reserved_62_62 : 1;
12293 uint64_t srio3 : 1; /**< SRIO3 interrupt
12294 See SRIO3_INT_REG, SRIO3_INT2_REG */
12295 uint64_t srio2 : 1; /**< SRIO2 interrupt
12296 See SRIO2_INT_REG, SRIO2_INT2_REG */
12297 uint64_t reserved_57_59 : 3;
12298 uint64_t dfm : 1; /**< DFM Interrupt
12299 See DFM_FNT_STAT */
12300 uint64_t reserved_53_55 : 3;
12301 uint64_t lmc0 : 1; /**< LMC0 interrupt
12303 uint64_t reserved_51_51 : 1;
12304 uint64_t srio0 : 1; /**< SRIO0 interrupt
12305 See SRIO0_INT_REG, SRIO0_INT2_REG */
12306 uint64_t pem1 : 1; /**< PEM1 interrupt
12307 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
12308 uint64_t pem0 : 1; /**< PEM0 interrupt
12309 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
12310 uint64_t ptp : 1; /**< PTP interrupt
12311 Set when HW decrements MIO_PTP_EVT_CNT to zero */
12312 uint64_t agl : 1; /**< AGL interrupt
12313 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
12314 uint64_t reserved_41_45 : 5;
12315 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
12316 TBD, See DPI DMA instruction completion */
12317 uint64_t reserved_38_39 : 2;
12318 uint64_t agx1 : 1; /**< GMX1 interrupt
12319 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
12320 PCS1_INT*_REG, PCSX1_INT_REG */
12321 uint64_t agx0 : 1; /**< GMX0 interrupt
12322 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
12323 PCS0_INT*_REG, PCSX0_INT_REG */
12324 uint64_t dpi : 1; /**< DPI interrupt
12326 uint64_t sli : 1; /**< SLI interrupt
12327 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
12328 uint64_t usb : 1; /**< USB UCTL0 interrupt
12329 See UCTL0_INT_REG */
12330 uint64_t dfa : 1; /**< DFA interrupt
12332 uint64_t key : 1; /**< KEY interrupt
12334 uint64_t rad : 1; /**< RAD interrupt
12335 See RAD_REG_ERROR */
12336 uint64_t tim : 1; /**< TIM interrupt
12337 See TIM_REG_ERROR */
12338 uint64_t zip : 1; /**< ZIP interrupt
12340 uint64_t pko : 1; /**< PKO interrupt
12341 See PKO_REG_ERROR */
12342 uint64_t pip : 1; /**< PIP interrupt
12344 uint64_t ipd : 1; /**< IPD interrupt
12346 uint64_t l2c : 1; /**< L2C interrupt
12348 uint64_t pow : 1; /**< POW err interrupt
12350 uint64_t fpa : 1; /**< FPA interrupt
12352 uint64_t iob : 1; /**< IOB interrupt
12354 uint64_t mio : 1; /**< MIO boot interrupt
12355 See MIO_BOOT_ERR */
12356 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
12357 See EMMC interrupt */
12358 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
12360 uint64_t reserved_10_17 : 8;
12361 uint64_t wdog : 10; /**< Per PP watchdog interrupts */
12363 uint64_t wdog : 10;
12364 uint64_t reserved_10_17 : 8;
12385 uint64_t reserved_38_39 : 2;
12386 uint64_t dpi_dma : 1;
12387 uint64_t reserved_41_45 : 5;
12392 uint64_t srio0 : 1;
12393 uint64_t reserved_51_51 : 1;
12395 uint64_t reserved_53_55 : 3;
12397 uint64_t reserved_57_59 : 3;
12398 uint64_t srio2 : 1;
12399 uint64_t srio3 : 1;
12400 uint64_t reserved_62_62 : 1;
12404 struct cvmx_ciu_sum1_ppx_ip4_cn61xx {
12405 #ifdef __BIG_ENDIAN_BITFIELD
12406 uint64_t rst : 1; /**< MIO RST interrupt
12408 uint64_t reserved_53_62 : 10;
12409 uint64_t lmc0 : 1; /**< LMC0 interrupt
12411 uint64_t reserved_50_51 : 2;
12412 uint64_t pem1 : 1; /**< PEM1 interrupt
12413 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
12414 uint64_t pem0 : 1; /**< PEM0 interrupt
12415 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
12416 uint64_t ptp : 1; /**< PTP interrupt
12417 Set when HW decrements MIO_PTP_EVT_CNT to zero */
12418 uint64_t agl : 1; /**< AGL interrupt
12419 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
12420 uint64_t reserved_41_45 : 5;
12421 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
12422 TBD, See DPI DMA instruction completion */
12423 uint64_t reserved_38_39 : 2;
12424 uint64_t agx1 : 1; /**< GMX1 interrupt
12425 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
12426 PCS1_INT*_REG, PCSX1_INT_REG */
12427 uint64_t agx0 : 1; /**< GMX0 interrupt
12428 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
12429 PCS0_INT*_REG, PCSX0_INT_REG */
12430 uint64_t dpi : 1; /**< DPI interrupt
12432 uint64_t sli : 1; /**< SLI interrupt
12433 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
12434 uint64_t usb : 1; /**< USB UCTL0 interrupt
12435 See UCTL0_INT_REG */
12436 uint64_t dfa : 1; /**< DFA interrupt
12438 uint64_t key : 1; /**< KEY interrupt
12440 uint64_t rad : 1; /**< RAD interrupt
12441 See RAD_REG_ERROR */
12442 uint64_t tim : 1; /**< TIM interrupt
12443 See TIM_REG_ERROR */
12444 uint64_t zip : 1; /**< ZIP interrupt
12446 uint64_t pko : 1; /**< PKO interrupt
12447 See PKO_REG_ERROR */
12448 uint64_t pip : 1; /**< PIP interrupt
12450 uint64_t ipd : 1; /**< IPD interrupt
12452 uint64_t l2c : 1; /**< L2C interrupt
12454 uint64_t pow : 1; /**< POW err interrupt
12456 uint64_t fpa : 1; /**< FPA interrupt
12458 uint64_t iob : 1; /**< IOB interrupt
12460 uint64_t mio : 1; /**< MIO boot interrupt
12461 See MIO_BOOT_ERR */
12462 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
12463 See EMMC interrupt */
12464 uint64_t mii1 : 1; /**< RGMII/MIX Interface 1 Interrupt
12466 uint64_t reserved_4_17 : 14;
12467 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
12470 uint64_t reserved_4_17 : 14;
12491 uint64_t reserved_38_39 : 2;
12492 uint64_t dpi_dma : 1;
12493 uint64_t reserved_41_45 : 5;
12498 uint64_t reserved_50_51 : 2;
12500 uint64_t reserved_53_62 : 10;
12504 struct cvmx_ciu_sum1_ppx_ip4_cn66xx {
12505 #ifdef __BIG_ENDIAN_BITFIELD
12506 uint64_t rst : 1; /**< MIO RST interrupt
12508 uint64_t reserved_62_62 : 1;
12509 uint64_t srio3 : 1; /**< SRIO3 interrupt
12510 See SRIO3_INT_REG, SRIO3_INT2_REG */
12511 uint64_t srio2 : 1; /**< SRIO2 interrupt
12512 See SRIO2_INT_REG, SRIO2_INT2_REG */
12513 uint64_t reserved_57_59 : 3;
12514 uint64_t dfm : 1; /**< DFM Interrupt
12515 See DFM_FNT_STAT */
12516 uint64_t reserved_53_55 : 3;
12517 uint64_t lmc0 : 1; /**< LMC0 interrupt
12519 uint64_t reserved_51_51 : 1;
12520 uint64_t srio0 : 1; /**< SRIO0 interrupt
12521 See SRIO0_INT_REG, SRIO0_INT2_REG */
12522 uint64_t pem1 : 1; /**< PEM1 interrupt
12523 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
12524 uint64_t pem0 : 1; /**< PEM0 interrupt
12525 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
12526 uint64_t ptp : 1; /**< PTP interrupt
12527 Set when HW decrements MIO_PTP_EVT_CNT to zero */
12528 uint64_t agl : 1; /**< AGL interrupt
12529 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
12530 uint64_t reserved_38_45 : 8;
12531 uint64_t agx1 : 1; /**< GMX1 interrupt
12532 See GMX1_RX*_INT_REG, GMX1_TX_INT_REG,
12533 PCS1_INT*_REG, PCSX1_INT_REG */
12534 uint64_t agx0 : 1; /**< GMX0 interrupt
12535 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
12536 PCS0_INT*_REG, PCSX0_INT_REG */
12537 uint64_t dpi : 1; /**< DPI interrupt
12539 uint64_t sli : 1; /**< SLI interrupt
12540 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
12541 uint64_t usb : 1; /**< USB UCTL0 interrupt
12542 See UCTL0_INT_REG */
12543 uint64_t dfa : 1; /**< DFA interrupt
12545 uint64_t key : 1; /**< KEY interrupt
12547 uint64_t rad : 1; /**< RAD interrupt
12548 See RAD_REG_ERROR */
12549 uint64_t tim : 1; /**< TIM interrupt
12550 See TIM_REG_ERROR */
12551 uint64_t zip : 1; /**< ZIP interrupt
12553 uint64_t pko : 1; /**< PKO interrupt
12554 See PKO_REG_ERROR */
12555 uint64_t pip : 1; /**< PIP interrupt
12557 uint64_t ipd : 1; /**< IPD interrupt
12559 uint64_t l2c : 1; /**< L2C interrupt
12561 uint64_t pow : 1; /**< POW err interrupt
12563 uint64_t fpa : 1; /**< FPA interrupt
12565 uint64_t iob : 1; /**< IOB interrupt
12567 uint64_t mio : 1; /**< MIO boot interrupt
12568 See MIO_BOOT_ERR */
12569 uint64_t nand : 1; /**< NAND Flash Controller interrupt
12571 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt
12573 uint64_t reserved_10_17 : 8;
12574 uint64_t wdog : 10; /**< 10 watchdog interrupts */
12576 uint64_t wdog : 10;
12577 uint64_t reserved_10_17 : 8;
12598 uint64_t reserved_38_45 : 8;
12603 uint64_t srio0 : 1;
12604 uint64_t reserved_51_51 : 1;
12606 uint64_t reserved_53_55 : 3;
12608 uint64_t reserved_57_59 : 3;
12609 uint64_t srio2 : 1;
12610 uint64_t srio3 : 1;
12611 uint64_t reserved_62_62 : 1;
12615 struct cvmx_ciu_sum1_ppx_ip4_cnf71xx {
12616 #ifdef __BIG_ENDIAN_BITFIELD
12617 uint64_t rst : 1; /**< MIO RST interrupt
12619 uint64_t reserved_53_62 : 10;
12620 uint64_t lmc0 : 1; /**< LMC0 interrupt
12622 uint64_t reserved_50_51 : 2;
12623 uint64_t pem1 : 1; /**< PEM1 interrupt
12624 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */
12625 uint64_t pem0 : 1; /**< PEM0 interrupt
12626 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */
12627 uint64_t ptp : 1; /**< PTP interrupt
12628 Set when HW decrements MIO_PTP_EVT_CNT to zero */
12629 uint64_t reserved_41_46 : 6;
12630 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
12631 TBD, See DPI DMA instruction completion */
12632 uint64_t reserved_37_39 : 3;
12633 uint64_t agx0 : 1; /**< GMX0 interrupt
12634 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG,
12635 PCS0_INT*_REG, PCSX0_INT_REG */
12636 uint64_t dpi : 1; /**< DPI interrupt
12638 uint64_t sli : 1; /**< SLI interrupt
12639 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
12640 uint64_t usb : 1; /**< USB UCTL0 interrupt
12641 See UCTL0_INT_REG */
12642 uint64_t reserved_32_32 : 1;
12643 uint64_t key : 1; /**< KEY interrupt
12645 uint64_t rad : 1; /**< RAD interrupt
12646 See RAD_REG_ERROR */
12647 uint64_t tim : 1; /**< TIM interrupt
12648 See TIM_REG_ERROR */
12649 uint64_t reserved_28_28 : 1;
12650 uint64_t pko : 1; /**< PKO interrupt
12651 See PKO_REG_ERROR */
12652 uint64_t pip : 1; /**< PIP interrupt
12654 uint64_t ipd : 1; /**< IPD interrupt
12656 uint64_t l2c : 1; /**< L2C interrupt
12658 uint64_t pow : 1; /**< POW err interrupt
12660 uint64_t fpa : 1; /**< FPA interrupt
12662 uint64_t iob : 1; /**< IOB interrupt
12664 uint64_t mio : 1; /**< MIO boot interrupt
12665 See MIO_BOOT_ERR */
12666 uint64_t nand : 1; /**< EMMC Flash Controller interrupt
12667 See EMMC interrupt */
12668 uint64_t reserved_4_18 : 15;
12669 uint64_t wdog : 4; /**< Per PP watchdog interrupts */
12672 uint64_t reserved_4_18 : 15;
12682 uint64_t reserved_28_28 : 1;
12686 uint64_t reserved_32_32 : 1;
12691 uint64_t reserved_37_39 : 3;
12692 uint64_t dpi_dma : 1;
12693 uint64_t reserved_41_46 : 6;
12697 uint64_t reserved_50_51 : 2;
12699 uint64_t reserved_53_62 : 10;
12704 typedef union cvmx_ciu_sum1_ppx_ip4 cvmx_ciu_sum1_ppx_ip4_t;
12707 * cvmx_ciu_sum2_io#_int
12710 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
12713 union cvmx_ciu_sum2_iox_int {
12715 struct cvmx_ciu_sum2_iox_int_s {
12716 #ifdef __BIG_ENDIAN_BITFIELD
12717 uint64_t reserved_15_63 : 49;
12718 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status
12719 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
12720 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */
12721 uint64_t reserved_10_11 : 2;
12722 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12723 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12724 common for all PP/IRQs, writing '1' to any PP/IRQ
12725 will clear all TIMERx(x=0..9) interrupts.
12726 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12727 are set at the same time, but clearing are based on
12728 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12729 The combination of this field and the
12730 CIU_INT*_SUM0/4[TIMER] field implement all 10
12731 CIU_TIM* interrupts. */
12732 uint64_t reserved_0_3 : 4;
12734 uint64_t reserved_0_3 : 4;
12735 uint64_t timer : 6;
12736 uint64_t reserved_10_11 : 2;
12738 uint64_t endor : 2;
12739 uint64_t reserved_15_63 : 49;
12742 struct cvmx_ciu_sum2_iox_int_cn61xx {
12743 #ifdef __BIG_ENDIAN_BITFIELD
12744 uint64_t reserved_10_63 : 54;
12745 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12746 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12747 common for all PP/IRQs, writing '1' to any PP/IRQ
12748 will clear all TIMERx(x=0..9) interrupts.
12749 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12750 are set at the same time, but clearing are based on
12751 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12752 The combination of this field and the
12753 CIU_INT*_SUM0/4[TIMER] field implement all 10
12754 CIU_TIM* interrupts. */
12755 uint64_t reserved_0_3 : 4;
12757 uint64_t reserved_0_3 : 4;
12758 uint64_t timer : 6;
12759 uint64_t reserved_10_63 : 54;
12762 struct cvmx_ciu_sum2_iox_int_cn61xx cn66xx;
12763 struct cvmx_ciu_sum2_iox_int_s cnf71xx;
12765 typedef union cvmx_ciu_sum2_iox_int cvmx_ciu_sum2_iox_int_t;
12768 * cvmx_ciu_sum2_pp#_ip2
12771 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
12774 union cvmx_ciu_sum2_ppx_ip2 {
12776 struct cvmx_ciu_sum2_ppx_ip2_s {
12777 #ifdef __BIG_ENDIAN_BITFIELD
12778 uint64_t reserved_15_63 : 49;
12779 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status
12780 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
12781 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */
12782 uint64_t reserved_10_11 : 2;
12783 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12784 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12785 common for all PP/IRQs, writing '1' to any PP/IRQ
12786 will clear all TIMERx(x=0..9) interrupts.
12787 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12788 are set at the same time, but clearing are based on
12789 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12790 The combination of this field and the
12791 CIU_INT*_SUM0/4[TIMER] field implement all 10
12792 CIU_TIM* interrupts. */
12793 uint64_t reserved_0_3 : 4;
12795 uint64_t reserved_0_3 : 4;
12796 uint64_t timer : 6;
12797 uint64_t reserved_10_11 : 2;
12799 uint64_t endor : 2;
12800 uint64_t reserved_15_63 : 49;
12803 struct cvmx_ciu_sum2_ppx_ip2_cn61xx {
12804 #ifdef __BIG_ENDIAN_BITFIELD
12805 uint64_t reserved_10_63 : 54;
12806 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12807 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12808 common for all PP/IRQs, writing '1' to any PP/IRQ
12809 will clear all TIMERx(x=0..9) interrupts.
12810 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12811 are set at the same time, but clearing are based on
12812 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12813 The combination of this field and the
12814 CIU_INT*_SUM0/4[TIMER] field implement all 10
12815 CIU_TIM* interrupts. */
12816 uint64_t reserved_0_3 : 4;
12818 uint64_t reserved_0_3 : 4;
12819 uint64_t timer : 6;
12820 uint64_t reserved_10_63 : 54;
12823 struct cvmx_ciu_sum2_ppx_ip2_cn61xx cn66xx;
12824 struct cvmx_ciu_sum2_ppx_ip2_s cnf71xx;
12826 typedef union cvmx_ciu_sum2_ppx_ip2 cvmx_ciu_sum2_ppx_ip2_t;
12829 * cvmx_ciu_sum2_pp#_ip3
12832 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
12835 union cvmx_ciu_sum2_ppx_ip3 {
12837 struct cvmx_ciu_sum2_ppx_ip3_s {
12838 #ifdef __BIG_ENDIAN_BITFIELD
12839 uint64_t reserved_15_63 : 49;
12840 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status
12841 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
12842 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */
12843 uint64_t reserved_10_11 : 2;
12844 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12845 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12846 common for all PP/IRQs, writing '1' to any PP/IRQ
12847 will clear all TIMERx(x=0..9) interrupts.
12848 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12849 are set at the same time, but clearing are based on
12850 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12851 The combination of this field and the
12852 CIU_INT*_SUM0/4[TIMER] field implement all 10
12853 CIU_TIM* interrupts. */
12854 uint64_t reserved_0_3 : 4;
12856 uint64_t reserved_0_3 : 4;
12857 uint64_t timer : 6;
12858 uint64_t reserved_10_11 : 2;
12860 uint64_t endor : 2;
12861 uint64_t reserved_15_63 : 49;
12864 struct cvmx_ciu_sum2_ppx_ip3_cn61xx {
12865 #ifdef __BIG_ENDIAN_BITFIELD
12866 uint64_t reserved_10_63 : 54;
12867 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12868 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12869 common for all PP/IRQs, writing '1' to any PP/IRQ
12870 will clear all TIMERx(x=0..9) interrupts.
12871 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12872 are set at the same time, but clearing are based on
12873 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12874 The combination of this field and the
12875 CIU_INT*_SUM0/4[TIMER] field implement all 10
12876 CIU_TIM* interrupts. */
12877 uint64_t reserved_0_3 : 4;
12879 uint64_t reserved_0_3 : 4;
12880 uint64_t timer : 6;
12881 uint64_t reserved_10_63 : 54;
12884 struct cvmx_ciu_sum2_ppx_ip3_cn61xx cn66xx;
12885 struct cvmx_ciu_sum2_ppx_ip3_s cnf71xx;
12887 typedef union cvmx_ciu_sum2_ppx_ip3 cvmx_ciu_sum2_ppx_ip3_t;
12890 * cvmx_ciu_sum2_pp#_ip4
12893 * These SUM2 CSR's did not exist prior to pass 1.2. CIU_TIM4-9 did not exist prior to pass 1.2.
12896 union cvmx_ciu_sum2_ppx_ip4 {
12898 struct cvmx_ciu_sum2_ppx_ip4_s {
12899 #ifdef __BIG_ENDIAN_BITFIELD
12900 uint64_t reserved_15_63 : 49;
12901 uint64_t endor : 2; /**< ENDOR PHY interrupts, see ENDOR interrupt status
12902 register ENDOR_RSTCLK_INTR0(1)_STATUS for details */
12903 uint64_t eoi : 1; /**< EOI rsl interrupt, see EOI_INT_STA */
12904 uint64_t reserved_10_11 : 2;
12905 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12906 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12907 common for all PP/IRQs, writing '1' to any PP/IRQ
12908 will clear all TIMERx(x=0..9) interrupts.
12909 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12910 are set at the same time, but clearing are based on
12911 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12912 The combination of this field and the
12913 CIU_INT*_SUM0/4[TIMER] field implement all 10
12914 CIU_TIM* interrupts. */
12915 uint64_t reserved_0_3 : 4;
12917 uint64_t reserved_0_3 : 4;
12918 uint64_t timer : 6;
12919 uint64_t reserved_10_11 : 2;
12921 uint64_t endor : 2;
12922 uint64_t reserved_15_63 : 49;
12925 struct cvmx_ciu_sum2_ppx_ip4_cn61xx {
12926 #ifdef __BIG_ENDIAN_BITFIELD
12927 uint64_t reserved_10_63 : 54;
12928 uint64_t timer : 6; /**< General timer 4-9 interrupts.
12929 When CIU_TIM_MULTI_CAST[EN] == 0, this interrupt is
12930 common for all PP/IRQs, writing '1' to any PP/IRQ
12931 will clear all TIMERx(x=0..9) interrupts.
12932 When CIU_TIM_MULTI_CAST[EN] == 1, TIMERx(x=0..9)
12933 are set at the same time, but clearing are based on
12934 per cnMIPS core. See CIU_TIM_MULTI_CAST for detail.
12935 The combination of this field and the
12936 CIU_INT*_SUM0/4[TIMER] field implement all 10
12937 CIU_TIM* interrupts. */
12938 uint64_t reserved_0_3 : 4;
12940 uint64_t reserved_0_3 : 4;
12941 uint64_t timer : 6;
12942 uint64_t reserved_10_63 : 54;
12945 struct cvmx_ciu_sum2_ppx_ip4_cn61xx cn66xx;
12946 struct cvmx_ciu_sum2_ppx_ip4_s cnf71xx;
12948 typedef union cvmx_ciu_sum2_ppx_ip4 cvmx_ciu_sum2_ppx_ip4_t;
12954 * CIU_TIM4-9 did not exist prior to pass 1.2
12957 union cvmx_ciu_timx {
12959 struct cvmx_ciu_timx_s {
12960 #ifdef __BIG_ENDIAN_BITFIELD
12961 uint64_t reserved_37_63 : 27;
12962 uint64_t one_shot : 1; /**< One-shot mode */
12963 uint64_t len : 36; /**< Timeout length in core clock cycles
12964 Periodic interrupts will occur every LEN+1 core
12965 clock cycles when ONE_SHOT==0
12966 Timer disabled when LEN==0 */
12969 uint64_t one_shot : 1;
12970 uint64_t reserved_37_63 : 27;
12973 struct cvmx_ciu_timx_s cn30xx;
12974 struct cvmx_ciu_timx_s cn31xx;
12975 struct cvmx_ciu_timx_s cn38xx;
12976 struct cvmx_ciu_timx_s cn38xxp2;
12977 struct cvmx_ciu_timx_s cn50xx;
12978 struct cvmx_ciu_timx_s cn52xx;
12979 struct cvmx_ciu_timx_s cn52xxp1;
12980 struct cvmx_ciu_timx_s cn56xx;
12981 struct cvmx_ciu_timx_s cn56xxp1;
12982 struct cvmx_ciu_timx_s cn58xx;
12983 struct cvmx_ciu_timx_s cn58xxp1;
12984 struct cvmx_ciu_timx_s cn61xx;
12985 struct cvmx_ciu_timx_s cn63xx;
12986 struct cvmx_ciu_timx_s cn63xxp1;
12987 struct cvmx_ciu_timx_s cn66xx;
12988 struct cvmx_ciu_timx_s cn68xx;
12989 struct cvmx_ciu_timx_s cn68xxp1;
12990 struct cvmx_ciu_timx_s cnf71xx;
12992 typedef union cvmx_ciu_timx cvmx_ciu_timx_t;
12995 * cvmx_ciu_tim_multi_cast
12998 * This register does not exist prior to pass 1.2 silicon. Those earlier chip passes operate as if
13001 union cvmx_ciu_tim_multi_cast {
13003 struct cvmx_ciu_tim_multi_cast_s {
13004 #ifdef __BIG_ENDIAN_BITFIELD
13005 uint64_t reserved_1_63 : 63;
13006 uint64_t en : 1; /**< General Timer Interrupt Mutli-Cast mode:
13007 - 0: Timer interrupt is common for all PP/IRQs.
13008 - 1: Timer interrupts are set at the same time for
13009 all PP/IRQs, but interrupt clearings can/need
13010 to be done Individually based on per cnMIPS core.
13011 Timer interrupts for IOs (X=32,33) will always use
13012 common interrupts. Clear any of the I/O interrupts
13013 will clear the common interrupt. */
13016 uint64_t reserved_1_63 : 63;
13019 struct cvmx_ciu_tim_multi_cast_s cn61xx;
13020 struct cvmx_ciu_tim_multi_cast_s cn66xx;
13021 struct cvmx_ciu_tim_multi_cast_s cnf71xx;
13023 typedef union cvmx_ciu_tim_multi_cast cvmx_ciu_tim_multi_cast_t;
13028 union cvmx_ciu_wdogx {
13030 struct cvmx_ciu_wdogx_s {
13031 #ifdef __BIG_ENDIAN_BITFIELD
13032 uint64_t reserved_46_63 : 18;
13033 uint64_t gstopen : 1; /**< GSTOPEN */
13034 uint64_t dstop : 1; /**< DSTOP */
13035 uint64_t cnt : 24; /**< Number of 256-cycle intervals until next watchdog
13036 expiration. Cleared on write to associated
13037 CIU_PP_POKE register. */
13038 uint64_t len : 16; /**< Watchdog time expiration length
13039 The 16 bits of LEN represent the most significant
13040 bits of a 24 bit decrementer that decrements
13042 LEN must be set > 0 */
13043 uint64_t state : 2; /**< Watchdog state
13044 number of watchdog time expirations since last
13045 PP poke. Cleared on write to associated
13046 CIU_PP_POKE register. */
13047 uint64_t mode : 2; /**< Watchdog mode
13050 2 = Interrupt + NMI
13051 3 = Interrupt + NMI + Soft-Reset */
13054 uint64_t state : 2;
13057 uint64_t dstop : 1;
13058 uint64_t gstopen : 1;
13059 uint64_t reserved_46_63 : 18;
13062 struct cvmx_ciu_wdogx_s cn30xx;
13063 struct cvmx_ciu_wdogx_s cn31xx;
13064 struct cvmx_ciu_wdogx_s cn38xx;
13065 struct cvmx_ciu_wdogx_s cn38xxp2;
13066 struct cvmx_ciu_wdogx_s cn50xx;
13067 struct cvmx_ciu_wdogx_s cn52xx;
13068 struct cvmx_ciu_wdogx_s cn52xxp1;
13069 struct cvmx_ciu_wdogx_s cn56xx;
13070 struct cvmx_ciu_wdogx_s cn56xxp1;
13071 struct cvmx_ciu_wdogx_s cn58xx;
13072 struct cvmx_ciu_wdogx_s cn58xxp1;
13073 struct cvmx_ciu_wdogx_s cn61xx;
13074 struct cvmx_ciu_wdogx_s cn63xx;
13075 struct cvmx_ciu_wdogx_s cn63xxp1;
13076 struct cvmx_ciu_wdogx_s cn66xx;
13077 struct cvmx_ciu_wdogx_s cn68xx;
13078 struct cvmx_ciu_wdogx_s cn68xxp1;
13079 struct cvmx_ciu_wdogx_s cnf71xx;
13081 typedef union cvmx_ciu_wdogx cvmx_ciu_wdogx_t;