1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_CIU2_DEFS_H__
53 #define __CVMX_CIU2_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_CIU2_ACK_IOX_INT(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
60 cvmx_warn("CVMX_CIU2_ACK_IOX_INT(%lu) is invalid on this chip\n", block_id);
61 return CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull;
64 #define CVMX_CIU2_ACK_IOX_INT(block_id) (CVMX_ADD_IO_SEG(0x00010701080C0800ull) + ((block_id) & 1) * 0x200000ull)
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 static inline uint64_t CVMX_CIU2_ACK_PPX_IP2(unsigned long block_id)
70 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
71 cvmx_warn("CVMX_CIU2_ACK_PPX_IP2(%lu) is invalid on this chip\n", block_id);
72 return CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull;
75 #define CVMX_CIU2_ACK_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0000ull) + ((block_id) & 31) * 0x200000ull)
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 static inline uint64_t CVMX_CIU2_ACK_PPX_IP3(unsigned long block_id)
81 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
82 cvmx_warn("CVMX_CIU2_ACK_PPX_IP3(%lu) is invalid on this chip\n", block_id);
83 return CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull;
86 #define CVMX_CIU2_ACK_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0200ull) + ((block_id) & 31) * 0x200000ull)
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 static inline uint64_t CVMX_CIU2_ACK_PPX_IP4(unsigned long block_id)
92 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
93 cvmx_warn("CVMX_CIU2_ACK_PPX_IP4(%lu) is invalid on this chip\n", block_id);
94 return CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull;
97 #define CVMX_CIU2_ACK_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C0400ull) + ((block_id) & 31) * 0x200000ull)
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 static inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO(unsigned long block_id)
103 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
104 cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id);
105 return CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull;
108 #define CVMX_CIU2_EN_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108097800ull) + ((block_id) & 1) * 0x200000ull)
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 static inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO_W1C(unsigned long block_id)
114 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
115 cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
116 return CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull;
119 #define CVMX_CIU2_EN_IOX_INT_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B7800ull) + ((block_id) & 1) * 0x200000ull)
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 static inline uint64_t CVMX_CIU2_EN_IOX_INT_GPIO_W1S(unsigned long block_id)
125 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
126 cvmx_warn("CVMX_CIU2_EN_IOX_INT_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
127 return CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull;
130 #define CVMX_CIU2_EN_IOX_INT_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A7800ull) + ((block_id) & 1) * 0x200000ull)
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 static inline uint64_t CVMX_CIU2_EN_IOX_INT_IO(unsigned long block_id)
136 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
137 cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO(%lu) is invalid on this chip\n", block_id);
138 return CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull;
141 #define CVMX_CIU2_EN_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108094800ull) + ((block_id) & 1) * 0x200000ull)
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 static inline uint64_t CVMX_CIU2_EN_IOX_INT_IO_W1C(unsigned long block_id)
147 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
148 cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO_W1C(%lu) is invalid on this chip\n", block_id);
149 return CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull;
152 #define CVMX_CIU2_EN_IOX_INT_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B4800ull) + ((block_id) & 1) * 0x200000ull)
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
155 static inline uint64_t CVMX_CIU2_EN_IOX_INT_IO_W1S(unsigned long block_id)
158 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
159 cvmx_warn("CVMX_CIU2_EN_IOX_INT_IO_W1S(%lu) is invalid on this chip\n", block_id);
160 return CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull;
163 #define CVMX_CIU2_EN_IOX_INT_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A4800ull) + ((block_id) & 1) * 0x200000ull)
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
166 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX(unsigned long block_id)
169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
170 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX(%lu) is invalid on this chip\n", block_id);
171 return CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull;
174 #define CVMX_CIU2_EN_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108098800ull) + ((block_id) & 1) * 0x200000ull)
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
177 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX_W1C(unsigned long block_id)
180 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
181 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
182 return CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull;
185 #define CVMX_CIU2_EN_IOX_INT_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B8800ull) + ((block_id) & 1) * 0x200000ull)
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MBOX_W1S(unsigned long block_id)
191 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
192 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
193 return CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull;
196 #define CVMX_CIU2_EN_IOX_INT_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A8800ull) + ((block_id) & 1) * 0x200000ull)
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
199 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM(unsigned long block_id)
202 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
203 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id);
204 return CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull;
207 #define CVMX_CIU2_EN_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108095800ull) + ((block_id) & 1) * 0x200000ull)
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
210 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM_W1C(unsigned long block_id)
213 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
214 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM_W1C(%lu) is invalid on this chip\n", block_id);
215 return CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull;
218 #define CVMX_CIU2_EN_IOX_INT_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B5800ull) + ((block_id) & 1) * 0x200000ull)
220 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
221 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MEM_W1S(unsigned long block_id)
224 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
225 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MEM_W1S(%lu) is invalid on this chip\n", block_id);
226 return CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull;
229 #define CVMX_CIU2_EN_IOX_INT_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A5800ull) + ((block_id) & 1) * 0x200000ull)
231 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
232 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO(unsigned long block_id)
235 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
236 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id);
237 return CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull;
240 #define CVMX_CIU2_EN_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108093800ull) + ((block_id) & 1) * 0x200000ull)
242 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
243 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO_W1C(unsigned long block_id)
246 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
247 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO_W1C(%lu) is invalid on this chip\n", block_id);
248 return CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull;
251 #define CVMX_CIU2_EN_IOX_INT_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B3800ull) + ((block_id) & 1) * 0x200000ull)
253 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
254 static inline uint64_t CVMX_CIU2_EN_IOX_INT_MIO_W1S(unsigned long block_id)
257 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
258 cvmx_warn("CVMX_CIU2_EN_IOX_INT_MIO_W1S(%lu) is invalid on this chip\n", block_id);
259 return CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull;
262 #define CVMX_CIU2_EN_IOX_INT_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A3800ull) + ((block_id) & 1) * 0x200000ull)
264 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
265 static inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT(unsigned long block_id)
268 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
269 cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id);
270 return CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull;
273 #define CVMX_CIU2_EN_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108096800ull) + ((block_id) & 1) * 0x200000ull)
275 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
276 static inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT_W1C(unsigned long block_id)
279 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
280 cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT_W1C(%lu) is invalid on this chip\n", block_id);
281 return CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull;
284 #define CVMX_CIU2_EN_IOX_INT_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B6800ull) + ((block_id) & 1) * 0x200000ull)
286 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
287 static inline uint64_t CVMX_CIU2_EN_IOX_INT_PKT_W1S(unsigned long block_id)
290 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
291 cvmx_warn("CVMX_CIU2_EN_IOX_INT_PKT_W1S(%lu) is invalid on this chip\n", block_id);
292 return CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull;
295 #define CVMX_CIU2_EN_IOX_INT_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A6800ull) + ((block_id) & 1) * 0x200000ull)
297 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
298 static inline uint64_t CVMX_CIU2_EN_IOX_INT_RML(unsigned long block_id)
301 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
302 cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML(%lu) is invalid on this chip\n", block_id);
303 return CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull;
306 #define CVMX_CIU2_EN_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108092800ull) + ((block_id) & 1) * 0x200000ull)
308 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
309 static inline uint64_t CVMX_CIU2_EN_IOX_INT_RML_W1C(unsigned long block_id)
312 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
313 cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML_W1C(%lu) is invalid on this chip\n", block_id);
314 return CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull;
317 #define CVMX_CIU2_EN_IOX_INT_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B2800ull) + ((block_id) & 1) * 0x200000ull)
319 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
320 static inline uint64_t CVMX_CIU2_EN_IOX_INT_RML_W1S(unsigned long block_id)
323 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
324 cvmx_warn("CVMX_CIU2_EN_IOX_INT_RML_W1S(%lu) is invalid on this chip\n", block_id);
325 return CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull;
328 #define CVMX_CIU2_EN_IOX_INT_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A2800ull) + ((block_id) & 1) * 0x200000ull)
330 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
331 static inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG(unsigned long block_id)
334 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
335 cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id);
336 return CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull;
339 #define CVMX_CIU2_EN_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108091800ull) + ((block_id) & 1) * 0x200000ull)
341 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
342 static inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG_W1C(unsigned long block_id)
345 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
346 cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
347 return CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull;
350 #define CVMX_CIU2_EN_IOX_INT_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B1800ull) + ((block_id) & 1) * 0x200000ull)
352 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
353 static inline uint64_t CVMX_CIU2_EN_IOX_INT_WDOG_W1S(unsigned long block_id)
356 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
357 cvmx_warn("CVMX_CIU2_EN_IOX_INT_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
358 return CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull;
361 #define CVMX_CIU2_EN_IOX_INT_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A1800ull) + ((block_id) & 1) * 0x200000ull)
363 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
364 static inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ(unsigned long block_id)
367 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
368 cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id);
369 return CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull;
372 #define CVMX_CIU2_EN_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108090800ull) + ((block_id) & 1) * 0x200000ull)
374 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
375 static inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(unsigned long block_id)
378 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
379 cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
380 return CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull;
383 #define CVMX_CIU2_EN_IOX_INT_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701080B0800ull) + ((block_id) & 1) * 0x200000ull)
385 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
386 static inline uint64_t CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(unsigned long block_id)
389 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
390 cvmx_warn("CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
391 return CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull;
394 #define CVMX_CIU2_EN_IOX_INT_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701080A0800ull) + ((block_id) & 1) * 0x200000ull)
396 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
397 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO(unsigned long block_id)
400 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
401 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id);
402 return CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull;
405 #define CVMX_CIU2_EN_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097000ull) + ((block_id) & 31) * 0x200000ull)
407 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
408 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(unsigned long block_id)
411 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
412 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
413 return CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull;
416 #define CVMX_CIU2_EN_PPX_IP2_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7000ull) + ((block_id) & 31) * 0x200000ull)
418 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
419 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(unsigned long block_id)
422 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
423 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
424 return CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull;
427 #define CVMX_CIU2_EN_PPX_IP2_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7000ull) + ((block_id) & 31) * 0x200000ull)
429 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
430 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO(unsigned long block_id)
433 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
434 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id);
435 return CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull;
438 #define CVMX_CIU2_EN_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094000ull) + ((block_id) & 31) * 0x200000ull)
440 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
441 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO_W1C(unsigned long block_id)
444 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
445 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO_W1C(%lu) is invalid on this chip\n", block_id);
446 return CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull;
449 #define CVMX_CIU2_EN_PPX_IP2_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4000ull) + ((block_id) & 31) * 0x200000ull)
451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
452 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_IO_W1S(unsigned long block_id)
455 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
456 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_IO_W1S(%lu) is invalid on this chip\n", block_id);
457 return CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull;
460 #define CVMX_CIU2_EN_PPX_IP2_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4000ull) + ((block_id) & 31) * 0x200000ull)
462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
463 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX(unsigned long block_id)
466 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
467 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX(%lu) is invalid on this chip\n", block_id);
468 return CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull;
471 #define CVMX_CIU2_EN_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098000ull) + ((block_id) & 31) * 0x200000ull)
473 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
474 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(unsigned long block_id)
477 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
478 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
479 return CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull;
482 #define CVMX_CIU2_EN_PPX_IP2_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8000ull) + ((block_id) & 31) * 0x200000ull)
484 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
485 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(unsigned long block_id)
488 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
489 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
490 return CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull;
493 #define CVMX_CIU2_EN_PPX_IP2_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8000ull) + ((block_id) & 31) * 0x200000ull)
495 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
496 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM(unsigned long block_id)
499 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
500 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id);
501 return CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull;
504 #define CVMX_CIU2_EN_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095000ull) + ((block_id) & 31) * 0x200000ull)
506 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
507 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM_W1C(unsigned long block_id)
510 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
511 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM_W1C(%lu) is invalid on this chip\n", block_id);
512 return CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull;
515 #define CVMX_CIU2_EN_PPX_IP2_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5000ull) + ((block_id) & 31) * 0x200000ull)
517 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
518 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MEM_W1S(unsigned long block_id)
521 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
522 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MEM_W1S(%lu) is invalid on this chip\n", block_id);
523 return CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull;
526 #define CVMX_CIU2_EN_PPX_IP2_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5000ull) + ((block_id) & 31) * 0x200000ull)
528 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
529 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO(unsigned long block_id)
532 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
533 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id);
534 return CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull;
537 #define CVMX_CIU2_EN_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093000ull) + ((block_id) & 31) * 0x200000ull)
539 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
540 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO_W1C(unsigned long block_id)
543 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
544 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO_W1C(%lu) is invalid on this chip\n", block_id);
545 return CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull;
548 #define CVMX_CIU2_EN_PPX_IP2_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3000ull) + ((block_id) & 31) * 0x200000ull)
550 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
551 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_MIO_W1S(unsigned long block_id)
554 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
555 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_MIO_W1S(%lu) is invalid on this chip\n", block_id);
556 return CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull;
559 #define CVMX_CIU2_EN_PPX_IP2_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3000ull) + ((block_id) & 31) * 0x200000ull)
561 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
562 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT(unsigned long block_id)
565 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
566 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id);
567 return CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull;
570 #define CVMX_CIU2_EN_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096000ull) + ((block_id) & 31) * 0x200000ull)
572 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
573 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT_W1C(unsigned long block_id)
576 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
577 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT_W1C(%lu) is invalid on this chip\n", block_id);
578 return CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull;
581 #define CVMX_CIU2_EN_PPX_IP2_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6000ull) + ((block_id) & 31) * 0x200000ull)
583 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
584 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_PKT_W1S(unsigned long block_id)
587 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
588 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_PKT_W1S(%lu) is invalid on this chip\n", block_id);
589 return CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull;
592 #define CVMX_CIU2_EN_PPX_IP2_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6000ull) + ((block_id) & 31) * 0x200000ull)
594 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
595 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML(unsigned long block_id)
598 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
599 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id);
600 return CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull;
603 #define CVMX_CIU2_EN_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092000ull) + ((block_id) & 31) * 0x200000ull)
605 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
606 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML_W1C(unsigned long block_id)
609 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
610 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML_W1C(%lu) is invalid on this chip\n", block_id);
611 return CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull;
614 #define CVMX_CIU2_EN_PPX_IP2_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2000ull) + ((block_id) & 31) * 0x200000ull)
616 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
617 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_RML_W1S(unsigned long block_id)
620 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
621 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_RML_W1S(%lu) is invalid on this chip\n", block_id);
622 return CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull;
625 #define CVMX_CIU2_EN_PPX_IP2_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2000ull) + ((block_id) & 31) * 0x200000ull)
627 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
628 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG(unsigned long block_id)
631 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
632 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id);
633 return CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull;
636 #define CVMX_CIU2_EN_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091000ull) + ((block_id) & 31) * 0x200000ull)
638 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
639 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(unsigned long block_id)
642 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
643 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
644 return CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull;
647 #define CVMX_CIU2_EN_PPX_IP2_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1000ull) + ((block_id) & 31) * 0x200000ull)
649 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
650 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(unsigned long block_id)
653 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
654 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
655 return CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull;
658 #define CVMX_CIU2_EN_PPX_IP2_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1000ull) + ((block_id) & 31) * 0x200000ull)
660 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
661 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ(unsigned long block_id)
664 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
665 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id);
666 return CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull;
669 #define CVMX_CIU2_EN_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090000ull) + ((block_id) & 31) * 0x200000ull)
671 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
672 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(unsigned long block_id)
675 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
676 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
677 return CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull;
680 #define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0000ull) + ((block_id) & 31) * 0x200000ull)
682 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
683 static inline uint64_t CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(unsigned long block_id)
686 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
687 cvmx_warn("CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
688 return CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull;
691 #define CVMX_CIU2_EN_PPX_IP2_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0000ull) + ((block_id) & 31) * 0x200000ull)
693 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
694 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO(unsigned long block_id)
697 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
698 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id);
699 return CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull;
702 #define CVMX_CIU2_EN_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097200ull) + ((block_id) & 31) * 0x200000ull)
704 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
705 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(unsigned long block_id)
708 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
709 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
710 return CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull;
713 #define CVMX_CIU2_EN_PPX_IP3_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7200ull) + ((block_id) & 31) * 0x200000ull)
715 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
716 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(unsigned long block_id)
719 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
720 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
721 return CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull;
724 #define CVMX_CIU2_EN_PPX_IP3_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7200ull) + ((block_id) & 31) * 0x200000ull)
726 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
727 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO(unsigned long block_id)
730 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
731 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id);
732 return CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull;
735 #define CVMX_CIU2_EN_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094200ull) + ((block_id) & 31) * 0x200000ull)
737 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
738 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO_W1C(unsigned long block_id)
741 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
742 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO_W1C(%lu) is invalid on this chip\n", block_id);
743 return CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull;
746 #define CVMX_CIU2_EN_PPX_IP3_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4200ull) + ((block_id) & 31) * 0x200000ull)
748 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
749 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_IO_W1S(unsigned long block_id)
752 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
753 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_IO_W1S(%lu) is invalid on this chip\n", block_id);
754 return CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull;
757 #define CVMX_CIU2_EN_PPX_IP3_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4200ull) + ((block_id) & 31) * 0x200000ull)
759 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
760 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX(unsigned long block_id)
763 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
764 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX(%lu) is invalid on this chip\n", block_id);
765 return CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull;
768 #define CVMX_CIU2_EN_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098200ull) + ((block_id) & 31) * 0x200000ull)
770 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
771 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(unsigned long block_id)
774 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
775 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
776 return CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull;
779 #define CVMX_CIU2_EN_PPX_IP3_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8200ull) + ((block_id) & 31) * 0x200000ull)
781 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
782 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(unsigned long block_id)
785 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
786 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
787 return CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull;
790 #define CVMX_CIU2_EN_PPX_IP3_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8200ull) + ((block_id) & 31) * 0x200000ull)
792 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
793 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM(unsigned long block_id)
796 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
797 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id);
798 return CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull;
801 #define CVMX_CIU2_EN_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095200ull) + ((block_id) & 31) * 0x200000ull)
803 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
804 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM_W1C(unsigned long block_id)
807 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
808 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM_W1C(%lu) is invalid on this chip\n", block_id);
809 return CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull;
812 #define CVMX_CIU2_EN_PPX_IP3_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5200ull) + ((block_id) & 31) * 0x200000ull)
814 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
815 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MEM_W1S(unsigned long block_id)
818 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
819 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MEM_W1S(%lu) is invalid on this chip\n", block_id);
820 return CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull;
823 #define CVMX_CIU2_EN_PPX_IP3_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5200ull) + ((block_id) & 31) * 0x200000ull)
825 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
826 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO(unsigned long block_id)
829 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
830 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id);
831 return CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull;
834 #define CVMX_CIU2_EN_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093200ull) + ((block_id) & 31) * 0x200000ull)
836 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
837 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO_W1C(unsigned long block_id)
840 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
841 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO_W1C(%lu) is invalid on this chip\n", block_id);
842 return CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull;
845 #define CVMX_CIU2_EN_PPX_IP3_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3200ull) + ((block_id) & 31) * 0x200000ull)
847 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
848 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_MIO_W1S(unsigned long block_id)
851 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
852 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_MIO_W1S(%lu) is invalid on this chip\n", block_id);
853 return CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull;
856 #define CVMX_CIU2_EN_PPX_IP3_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3200ull) + ((block_id) & 31) * 0x200000ull)
858 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
859 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT(unsigned long block_id)
862 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
863 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id);
864 return CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull;
867 #define CVMX_CIU2_EN_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096200ull) + ((block_id) & 31) * 0x200000ull)
869 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
870 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT_W1C(unsigned long block_id)
873 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
874 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT_W1C(%lu) is invalid on this chip\n", block_id);
875 return CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull;
878 #define CVMX_CIU2_EN_PPX_IP3_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6200ull) + ((block_id) & 31) * 0x200000ull)
880 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
881 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_PKT_W1S(unsigned long block_id)
884 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
885 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_PKT_W1S(%lu) is invalid on this chip\n", block_id);
886 return CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull;
889 #define CVMX_CIU2_EN_PPX_IP3_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6200ull) + ((block_id) & 31) * 0x200000ull)
891 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
892 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML(unsigned long block_id)
895 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
896 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id);
897 return CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull;
900 #define CVMX_CIU2_EN_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092200ull) + ((block_id) & 31) * 0x200000ull)
902 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
903 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML_W1C(unsigned long block_id)
906 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
907 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML_W1C(%lu) is invalid on this chip\n", block_id);
908 return CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull;
911 #define CVMX_CIU2_EN_PPX_IP3_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2200ull) + ((block_id) & 31) * 0x200000ull)
913 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
914 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_RML_W1S(unsigned long block_id)
917 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
918 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_RML_W1S(%lu) is invalid on this chip\n", block_id);
919 return CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull;
922 #define CVMX_CIU2_EN_PPX_IP3_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2200ull) + ((block_id) & 31) * 0x200000ull)
924 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
925 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG(unsigned long block_id)
928 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
929 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id);
930 return CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull;
933 #define CVMX_CIU2_EN_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091200ull) + ((block_id) & 31) * 0x200000ull)
935 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
936 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(unsigned long block_id)
939 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
940 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
941 return CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull;
944 #define CVMX_CIU2_EN_PPX_IP3_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1200ull) + ((block_id) & 31) * 0x200000ull)
946 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
947 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(unsigned long block_id)
950 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
951 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
952 return CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull;
955 #define CVMX_CIU2_EN_PPX_IP3_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1200ull) + ((block_id) & 31) * 0x200000ull)
957 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
958 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ(unsigned long block_id)
961 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
962 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id);
963 return CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull;
966 #define CVMX_CIU2_EN_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090200ull) + ((block_id) & 31) * 0x200000ull)
968 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
969 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(unsigned long block_id)
972 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
973 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
974 return CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull;
977 #define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0200ull) + ((block_id) & 31) * 0x200000ull)
979 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
980 static inline uint64_t CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(unsigned long block_id)
983 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
984 cvmx_warn("CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
985 return CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull;
988 #define CVMX_CIU2_EN_PPX_IP3_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0200ull) + ((block_id) & 31) * 0x200000ull)
990 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
991 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO(unsigned long block_id)
994 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
995 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id);
996 return CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull;
999 #define CVMX_CIU2_EN_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100097400ull) + ((block_id) & 31) * 0x200000ull)
1001 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1002 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(unsigned long block_id)
1005 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1006 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(%lu) is invalid on this chip\n", block_id);
1007 return CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull;
1010 #define CVMX_CIU2_EN_PPX_IP4_GPIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B7400ull) + ((block_id) & 31) * 0x200000ull)
1012 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1013 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(unsigned long block_id)
1016 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1017 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(%lu) is invalid on this chip\n", block_id);
1018 return CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull;
1021 #define CVMX_CIU2_EN_PPX_IP4_GPIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A7400ull) + ((block_id) & 31) * 0x200000ull)
1023 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1024 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO(unsigned long block_id)
1027 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1028 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id);
1029 return CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull;
1032 #define CVMX_CIU2_EN_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100094400ull) + ((block_id) & 31) * 0x200000ull)
1034 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1035 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO_W1C(unsigned long block_id)
1038 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1039 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO_W1C(%lu) is invalid on this chip\n", block_id);
1040 return CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull;
1043 #define CVMX_CIU2_EN_PPX_IP4_IO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B4400ull) + ((block_id) & 31) * 0x200000ull)
1045 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1046 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_IO_W1S(unsigned long block_id)
1049 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1050 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_IO_W1S(%lu) is invalid on this chip\n", block_id);
1051 return CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull;
1054 #define CVMX_CIU2_EN_PPX_IP4_IO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A4400ull) + ((block_id) & 31) * 0x200000ull)
1056 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1057 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX(unsigned long block_id)
1060 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1061 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX(%lu) is invalid on this chip\n", block_id);
1062 return CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull;
1065 #define CVMX_CIU2_EN_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100098400ull) + ((block_id) & 31) * 0x200000ull)
1067 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1068 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(unsigned long block_id)
1071 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1072 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(%lu) is invalid on this chip\n", block_id);
1073 return CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull;
1076 #define CVMX_CIU2_EN_PPX_IP4_MBOX_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B8400ull) + ((block_id) & 31) * 0x200000ull)
1078 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1079 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(unsigned long block_id)
1082 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1083 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(%lu) is invalid on this chip\n", block_id);
1084 return CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull;
1087 #define CVMX_CIU2_EN_PPX_IP4_MBOX_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A8400ull) + ((block_id) & 31) * 0x200000ull)
1089 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1090 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM(unsigned long block_id)
1093 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1094 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id);
1095 return CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull;
1098 #define CVMX_CIU2_EN_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100095400ull) + ((block_id) & 31) * 0x200000ull)
1100 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1101 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM_W1C(unsigned long block_id)
1104 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1105 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM_W1C(%lu) is invalid on this chip\n", block_id);
1106 return CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull;
1109 #define CVMX_CIU2_EN_PPX_IP4_MEM_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B5400ull) + ((block_id) & 31) * 0x200000ull)
1111 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1112 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MEM_W1S(unsigned long block_id)
1115 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1116 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MEM_W1S(%lu) is invalid on this chip\n", block_id);
1117 return CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull;
1120 #define CVMX_CIU2_EN_PPX_IP4_MEM_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A5400ull) + ((block_id) & 31) * 0x200000ull)
1122 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1123 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO(unsigned long block_id)
1126 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1127 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id);
1128 return CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull;
1131 #define CVMX_CIU2_EN_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100093400ull) + ((block_id) & 31) * 0x200000ull)
1133 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1134 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO_W1C(unsigned long block_id)
1137 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1138 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO_W1C(%lu) is invalid on this chip\n", block_id);
1139 return CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull;
1142 #define CVMX_CIU2_EN_PPX_IP4_MIO_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B3400ull) + ((block_id) & 31) * 0x200000ull)
1144 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1145 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_MIO_W1S(unsigned long block_id)
1148 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1149 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_MIO_W1S(%lu) is invalid on this chip\n", block_id);
1150 return CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull;
1153 #define CVMX_CIU2_EN_PPX_IP4_MIO_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A3400ull) + ((block_id) & 31) * 0x200000ull)
1155 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1156 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT(unsigned long block_id)
1159 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1160 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id);
1161 return CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull;
1164 #define CVMX_CIU2_EN_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100096400ull) + ((block_id) & 31) * 0x200000ull)
1166 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1167 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT_W1C(unsigned long block_id)
1170 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1171 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT_W1C(%lu) is invalid on this chip\n", block_id);
1172 return CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull;
1175 #define CVMX_CIU2_EN_PPX_IP4_PKT_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B6400ull) + ((block_id) & 31) * 0x200000ull)
1177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1178 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_PKT_W1S(unsigned long block_id)
1181 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1182 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_PKT_W1S(%lu) is invalid on this chip\n", block_id);
1183 return CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull;
1186 #define CVMX_CIU2_EN_PPX_IP4_PKT_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A6400ull) + ((block_id) & 31) * 0x200000ull)
1188 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1189 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML(unsigned long block_id)
1192 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1193 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id);
1194 return CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull;
1197 #define CVMX_CIU2_EN_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100092400ull) + ((block_id) & 31) * 0x200000ull)
1199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1200 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML_W1C(unsigned long block_id)
1203 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1204 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML_W1C(%lu) is invalid on this chip\n", block_id);
1205 return CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull;
1208 #define CVMX_CIU2_EN_PPX_IP4_RML_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B2400ull) + ((block_id) & 31) * 0x200000ull)
1210 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1211 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_RML_W1S(unsigned long block_id)
1214 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1215 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_RML_W1S(%lu) is invalid on this chip\n", block_id);
1216 return CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull;
1219 #define CVMX_CIU2_EN_PPX_IP4_RML_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A2400ull) + ((block_id) & 31) * 0x200000ull)
1221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1222 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG(unsigned long block_id)
1225 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1226 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id);
1227 return CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull;
1230 #define CVMX_CIU2_EN_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100091400ull) + ((block_id) & 31) * 0x200000ull)
1232 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1233 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(unsigned long block_id)
1236 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1237 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(%lu) is invalid on this chip\n", block_id);
1238 return CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull;
1241 #define CVMX_CIU2_EN_PPX_IP4_WDOG_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B1400ull) + ((block_id) & 31) * 0x200000ull)
1243 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1244 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(unsigned long block_id)
1247 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1248 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(%lu) is invalid on this chip\n", block_id);
1249 return CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull;
1252 #define CVMX_CIU2_EN_PPX_IP4_WDOG_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A1400ull) + ((block_id) & 31) * 0x200000ull)
1254 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1255 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ(unsigned long block_id)
1258 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1259 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id);
1260 return CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull;
1263 #define CVMX_CIU2_EN_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100090400ull) + ((block_id) & 31) * 0x200000ull)
1265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1266 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(unsigned long block_id)
1269 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1270 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(%lu) is invalid on this chip\n", block_id);
1271 return CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull;
1274 #define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1C(block_id) (CVMX_ADD_IO_SEG(0x00010701000B0400ull) + ((block_id) & 31) * 0x200000ull)
1276 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1277 static inline uint64_t CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(unsigned long block_id)
1280 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1281 cvmx_warn("CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(%lu) is invalid on this chip\n", block_id);
1282 return CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull;
1285 #define CVMX_CIU2_EN_PPX_IP4_WRKQ_W1S(block_id) (CVMX_ADD_IO_SEG(0x00010701000A0400ull) + ((block_id) & 31) * 0x200000ull)
1287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1288 #define CVMX_CIU2_INTR_CIU_READY CVMX_CIU2_INTR_CIU_READY_FUNC()
1289 static inline uint64_t CVMX_CIU2_INTR_CIU_READY_FUNC(void)
1291 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
1292 cvmx_warn("CVMX_CIU2_INTR_CIU_READY not supported on this chip\n");
1293 return CVMX_ADD_IO_SEG(0x0001070100102008ull);
1296 #define CVMX_CIU2_INTR_CIU_READY (CVMX_ADD_IO_SEG(0x0001070100102008ull))
1298 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1299 #define CVMX_CIU2_INTR_RAM_ECC_CTL CVMX_CIU2_INTR_RAM_ECC_CTL_FUNC()
1300 static inline uint64_t CVMX_CIU2_INTR_RAM_ECC_CTL_FUNC(void)
1302 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
1303 cvmx_warn("CVMX_CIU2_INTR_RAM_ECC_CTL not supported on this chip\n");
1304 return CVMX_ADD_IO_SEG(0x0001070100102010ull);
1307 #define CVMX_CIU2_INTR_RAM_ECC_CTL (CVMX_ADD_IO_SEG(0x0001070100102010ull))
1309 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1310 #define CVMX_CIU2_INTR_RAM_ECC_ST CVMX_CIU2_INTR_RAM_ECC_ST_FUNC()
1311 static inline uint64_t CVMX_CIU2_INTR_RAM_ECC_ST_FUNC(void)
1313 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
1314 cvmx_warn("CVMX_CIU2_INTR_RAM_ECC_ST not supported on this chip\n");
1315 return CVMX_ADD_IO_SEG(0x0001070100102018ull);
1318 #define CVMX_CIU2_INTR_RAM_ECC_ST (CVMX_ADD_IO_SEG(0x0001070100102018ull))
1320 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1321 #define CVMX_CIU2_INTR_SLOWDOWN CVMX_CIU2_INTR_SLOWDOWN_FUNC()
1322 static inline uint64_t CVMX_CIU2_INTR_SLOWDOWN_FUNC(void)
1324 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
1325 cvmx_warn("CVMX_CIU2_INTR_SLOWDOWN not supported on this chip\n");
1326 return CVMX_ADD_IO_SEG(0x0001070100102000ull);
1329 #define CVMX_CIU2_INTR_SLOWDOWN (CVMX_ADD_IO_SEG(0x0001070100102000ull))
1331 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1332 static inline uint64_t CVMX_CIU2_MSIRED_PPX_IP2(unsigned long block_id)
1335 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1336 cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP2(%lu) is invalid on this chip\n", block_id);
1337 return CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull;
1340 #define CVMX_CIU2_MSIRED_PPX_IP2(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1000ull) + ((block_id) & 31) * 0x200000ull)
1342 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1343 static inline uint64_t CVMX_CIU2_MSIRED_PPX_IP3(unsigned long block_id)
1346 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1347 cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP3(%lu) is invalid on this chip\n", block_id);
1348 return CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull;
1351 #define CVMX_CIU2_MSIRED_PPX_IP3(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1200ull) + ((block_id) & 31) * 0x200000ull)
1353 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1354 static inline uint64_t CVMX_CIU2_MSIRED_PPX_IP4(unsigned long block_id)
1357 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1358 cvmx_warn("CVMX_CIU2_MSIRED_PPX_IP4(%lu) is invalid on this chip\n", block_id);
1359 return CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull;
1362 #define CVMX_CIU2_MSIRED_PPX_IP4(block_id) (CVMX_ADD_IO_SEG(0x00010701000C1400ull) + ((block_id) & 31) * 0x200000ull)
1364 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1365 static inline uint64_t CVMX_CIU2_MSI_RCVX(unsigned long offset)
1368 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255)))))
1369 cvmx_warn("CVMX_CIU2_MSI_RCVX(%lu) is invalid on this chip\n", offset);
1370 return CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8;
1373 #define CVMX_CIU2_MSI_RCVX(offset) (CVMX_ADD_IO_SEG(0x00010701000C2000ull) + ((offset) & 255) * 8)
1375 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1376 static inline uint64_t CVMX_CIU2_MSI_SELX(unsigned long offset)
1379 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 255)))))
1380 cvmx_warn("CVMX_CIU2_MSI_SELX(%lu) is invalid on this chip\n", offset);
1381 return CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8;
1384 #define CVMX_CIU2_MSI_SELX(offset) (CVMX_ADD_IO_SEG(0x00010701000C3000ull) + ((offset) & 255) * 8)
1386 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1387 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_GPIO(unsigned long block_id)
1390 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1391 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id);
1392 return CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull;
1395 #define CVMX_CIU2_RAW_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108047800ull) + ((block_id) & 1) * 0x200000ull)
1397 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1398 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_IO(unsigned long block_id)
1401 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1402 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_IO(%lu) is invalid on this chip\n", block_id);
1403 return CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull;
1406 #define CVMX_CIU2_RAW_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108044800ull) + ((block_id) & 1) * 0x200000ull)
1408 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1409 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_MEM(unsigned long block_id)
1412 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1413 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id);
1414 return CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull;
1417 #define CVMX_CIU2_RAW_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108045800ull) + ((block_id) & 1) * 0x200000ull)
1419 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1420 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_MIO(unsigned long block_id)
1423 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1424 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id);
1425 return CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull;
1428 #define CVMX_CIU2_RAW_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108043800ull) + ((block_id) & 1) * 0x200000ull)
1430 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1431 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_PKT(unsigned long block_id)
1434 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1435 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id);
1436 return CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull;
1439 #define CVMX_CIU2_RAW_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108046800ull) + ((block_id) & 1) * 0x200000ull)
1441 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1442 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_RML(unsigned long block_id)
1445 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1446 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_RML(%lu) is invalid on this chip\n", block_id);
1447 return CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull;
1450 #define CVMX_CIU2_RAW_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108042800ull) + ((block_id) & 1) * 0x200000ull)
1452 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1453 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_WDOG(unsigned long block_id)
1456 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1457 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id);
1458 return CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull;
1461 #define CVMX_CIU2_RAW_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108041800ull) + ((block_id) & 1) * 0x200000ull)
1463 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1464 static inline uint64_t CVMX_CIU2_RAW_IOX_INT_WRKQ(unsigned long block_id)
1467 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1468 cvmx_warn("CVMX_CIU2_RAW_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id);
1469 return CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull;
1472 #define CVMX_CIU2_RAW_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108040800ull) + ((block_id) & 1) * 0x200000ull)
1474 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1475 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_GPIO(unsigned long block_id)
1478 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1479 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id);
1480 return CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull;
1483 #define CVMX_CIU2_RAW_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047000ull) + ((block_id) & 31) * 0x200000ull)
1485 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1486 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_IO(unsigned long block_id)
1489 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1490 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id);
1491 return CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull;
1494 #define CVMX_CIU2_RAW_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044000ull) + ((block_id) & 31) * 0x200000ull)
1496 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1497 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_MEM(unsigned long block_id)
1500 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1501 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id);
1502 return CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull;
1505 #define CVMX_CIU2_RAW_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045000ull) + ((block_id) & 31) * 0x200000ull)
1507 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1508 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_MIO(unsigned long block_id)
1511 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1512 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id);
1513 return CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull;
1516 #define CVMX_CIU2_RAW_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043000ull) + ((block_id) & 31) * 0x200000ull)
1518 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1519 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_PKT(unsigned long block_id)
1522 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1523 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id);
1524 return CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull;
1527 #define CVMX_CIU2_RAW_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046000ull) + ((block_id) & 31) * 0x200000ull)
1529 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1530 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_RML(unsigned long block_id)
1533 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1534 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id);
1535 return CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull;
1538 #define CVMX_CIU2_RAW_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042000ull) + ((block_id) & 31) * 0x200000ull)
1540 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1541 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_WDOG(unsigned long block_id)
1544 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1545 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id);
1546 return CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull;
1549 #define CVMX_CIU2_RAW_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041000ull) + ((block_id) & 31) * 0x200000ull)
1551 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1552 static inline uint64_t CVMX_CIU2_RAW_PPX_IP2_WRKQ(unsigned long block_id)
1555 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1556 cvmx_warn("CVMX_CIU2_RAW_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id);
1557 return CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull;
1560 #define CVMX_CIU2_RAW_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040000ull) + ((block_id) & 31) * 0x200000ull)
1562 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1563 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_GPIO(unsigned long block_id)
1566 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1567 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id);
1568 return CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull;
1571 #define CVMX_CIU2_RAW_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047200ull) + ((block_id) & 31) * 0x200000ull)
1573 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1574 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_IO(unsigned long block_id)
1577 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1578 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id);
1579 return CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull;
1582 #define CVMX_CIU2_RAW_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044200ull) + ((block_id) & 31) * 0x200000ull)
1584 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1585 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_MEM(unsigned long block_id)
1588 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1589 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id);
1590 return CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull;
1593 #define CVMX_CIU2_RAW_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045200ull) + ((block_id) & 31) * 0x200000ull)
1595 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1596 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_MIO(unsigned long block_id)
1599 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1600 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id);
1601 return CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull;
1604 #define CVMX_CIU2_RAW_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043200ull) + ((block_id) & 31) * 0x200000ull)
1606 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1607 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_PKT(unsigned long block_id)
1610 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1611 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id);
1612 return CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull;
1615 #define CVMX_CIU2_RAW_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046200ull) + ((block_id) & 31) * 0x200000ull)
1617 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1618 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_RML(unsigned long block_id)
1621 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1622 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id);
1623 return CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull;
1626 #define CVMX_CIU2_RAW_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042200ull) + ((block_id) & 31) * 0x200000ull)
1628 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1629 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_WDOG(unsigned long block_id)
1632 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1633 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id);
1634 return CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull;
1637 #define CVMX_CIU2_RAW_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041200ull) + ((block_id) & 31) * 0x200000ull)
1639 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1640 static inline uint64_t CVMX_CIU2_RAW_PPX_IP3_WRKQ(unsigned long block_id)
1643 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1644 cvmx_warn("CVMX_CIU2_RAW_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id);
1645 return CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull;
1648 #define CVMX_CIU2_RAW_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040200ull) + ((block_id) & 31) * 0x200000ull)
1650 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1651 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_GPIO(unsigned long block_id)
1654 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1655 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id);
1656 return CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull;
1659 #define CVMX_CIU2_RAW_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100047400ull) + ((block_id) & 31) * 0x200000ull)
1661 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1662 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_IO(unsigned long block_id)
1665 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1666 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id);
1667 return CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull;
1670 #define CVMX_CIU2_RAW_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100044400ull) + ((block_id) & 31) * 0x200000ull)
1672 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1673 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_MEM(unsigned long block_id)
1676 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1677 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id);
1678 return CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull;
1681 #define CVMX_CIU2_RAW_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100045400ull) + ((block_id) & 31) * 0x200000ull)
1683 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1684 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_MIO(unsigned long block_id)
1687 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1688 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id);
1689 return CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull;
1692 #define CVMX_CIU2_RAW_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100043400ull) + ((block_id) & 31) * 0x200000ull)
1694 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1695 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_PKT(unsigned long block_id)
1698 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1699 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id);
1700 return CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull;
1703 #define CVMX_CIU2_RAW_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100046400ull) + ((block_id) & 31) * 0x200000ull)
1705 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1706 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_RML(unsigned long block_id)
1709 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1710 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id);
1711 return CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull;
1714 #define CVMX_CIU2_RAW_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100042400ull) + ((block_id) & 31) * 0x200000ull)
1716 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1717 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_WDOG(unsigned long block_id)
1720 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1721 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id);
1722 return CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull;
1725 #define CVMX_CIU2_RAW_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100041400ull) + ((block_id) & 31) * 0x200000ull)
1727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1728 static inline uint64_t CVMX_CIU2_RAW_PPX_IP4_WRKQ(unsigned long block_id)
1731 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1732 cvmx_warn("CVMX_CIU2_RAW_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id);
1733 return CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull;
1736 #define CVMX_CIU2_RAW_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100040400ull) + ((block_id) & 31) * 0x200000ull)
1738 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1739 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_GPIO(unsigned long block_id)
1742 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1743 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_GPIO(%lu) is invalid on this chip\n", block_id);
1744 return CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull;
1747 #define CVMX_CIU2_SRC_IOX_INT_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108087800ull) + ((block_id) & 1) * 0x200000ull)
1749 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1750 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_IO(unsigned long block_id)
1753 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1754 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_IO(%lu) is invalid on this chip\n", block_id);
1755 return CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull;
1758 #define CVMX_CIU2_SRC_IOX_INT_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070108084800ull) + ((block_id) & 1) * 0x200000ull)
1760 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1761 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_MBOX(unsigned long block_id)
1764 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1765 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MBOX(%lu) is invalid on this chip\n", block_id);
1766 return CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull;
1769 #define CVMX_CIU2_SRC_IOX_INT_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070108088800ull) + ((block_id) & 1) * 0x200000ull)
1771 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1772 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_MEM(unsigned long block_id)
1775 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1776 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MEM(%lu) is invalid on this chip\n", block_id);
1777 return CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull;
1780 #define CVMX_CIU2_SRC_IOX_INT_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070108085800ull) + ((block_id) & 1) * 0x200000ull)
1782 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1783 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_MIO(unsigned long block_id)
1786 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1787 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_MIO(%lu) is invalid on this chip\n", block_id);
1788 return CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull;
1791 #define CVMX_CIU2_SRC_IOX_INT_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070108083800ull) + ((block_id) & 1) * 0x200000ull)
1793 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1794 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_PKT(unsigned long block_id)
1797 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1798 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_PKT(%lu) is invalid on this chip\n", block_id);
1799 return CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull;
1802 #define CVMX_CIU2_SRC_IOX_INT_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070108086800ull) + ((block_id) & 1) * 0x200000ull)
1804 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1805 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_RML(unsigned long block_id)
1808 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1809 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_RML(%lu) is invalid on this chip\n", block_id);
1810 return CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull;
1813 #define CVMX_CIU2_SRC_IOX_INT_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070108082800ull) + ((block_id) & 1) * 0x200000ull)
1815 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1816 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_WDOG(unsigned long block_id)
1819 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1820 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_WDOG(%lu) is invalid on this chip\n", block_id);
1821 return CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull;
1824 #define CVMX_CIU2_SRC_IOX_INT_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070108081800ull) + ((block_id) & 1) * 0x200000ull)
1826 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1827 static inline uint64_t CVMX_CIU2_SRC_IOX_INT_WRKQ(unsigned long block_id)
1830 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1)))))
1831 cvmx_warn("CVMX_CIU2_SRC_IOX_INT_WRKQ(%lu) is invalid on this chip\n", block_id);
1832 return CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull;
1835 #define CVMX_CIU2_SRC_IOX_INT_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070108080800ull) + ((block_id) & 1) * 0x200000ull)
1837 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1838 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_GPIO(unsigned long block_id)
1841 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1842 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_GPIO(%lu) is invalid on this chip\n", block_id);
1843 return CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull;
1846 #define CVMX_CIU2_SRC_PPX_IP2_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087000ull) + ((block_id) & 31) * 0x200000ull)
1848 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1849 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_IO(unsigned long block_id)
1852 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1853 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_IO(%lu) is invalid on this chip\n", block_id);
1854 return CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull;
1857 #define CVMX_CIU2_SRC_PPX_IP2_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084000ull) + ((block_id) & 31) * 0x200000ull)
1859 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1860 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MBOX(unsigned long block_id)
1863 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1864 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MBOX(%lu) is invalid on this chip\n", block_id);
1865 return CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull;
1868 #define CVMX_CIU2_SRC_PPX_IP2_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088000ull) + ((block_id) & 31) * 0x200000ull)
1870 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1871 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MEM(unsigned long block_id)
1874 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1875 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MEM(%lu) is invalid on this chip\n", block_id);
1876 return CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull;
1879 #define CVMX_CIU2_SRC_PPX_IP2_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085000ull) + ((block_id) & 31) * 0x200000ull)
1881 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1882 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_MIO(unsigned long block_id)
1885 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1886 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_MIO(%lu) is invalid on this chip\n", block_id);
1887 return CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull;
1890 #define CVMX_CIU2_SRC_PPX_IP2_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083000ull) + ((block_id) & 31) * 0x200000ull)
1892 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1893 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_PKT(unsigned long block_id)
1896 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1897 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_PKT(%lu) is invalid on this chip\n", block_id);
1898 return CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull;
1901 #define CVMX_CIU2_SRC_PPX_IP2_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086000ull) + ((block_id) & 31) * 0x200000ull)
1903 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1904 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_RML(unsigned long block_id)
1907 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1908 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_RML(%lu) is invalid on this chip\n", block_id);
1909 return CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull;
1912 #define CVMX_CIU2_SRC_PPX_IP2_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082000ull) + ((block_id) & 31) * 0x200000ull)
1914 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1915 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_WDOG(unsigned long block_id)
1918 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1919 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_WDOG(%lu) is invalid on this chip\n", block_id);
1920 return CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull;
1923 #define CVMX_CIU2_SRC_PPX_IP2_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081000ull) + ((block_id) & 31) * 0x200000ull)
1925 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1926 static inline uint64_t CVMX_CIU2_SRC_PPX_IP2_WRKQ(unsigned long block_id)
1929 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1930 cvmx_warn("CVMX_CIU2_SRC_PPX_IP2_WRKQ(%lu) is invalid on this chip\n", block_id);
1931 return CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull;
1934 #define CVMX_CIU2_SRC_PPX_IP2_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080000ull) + ((block_id) & 31) * 0x200000ull)
1936 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1937 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_GPIO(unsigned long block_id)
1940 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1941 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_GPIO(%lu) is invalid on this chip\n", block_id);
1942 return CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull;
1945 #define CVMX_CIU2_SRC_PPX_IP3_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087200ull) + ((block_id) & 31) * 0x200000ull)
1947 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1948 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_IO(unsigned long block_id)
1951 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1952 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_IO(%lu) is invalid on this chip\n", block_id);
1953 return CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull;
1956 #define CVMX_CIU2_SRC_PPX_IP3_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084200ull) + ((block_id) & 31) * 0x200000ull)
1958 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1959 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MBOX(unsigned long block_id)
1962 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1963 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MBOX(%lu) is invalid on this chip\n", block_id);
1964 return CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull;
1967 #define CVMX_CIU2_SRC_PPX_IP3_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088200ull) + ((block_id) & 31) * 0x200000ull)
1969 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1970 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MEM(unsigned long block_id)
1973 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1974 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MEM(%lu) is invalid on this chip\n", block_id);
1975 return CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull;
1978 #define CVMX_CIU2_SRC_PPX_IP3_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085200ull) + ((block_id) & 31) * 0x200000ull)
1980 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1981 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_MIO(unsigned long block_id)
1984 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1985 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_MIO(%lu) is invalid on this chip\n", block_id);
1986 return CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull;
1989 #define CVMX_CIU2_SRC_PPX_IP3_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083200ull) + ((block_id) & 31) * 0x200000ull)
1991 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1992 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_PKT(unsigned long block_id)
1995 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
1996 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_PKT(%lu) is invalid on this chip\n", block_id);
1997 return CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull;
2000 #define CVMX_CIU2_SRC_PPX_IP3_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086200ull) + ((block_id) & 31) * 0x200000ull)
2002 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2003 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_RML(unsigned long block_id)
2006 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2007 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_RML(%lu) is invalid on this chip\n", block_id);
2008 return CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull;
2011 #define CVMX_CIU2_SRC_PPX_IP3_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082200ull) + ((block_id) & 31) * 0x200000ull)
2013 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2014 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_WDOG(unsigned long block_id)
2017 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2018 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_WDOG(%lu) is invalid on this chip\n", block_id);
2019 return CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull;
2022 #define CVMX_CIU2_SRC_PPX_IP3_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081200ull) + ((block_id) & 31) * 0x200000ull)
2024 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2025 static inline uint64_t CVMX_CIU2_SRC_PPX_IP3_WRKQ(unsigned long block_id)
2028 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2029 cvmx_warn("CVMX_CIU2_SRC_PPX_IP3_WRKQ(%lu) is invalid on this chip\n", block_id);
2030 return CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull;
2033 #define CVMX_CIU2_SRC_PPX_IP3_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080200ull) + ((block_id) & 31) * 0x200000ull)
2035 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2036 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_GPIO(unsigned long block_id)
2039 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2040 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_GPIO(%lu) is invalid on this chip\n", block_id);
2041 return CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull;
2044 #define CVMX_CIU2_SRC_PPX_IP4_GPIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100087400ull) + ((block_id) & 31) * 0x200000ull)
2046 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2047 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_IO(unsigned long block_id)
2050 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2051 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_IO(%lu) is invalid on this chip\n", block_id);
2052 return CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull;
2055 #define CVMX_CIU2_SRC_PPX_IP4_IO(block_id) (CVMX_ADD_IO_SEG(0x0001070100084400ull) + ((block_id) & 31) * 0x200000ull)
2057 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2058 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MBOX(unsigned long block_id)
2061 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2062 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MBOX(%lu) is invalid on this chip\n", block_id);
2063 return CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull;
2066 #define CVMX_CIU2_SRC_PPX_IP4_MBOX(block_id) (CVMX_ADD_IO_SEG(0x0001070100088400ull) + ((block_id) & 31) * 0x200000ull)
2068 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2069 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MEM(unsigned long block_id)
2072 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2073 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MEM(%lu) is invalid on this chip\n", block_id);
2074 return CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull;
2077 #define CVMX_CIU2_SRC_PPX_IP4_MEM(block_id) (CVMX_ADD_IO_SEG(0x0001070100085400ull) + ((block_id) & 31) * 0x200000ull)
2079 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2080 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_MIO(unsigned long block_id)
2083 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2084 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_MIO(%lu) is invalid on this chip\n", block_id);
2085 return CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull;
2088 #define CVMX_CIU2_SRC_PPX_IP4_MIO(block_id) (CVMX_ADD_IO_SEG(0x0001070100083400ull) + ((block_id) & 31) * 0x200000ull)
2090 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2091 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_PKT(unsigned long block_id)
2094 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2095 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_PKT(%lu) is invalid on this chip\n", block_id);
2096 return CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull;
2099 #define CVMX_CIU2_SRC_PPX_IP4_PKT(block_id) (CVMX_ADD_IO_SEG(0x0001070100086400ull) + ((block_id) & 31) * 0x200000ull)
2101 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2102 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_RML(unsigned long block_id)
2105 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2106 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_RML(%lu) is invalid on this chip\n", block_id);
2107 return CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull;
2110 #define CVMX_CIU2_SRC_PPX_IP4_RML(block_id) (CVMX_ADD_IO_SEG(0x0001070100082400ull) + ((block_id) & 31) * 0x200000ull)
2112 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2113 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_WDOG(unsigned long block_id)
2116 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2117 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_WDOG(%lu) is invalid on this chip\n", block_id);
2118 return CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull;
2121 #define CVMX_CIU2_SRC_PPX_IP4_WDOG(block_id) (CVMX_ADD_IO_SEG(0x0001070100081400ull) + ((block_id) & 31) * 0x200000ull)
2123 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2124 static inline uint64_t CVMX_CIU2_SRC_PPX_IP4_WRKQ(unsigned long block_id)
2127 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 31)))))
2128 cvmx_warn("CVMX_CIU2_SRC_PPX_IP4_WRKQ(%lu) is invalid on this chip\n", block_id);
2129 return CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull;
2132 #define CVMX_CIU2_SRC_PPX_IP4_WRKQ(block_id) (CVMX_ADD_IO_SEG(0x0001070100080400ull) + ((block_id) & 31) * 0x200000ull)
2134 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2135 static inline uint64_t CVMX_CIU2_SUM_IOX_INT(unsigned long offset)
2138 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
2139 cvmx_warn("CVMX_CIU2_SUM_IOX_INT(%lu) is invalid on this chip\n", offset);
2140 return CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8;
2143 #define CVMX_CIU2_SUM_IOX_INT(offset) (CVMX_ADD_IO_SEG(0x0001070100000800ull) + ((offset) & 1) * 8)
2145 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2146 static inline uint64_t CVMX_CIU2_SUM_PPX_IP2(unsigned long offset)
2149 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
2150 cvmx_warn("CVMX_CIU2_SUM_PPX_IP2(%lu) is invalid on this chip\n", offset);
2151 return CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8;
2154 #define CVMX_CIU2_SUM_PPX_IP2(offset) (CVMX_ADD_IO_SEG(0x0001070100000000ull) + ((offset) & 31) * 8)
2156 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2157 static inline uint64_t CVMX_CIU2_SUM_PPX_IP3(unsigned long offset)
2160 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
2161 cvmx_warn("CVMX_CIU2_SUM_PPX_IP3(%lu) is invalid on this chip\n", offset);
2162 return CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8;
2165 #define CVMX_CIU2_SUM_PPX_IP3(offset) (CVMX_ADD_IO_SEG(0x0001070100000200ull) + ((offset) & 31) * 8)
2167 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2168 static inline uint64_t CVMX_CIU2_SUM_PPX_IP4(unsigned long offset)
2171 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
2172 cvmx_warn("CVMX_CIU2_SUM_PPX_IP4(%lu) is invalid on this chip\n", offset);
2173 return CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8;
2176 #define CVMX_CIU2_SUM_PPX_IP4(offset) (CVMX_ADD_IO_SEG(0x0001070100000400ull) + ((offset) & 31) * 8)
2180 * cvmx_ciu2_ack_io#_int
2182 union cvmx_ciu2_ack_iox_int {
2184 struct cvmx_ciu2_ack_iox_int_s {
2185 #ifdef __BIG_ENDIAN_BITFIELD
2186 uint64_t reserved_1_63 : 63;
2187 uint64_t ack : 1; /**< Read to clear the corresponding interrupt to
2188 PP/IO. Without this read the interrupt will not
2189 deassert until the next CIU interrupt scan, up to
2193 uint64_t reserved_1_63 : 63;
2196 struct cvmx_ciu2_ack_iox_int_s cn68xx;
2197 struct cvmx_ciu2_ack_iox_int_s cn68xxp1;
2199 typedef union cvmx_ciu2_ack_iox_int cvmx_ciu2_ack_iox_int_t;
2202 * cvmx_ciu2_ack_pp#_ip2
2204 * CIU2_ACK_PPX_IPx (Pass 2)
2207 union cvmx_ciu2_ack_ppx_ip2 {
2209 struct cvmx_ciu2_ack_ppx_ip2_s {
2210 #ifdef __BIG_ENDIAN_BITFIELD
2211 uint64_t reserved_1_63 : 63;
2212 uint64_t ack : 1; /**< Read to clear the corresponding interrupt to
2213 PP/IO. Without this read the interrupt will not
2214 deassert until the next CIU interrupt scan, up to
2218 uint64_t reserved_1_63 : 63;
2221 struct cvmx_ciu2_ack_ppx_ip2_s cn68xx;
2222 struct cvmx_ciu2_ack_ppx_ip2_s cn68xxp1;
2224 typedef union cvmx_ciu2_ack_ppx_ip2 cvmx_ciu2_ack_ppx_ip2_t;
2227 * cvmx_ciu2_ack_pp#_ip3
2229 union cvmx_ciu2_ack_ppx_ip3 {
2231 struct cvmx_ciu2_ack_ppx_ip3_s {
2232 #ifdef __BIG_ENDIAN_BITFIELD
2233 uint64_t reserved_1_63 : 63;
2234 uint64_t ack : 1; /**< Read to clear the corresponding interrupt to
2235 PP/IO. Without this read the interrupt will not
2236 deassert until the next CIU interrupt scan, up to
2240 uint64_t reserved_1_63 : 63;
2243 struct cvmx_ciu2_ack_ppx_ip3_s cn68xx;
2244 struct cvmx_ciu2_ack_ppx_ip3_s cn68xxp1;
2246 typedef union cvmx_ciu2_ack_ppx_ip3 cvmx_ciu2_ack_ppx_ip3_t;
2249 * cvmx_ciu2_ack_pp#_ip4
2251 union cvmx_ciu2_ack_ppx_ip4 {
2253 struct cvmx_ciu2_ack_ppx_ip4_s {
2254 #ifdef __BIG_ENDIAN_BITFIELD
2255 uint64_t reserved_1_63 : 63;
2256 uint64_t ack : 1; /**< Read to clear the corresponding interrupt to
2257 PP/IO. Without this read the interrupt will not
2258 deassert until the next CIU interrupt scan, up to
2262 uint64_t reserved_1_63 : 63;
2265 struct cvmx_ciu2_ack_ppx_ip4_s cn68xx;
2266 struct cvmx_ciu2_ack_ppx_ip4_s cn68xxp1;
2268 typedef union cvmx_ciu2_ack_ppx_ip4 cvmx_ciu2_ack_ppx_ip4_t;
2271 * cvmx_ciu2_en_io#_int_gpio
2273 union cvmx_ciu2_en_iox_int_gpio {
2275 struct cvmx_ciu2_en_iox_int_gpio_s {
2276 #ifdef __BIG_ENDIAN_BITFIELD
2277 uint64_t reserved_16_63 : 48;
2278 uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */
2281 uint64_t reserved_16_63 : 48;
2284 struct cvmx_ciu2_en_iox_int_gpio_s cn68xx;
2285 struct cvmx_ciu2_en_iox_int_gpio_s cn68xxp1;
2287 typedef union cvmx_ciu2_en_iox_int_gpio cvmx_ciu2_en_iox_int_gpio_t;
2290 * cvmx_ciu2_en_io#_int_gpio_w1c
2292 union cvmx_ciu2_en_iox_int_gpio_w1c {
2294 struct cvmx_ciu2_en_iox_int_gpio_w1c_s {
2295 #ifdef __BIG_ENDIAN_BITFIELD
2296 uint64_t reserved_16_63 : 48;
2297 uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
2300 uint64_t reserved_16_63 : 48;
2303 struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xx;
2304 struct cvmx_ciu2_en_iox_int_gpio_w1c_s cn68xxp1;
2306 typedef union cvmx_ciu2_en_iox_int_gpio_w1c cvmx_ciu2_en_iox_int_gpio_w1c_t;
2309 * cvmx_ciu2_en_io#_int_gpio_w1s
2311 union cvmx_ciu2_en_iox_int_gpio_w1s {
2313 struct cvmx_ciu2_en_iox_int_gpio_w1s_s {
2314 #ifdef __BIG_ENDIAN_BITFIELD
2315 uint64_t reserved_16_63 : 48;
2316 uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
2319 uint64_t reserved_16_63 : 48;
2322 struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xx;
2323 struct cvmx_ciu2_en_iox_int_gpio_w1s_s cn68xxp1;
2325 typedef union cvmx_ciu2_en_iox_int_gpio_w1s cvmx_ciu2_en_iox_int_gpio_w1s_t;
2328 * cvmx_ciu2_en_io#_int_io
2330 union cvmx_ciu2_en_iox_int_io {
2332 struct cvmx_ciu2_en_iox_int_io_s {
2333 #ifdef __BIG_ENDIAN_BITFIELD
2334 uint64_t reserved_34_63 : 30;
2335 uint64_t pem : 2; /**< PEMx interrupt-enable */
2336 uint64_t reserved_18_31 : 14;
2337 uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */
2338 uint64_t reserved_13_15 : 3;
2339 uint64_t msired : 1; /**< MSI summary bit interrupt-enable
2340 This bit may not be functional in pass 1. */
2341 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */
2342 uint64_t reserved_4_7 : 4;
2343 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */
2345 uint64_t pci_intr : 4;
2346 uint64_t reserved_4_7 : 4;
2347 uint64_t pci_msi : 4;
2348 uint64_t msired : 1;
2349 uint64_t reserved_13_15 : 3;
2350 uint64_t pci_inta : 2;
2351 uint64_t reserved_18_31 : 14;
2353 uint64_t reserved_34_63 : 30;
2356 struct cvmx_ciu2_en_iox_int_io_s cn68xx;
2357 struct cvmx_ciu2_en_iox_int_io_s cn68xxp1;
2359 typedef union cvmx_ciu2_en_iox_int_io cvmx_ciu2_en_iox_int_io_t;
2362 * cvmx_ciu2_en_io#_int_io_w1c
2364 union cvmx_ciu2_en_iox_int_io_w1c {
2366 struct cvmx_ciu2_en_iox_int_io_w1c_s {
2367 #ifdef __BIG_ENDIAN_BITFIELD
2368 uint64_t reserved_34_63 : 30;
2369 uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
2370 uint64_t reserved_18_31 : 14;
2371 uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
2372 uint64_t reserved_13_15 : 3;
2373 uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
2374 This bit may not be functional in pass 1. */
2375 uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
2376 uint64_t reserved_4_7 : 4;
2377 uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
2379 uint64_t pci_intr : 4;
2380 uint64_t reserved_4_7 : 4;
2381 uint64_t pci_msi : 4;
2382 uint64_t msired : 1;
2383 uint64_t reserved_13_15 : 3;
2384 uint64_t pci_inta : 2;
2385 uint64_t reserved_18_31 : 14;
2387 uint64_t reserved_34_63 : 30;
2390 struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xx;
2391 struct cvmx_ciu2_en_iox_int_io_w1c_s cn68xxp1;
2393 typedef union cvmx_ciu2_en_iox_int_io_w1c cvmx_ciu2_en_iox_int_io_w1c_t;
2396 * cvmx_ciu2_en_io#_int_io_w1s
2398 union cvmx_ciu2_en_iox_int_io_w1s {
2400 struct cvmx_ciu2_en_iox_int_io_w1s_s {
2401 #ifdef __BIG_ENDIAN_BITFIELD
2402 uint64_t reserved_34_63 : 30;
2403 uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
2404 uint64_t reserved_18_31 : 14;
2405 uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
2406 uint64_t reserved_13_15 : 3;
2407 uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
2408 This bit may not be functional in pass 1. */
2409 uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
2410 uint64_t reserved_4_7 : 4;
2411 uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
2413 uint64_t pci_intr : 4;
2414 uint64_t reserved_4_7 : 4;
2415 uint64_t pci_msi : 4;
2416 uint64_t msired : 1;
2417 uint64_t reserved_13_15 : 3;
2418 uint64_t pci_inta : 2;
2419 uint64_t reserved_18_31 : 14;
2421 uint64_t reserved_34_63 : 30;
2424 struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xx;
2425 struct cvmx_ciu2_en_iox_int_io_w1s_s cn68xxp1;
2427 typedef union cvmx_ciu2_en_iox_int_io_w1s cvmx_ciu2_en_iox_int_io_w1s_t;
2430 * cvmx_ciu2_en_io#_int_mbox
2432 union cvmx_ciu2_en_iox_int_mbox {
2434 struct cvmx_ciu2_en_iox_int_mbox_s {
2435 #ifdef __BIG_ENDIAN_BITFIELD
2436 uint64_t reserved_4_63 : 60;
2437 uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX
2438 to generate CIU2_SRC_xx_yy_MBOX */
2441 uint64_t reserved_4_63 : 60;
2444 struct cvmx_ciu2_en_iox_int_mbox_s cn68xx;
2445 struct cvmx_ciu2_en_iox_int_mbox_s cn68xxp1;
2447 typedef union cvmx_ciu2_en_iox_int_mbox cvmx_ciu2_en_iox_int_mbox_t;
2450 * cvmx_ciu2_en_io#_int_mbox_w1c
2452 union cvmx_ciu2_en_iox_int_mbox_w1c {
2454 struct cvmx_ciu2_en_iox_int_mbox_w1c_s {
2455 #ifdef __BIG_ENDIAN_BITFIELD
2456 uint64_t reserved_4_63 : 60;
2457 uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
2460 uint64_t reserved_4_63 : 60;
2463 struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xx;
2464 struct cvmx_ciu2_en_iox_int_mbox_w1c_s cn68xxp1;
2466 typedef union cvmx_ciu2_en_iox_int_mbox_w1c cvmx_ciu2_en_iox_int_mbox_w1c_t;
2469 * cvmx_ciu2_en_io#_int_mbox_w1s
2471 union cvmx_ciu2_en_iox_int_mbox_w1s {
2473 struct cvmx_ciu2_en_iox_int_mbox_w1s_s {
2474 #ifdef __BIG_ENDIAN_BITFIELD
2475 uint64_t reserved_4_63 : 60;
2476 uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
2479 uint64_t reserved_4_63 : 60;
2482 struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xx;
2483 struct cvmx_ciu2_en_iox_int_mbox_w1s_s cn68xxp1;
2485 typedef union cvmx_ciu2_en_iox_int_mbox_w1s cvmx_ciu2_en_iox_int_mbox_w1s_t;
2488 * cvmx_ciu2_en_io#_int_mem
2490 union cvmx_ciu2_en_iox_int_mem {
2492 struct cvmx_ciu2_en_iox_int_mem_s {
2493 #ifdef __BIG_ENDIAN_BITFIELD
2494 uint64_t reserved_4_63 : 60;
2495 uint64_t lmc : 4; /**< LMC* interrupt-enable */
2498 uint64_t reserved_4_63 : 60;
2501 struct cvmx_ciu2_en_iox_int_mem_s cn68xx;
2502 struct cvmx_ciu2_en_iox_int_mem_s cn68xxp1;
2504 typedef union cvmx_ciu2_en_iox_int_mem cvmx_ciu2_en_iox_int_mem_t;
2507 * cvmx_ciu2_en_io#_int_mem_w1c
2509 union cvmx_ciu2_en_iox_int_mem_w1c {
2511 struct cvmx_ciu2_en_iox_int_mem_w1c_s {
2512 #ifdef __BIG_ENDIAN_BITFIELD
2513 uint64_t reserved_4_63 : 60;
2514 uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
2517 uint64_t reserved_4_63 : 60;
2520 struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xx;
2521 struct cvmx_ciu2_en_iox_int_mem_w1c_s cn68xxp1;
2523 typedef union cvmx_ciu2_en_iox_int_mem_w1c cvmx_ciu2_en_iox_int_mem_w1c_t;
2526 * cvmx_ciu2_en_io#_int_mem_w1s
2528 union cvmx_ciu2_en_iox_int_mem_w1s {
2530 struct cvmx_ciu2_en_iox_int_mem_w1s_s {
2531 #ifdef __BIG_ENDIAN_BITFIELD
2532 uint64_t reserved_4_63 : 60;
2533 uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
2536 uint64_t reserved_4_63 : 60;
2539 struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xx;
2540 struct cvmx_ciu2_en_iox_int_mem_w1s_s cn68xxp1;
2542 typedef union cvmx_ciu2_en_iox_int_mem_w1s cvmx_ciu2_en_iox_int_mem_w1s_t;
2545 * cvmx_ciu2_en_io#_int_mio
2547 union cvmx_ciu2_en_iox_int_mio {
2549 struct cvmx_ciu2_en_iox_int_mio_s {
2550 #ifdef __BIG_ENDIAN_BITFIELD
2551 uint64_t rst : 1; /**< MIO RST interrupt-enable */
2552 uint64_t reserved_49_62 : 14;
2553 uint64_t ptp : 1; /**< PTP interrupt-enable */
2554 uint64_t reserved_45_47 : 3;
2555 uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */
2556 uint64_t reserved_41_43 : 3;
2557 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */
2558 uint64_t reserved_38_39 : 2;
2559 uint64_t uart : 2; /**< Two UART interrupt-enable */
2560 uint64_t reserved_34_35 : 2;
2561 uint64_t twsi : 2; /**< TWSI x interrupt-enable */
2562 uint64_t reserved_19_31 : 13;
2563 uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */
2564 uint64_t mio : 1; /**< MIO boot interrupt-enable */
2565 uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */
2566 uint64_t reserved_12_15 : 4;
2567 uint64_t timer : 4; /**< General timer interrupt-enable */
2568 uint64_t reserved_3_7 : 5;
2569 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */
2570 uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */
2571 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */
2573 uint64_t ipdppthr : 1;
2575 uint64_t ipd_drp : 1;
2576 uint64_t reserved_3_7 : 5;
2578 uint64_t reserved_12_15 : 4;
2581 uint64_t bootdma : 1;
2582 uint64_t reserved_19_31 : 13;
2584 uint64_t reserved_34_35 : 2;
2586 uint64_t reserved_38_39 : 2;
2587 uint64_t usb_uctl : 1;
2588 uint64_t reserved_41_43 : 3;
2589 uint64_t usb_hci : 1;
2590 uint64_t reserved_45_47 : 3;
2592 uint64_t reserved_49_62 : 14;
2596 struct cvmx_ciu2_en_iox_int_mio_s cn68xx;
2597 struct cvmx_ciu2_en_iox_int_mio_s cn68xxp1;
2599 typedef union cvmx_ciu2_en_iox_int_mio cvmx_ciu2_en_iox_int_mio_t;
2602 * cvmx_ciu2_en_io#_int_mio_w1c
2604 union cvmx_ciu2_en_iox_int_mio_w1c {
2606 struct cvmx_ciu2_en_iox_int_mio_w1c_s {
2607 #ifdef __BIG_ENDIAN_BITFIELD
2608 uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
2609 uint64_t reserved_49_62 : 14;
2610 uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
2611 uint64_t reserved_45_47 : 3;
2612 uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
2613 uint64_t reserved_41_43 : 3;
2614 uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
2615 uint64_t reserved_38_39 : 2;
2616 uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
2617 uint64_t reserved_34_35 : 2;
2618 uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
2619 uint64_t reserved_19_31 : 13;
2620 uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
2621 uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
2622 uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
2623 uint64_t reserved_12_15 : 4;
2624 uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
2625 uint64_t reserved_3_7 : 5;
2626 uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
2627 uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
2628 uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
2630 uint64_t ipdppthr : 1;
2632 uint64_t ipd_drp : 1;
2633 uint64_t reserved_3_7 : 5;
2635 uint64_t reserved_12_15 : 4;
2638 uint64_t bootdma : 1;
2639 uint64_t reserved_19_31 : 13;
2641 uint64_t reserved_34_35 : 2;
2643 uint64_t reserved_38_39 : 2;
2644 uint64_t usb_uctl : 1;
2645 uint64_t reserved_41_43 : 3;
2646 uint64_t usb_hci : 1;
2647 uint64_t reserved_45_47 : 3;
2649 uint64_t reserved_49_62 : 14;
2653 struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xx;
2654 struct cvmx_ciu2_en_iox_int_mio_w1c_s cn68xxp1;
2656 typedef union cvmx_ciu2_en_iox_int_mio_w1c cvmx_ciu2_en_iox_int_mio_w1c_t;
2659 * cvmx_ciu2_en_io#_int_mio_w1s
2661 union cvmx_ciu2_en_iox_int_mio_w1s {
2663 struct cvmx_ciu2_en_iox_int_mio_w1s_s {
2664 #ifdef __BIG_ENDIAN_BITFIELD
2665 uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
2666 uint64_t reserved_49_62 : 14;
2667 uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
2668 uint64_t reserved_45_47 : 3;
2669 uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
2670 uint64_t reserved_41_43 : 3;
2671 uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
2672 uint64_t reserved_38_39 : 2;
2673 uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
2674 uint64_t reserved_34_35 : 2;
2675 uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
2676 uint64_t reserved_19_31 : 13;
2677 uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
2678 uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
2679 uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
2680 uint64_t reserved_12_15 : 4;
2681 uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
2682 uint64_t reserved_3_7 : 5;
2683 uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
2684 uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
2685 uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
2687 uint64_t ipdppthr : 1;
2689 uint64_t ipd_drp : 1;
2690 uint64_t reserved_3_7 : 5;
2692 uint64_t reserved_12_15 : 4;
2695 uint64_t bootdma : 1;
2696 uint64_t reserved_19_31 : 13;
2698 uint64_t reserved_34_35 : 2;
2700 uint64_t reserved_38_39 : 2;
2701 uint64_t usb_uctl : 1;
2702 uint64_t reserved_41_43 : 3;
2703 uint64_t usb_hci : 1;
2704 uint64_t reserved_45_47 : 3;
2706 uint64_t reserved_49_62 : 14;
2710 struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xx;
2711 struct cvmx_ciu2_en_iox_int_mio_w1s_s cn68xxp1;
2713 typedef union cvmx_ciu2_en_iox_int_mio_w1s cvmx_ciu2_en_iox_int_mio_w1s_t;
2716 * cvmx_ciu2_en_io#_int_pkt
2718 union cvmx_ciu2_en_iox_int_pkt {
2720 struct cvmx_ciu2_en_iox_int_pkt_s {
2721 #ifdef __BIG_ENDIAN_BITFIELD
2722 uint64_t reserved_54_63 : 10;
2723 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */
2724 uint64_t reserved_49_51 : 3;
2725 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
2726 uint64_t reserved_41_47 : 7;
2727 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
2728 uint64_t reserved_33_39 : 7;
2729 uint64_t agl : 1; /**< AGL interrupt-enable */
2730 uint64_t reserved_13_31 : 19;
2731 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
2732 uint64_t reserved_5_7 : 3;
2733 uint64_t agx : 5; /**< GMX interrupt-enable */
2736 uint64_t reserved_5_7 : 3;
2737 uint64_t gmx_drp : 5;
2738 uint64_t reserved_13_31 : 19;
2740 uint64_t reserved_33_39 : 7;
2742 uint64_t reserved_41_47 : 7;
2744 uint64_t reserved_49_51 : 3;
2745 uint64_t ilk_drp : 2;
2746 uint64_t reserved_54_63 : 10;
2749 struct cvmx_ciu2_en_iox_int_pkt_s cn68xx;
2750 struct cvmx_ciu2_en_iox_int_pkt_cn68xxp1 {
2751 #ifdef __BIG_ENDIAN_BITFIELD
2752 uint64_t reserved_49_63 : 15;
2753 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
2754 uint64_t reserved_41_47 : 7;
2755 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
2756 uint64_t reserved_33_39 : 7;
2757 uint64_t agl : 1; /**< AGL interrupt-enable */
2758 uint64_t reserved_13_31 : 19;
2759 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
2760 uint64_t reserved_5_7 : 3;
2761 uint64_t agx : 5; /**< GMX interrupt-enable */
2764 uint64_t reserved_5_7 : 3;
2765 uint64_t gmx_drp : 5;
2766 uint64_t reserved_13_31 : 19;
2768 uint64_t reserved_33_39 : 7;
2770 uint64_t reserved_41_47 : 7;
2772 uint64_t reserved_49_63 : 15;
2776 typedef union cvmx_ciu2_en_iox_int_pkt cvmx_ciu2_en_iox_int_pkt_t;
2779 * cvmx_ciu2_en_io#_int_pkt_w1c
2781 union cvmx_ciu2_en_iox_int_pkt_w1c {
2783 struct cvmx_ciu2_en_iox_int_pkt_w1c_s {
2784 #ifdef __BIG_ENDIAN_BITFIELD
2785 uint64_t reserved_54_63 : 10;
2786 uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
2787 uint64_t reserved_49_51 : 3;
2788 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
2789 uint64_t reserved_41_47 : 7;
2790 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
2791 uint64_t reserved_33_39 : 7;
2792 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
2793 uint64_t reserved_13_31 : 19;
2794 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
2795 uint64_t reserved_5_7 : 3;
2796 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
2799 uint64_t reserved_5_7 : 3;
2800 uint64_t gmx_drp : 5;
2801 uint64_t reserved_13_31 : 19;
2803 uint64_t reserved_33_39 : 7;
2805 uint64_t reserved_41_47 : 7;
2807 uint64_t reserved_49_51 : 3;
2808 uint64_t ilk_drp : 2;
2809 uint64_t reserved_54_63 : 10;
2812 struct cvmx_ciu2_en_iox_int_pkt_w1c_s cn68xx;
2813 struct cvmx_ciu2_en_iox_int_pkt_w1c_cn68xxp1 {
2814 #ifdef __BIG_ENDIAN_BITFIELD
2815 uint64_t reserved_49_63 : 15;
2816 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
2817 uint64_t reserved_41_47 : 7;
2818 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
2819 uint64_t reserved_33_39 : 7;
2820 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
2821 uint64_t reserved_13_31 : 19;
2822 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
2823 uint64_t reserved_5_7 : 3;
2824 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
2827 uint64_t reserved_5_7 : 3;
2828 uint64_t gmx_drp : 5;
2829 uint64_t reserved_13_31 : 19;
2831 uint64_t reserved_33_39 : 7;
2833 uint64_t reserved_41_47 : 7;
2835 uint64_t reserved_49_63 : 15;
2839 typedef union cvmx_ciu2_en_iox_int_pkt_w1c cvmx_ciu2_en_iox_int_pkt_w1c_t;
2842 * cvmx_ciu2_en_io#_int_pkt_w1s
2844 union cvmx_ciu2_en_iox_int_pkt_w1s {
2846 struct cvmx_ciu2_en_iox_int_pkt_w1s_s {
2847 #ifdef __BIG_ENDIAN_BITFIELD
2848 uint64_t reserved_54_63 : 10;
2849 uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
2850 uint64_t reserved_49_51 : 3;
2851 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
2852 uint64_t reserved_41_47 : 7;
2853 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
2854 uint64_t reserved_33_39 : 7;
2855 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
2856 uint64_t reserved_13_31 : 19;
2857 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
2858 uint64_t reserved_5_7 : 3;
2859 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
2862 uint64_t reserved_5_7 : 3;
2863 uint64_t gmx_drp : 5;
2864 uint64_t reserved_13_31 : 19;
2866 uint64_t reserved_33_39 : 7;
2868 uint64_t reserved_41_47 : 7;
2870 uint64_t reserved_49_51 : 3;
2871 uint64_t ilk_drp : 2;
2872 uint64_t reserved_54_63 : 10;
2875 struct cvmx_ciu2_en_iox_int_pkt_w1s_s cn68xx;
2876 struct cvmx_ciu2_en_iox_int_pkt_w1s_cn68xxp1 {
2877 #ifdef __BIG_ENDIAN_BITFIELD
2878 uint64_t reserved_49_63 : 15;
2879 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
2880 uint64_t reserved_41_47 : 7;
2881 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
2882 uint64_t reserved_33_39 : 7;
2883 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
2884 uint64_t reserved_13_31 : 19;
2885 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
2886 uint64_t reserved_5_7 : 3;
2887 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
2890 uint64_t reserved_5_7 : 3;
2891 uint64_t gmx_drp : 5;
2892 uint64_t reserved_13_31 : 19;
2894 uint64_t reserved_33_39 : 7;
2896 uint64_t reserved_41_47 : 7;
2898 uint64_t reserved_49_63 : 15;
2902 typedef union cvmx_ciu2_en_iox_int_pkt_w1s cvmx_ciu2_en_iox_int_pkt_w1s_t;
2905 * cvmx_ciu2_en_io#_int_rml
2907 union cvmx_ciu2_en_iox_int_rml {
2909 struct cvmx_ciu2_en_iox_int_rml_s {
2910 #ifdef __BIG_ENDIAN_BITFIELD
2911 uint64_t reserved_56_63 : 8;
2912 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
2913 uint64_t reserved_49_51 : 3;
2914 uint64_t l2c : 1; /**< L2C interrupt-enable */
2915 uint64_t reserved_41_47 : 7;
2916 uint64_t dfa : 1; /**< DFA interrupt-enable */
2917 uint64_t reserved_37_39 : 3;
2918 uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */
2919 uint64_t reserved_34_35 : 2;
2920 uint64_t dpi : 1; /**< DPI interrupt-enable */
2921 uint64_t sli : 1; /**< SLI interrupt-enable */
2922 uint64_t reserved_31_31 : 1;
2923 uint64_t key : 1; /**< KEY interrupt-enable */
2924 uint64_t rad : 1; /**< RAD interrupt-enable */
2925 uint64_t tim : 1; /**< TIM interrupt-enable */
2926 uint64_t reserved_25_27 : 3;
2927 uint64_t zip : 1; /**< ZIP interrupt-enable */
2928 uint64_t reserved_17_23 : 7;
2929 uint64_t sso : 1; /**< SSO err interrupt-enable */
2930 uint64_t reserved_8_15 : 8;
2931 uint64_t pko : 1; /**< PKO interrupt-enable */
2932 uint64_t pip : 1; /**< PIP interrupt-enable */
2933 uint64_t ipd : 1; /**< IPD interrupt-enable */
2934 uint64_t fpa : 1; /**< FPA interrupt-enable */
2935 uint64_t reserved_1_3 : 3;
2936 uint64_t iob : 1; /**< IOB interrupt-enable */
2939 uint64_t reserved_1_3 : 3;
2944 uint64_t reserved_8_15 : 8;
2946 uint64_t reserved_17_23 : 7;
2948 uint64_t reserved_25_27 : 3;
2952 uint64_t reserved_31_31 : 1;
2955 uint64_t reserved_34_35 : 2;
2956 uint64_t dpi_dma : 1;
2957 uint64_t reserved_37_39 : 3;
2959 uint64_t reserved_41_47 : 7;
2961 uint64_t reserved_49_51 : 3;
2963 uint64_t reserved_56_63 : 8;
2966 struct cvmx_ciu2_en_iox_int_rml_s cn68xx;
2967 struct cvmx_ciu2_en_iox_int_rml_cn68xxp1 {
2968 #ifdef __BIG_ENDIAN_BITFIELD
2969 uint64_t reserved_56_63 : 8;
2970 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
2971 uint64_t reserved_49_51 : 3;
2972 uint64_t l2c : 1; /**< L2C interrupt-enable */
2973 uint64_t reserved_41_47 : 7;
2974 uint64_t dfa : 1; /**< DFA interrupt-enable */
2975 uint64_t reserved_34_39 : 6;
2976 uint64_t dpi : 1; /**< DPI interrupt-enable */
2977 uint64_t sli : 1; /**< SLI interrupt-enable */
2978 uint64_t reserved_31_31 : 1;
2979 uint64_t key : 1; /**< KEY interrupt-enable */
2980 uint64_t rad : 1; /**< RAD interrupt-enable */
2981 uint64_t tim : 1; /**< TIM interrupt-enable */
2982 uint64_t reserved_25_27 : 3;
2983 uint64_t zip : 1; /**< ZIP interrupt-enable */
2984 uint64_t reserved_17_23 : 7;
2985 uint64_t sso : 1; /**< SSO err interrupt-enable */
2986 uint64_t reserved_8_15 : 8;
2987 uint64_t pko : 1; /**< PKO interrupt-enable */
2988 uint64_t pip : 1; /**< PIP interrupt-enable */
2989 uint64_t ipd : 1; /**< IPD interrupt-enable */
2990 uint64_t fpa : 1; /**< FPA interrupt-enable */
2991 uint64_t reserved_1_3 : 3;
2992 uint64_t iob : 1; /**< IOB interrupt-enable */
2995 uint64_t reserved_1_3 : 3;
3000 uint64_t reserved_8_15 : 8;
3002 uint64_t reserved_17_23 : 7;
3004 uint64_t reserved_25_27 : 3;
3008 uint64_t reserved_31_31 : 1;
3011 uint64_t reserved_34_39 : 6;
3013 uint64_t reserved_41_47 : 7;
3015 uint64_t reserved_49_51 : 3;
3017 uint64_t reserved_56_63 : 8;
3021 typedef union cvmx_ciu2_en_iox_int_rml cvmx_ciu2_en_iox_int_rml_t;
3024 * cvmx_ciu2_en_io#_int_rml_w1c
3026 union cvmx_ciu2_en_iox_int_rml_w1c {
3028 struct cvmx_ciu2_en_iox_int_rml_w1c_s {
3029 #ifdef __BIG_ENDIAN_BITFIELD
3030 uint64_t reserved_56_63 : 8;
3031 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
3032 uint64_t reserved_49_51 : 3;
3033 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
3034 uint64_t reserved_41_47 : 7;
3035 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
3036 uint64_t reserved_37_39 : 3;
3037 uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
3038 uint64_t reserved_34_35 : 2;
3039 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
3040 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
3041 uint64_t reserved_31_31 : 1;
3042 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
3043 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
3044 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
3045 uint64_t reserved_25_27 : 3;
3046 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
3047 uint64_t reserved_17_23 : 7;
3048 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
3049 uint64_t reserved_8_15 : 8;
3050 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
3051 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
3052 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
3053 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
3054 uint64_t reserved_1_3 : 3;
3055 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
3058 uint64_t reserved_1_3 : 3;
3063 uint64_t reserved_8_15 : 8;
3065 uint64_t reserved_17_23 : 7;
3067 uint64_t reserved_25_27 : 3;
3071 uint64_t reserved_31_31 : 1;
3074 uint64_t reserved_34_35 : 2;
3075 uint64_t dpi_dma : 1;
3076 uint64_t reserved_37_39 : 3;
3078 uint64_t reserved_41_47 : 7;
3080 uint64_t reserved_49_51 : 3;
3082 uint64_t reserved_56_63 : 8;
3085 struct cvmx_ciu2_en_iox_int_rml_w1c_s cn68xx;
3086 struct cvmx_ciu2_en_iox_int_rml_w1c_cn68xxp1 {
3087 #ifdef __BIG_ENDIAN_BITFIELD
3088 uint64_t reserved_56_63 : 8;
3089 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
3090 uint64_t reserved_49_51 : 3;
3091 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
3092 uint64_t reserved_41_47 : 7;
3093 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
3094 uint64_t reserved_34_39 : 6;
3095 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
3096 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
3097 uint64_t reserved_31_31 : 1;
3098 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
3099 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
3100 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
3101 uint64_t reserved_25_27 : 3;
3102 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
3103 uint64_t reserved_17_23 : 7;
3104 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
3105 uint64_t reserved_8_15 : 8;
3106 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
3107 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
3108 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
3109 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
3110 uint64_t reserved_1_3 : 3;
3111 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
3114 uint64_t reserved_1_3 : 3;
3119 uint64_t reserved_8_15 : 8;
3121 uint64_t reserved_17_23 : 7;
3123 uint64_t reserved_25_27 : 3;
3127 uint64_t reserved_31_31 : 1;
3130 uint64_t reserved_34_39 : 6;
3132 uint64_t reserved_41_47 : 7;
3134 uint64_t reserved_49_51 : 3;
3136 uint64_t reserved_56_63 : 8;
3140 typedef union cvmx_ciu2_en_iox_int_rml_w1c cvmx_ciu2_en_iox_int_rml_w1c_t;
3143 * cvmx_ciu2_en_io#_int_rml_w1s
3145 union cvmx_ciu2_en_iox_int_rml_w1s {
3147 struct cvmx_ciu2_en_iox_int_rml_w1s_s {
3148 #ifdef __BIG_ENDIAN_BITFIELD
3149 uint64_t reserved_56_63 : 8;
3150 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
3151 uint64_t reserved_49_51 : 3;
3152 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
3153 uint64_t reserved_41_47 : 7;
3154 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
3155 uint64_t reserved_37_39 : 3;
3156 uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
3157 uint64_t reserved_34_35 : 2;
3158 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
3159 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
3160 uint64_t reserved_31_31 : 1;
3161 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
3162 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
3163 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
3164 uint64_t reserved_25_27 : 3;
3165 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
3166 uint64_t reserved_17_23 : 7;
3167 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
3168 uint64_t reserved_8_15 : 8;
3169 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
3170 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
3171 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
3172 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
3173 uint64_t reserved_1_3 : 3;
3174 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
3177 uint64_t reserved_1_3 : 3;
3182 uint64_t reserved_8_15 : 8;
3184 uint64_t reserved_17_23 : 7;
3186 uint64_t reserved_25_27 : 3;
3190 uint64_t reserved_31_31 : 1;
3193 uint64_t reserved_34_35 : 2;
3194 uint64_t dpi_dma : 1;
3195 uint64_t reserved_37_39 : 3;
3197 uint64_t reserved_41_47 : 7;
3199 uint64_t reserved_49_51 : 3;
3201 uint64_t reserved_56_63 : 8;
3204 struct cvmx_ciu2_en_iox_int_rml_w1s_s cn68xx;
3205 struct cvmx_ciu2_en_iox_int_rml_w1s_cn68xxp1 {
3206 #ifdef __BIG_ENDIAN_BITFIELD
3207 uint64_t reserved_56_63 : 8;
3208 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
3209 uint64_t reserved_49_51 : 3;
3210 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
3211 uint64_t reserved_41_47 : 7;
3212 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
3213 uint64_t reserved_34_39 : 6;
3214 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
3215 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
3216 uint64_t reserved_31_31 : 1;
3217 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
3218 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
3219 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
3220 uint64_t reserved_25_27 : 3;
3221 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
3222 uint64_t reserved_17_23 : 7;
3223 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
3224 uint64_t reserved_8_15 : 8;
3225 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
3226 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
3227 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
3228 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
3229 uint64_t reserved_1_3 : 3;
3230 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
3233 uint64_t reserved_1_3 : 3;
3238 uint64_t reserved_8_15 : 8;
3240 uint64_t reserved_17_23 : 7;
3242 uint64_t reserved_25_27 : 3;
3246 uint64_t reserved_31_31 : 1;
3249 uint64_t reserved_34_39 : 6;
3251 uint64_t reserved_41_47 : 7;
3253 uint64_t reserved_49_51 : 3;
3255 uint64_t reserved_56_63 : 8;
3259 typedef union cvmx_ciu2_en_iox_int_rml_w1s cvmx_ciu2_en_iox_int_rml_w1s_t;
3262 * cvmx_ciu2_en_io#_int_wdog
3264 union cvmx_ciu2_en_iox_int_wdog {
3266 struct cvmx_ciu2_en_iox_int_wdog_s {
3267 #ifdef __BIG_ENDIAN_BITFIELD
3268 uint64_t reserved_32_63 : 32;
3269 uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */
3272 uint64_t reserved_32_63 : 32;
3275 struct cvmx_ciu2_en_iox_int_wdog_s cn68xx;
3276 struct cvmx_ciu2_en_iox_int_wdog_s cn68xxp1;
3278 typedef union cvmx_ciu2_en_iox_int_wdog cvmx_ciu2_en_iox_int_wdog_t;
3281 * cvmx_ciu2_en_io#_int_wdog_w1c
3283 union cvmx_ciu2_en_iox_int_wdog_w1c {
3285 struct cvmx_ciu2_en_iox_int_wdog_w1c_s {
3286 #ifdef __BIG_ENDIAN_BITFIELD
3287 uint64_t reserved_32_63 : 32;
3288 uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
3291 uint64_t reserved_32_63 : 32;
3294 struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xx;
3295 struct cvmx_ciu2_en_iox_int_wdog_w1c_s cn68xxp1;
3297 typedef union cvmx_ciu2_en_iox_int_wdog_w1c cvmx_ciu2_en_iox_int_wdog_w1c_t;
3300 * cvmx_ciu2_en_io#_int_wdog_w1s
3302 union cvmx_ciu2_en_iox_int_wdog_w1s {
3304 struct cvmx_ciu2_en_iox_int_wdog_w1s_s {
3305 #ifdef __BIG_ENDIAN_BITFIELD
3306 uint64_t reserved_32_63 : 32;
3307 uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
3310 uint64_t reserved_32_63 : 32;
3313 struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xx;
3314 struct cvmx_ciu2_en_iox_int_wdog_w1s_s cn68xxp1;
3316 typedef union cvmx_ciu2_en_iox_int_wdog_w1s cvmx_ciu2_en_iox_int_wdog_w1s_t;
3319 * cvmx_ciu2_en_io#_int_wrkq
3321 union cvmx_ciu2_en_iox_int_wrkq {
3323 struct cvmx_ciu2_en_iox_int_wrkq_s {
3324 #ifdef __BIG_ENDIAN_BITFIELD
3325 uint64_t workq : 64; /**< 64 work queue interrupt-enable */
3327 uint64_t workq : 64;
3330 struct cvmx_ciu2_en_iox_int_wrkq_s cn68xx;
3331 struct cvmx_ciu2_en_iox_int_wrkq_s cn68xxp1;
3333 typedef union cvmx_ciu2_en_iox_int_wrkq cvmx_ciu2_en_iox_int_wrkq_t;
3336 * cvmx_ciu2_en_io#_int_wrkq_w1c
3338 union cvmx_ciu2_en_iox_int_wrkq_w1c {
3340 struct cvmx_ciu2_en_iox_int_wrkq_w1c_s {
3341 #ifdef __BIG_ENDIAN_BITFIELD
3342 uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
3343 For W1C bits, write 1 to clear the corresponding
3344 CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
3346 uint64_t workq : 64;
3349 struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xx;
3350 struct cvmx_ciu2_en_iox_int_wrkq_w1c_s cn68xxp1;
3352 typedef union cvmx_ciu2_en_iox_int_wrkq_w1c cvmx_ciu2_en_iox_int_wrkq_w1c_t;
3355 * cvmx_ciu2_en_io#_int_wrkq_w1s
3357 union cvmx_ciu2_en_iox_int_wrkq_w1s {
3359 struct cvmx_ciu2_en_iox_int_wrkq_w1s_s {
3360 #ifdef __BIG_ENDIAN_BITFIELD
3361 uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
3362 1 bit/group. For all W1S bits, write 1 to enable
3363 corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
3364 writing 0 to retain previous value. */
3366 uint64_t workq : 64;
3369 struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xx;
3370 struct cvmx_ciu2_en_iox_int_wrkq_w1s_s cn68xxp1;
3372 typedef union cvmx_ciu2_en_iox_int_wrkq_w1s cvmx_ciu2_en_iox_int_wrkq_w1s_t;
3375 * cvmx_ciu2_en_pp#_ip2_gpio
3377 union cvmx_ciu2_en_ppx_ip2_gpio {
3379 struct cvmx_ciu2_en_ppx_ip2_gpio_s {
3380 #ifdef __BIG_ENDIAN_BITFIELD
3381 uint64_t reserved_16_63 : 48;
3382 uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */
3385 uint64_t reserved_16_63 : 48;
3388 struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xx;
3389 struct cvmx_ciu2_en_ppx_ip2_gpio_s cn68xxp1;
3391 typedef union cvmx_ciu2_en_ppx_ip2_gpio cvmx_ciu2_en_ppx_ip2_gpio_t;
3394 * cvmx_ciu2_en_pp#_ip2_gpio_w1c
3396 union cvmx_ciu2_en_ppx_ip2_gpio_w1c {
3398 struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s {
3399 #ifdef __BIG_ENDIAN_BITFIELD
3400 uint64_t reserved_16_63 : 48;
3401 uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
3404 uint64_t reserved_16_63 : 48;
3407 struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xx;
3408 struct cvmx_ciu2_en_ppx_ip2_gpio_w1c_s cn68xxp1;
3410 typedef union cvmx_ciu2_en_ppx_ip2_gpio_w1c cvmx_ciu2_en_ppx_ip2_gpio_w1c_t;
3413 * cvmx_ciu2_en_pp#_ip2_gpio_w1s
3415 union cvmx_ciu2_en_ppx_ip2_gpio_w1s {
3417 struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s {
3418 #ifdef __BIG_ENDIAN_BITFIELD
3419 uint64_t reserved_16_63 : 48;
3420 uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
3423 uint64_t reserved_16_63 : 48;
3426 struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xx;
3427 struct cvmx_ciu2_en_ppx_ip2_gpio_w1s_s cn68xxp1;
3429 typedef union cvmx_ciu2_en_ppx_ip2_gpio_w1s cvmx_ciu2_en_ppx_ip2_gpio_w1s_t;
3432 * cvmx_ciu2_en_pp#_ip2_io
3434 union cvmx_ciu2_en_ppx_ip2_io {
3436 struct cvmx_ciu2_en_ppx_ip2_io_s {
3437 #ifdef __BIG_ENDIAN_BITFIELD
3438 uint64_t reserved_34_63 : 30;
3439 uint64_t pem : 2; /**< PEMx interrupt-enable */
3440 uint64_t reserved_18_31 : 14;
3441 uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */
3442 uint64_t reserved_13_15 : 3;
3443 uint64_t msired : 1; /**< MSI summary bit interrupt-enable
3444 This bit may not be functional in pass 1. */
3445 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */
3446 uint64_t reserved_4_7 : 4;
3447 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */
3449 uint64_t pci_intr : 4;
3450 uint64_t reserved_4_7 : 4;
3451 uint64_t pci_msi : 4;
3452 uint64_t msired : 1;
3453 uint64_t reserved_13_15 : 3;
3454 uint64_t pci_inta : 2;
3455 uint64_t reserved_18_31 : 14;
3457 uint64_t reserved_34_63 : 30;
3460 struct cvmx_ciu2_en_ppx_ip2_io_s cn68xx;
3461 struct cvmx_ciu2_en_ppx_ip2_io_s cn68xxp1;
3463 typedef union cvmx_ciu2_en_ppx_ip2_io cvmx_ciu2_en_ppx_ip2_io_t;
3466 * cvmx_ciu2_en_pp#_ip2_io_w1c
3468 union cvmx_ciu2_en_ppx_ip2_io_w1c {
3470 struct cvmx_ciu2_en_ppx_ip2_io_w1c_s {
3471 #ifdef __BIG_ENDIAN_BITFIELD
3472 uint64_t reserved_34_63 : 30;
3473 uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
3474 uint64_t reserved_18_31 : 14;
3475 uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
3476 uint64_t reserved_13_15 : 3;
3477 uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
3478 This bit may not be functional in pass 1. */
3479 uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
3480 uint64_t reserved_4_7 : 4;
3481 uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
3483 uint64_t pci_intr : 4;
3484 uint64_t reserved_4_7 : 4;
3485 uint64_t pci_msi : 4;
3486 uint64_t msired : 1;
3487 uint64_t reserved_13_15 : 3;
3488 uint64_t pci_inta : 2;
3489 uint64_t reserved_18_31 : 14;
3491 uint64_t reserved_34_63 : 30;
3494 struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xx;
3495 struct cvmx_ciu2_en_ppx_ip2_io_w1c_s cn68xxp1;
3497 typedef union cvmx_ciu2_en_ppx_ip2_io_w1c cvmx_ciu2_en_ppx_ip2_io_w1c_t;
3500 * cvmx_ciu2_en_pp#_ip2_io_w1s
3502 union cvmx_ciu2_en_ppx_ip2_io_w1s {
3504 struct cvmx_ciu2_en_ppx_ip2_io_w1s_s {
3505 #ifdef __BIG_ENDIAN_BITFIELD
3506 uint64_t reserved_34_63 : 30;
3507 uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
3508 uint64_t reserved_18_31 : 14;
3509 uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
3510 uint64_t reserved_13_15 : 3;
3511 uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
3512 This bit may not be functional in pass 1. */
3513 uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
3514 uint64_t reserved_4_7 : 4;
3515 uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
3517 uint64_t pci_intr : 4;
3518 uint64_t reserved_4_7 : 4;
3519 uint64_t pci_msi : 4;
3520 uint64_t msired : 1;
3521 uint64_t reserved_13_15 : 3;
3522 uint64_t pci_inta : 2;
3523 uint64_t reserved_18_31 : 14;
3525 uint64_t reserved_34_63 : 30;
3528 struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xx;
3529 struct cvmx_ciu2_en_ppx_ip2_io_w1s_s cn68xxp1;
3531 typedef union cvmx_ciu2_en_ppx_ip2_io_w1s cvmx_ciu2_en_ppx_ip2_io_w1s_t;
3534 * cvmx_ciu2_en_pp#_ip2_mbox
3536 union cvmx_ciu2_en_ppx_ip2_mbox {
3538 struct cvmx_ciu2_en_ppx_ip2_mbox_s {
3539 #ifdef __BIG_ENDIAN_BITFIELD
3540 uint64_t reserved_4_63 : 60;
3541 uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX
3542 to generate CIU2_SRC_xx_yy_MBOX */
3545 uint64_t reserved_4_63 : 60;
3548 struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xx;
3549 struct cvmx_ciu2_en_ppx_ip2_mbox_s cn68xxp1;
3551 typedef union cvmx_ciu2_en_ppx_ip2_mbox cvmx_ciu2_en_ppx_ip2_mbox_t;
3554 * cvmx_ciu2_en_pp#_ip2_mbox_w1c
3556 union cvmx_ciu2_en_ppx_ip2_mbox_w1c {
3558 struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s {
3559 #ifdef __BIG_ENDIAN_BITFIELD
3560 uint64_t reserved_4_63 : 60;
3561 uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
3564 uint64_t reserved_4_63 : 60;
3567 struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xx;
3568 struct cvmx_ciu2_en_ppx_ip2_mbox_w1c_s cn68xxp1;
3570 typedef union cvmx_ciu2_en_ppx_ip2_mbox_w1c cvmx_ciu2_en_ppx_ip2_mbox_w1c_t;
3573 * cvmx_ciu2_en_pp#_ip2_mbox_w1s
3575 union cvmx_ciu2_en_ppx_ip2_mbox_w1s {
3577 struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s {
3578 #ifdef __BIG_ENDIAN_BITFIELD
3579 uint64_t reserved_4_63 : 60;
3580 uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
3583 uint64_t reserved_4_63 : 60;
3586 struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xx;
3587 struct cvmx_ciu2_en_ppx_ip2_mbox_w1s_s cn68xxp1;
3589 typedef union cvmx_ciu2_en_ppx_ip2_mbox_w1s cvmx_ciu2_en_ppx_ip2_mbox_w1s_t;
3592 * cvmx_ciu2_en_pp#_ip2_mem
3594 union cvmx_ciu2_en_ppx_ip2_mem {
3596 struct cvmx_ciu2_en_ppx_ip2_mem_s {
3597 #ifdef __BIG_ENDIAN_BITFIELD
3598 uint64_t reserved_4_63 : 60;
3599 uint64_t lmc : 4; /**< LMC* interrupt-enable */
3602 uint64_t reserved_4_63 : 60;
3605 struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xx;
3606 struct cvmx_ciu2_en_ppx_ip2_mem_s cn68xxp1;
3608 typedef union cvmx_ciu2_en_ppx_ip2_mem cvmx_ciu2_en_ppx_ip2_mem_t;
3611 * cvmx_ciu2_en_pp#_ip2_mem_w1c
3613 union cvmx_ciu2_en_ppx_ip2_mem_w1c {
3615 struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s {
3616 #ifdef __BIG_ENDIAN_BITFIELD
3617 uint64_t reserved_4_63 : 60;
3618 uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
3621 uint64_t reserved_4_63 : 60;
3624 struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xx;
3625 struct cvmx_ciu2_en_ppx_ip2_mem_w1c_s cn68xxp1;
3627 typedef union cvmx_ciu2_en_ppx_ip2_mem_w1c cvmx_ciu2_en_ppx_ip2_mem_w1c_t;
3630 * cvmx_ciu2_en_pp#_ip2_mem_w1s
3632 union cvmx_ciu2_en_ppx_ip2_mem_w1s {
3634 struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s {
3635 #ifdef __BIG_ENDIAN_BITFIELD
3636 uint64_t reserved_4_63 : 60;
3637 uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
3640 uint64_t reserved_4_63 : 60;
3643 struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xx;
3644 struct cvmx_ciu2_en_ppx_ip2_mem_w1s_s cn68xxp1;
3646 typedef union cvmx_ciu2_en_ppx_ip2_mem_w1s cvmx_ciu2_en_ppx_ip2_mem_w1s_t;
3649 * cvmx_ciu2_en_pp#_ip2_mio
3651 union cvmx_ciu2_en_ppx_ip2_mio {
3653 struct cvmx_ciu2_en_ppx_ip2_mio_s {
3654 #ifdef __BIG_ENDIAN_BITFIELD
3655 uint64_t rst : 1; /**< MIO RST interrupt-enable */
3656 uint64_t reserved_49_62 : 14;
3657 uint64_t ptp : 1; /**< PTP interrupt-enable */
3658 uint64_t reserved_45_47 : 3;
3659 uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */
3660 uint64_t reserved_41_43 : 3;
3661 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */
3662 uint64_t reserved_38_39 : 2;
3663 uint64_t uart : 2; /**< Two UART interrupt-enable */
3664 uint64_t reserved_34_35 : 2;
3665 uint64_t twsi : 2; /**< TWSI x interrupt-enable */
3666 uint64_t reserved_19_31 : 13;
3667 uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */
3668 uint64_t mio : 1; /**< MIO boot interrupt-enable */
3669 uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */
3670 uint64_t reserved_12_15 : 4;
3671 uint64_t timer : 4; /**< General timer interrupt-enable */
3672 uint64_t reserved_3_7 : 5;
3673 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */
3674 uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */
3675 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */
3677 uint64_t ipdppthr : 1;
3679 uint64_t ipd_drp : 1;
3680 uint64_t reserved_3_7 : 5;
3682 uint64_t reserved_12_15 : 4;
3685 uint64_t bootdma : 1;
3686 uint64_t reserved_19_31 : 13;
3688 uint64_t reserved_34_35 : 2;
3690 uint64_t reserved_38_39 : 2;
3691 uint64_t usb_uctl : 1;
3692 uint64_t reserved_41_43 : 3;
3693 uint64_t usb_hci : 1;
3694 uint64_t reserved_45_47 : 3;
3696 uint64_t reserved_49_62 : 14;
3700 struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xx;
3701 struct cvmx_ciu2_en_ppx_ip2_mio_s cn68xxp1;
3703 typedef union cvmx_ciu2_en_ppx_ip2_mio cvmx_ciu2_en_ppx_ip2_mio_t;
3706 * cvmx_ciu2_en_pp#_ip2_mio_w1c
3708 union cvmx_ciu2_en_ppx_ip2_mio_w1c {
3710 struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s {
3711 #ifdef __BIG_ENDIAN_BITFIELD
3712 uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
3713 uint64_t reserved_49_62 : 14;
3714 uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
3715 uint64_t reserved_45_47 : 3;
3716 uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
3717 uint64_t reserved_41_43 : 3;
3718 uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
3719 uint64_t reserved_38_39 : 2;
3720 uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
3721 uint64_t reserved_34_35 : 2;
3722 uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
3723 uint64_t reserved_19_31 : 13;
3724 uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
3725 uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
3726 uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
3727 uint64_t reserved_12_15 : 4;
3728 uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
3729 uint64_t reserved_3_7 : 5;
3730 uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
3731 uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
3732 uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
3734 uint64_t ipdppthr : 1;
3736 uint64_t ipd_drp : 1;
3737 uint64_t reserved_3_7 : 5;
3739 uint64_t reserved_12_15 : 4;
3742 uint64_t bootdma : 1;
3743 uint64_t reserved_19_31 : 13;
3745 uint64_t reserved_34_35 : 2;
3747 uint64_t reserved_38_39 : 2;
3748 uint64_t usb_uctl : 1;
3749 uint64_t reserved_41_43 : 3;
3750 uint64_t usb_hci : 1;
3751 uint64_t reserved_45_47 : 3;
3753 uint64_t reserved_49_62 : 14;
3757 struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xx;
3758 struct cvmx_ciu2_en_ppx_ip2_mio_w1c_s cn68xxp1;
3760 typedef union cvmx_ciu2_en_ppx_ip2_mio_w1c cvmx_ciu2_en_ppx_ip2_mio_w1c_t;
3763 * cvmx_ciu2_en_pp#_ip2_mio_w1s
3765 union cvmx_ciu2_en_ppx_ip2_mio_w1s {
3767 struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s {
3768 #ifdef __BIG_ENDIAN_BITFIELD
3769 uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
3770 uint64_t reserved_49_62 : 14;
3771 uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
3772 uint64_t reserved_45_47 : 3;
3773 uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
3774 uint64_t reserved_41_43 : 3;
3775 uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
3776 uint64_t reserved_38_39 : 2;
3777 uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
3778 uint64_t reserved_34_35 : 2;
3779 uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
3780 uint64_t reserved_19_31 : 13;
3781 uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
3782 uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
3783 uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
3784 uint64_t reserved_12_15 : 4;
3785 uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
3786 uint64_t reserved_3_7 : 5;
3787 uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
3788 uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
3789 uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
3791 uint64_t ipdppthr : 1;
3793 uint64_t ipd_drp : 1;
3794 uint64_t reserved_3_7 : 5;
3796 uint64_t reserved_12_15 : 4;
3799 uint64_t bootdma : 1;
3800 uint64_t reserved_19_31 : 13;
3802 uint64_t reserved_34_35 : 2;
3804 uint64_t reserved_38_39 : 2;
3805 uint64_t usb_uctl : 1;
3806 uint64_t reserved_41_43 : 3;
3807 uint64_t usb_hci : 1;
3808 uint64_t reserved_45_47 : 3;
3810 uint64_t reserved_49_62 : 14;
3814 struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xx;
3815 struct cvmx_ciu2_en_ppx_ip2_mio_w1s_s cn68xxp1;
3817 typedef union cvmx_ciu2_en_ppx_ip2_mio_w1s cvmx_ciu2_en_ppx_ip2_mio_w1s_t;
3820 * cvmx_ciu2_en_pp#_ip2_pkt
3822 union cvmx_ciu2_en_ppx_ip2_pkt {
3824 struct cvmx_ciu2_en_ppx_ip2_pkt_s {
3825 #ifdef __BIG_ENDIAN_BITFIELD
3826 uint64_t reserved_54_63 : 10;
3827 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */
3828 uint64_t reserved_49_51 : 3;
3829 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
3830 uint64_t reserved_41_47 : 7;
3831 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
3832 uint64_t reserved_33_39 : 7;
3833 uint64_t agl : 1; /**< AGL interrupt-enable */
3834 uint64_t reserved_13_31 : 19;
3835 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
3836 uint64_t reserved_5_7 : 3;
3837 uint64_t agx : 5; /**< GMX interrupt-enable */
3840 uint64_t reserved_5_7 : 3;
3841 uint64_t gmx_drp : 5;
3842 uint64_t reserved_13_31 : 19;
3844 uint64_t reserved_33_39 : 7;
3846 uint64_t reserved_41_47 : 7;
3848 uint64_t reserved_49_51 : 3;
3849 uint64_t ilk_drp : 2;
3850 uint64_t reserved_54_63 : 10;
3853 struct cvmx_ciu2_en_ppx_ip2_pkt_s cn68xx;
3854 struct cvmx_ciu2_en_ppx_ip2_pkt_cn68xxp1 {
3855 #ifdef __BIG_ENDIAN_BITFIELD
3856 uint64_t reserved_49_63 : 15;
3857 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
3858 uint64_t reserved_41_47 : 7;
3859 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
3860 uint64_t reserved_33_39 : 7;
3861 uint64_t agl : 1; /**< AGL interrupt-enable */
3862 uint64_t reserved_13_31 : 19;
3863 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
3864 uint64_t reserved_5_7 : 3;
3865 uint64_t agx : 5; /**< GMX interrupt-enable */
3868 uint64_t reserved_5_7 : 3;
3869 uint64_t gmx_drp : 5;
3870 uint64_t reserved_13_31 : 19;
3872 uint64_t reserved_33_39 : 7;
3874 uint64_t reserved_41_47 : 7;
3876 uint64_t reserved_49_63 : 15;
3880 typedef union cvmx_ciu2_en_ppx_ip2_pkt cvmx_ciu2_en_ppx_ip2_pkt_t;
3883 * cvmx_ciu2_en_pp#_ip2_pkt_w1c
3885 union cvmx_ciu2_en_ppx_ip2_pkt_w1c {
3887 struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s {
3888 #ifdef __BIG_ENDIAN_BITFIELD
3889 uint64_t reserved_54_63 : 10;
3890 uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
3891 uint64_t reserved_49_51 : 3;
3892 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
3893 uint64_t reserved_41_47 : 7;
3894 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
3895 uint64_t reserved_33_39 : 7;
3896 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
3897 uint64_t reserved_13_31 : 19;
3898 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
3899 uint64_t reserved_5_7 : 3;
3900 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
3903 uint64_t reserved_5_7 : 3;
3904 uint64_t gmx_drp : 5;
3905 uint64_t reserved_13_31 : 19;
3907 uint64_t reserved_33_39 : 7;
3909 uint64_t reserved_41_47 : 7;
3911 uint64_t reserved_49_51 : 3;
3912 uint64_t ilk_drp : 2;
3913 uint64_t reserved_54_63 : 10;
3916 struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_s cn68xx;
3917 struct cvmx_ciu2_en_ppx_ip2_pkt_w1c_cn68xxp1 {
3918 #ifdef __BIG_ENDIAN_BITFIELD
3919 uint64_t reserved_49_63 : 15;
3920 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
3921 uint64_t reserved_41_47 : 7;
3922 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
3923 uint64_t reserved_33_39 : 7;
3924 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
3925 uint64_t reserved_13_31 : 19;
3926 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
3927 uint64_t reserved_5_7 : 3;
3928 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
3931 uint64_t reserved_5_7 : 3;
3932 uint64_t gmx_drp : 5;
3933 uint64_t reserved_13_31 : 19;
3935 uint64_t reserved_33_39 : 7;
3937 uint64_t reserved_41_47 : 7;
3939 uint64_t reserved_49_63 : 15;
3943 typedef union cvmx_ciu2_en_ppx_ip2_pkt_w1c cvmx_ciu2_en_ppx_ip2_pkt_w1c_t;
3946 * cvmx_ciu2_en_pp#_ip2_pkt_w1s
3948 union cvmx_ciu2_en_ppx_ip2_pkt_w1s {
3950 struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s {
3951 #ifdef __BIG_ENDIAN_BITFIELD
3952 uint64_t reserved_54_63 : 10;
3953 uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
3954 uint64_t reserved_49_51 : 3;
3955 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
3956 uint64_t reserved_41_47 : 7;
3957 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
3958 uint64_t reserved_33_39 : 7;
3959 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
3960 uint64_t reserved_13_31 : 19;
3961 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
3962 uint64_t reserved_5_7 : 3;
3963 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
3966 uint64_t reserved_5_7 : 3;
3967 uint64_t gmx_drp : 5;
3968 uint64_t reserved_13_31 : 19;
3970 uint64_t reserved_33_39 : 7;
3972 uint64_t reserved_41_47 : 7;
3974 uint64_t reserved_49_51 : 3;
3975 uint64_t ilk_drp : 2;
3976 uint64_t reserved_54_63 : 10;
3979 struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_s cn68xx;
3980 struct cvmx_ciu2_en_ppx_ip2_pkt_w1s_cn68xxp1 {
3981 #ifdef __BIG_ENDIAN_BITFIELD
3982 uint64_t reserved_49_63 : 15;
3983 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
3984 uint64_t reserved_41_47 : 7;
3985 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
3986 uint64_t reserved_33_39 : 7;
3987 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
3988 uint64_t reserved_13_31 : 19;
3989 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
3990 uint64_t reserved_5_7 : 3;
3991 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
3994 uint64_t reserved_5_7 : 3;
3995 uint64_t gmx_drp : 5;
3996 uint64_t reserved_13_31 : 19;
3998 uint64_t reserved_33_39 : 7;
4000 uint64_t reserved_41_47 : 7;
4002 uint64_t reserved_49_63 : 15;
4006 typedef union cvmx_ciu2_en_ppx_ip2_pkt_w1s cvmx_ciu2_en_ppx_ip2_pkt_w1s_t;
4009 * cvmx_ciu2_en_pp#_ip2_rml
4011 union cvmx_ciu2_en_ppx_ip2_rml {
4013 struct cvmx_ciu2_en_ppx_ip2_rml_s {
4014 #ifdef __BIG_ENDIAN_BITFIELD
4015 uint64_t reserved_56_63 : 8;
4016 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
4017 uint64_t reserved_49_51 : 3;
4018 uint64_t l2c : 1; /**< L2C interrupt-enable */
4019 uint64_t reserved_41_47 : 7;
4020 uint64_t dfa : 1; /**< DFA interrupt-enable */
4021 uint64_t reserved_37_39 : 3;
4022 uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */
4023 uint64_t reserved_34_35 : 2;
4024 uint64_t dpi : 1; /**< DPI interrupt-enable */
4025 uint64_t sli : 1; /**< SLI interrupt-enable */
4026 uint64_t reserved_31_31 : 1;
4027 uint64_t key : 1; /**< KEY interrupt-enable */
4028 uint64_t rad : 1; /**< RAD interrupt-enable */
4029 uint64_t tim : 1; /**< TIM interrupt-enable */
4030 uint64_t reserved_25_27 : 3;
4031 uint64_t zip : 1; /**< ZIP interrupt-enable */
4032 uint64_t reserved_17_23 : 7;
4033 uint64_t sso : 1; /**< SSO err interrupt-enable */
4034 uint64_t reserved_8_15 : 8;
4035 uint64_t pko : 1; /**< PKO interrupt-enable */
4036 uint64_t pip : 1; /**< PIP interrupt-enable */
4037 uint64_t ipd : 1; /**< IPD interrupt-enable */
4038 uint64_t fpa : 1; /**< FPA interrupt-enable */
4039 uint64_t reserved_1_3 : 3;
4040 uint64_t iob : 1; /**< IOB interrupt-enable */
4043 uint64_t reserved_1_3 : 3;
4048 uint64_t reserved_8_15 : 8;
4050 uint64_t reserved_17_23 : 7;
4052 uint64_t reserved_25_27 : 3;
4056 uint64_t reserved_31_31 : 1;
4059 uint64_t reserved_34_35 : 2;
4060 uint64_t dpi_dma : 1;
4061 uint64_t reserved_37_39 : 3;
4063 uint64_t reserved_41_47 : 7;
4065 uint64_t reserved_49_51 : 3;
4067 uint64_t reserved_56_63 : 8;
4070 struct cvmx_ciu2_en_ppx_ip2_rml_s cn68xx;
4071 struct cvmx_ciu2_en_ppx_ip2_rml_cn68xxp1 {
4072 #ifdef __BIG_ENDIAN_BITFIELD
4073 uint64_t reserved_56_63 : 8;
4074 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
4075 uint64_t reserved_49_51 : 3;
4076 uint64_t l2c : 1; /**< L2C interrupt-enable */
4077 uint64_t reserved_41_47 : 7;
4078 uint64_t dfa : 1; /**< DFA interrupt-enable */
4079 uint64_t reserved_34_39 : 6;
4080 uint64_t dpi : 1; /**< DPI interrupt-enable */
4081 uint64_t sli : 1; /**< SLI interrupt-enable */
4082 uint64_t reserved_31_31 : 1;
4083 uint64_t key : 1; /**< KEY interrupt-enable */
4084 uint64_t rad : 1; /**< RAD interrupt-enable */
4085 uint64_t tim : 1; /**< TIM interrupt-enable */
4086 uint64_t reserved_25_27 : 3;
4087 uint64_t zip : 1; /**< ZIP interrupt-enable */
4088 uint64_t reserved_17_23 : 7;
4089 uint64_t sso : 1; /**< SSO err interrupt-enable */
4090 uint64_t reserved_8_15 : 8;
4091 uint64_t pko : 1; /**< PKO interrupt-enable */
4092 uint64_t pip : 1; /**< PIP interrupt-enable */
4093 uint64_t ipd : 1; /**< IPD interrupt-enable */
4094 uint64_t fpa : 1; /**< FPA interrupt-enable */
4095 uint64_t reserved_1_3 : 3;
4096 uint64_t iob : 1; /**< IOB interrupt-enable */
4099 uint64_t reserved_1_3 : 3;
4104 uint64_t reserved_8_15 : 8;
4106 uint64_t reserved_17_23 : 7;
4108 uint64_t reserved_25_27 : 3;
4112 uint64_t reserved_31_31 : 1;
4115 uint64_t reserved_34_39 : 6;
4117 uint64_t reserved_41_47 : 7;
4119 uint64_t reserved_49_51 : 3;
4121 uint64_t reserved_56_63 : 8;
4125 typedef union cvmx_ciu2_en_ppx_ip2_rml cvmx_ciu2_en_ppx_ip2_rml_t;
4128 * cvmx_ciu2_en_pp#_ip2_rml_w1c
4130 union cvmx_ciu2_en_ppx_ip2_rml_w1c {
4132 struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s {
4133 #ifdef __BIG_ENDIAN_BITFIELD
4134 uint64_t reserved_56_63 : 8;
4135 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
4136 uint64_t reserved_49_51 : 3;
4137 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
4138 uint64_t reserved_41_47 : 7;
4139 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
4140 uint64_t reserved_37_39 : 3;
4141 uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
4142 uint64_t reserved_34_35 : 2;
4143 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
4144 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
4145 uint64_t reserved_31_31 : 1;
4146 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
4147 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
4148 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
4149 uint64_t reserved_25_27 : 3;
4150 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
4151 uint64_t reserved_17_23 : 7;
4152 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
4153 uint64_t reserved_8_15 : 8;
4154 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
4155 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
4156 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
4157 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
4158 uint64_t reserved_1_3 : 3;
4159 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
4162 uint64_t reserved_1_3 : 3;
4167 uint64_t reserved_8_15 : 8;
4169 uint64_t reserved_17_23 : 7;
4171 uint64_t reserved_25_27 : 3;
4175 uint64_t reserved_31_31 : 1;
4178 uint64_t reserved_34_35 : 2;
4179 uint64_t dpi_dma : 1;
4180 uint64_t reserved_37_39 : 3;
4182 uint64_t reserved_41_47 : 7;
4184 uint64_t reserved_49_51 : 3;
4186 uint64_t reserved_56_63 : 8;
4189 struct cvmx_ciu2_en_ppx_ip2_rml_w1c_s cn68xx;
4190 struct cvmx_ciu2_en_ppx_ip2_rml_w1c_cn68xxp1 {
4191 #ifdef __BIG_ENDIAN_BITFIELD
4192 uint64_t reserved_56_63 : 8;
4193 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
4194 uint64_t reserved_49_51 : 3;
4195 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
4196 uint64_t reserved_41_47 : 7;
4197 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
4198 uint64_t reserved_34_39 : 6;
4199 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
4200 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
4201 uint64_t reserved_31_31 : 1;
4202 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
4203 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
4204 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
4205 uint64_t reserved_25_27 : 3;
4206 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
4207 uint64_t reserved_17_23 : 7;
4208 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
4209 uint64_t reserved_8_15 : 8;
4210 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
4211 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
4212 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
4213 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
4214 uint64_t reserved_1_3 : 3;
4215 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
4218 uint64_t reserved_1_3 : 3;
4223 uint64_t reserved_8_15 : 8;
4225 uint64_t reserved_17_23 : 7;
4227 uint64_t reserved_25_27 : 3;
4231 uint64_t reserved_31_31 : 1;
4234 uint64_t reserved_34_39 : 6;
4236 uint64_t reserved_41_47 : 7;
4238 uint64_t reserved_49_51 : 3;
4240 uint64_t reserved_56_63 : 8;
4244 typedef union cvmx_ciu2_en_ppx_ip2_rml_w1c cvmx_ciu2_en_ppx_ip2_rml_w1c_t;
4247 * cvmx_ciu2_en_pp#_ip2_rml_w1s
4249 union cvmx_ciu2_en_ppx_ip2_rml_w1s {
4251 struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s {
4252 #ifdef __BIG_ENDIAN_BITFIELD
4253 uint64_t reserved_56_63 : 8;
4254 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
4255 uint64_t reserved_49_51 : 3;
4256 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
4257 uint64_t reserved_41_47 : 7;
4258 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
4259 uint64_t reserved_37_39 : 3;
4260 uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
4261 uint64_t reserved_34_35 : 2;
4262 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
4263 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
4264 uint64_t reserved_31_31 : 1;
4265 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
4266 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
4267 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
4268 uint64_t reserved_25_27 : 3;
4269 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
4270 uint64_t reserved_17_23 : 7;
4271 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
4272 uint64_t reserved_8_15 : 8;
4273 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
4274 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
4275 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
4276 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
4277 uint64_t reserved_1_3 : 3;
4278 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
4281 uint64_t reserved_1_3 : 3;
4286 uint64_t reserved_8_15 : 8;
4288 uint64_t reserved_17_23 : 7;
4290 uint64_t reserved_25_27 : 3;
4294 uint64_t reserved_31_31 : 1;
4297 uint64_t reserved_34_35 : 2;
4298 uint64_t dpi_dma : 1;
4299 uint64_t reserved_37_39 : 3;
4301 uint64_t reserved_41_47 : 7;
4303 uint64_t reserved_49_51 : 3;
4305 uint64_t reserved_56_63 : 8;
4308 struct cvmx_ciu2_en_ppx_ip2_rml_w1s_s cn68xx;
4309 struct cvmx_ciu2_en_ppx_ip2_rml_w1s_cn68xxp1 {
4310 #ifdef __BIG_ENDIAN_BITFIELD
4311 uint64_t reserved_56_63 : 8;
4312 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
4313 uint64_t reserved_49_51 : 3;
4314 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
4315 uint64_t reserved_41_47 : 7;
4316 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
4317 uint64_t reserved_34_39 : 6;
4318 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
4319 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
4320 uint64_t reserved_31_31 : 1;
4321 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
4322 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
4323 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
4324 uint64_t reserved_25_27 : 3;
4325 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
4326 uint64_t reserved_17_23 : 7;
4327 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
4328 uint64_t reserved_8_15 : 8;
4329 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
4330 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
4331 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
4332 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
4333 uint64_t reserved_1_3 : 3;
4334 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
4337 uint64_t reserved_1_3 : 3;
4342 uint64_t reserved_8_15 : 8;
4344 uint64_t reserved_17_23 : 7;
4346 uint64_t reserved_25_27 : 3;
4350 uint64_t reserved_31_31 : 1;
4353 uint64_t reserved_34_39 : 6;
4355 uint64_t reserved_41_47 : 7;
4357 uint64_t reserved_49_51 : 3;
4359 uint64_t reserved_56_63 : 8;
4363 typedef union cvmx_ciu2_en_ppx_ip2_rml_w1s cvmx_ciu2_en_ppx_ip2_rml_w1s_t;
4366 * cvmx_ciu2_en_pp#_ip2_wdog
4368 union cvmx_ciu2_en_ppx_ip2_wdog {
4370 struct cvmx_ciu2_en_ppx_ip2_wdog_s {
4371 #ifdef __BIG_ENDIAN_BITFIELD
4372 uint64_t reserved_32_63 : 32;
4373 uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */
4376 uint64_t reserved_32_63 : 32;
4379 struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xx;
4380 struct cvmx_ciu2_en_ppx_ip2_wdog_s cn68xxp1;
4382 typedef union cvmx_ciu2_en_ppx_ip2_wdog cvmx_ciu2_en_ppx_ip2_wdog_t;
4385 * cvmx_ciu2_en_pp#_ip2_wdog_w1c
4387 union cvmx_ciu2_en_ppx_ip2_wdog_w1c {
4389 struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s {
4390 #ifdef __BIG_ENDIAN_BITFIELD
4391 uint64_t reserved_32_63 : 32;
4392 uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
4395 uint64_t reserved_32_63 : 32;
4398 struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xx;
4399 struct cvmx_ciu2_en_ppx_ip2_wdog_w1c_s cn68xxp1;
4401 typedef union cvmx_ciu2_en_ppx_ip2_wdog_w1c cvmx_ciu2_en_ppx_ip2_wdog_w1c_t;
4404 * cvmx_ciu2_en_pp#_ip2_wdog_w1s
4406 union cvmx_ciu2_en_ppx_ip2_wdog_w1s {
4408 struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s {
4409 #ifdef __BIG_ENDIAN_BITFIELD
4410 uint64_t reserved_32_63 : 32;
4411 uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
4414 uint64_t reserved_32_63 : 32;
4417 struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xx;
4418 struct cvmx_ciu2_en_ppx_ip2_wdog_w1s_s cn68xxp1;
4420 typedef union cvmx_ciu2_en_ppx_ip2_wdog_w1s cvmx_ciu2_en_ppx_ip2_wdog_w1s_t;
4423 * cvmx_ciu2_en_pp#_ip2_wrkq
4425 union cvmx_ciu2_en_ppx_ip2_wrkq {
4427 struct cvmx_ciu2_en_ppx_ip2_wrkq_s {
4428 #ifdef __BIG_ENDIAN_BITFIELD
4429 uint64_t workq : 64; /**< 64 work queue interrupt-enable */
4431 uint64_t workq : 64;
4434 struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xx;
4435 struct cvmx_ciu2_en_ppx_ip2_wrkq_s cn68xxp1;
4437 typedef union cvmx_ciu2_en_ppx_ip2_wrkq cvmx_ciu2_en_ppx_ip2_wrkq_t;
4440 * cvmx_ciu2_en_pp#_ip2_wrkq_w1c
4442 union cvmx_ciu2_en_ppx_ip2_wrkq_w1c {
4444 struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s {
4445 #ifdef __BIG_ENDIAN_BITFIELD
4446 uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
4447 For W1C bits, write 1 to clear the corresponding
4448 CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
4450 uint64_t workq : 64;
4453 struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xx;
4454 struct cvmx_ciu2_en_ppx_ip2_wrkq_w1c_s cn68xxp1;
4456 typedef union cvmx_ciu2_en_ppx_ip2_wrkq_w1c cvmx_ciu2_en_ppx_ip2_wrkq_w1c_t;
4459 * cvmx_ciu2_en_pp#_ip2_wrkq_w1s
4461 union cvmx_ciu2_en_ppx_ip2_wrkq_w1s {
4463 struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s {
4464 #ifdef __BIG_ENDIAN_BITFIELD
4465 uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
4466 1 bit/group. For all W1S bits, write 1 to enable
4467 corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
4468 writing 0 to retain previous value. */
4470 uint64_t workq : 64;
4473 struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xx;
4474 struct cvmx_ciu2_en_ppx_ip2_wrkq_w1s_s cn68xxp1;
4476 typedef union cvmx_ciu2_en_ppx_ip2_wrkq_w1s cvmx_ciu2_en_ppx_ip2_wrkq_w1s_t;
4479 * cvmx_ciu2_en_pp#_ip3_gpio
4481 union cvmx_ciu2_en_ppx_ip3_gpio {
4483 struct cvmx_ciu2_en_ppx_ip3_gpio_s {
4484 #ifdef __BIG_ENDIAN_BITFIELD
4485 uint64_t reserved_16_63 : 48;
4486 uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */
4489 uint64_t reserved_16_63 : 48;
4492 struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xx;
4493 struct cvmx_ciu2_en_ppx_ip3_gpio_s cn68xxp1;
4495 typedef union cvmx_ciu2_en_ppx_ip3_gpio cvmx_ciu2_en_ppx_ip3_gpio_t;
4498 * cvmx_ciu2_en_pp#_ip3_gpio_w1c
4500 union cvmx_ciu2_en_ppx_ip3_gpio_w1c {
4502 struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s {
4503 #ifdef __BIG_ENDIAN_BITFIELD
4504 uint64_t reserved_16_63 : 48;
4505 uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
4508 uint64_t reserved_16_63 : 48;
4511 struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xx;
4512 struct cvmx_ciu2_en_ppx_ip3_gpio_w1c_s cn68xxp1;
4514 typedef union cvmx_ciu2_en_ppx_ip3_gpio_w1c cvmx_ciu2_en_ppx_ip3_gpio_w1c_t;
4517 * cvmx_ciu2_en_pp#_ip3_gpio_w1s
4519 union cvmx_ciu2_en_ppx_ip3_gpio_w1s {
4521 struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s {
4522 #ifdef __BIG_ENDIAN_BITFIELD
4523 uint64_t reserved_16_63 : 48;
4524 uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
4527 uint64_t reserved_16_63 : 48;
4530 struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xx;
4531 struct cvmx_ciu2_en_ppx_ip3_gpio_w1s_s cn68xxp1;
4533 typedef union cvmx_ciu2_en_ppx_ip3_gpio_w1s cvmx_ciu2_en_ppx_ip3_gpio_w1s_t;
4536 * cvmx_ciu2_en_pp#_ip3_io
4538 union cvmx_ciu2_en_ppx_ip3_io {
4540 struct cvmx_ciu2_en_ppx_ip3_io_s {
4541 #ifdef __BIG_ENDIAN_BITFIELD
4542 uint64_t reserved_34_63 : 30;
4543 uint64_t pem : 2; /**< PEMx interrupt-enable */
4544 uint64_t reserved_18_31 : 14;
4545 uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */
4546 uint64_t reserved_13_15 : 3;
4547 uint64_t msired : 1; /**< MSI summary bit interrupt-enable
4548 This bit may not be functional in pass 1. */
4549 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */
4550 uint64_t reserved_4_7 : 4;
4551 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */
4553 uint64_t pci_intr : 4;
4554 uint64_t reserved_4_7 : 4;
4555 uint64_t pci_msi : 4;
4556 uint64_t msired : 1;
4557 uint64_t reserved_13_15 : 3;
4558 uint64_t pci_inta : 2;
4559 uint64_t reserved_18_31 : 14;
4561 uint64_t reserved_34_63 : 30;
4564 struct cvmx_ciu2_en_ppx_ip3_io_s cn68xx;
4565 struct cvmx_ciu2_en_ppx_ip3_io_s cn68xxp1;
4567 typedef union cvmx_ciu2_en_ppx_ip3_io cvmx_ciu2_en_ppx_ip3_io_t;
4570 * cvmx_ciu2_en_pp#_ip3_io_w1c
4572 union cvmx_ciu2_en_ppx_ip3_io_w1c {
4574 struct cvmx_ciu2_en_ppx_ip3_io_w1c_s {
4575 #ifdef __BIG_ENDIAN_BITFIELD
4576 uint64_t reserved_34_63 : 30;
4577 uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
4578 uint64_t reserved_18_31 : 14;
4579 uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
4580 uint64_t reserved_13_15 : 3;
4581 uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
4582 This bit may not be functional in pass 1. */
4583 uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
4584 uint64_t reserved_4_7 : 4;
4585 uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
4587 uint64_t pci_intr : 4;
4588 uint64_t reserved_4_7 : 4;
4589 uint64_t pci_msi : 4;
4590 uint64_t msired : 1;
4591 uint64_t reserved_13_15 : 3;
4592 uint64_t pci_inta : 2;
4593 uint64_t reserved_18_31 : 14;
4595 uint64_t reserved_34_63 : 30;
4598 struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xx;
4599 struct cvmx_ciu2_en_ppx_ip3_io_w1c_s cn68xxp1;
4601 typedef union cvmx_ciu2_en_ppx_ip3_io_w1c cvmx_ciu2_en_ppx_ip3_io_w1c_t;
4604 * cvmx_ciu2_en_pp#_ip3_io_w1s
4606 union cvmx_ciu2_en_ppx_ip3_io_w1s {
4608 struct cvmx_ciu2_en_ppx_ip3_io_w1s_s {
4609 #ifdef __BIG_ENDIAN_BITFIELD
4610 uint64_t reserved_34_63 : 30;
4611 uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
4612 uint64_t reserved_18_31 : 14;
4613 uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
4614 uint64_t reserved_13_15 : 3;
4615 uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
4616 This bit may not be functional in pass 1. */
4617 uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
4618 uint64_t reserved_4_7 : 4;
4619 uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
4621 uint64_t pci_intr : 4;
4622 uint64_t reserved_4_7 : 4;
4623 uint64_t pci_msi : 4;
4624 uint64_t msired : 1;
4625 uint64_t reserved_13_15 : 3;
4626 uint64_t pci_inta : 2;
4627 uint64_t reserved_18_31 : 14;
4629 uint64_t reserved_34_63 : 30;
4632 struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xx;
4633 struct cvmx_ciu2_en_ppx_ip3_io_w1s_s cn68xxp1;
4635 typedef union cvmx_ciu2_en_ppx_ip3_io_w1s cvmx_ciu2_en_ppx_ip3_io_w1s_t;
4638 * cvmx_ciu2_en_pp#_ip3_mbox
4640 union cvmx_ciu2_en_ppx_ip3_mbox {
4642 struct cvmx_ciu2_en_ppx_ip3_mbox_s {
4643 #ifdef __BIG_ENDIAN_BITFIELD
4644 uint64_t reserved_4_63 : 60;
4645 uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX
4646 to generate CIU2_SRC_xx_yy_MBOX */
4649 uint64_t reserved_4_63 : 60;
4652 struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xx;
4653 struct cvmx_ciu2_en_ppx_ip3_mbox_s cn68xxp1;
4655 typedef union cvmx_ciu2_en_ppx_ip3_mbox cvmx_ciu2_en_ppx_ip3_mbox_t;
4658 * cvmx_ciu2_en_pp#_ip3_mbox_w1c
4660 union cvmx_ciu2_en_ppx_ip3_mbox_w1c {
4662 struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s {
4663 #ifdef __BIG_ENDIAN_BITFIELD
4664 uint64_t reserved_4_63 : 60;
4665 uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
4668 uint64_t reserved_4_63 : 60;
4671 struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xx;
4672 struct cvmx_ciu2_en_ppx_ip3_mbox_w1c_s cn68xxp1;
4674 typedef union cvmx_ciu2_en_ppx_ip3_mbox_w1c cvmx_ciu2_en_ppx_ip3_mbox_w1c_t;
4677 * cvmx_ciu2_en_pp#_ip3_mbox_w1s
4679 union cvmx_ciu2_en_ppx_ip3_mbox_w1s {
4681 struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s {
4682 #ifdef __BIG_ENDIAN_BITFIELD
4683 uint64_t reserved_4_63 : 60;
4684 uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
4687 uint64_t reserved_4_63 : 60;
4690 struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xx;
4691 struct cvmx_ciu2_en_ppx_ip3_mbox_w1s_s cn68xxp1;
4693 typedef union cvmx_ciu2_en_ppx_ip3_mbox_w1s cvmx_ciu2_en_ppx_ip3_mbox_w1s_t;
4696 * cvmx_ciu2_en_pp#_ip3_mem
4698 union cvmx_ciu2_en_ppx_ip3_mem {
4700 struct cvmx_ciu2_en_ppx_ip3_mem_s {
4701 #ifdef __BIG_ENDIAN_BITFIELD
4702 uint64_t reserved_4_63 : 60;
4703 uint64_t lmc : 4; /**< LMC* interrupt-enable */
4706 uint64_t reserved_4_63 : 60;
4709 struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xx;
4710 struct cvmx_ciu2_en_ppx_ip3_mem_s cn68xxp1;
4712 typedef union cvmx_ciu2_en_ppx_ip3_mem cvmx_ciu2_en_ppx_ip3_mem_t;
4715 * cvmx_ciu2_en_pp#_ip3_mem_w1c
4717 union cvmx_ciu2_en_ppx_ip3_mem_w1c {
4719 struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s {
4720 #ifdef __BIG_ENDIAN_BITFIELD
4721 uint64_t reserved_4_63 : 60;
4722 uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
4725 uint64_t reserved_4_63 : 60;
4728 struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xx;
4729 struct cvmx_ciu2_en_ppx_ip3_mem_w1c_s cn68xxp1;
4731 typedef union cvmx_ciu2_en_ppx_ip3_mem_w1c cvmx_ciu2_en_ppx_ip3_mem_w1c_t;
4734 * cvmx_ciu2_en_pp#_ip3_mem_w1s
4736 union cvmx_ciu2_en_ppx_ip3_mem_w1s {
4738 struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s {
4739 #ifdef __BIG_ENDIAN_BITFIELD
4740 uint64_t reserved_4_63 : 60;
4741 uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
4744 uint64_t reserved_4_63 : 60;
4747 struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xx;
4748 struct cvmx_ciu2_en_ppx_ip3_mem_w1s_s cn68xxp1;
4750 typedef union cvmx_ciu2_en_ppx_ip3_mem_w1s cvmx_ciu2_en_ppx_ip3_mem_w1s_t;
4753 * cvmx_ciu2_en_pp#_ip3_mio
4755 union cvmx_ciu2_en_ppx_ip3_mio {
4757 struct cvmx_ciu2_en_ppx_ip3_mio_s {
4758 #ifdef __BIG_ENDIAN_BITFIELD
4759 uint64_t rst : 1; /**< MIO RST interrupt-enable */
4760 uint64_t reserved_49_62 : 14;
4761 uint64_t ptp : 1; /**< PTP interrupt-enable */
4762 uint64_t reserved_45_47 : 3;
4763 uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */
4764 uint64_t reserved_41_43 : 3;
4765 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */
4766 uint64_t reserved_38_39 : 2;
4767 uint64_t uart : 2; /**< Two UART interrupt-enable */
4768 uint64_t reserved_34_35 : 2;
4769 uint64_t twsi : 2; /**< TWSI x interrupt-enable */
4770 uint64_t reserved_19_31 : 13;
4771 uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */
4772 uint64_t mio : 1; /**< MIO boot interrupt-enable */
4773 uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */
4774 uint64_t reserved_12_15 : 4;
4775 uint64_t timer : 4; /**< General timer interrupt-enable */
4776 uint64_t reserved_3_7 : 5;
4777 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */
4778 uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */
4779 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */
4781 uint64_t ipdppthr : 1;
4783 uint64_t ipd_drp : 1;
4784 uint64_t reserved_3_7 : 5;
4786 uint64_t reserved_12_15 : 4;
4789 uint64_t bootdma : 1;
4790 uint64_t reserved_19_31 : 13;
4792 uint64_t reserved_34_35 : 2;
4794 uint64_t reserved_38_39 : 2;
4795 uint64_t usb_uctl : 1;
4796 uint64_t reserved_41_43 : 3;
4797 uint64_t usb_hci : 1;
4798 uint64_t reserved_45_47 : 3;
4800 uint64_t reserved_49_62 : 14;
4804 struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xx;
4805 struct cvmx_ciu2_en_ppx_ip3_mio_s cn68xxp1;
4807 typedef union cvmx_ciu2_en_ppx_ip3_mio cvmx_ciu2_en_ppx_ip3_mio_t;
4810 * cvmx_ciu2_en_pp#_ip3_mio_w1c
4812 union cvmx_ciu2_en_ppx_ip3_mio_w1c {
4814 struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s {
4815 #ifdef __BIG_ENDIAN_BITFIELD
4816 uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
4817 uint64_t reserved_49_62 : 14;
4818 uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
4819 uint64_t reserved_45_47 : 3;
4820 uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
4821 uint64_t reserved_41_43 : 3;
4822 uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
4823 uint64_t reserved_38_39 : 2;
4824 uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
4825 uint64_t reserved_34_35 : 2;
4826 uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
4827 uint64_t reserved_19_31 : 13;
4828 uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
4829 uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
4830 uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
4831 uint64_t reserved_12_15 : 4;
4832 uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
4833 uint64_t reserved_3_7 : 5;
4834 uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
4835 uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
4836 uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
4838 uint64_t ipdppthr : 1;
4840 uint64_t ipd_drp : 1;
4841 uint64_t reserved_3_7 : 5;
4843 uint64_t reserved_12_15 : 4;
4846 uint64_t bootdma : 1;
4847 uint64_t reserved_19_31 : 13;
4849 uint64_t reserved_34_35 : 2;
4851 uint64_t reserved_38_39 : 2;
4852 uint64_t usb_uctl : 1;
4853 uint64_t reserved_41_43 : 3;
4854 uint64_t usb_hci : 1;
4855 uint64_t reserved_45_47 : 3;
4857 uint64_t reserved_49_62 : 14;
4861 struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xx;
4862 struct cvmx_ciu2_en_ppx_ip3_mio_w1c_s cn68xxp1;
4864 typedef union cvmx_ciu2_en_ppx_ip3_mio_w1c cvmx_ciu2_en_ppx_ip3_mio_w1c_t;
4867 * cvmx_ciu2_en_pp#_ip3_mio_w1s
4869 union cvmx_ciu2_en_ppx_ip3_mio_w1s {
4871 struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s {
4872 #ifdef __BIG_ENDIAN_BITFIELD
4873 uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
4874 uint64_t reserved_49_62 : 14;
4875 uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
4876 uint64_t reserved_45_47 : 3;
4877 uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
4878 uint64_t reserved_41_43 : 3;
4879 uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
4880 uint64_t reserved_38_39 : 2;
4881 uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
4882 uint64_t reserved_34_35 : 2;
4883 uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
4884 uint64_t reserved_19_31 : 13;
4885 uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
4886 uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
4887 uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
4888 uint64_t reserved_12_15 : 4;
4889 uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
4890 uint64_t reserved_3_7 : 5;
4891 uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
4892 uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
4893 uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
4895 uint64_t ipdppthr : 1;
4897 uint64_t ipd_drp : 1;
4898 uint64_t reserved_3_7 : 5;
4900 uint64_t reserved_12_15 : 4;
4903 uint64_t bootdma : 1;
4904 uint64_t reserved_19_31 : 13;
4906 uint64_t reserved_34_35 : 2;
4908 uint64_t reserved_38_39 : 2;
4909 uint64_t usb_uctl : 1;
4910 uint64_t reserved_41_43 : 3;
4911 uint64_t usb_hci : 1;
4912 uint64_t reserved_45_47 : 3;
4914 uint64_t reserved_49_62 : 14;
4918 struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xx;
4919 struct cvmx_ciu2_en_ppx_ip3_mio_w1s_s cn68xxp1;
4921 typedef union cvmx_ciu2_en_ppx_ip3_mio_w1s cvmx_ciu2_en_ppx_ip3_mio_w1s_t;
4924 * cvmx_ciu2_en_pp#_ip3_pkt
4926 union cvmx_ciu2_en_ppx_ip3_pkt {
4928 struct cvmx_ciu2_en_ppx_ip3_pkt_s {
4929 #ifdef __BIG_ENDIAN_BITFIELD
4930 uint64_t reserved_54_63 : 10;
4931 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */
4932 uint64_t reserved_49_51 : 3;
4933 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
4934 uint64_t reserved_41_47 : 7;
4935 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
4936 uint64_t reserved_33_39 : 7;
4937 uint64_t agl : 1; /**< AGL interrupt-enable */
4938 uint64_t reserved_13_31 : 19;
4939 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
4940 uint64_t reserved_5_7 : 3;
4941 uint64_t agx : 5; /**< GMX interrupt-enable */
4944 uint64_t reserved_5_7 : 3;
4945 uint64_t gmx_drp : 5;
4946 uint64_t reserved_13_31 : 19;
4948 uint64_t reserved_33_39 : 7;
4950 uint64_t reserved_41_47 : 7;
4952 uint64_t reserved_49_51 : 3;
4953 uint64_t ilk_drp : 2;
4954 uint64_t reserved_54_63 : 10;
4957 struct cvmx_ciu2_en_ppx_ip3_pkt_s cn68xx;
4958 struct cvmx_ciu2_en_ppx_ip3_pkt_cn68xxp1 {
4959 #ifdef __BIG_ENDIAN_BITFIELD
4960 uint64_t reserved_49_63 : 15;
4961 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
4962 uint64_t reserved_41_47 : 7;
4963 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
4964 uint64_t reserved_33_39 : 7;
4965 uint64_t agl : 1; /**< AGL interrupt-enable */
4966 uint64_t reserved_13_31 : 19;
4967 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
4968 uint64_t reserved_5_7 : 3;
4969 uint64_t agx : 5; /**< GMX interrupt-enable */
4972 uint64_t reserved_5_7 : 3;
4973 uint64_t gmx_drp : 5;
4974 uint64_t reserved_13_31 : 19;
4976 uint64_t reserved_33_39 : 7;
4978 uint64_t reserved_41_47 : 7;
4980 uint64_t reserved_49_63 : 15;
4984 typedef union cvmx_ciu2_en_ppx_ip3_pkt cvmx_ciu2_en_ppx_ip3_pkt_t;
4987 * cvmx_ciu2_en_pp#_ip3_pkt_w1c
4989 union cvmx_ciu2_en_ppx_ip3_pkt_w1c {
4991 struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s {
4992 #ifdef __BIG_ENDIAN_BITFIELD
4993 uint64_t reserved_54_63 : 10;
4994 uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
4995 uint64_t reserved_49_51 : 3;
4996 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
4997 uint64_t reserved_41_47 : 7;
4998 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
4999 uint64_t reserved_33_39 : 7;
5000 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
5001 uint64_t reserved_13_31 : 19;
5002 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
5003 uint64_t reserved_5_7 : 3;
5004 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
5007 uint64_t reserved_5_7 : 3;
5008 uint64_t gmx_drp : 5;
5009 uint64_t reserved_13_31 : 19;
5011 uint64_t reserved_33_39 : 7;
5013 uint64_t reserved_41_47 : 7;
5015 uint64_t reserved_49_51 : 3;
5016 uint64_t ilk_drp : 2;
5017 uint64_t reserved_54_63 : 10;
5020 struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_s cn68xx;
5021 struct cvmx_ciu2_en_ppx_ip3_pkt_w1c_cn68xxp1 {
5022 #ifdef __BIG_ENDIAN_BITFIELD
5023 uint64_t reserved_49_63 : 15;
5024 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
5025 uint64_t reserved_41_47 : 7;
5026 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
5027 uint64_t reserved_33_39 : 7;
5028 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
5029 uint64_t reserved_13_31 : 19;
5030 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
5031 uint64_t reserved_5_7 : 3;
5032 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
5035 uint64_t reserved_5_7 : 3;
5036 uint64_t gmx_drp : 5;
5037 uint64_t reserved_13_31 : 19;
5039 uint64_t reserved_33_39 : 7;
5041 uint64_t reserved_41_47 : 7;
5043 uint64_t reserved_49_63 : 15;
5047 typedef union cvmx_ciu2_en_ppx_ip3_pkt_w1c cvmx_ciu2_en_ppx_ip3_pkt_w1c_t;
5050 * cvmx_ciu2_en_pp#_ip3_pkt_w1s
5052 union cvmx_ciu2_en_ppx_ip3_pkt_w1s {
5054 struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s {
5055 #ifdef __BIG_ENDIAN_BITFIELD
5056 uint64_t reserved_54_63 : 10;
5057 uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
5058 uint64_t reserved_49_51 : 3;
5059 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
5060 uint64_t reserved_41_47 : 7;
5061 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
5062 uint64_t reserved_33_39 : 7;
5063 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
5064 uint64_t reserved_13_31 : 19;
5065 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
5066 uint64_t reserved_5_7 : 3;
5067 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
5070 uint64_t reserved_5_7 : 3;
5071 uint64_t gmx_drp : 5;
5072 uint64_t reserved_13_31 : 19;
5074 uint64_t reserved_33_39 : 7;
5076 uint64_t reserved_41_47 : 7;
5078 uint64_t reserved_49_51 : 3;
5079 uint64_t ilk_drp : 2;
5080 uint64_t reserved_54_63 : 10;
5083 struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_s cn68xx;
5084 struct cvmx_ciu2_en_ppx_ip3_pkt_w1s_cn68xxp1 {
5085 #ifdef __BIG_ENDIAN_BITFIELD
5086 uint64_t reserved_49_63 : 15;
5087 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
5088 uint64_t reserved_41_47 : 7;
5089 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
5090 uint64_t reserved_33_39 : 7;
5091 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
5092 uint64_t reserved_13_31 : 19;
5093 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
5094 uint64_t reserved_5_7 : 3;
5095 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
5098 uint64_t reserved_5_7 : 3;
5099 uint64_t gmx_drp : 5;
5100 uint64_t reserved_13_31 : 19;
5102 uint64_t reserved_33_39 : 7;
5104 uint64_t reserved_41_47 : 7;
5106 uint64_t reserved_49_63 : 15;
5110 typedef union cvmx_ciu2_en_ppx_ip3_pkt_w1s cvmx_ciu2_en_ppx_ip3_pkt_w1s_t;
5113 * cvmx_ciu2_en_pp#_ip3_rml
5115 union cvmx_ciu2_en_ppx_ip3_rml {
5117 struct cvmx_ciu2_en_ppx_ip3_rml_s {
5118 #ifdef __BIG_ENDIAN_BITFIELD
5119 uint64_t reserved_56_63 : 8;
5120 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
5121 uint64_t reserved_49_51 : 3;
5122 uint64_t l2c : 1; /**< L2C interrupt-enable */
5123 uint64_t reserved_41_47 : 7;
5124 uint64_t dfa : 1; /**< DFA interrupt-enable */
5125 uint64_t reserved_37_39 : 3;
5126 uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */
5127 uint64_t reserved_34_35 : 2;
5128 uint64_t dpi : 1; /**< DPI interrupt-enable */
5129 uint64_t sli : 1; /**< SLI interrupt-enable */
5130 uint64_t reserved_31_31 : 1;
5131 uint64_t key : 1; /**< KEY interrupt-enable */
5132 uint64_t rad : 1; /**< RAD interrupt-enable */
5133 uint64_t tim : 1; /**< TIM interrupt-enable */
5134 uint64_t reserved_25_27 : 3;
5135 uint64_t zip : 1; /**< ZIP interrupt-enable */
5136 uint64_t reserved_17_23 : 7;
5137 uint64_t sso : 1; /**< SSO err interrupt-enable */
5138 uint64_t reserved_8_15 : 8;
5139 uint64_t pko : 1; /**< PKO interrupt-enable */
5140 uint64_t pip : 1; /**< PIP interrupt-enable */
5141 uint64_t ipd : 1; /**< IPD interrupt-enable */
5142 uint64_t fpa : 1; /**< FPA interrupt-enable */
5143 uint64_t reserved_1_3 : 3;
5144 uint64_t iob : 1; /**< IOB interrupt-enable */
5147 uint64_t reserved_1_3 : 3;
5152 uint64_t reserved_8_15 : 8;
5154 uint64_t reserved_17_23 : 7;
5156 uint64_t reserved_25_27 : 3;
5160 uint64_t reserved_31_31 : 1;
5163 uint64_t reserved_34_35 : 2;
5164 uint64_t dpi_dma : 1;
5165 uint64_t reserved_37_39 : 3;
5167 uint64_t reserved_41_47 : 7;
5169 uint64_t reserved_49_51 : 3;
5171 uint64_t reserved_56_63 : 8;
5174 struct cvmx_ciu2_en_ppx_ip3_rml_s cn68xx;
5175 struct cvmx_ciu2_en_ppx_ip3_rml_cn68xxp1 {
5176 #ifdef __BIG_ENDIAN_BITFIELD
5177 uint64_t reserved_56_63 : 8;
5178 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
5179 uint64_t reserved_49_51 : 3;
5180 uint64_t l2c : 1; /**< L2C interrupt-enable */
5181 uint64_t reserved_41_47 : 7;
5182 uint64_t dfa : 1; /**< DFA interrupt-enable */
5183 uint64_t reserved_34_39 : 6;
5184 uint64_t dpi : 1; /**< DPI interrupt-enable */
5185 uint64_t sli : 1; /**< SLI interrupt-enable */
5186 uint64_t reserved_31_31 : 1;
5187 uint64_t key : 1; /**< KEY interrupt-enable */
5188 uint64_t rad : 1; /**< RAD interrupt-enable */
5189 uint64_t tim : 1; /**< TIM interrupt-enable */
5190 uint64_t reserved_25_27 : 3;
5191 uint64_t zip : 1; /**< ZIP interrupt-enable */
5192 uint64_t reserved_17_23 : 7;
5193 uint64_t sso : 1; /**< SSO err interrupt-enable */
5194 uint64_t reserved_8_15 : 8;
5195 uint64_t pko : 1; /**< PKO interrupt-enable */
5196 uint64_t pip : 1; /**< PIP interrupt-enable */
5197 uint64_t ipd : 1; /**< IPD interrupt-enable */
5198 uint64_t fpa : 1; /**< FPA interrupt-enable */
5199 uint64_t reserved_1_3 : 3;
5200 uint64_t iob : 1; /**< IOB interrupt-enable */
5203 uint64_t reserved_1_3 : 3;
5208 uint64_t reserved_8_15 : 8;
5210 uint64_t reserved_17_23 : 7;
5212 uint64_t reserved_25_27 : 3;
5216 uint64_t reserved_31_31 : 1;
5219 uint64_t reserved_34_39 : 6;
5221 uint64_t reserved_41_47 : 7;
5223 uint64_t reserved_49_51 : 3;
5225 uint64_t reserved_56_63 : 8;
5229 typedef union cvmx_ciu2_en_ppx_ip3_rml cvmx_ciu2_en_ppx_ip3_rml_t;
5232 * cvmx_ciu2_en_pp#_ip3_rml_w1c
5234 union cvmx_ciu2_en_ppx_ip3_rml_w1c {
5236 struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s {
5237 #ifdef __BIG_ENDIAN_BITFIELD
5238 uint64_t reserved_56_63 : 8;
5239 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
5240 uint64_t reserved_49_51 : 3;
5241 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
5242 uint64_t reserved_41_47 : 7;
5243 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
5244 uint64_t reserved_37_39 : 3;
5245 uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
5246 uint64_t reserved_34_35 : 2;
5247 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
5248 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
5249 uint64_t reserved_31_31 : 1;
5250 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
5251 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
5252 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
5253 uint64_t reserved_25_27 : 3;
5254 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
5255 uint64_t reserved_17_23 : 7;
5256 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
5257 uint64_t reserved_8_15 : 8;
5258 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
5259 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
5260 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
5261 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
5262 uint64_t reserved_1_3 : 3;
5263 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
5266 uint64_t reserved_1_3 : 3;
5271 uint64_t reserved_8_15 : 8;
5273 uint64_t reserved_17_23 : 7;
5275 uint64_t reserved_25_27 : 3;
5279 uint64_t reserved_31_31 : 1;
5282 uint64_t reserved_34_35 : 2;
5283 uint64_t dpi_dma : 1;
5284 uint64_t reserved_37_39 : 3;
5286 uint64_t reserved_41_47 : 7;
5288 uint64_t reserved_49_51 : 3;
5290 uint64_t reserved_56_63 : 8;
5293 struct cvmx_ciu2_en_ppx_ip3_rml_w1c_s cn68xx;
5294 struct cvmx_ciu2_en_ppx_ip3_rml_w1c_cn68xxp1 {
5295 #ifdef __BIG_ENDIAN_BITFIELD
5296 uint64_t reserved_56_63 : 8;
5297 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
5298 uint64_t reserved_49_51 : 3;
5299 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
5300 uint64_t reserved_41_47 : 7;
5301 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
5302 uint64_t reserved_34_39 : 6;
5303 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
5304 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
5305 uint64_t reserved_31_31 : 1;
5306 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
5307 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
5308 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
5309 uint64_t reserved_25_27 : 3;
5310 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
5311 uint64_t reserved_17_23 : 7;
5312 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
5313 uint64_t reserved_8_15 : 8;
5314 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
5315 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
5316 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
5317 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
5318 uint64_t reserved_1_3 : 3;
5319 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
5322 uint64_t reserved_1_3 : 3;
5327 uint64_t reserved_8_15 : 8;
5329 uint64_t reserved_17_23 : 7;
5331 uint64_t reserved_25_27 : 3;
5335 uint64_t reserved_31_31 : 1;
5338 uint64_t reserved_34_39 : 6;
5340 uint64_t reserved_41_47 : 7;
5342 uint64_t reserved_49_51 : 3;
5344 uint64_t reserved_56_63 : 8;
5348 typedef union cvmx_ciu2_en_ppx_ip3_rml_w1c cvmx_ciu2_en_ppx_ip3_rml_w1c_t;
5351 * cvmx_ciu2_en_pp#_ip3_rml_w1s
5353 union cvmx_ciu2_en_ppx_ip3_rml_w1s {
5355 struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s {
5356 #ifdef __BIG_ENDIAN_BITFIELD
5357 uint64_t reserved_56_63 : 8;
5358 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
5359 uint64_t reserved_49_51 : 3;
5360 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
5361 uint64_t reserved_41_47 : 7;
5362 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
5363 uint64_t reserved_37_39 : 3;
5364 uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
5365 uint64_t reserved_34_35 : 2;
5366 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
5367 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
5368 uint64_t reserved_31_31 : 1;
5369 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
5370 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
5371 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
5372 uint64_t reserved_25_27 : 3;
5373 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
5374 uint64_t reserved_17_23 : 7;
5375 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
5376 uint64_t reserved_8_15 : 8;
5377 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
5378 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
5379 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
5380 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
5381 uint64_t reserved_1_3 : 3;
5382 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
5385 uint64_t reserved_1_3 : 3;
5390 uint64_t reserved_8_15 : 8;
5392 uint64_t reserved_17_23 : 7;
5394 uint64_t reserved_25_27 : 3;
5398 uint64_t reserved_31_31 : 1;
5401 uint64_t reserved_34_35 : 2;
5402 uint64_t dpi_dma : 1;
5403 uint64_t reserved_37_39 : 3;
5405 uint64_t reserved_41_47 : 7;
5407 uint64_t reserved_49_51 : 3;
5409 uint64_t reserved_56_63 : 8;
5412 struct cvmx_ciu2_en_ppx_ip3_rml_w1s_s cn68xx;
5413 struct cvmx_ciu2_en_ppx_ip3_rml_w1s_cn68xxp1 {
5414 #ifdef __BIG_ENDIAN_BITFIELD
5415 uint64_t reserved_56_63 : 8;
5416 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
5417 uint64_t reserved_49_51 : 3;
5418 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
5419 uint64_t reserved_41_47 : 7;
5420 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
5421 uint64_t reserved_34_39 : 6;
5422 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
5423 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
5424 uint64_t reserved_31_31 : 1;
5425 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
5426 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
5427 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
5428 uint64_t reserved_25_27 : 3;
5429 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
5430 uint64_t reserved_17_23 : 7;
5431 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
5432 uint64_t reserved_8_15 : 8;
5433 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
5434 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
5435 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
5436 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
5437 uint64_t reserved_1_3 : 3;
5438 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
5441 uint64_t reserved_1_3 : 3;
5446 uint64_t reserved_8_15 : 8;
5448 uint64_t reserved_17_23 : 7;
5450 uint64_t reserved_25_27 : 3;
5454 uint64_t reserved_31_31 : 1;
5457 uint64_t reserved_34_39 : 6;
5459 uint64_t reserved_41_47 : 7;
5461 uint64_t reserved_49_51 : 3;
5463 uint64_t reserved_56_63 : 8;
5467 typedef union cvmx_ciu2_en_ppx_ip3_rml_w1s cvmx_ciu2_en_ppx_ip3_rml_w1s_t;
5470 * cvmx_ciu2_en_pp#_ip3_wdog
5472 union cvmx_ciu2_en_ppx_ip3_wdog {
5474 struct cvmx_ciu2_en_ppx_ip3_wdog_s {
5475 #ifdef __BIG_ENDIAN_BITFIELD
5476 uint64_t reserved_32_63 : 32;
5477 uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */
5480 uint64_t reserved_32_63 : 32;
5483 struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xx;
5484 struct cvmx_ciu2_en_ppx_ip3_wdog_s cn68xxp1;
5486 typedef union cvmx_ciu2_en_ppx_ip3_wdog cvmx_ciu2_en_ppx_ip3_wdog_t;
5489 * cvmx_ciu2_en_pp#_ip3_wdog_w1c
5491 union cvmx_ciu2_en_ppx_ip3_wdog_w1c {
5493 struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s {
5494 #ifdef __BIG_ENDIAN_BITFIELD
5495 uint64_t reserved_32_63 : 32;
5496 uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
5499 uint64_t reserved_32_63 : 32;
5502 struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xx;
5503 struct cvmx_ciu2_en_ppx_ip3_wdog_w1c_s cn68xxp1;
5505 typedef union cvmx_ciu2_en_ppx_ip3_wdog_w1c cvmx_ciu2_en_ppx_ip3_wdog_w1c_t;
5508 * cvmx_ciu2_en_pp#_ip3_wdog_w1s
5510 union cvmx_ciu2_en_ppx_ip3_wdog_w1s {
5512 struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s {
5513 #ifdef __BIG_ENDIAN_BITFIELD
5514 uint64_t reserved_32_63 : 32;
5515 uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
5518 uint64_t reserved_32_63 : 32;
5521 struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xx;
5522 struct cvmx_ciu2_en_ppx_ip3_wdog_w1s_s cn68xxp1;
5524 typedef union cvmx_ciu2_en_ppx_ip3_wdog_w1s cvmx_ciu2_en_ppx_ip3_wdog_w1s_t;
5527 * cvmx_ciu2_en_pp#_ip3_wrkq
5529 union cvmx_ciu2_en_ppx_ip3_wrkq {
5531 struct cvmx_ciu2_en_ppx_ip3_wrkq_s {
5532 #ifdef __BIG_ENDIAN_BITFIELD
5533 uint64_t workq : 64; /**< 64 work queue interrupt-enable */
5535 uint64_t workq : 64;
5538 struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xx;
5539 struct cvmx_ciu2_en_ppx_ip3_wrkq_s cn68xxp1;
5541 typedef union cvmx_ciu2_en_ppx_ip3_wrkq cvmx_ciu2_en_ppx_ip3_wrkq_t;
5544 * cvmx_ciu2_en_pp#_ip3_wrkq_w1c
5546 union cvmx_ciu2_en_ppx_ip3_wrkq_w1c {
5548 struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s {
5549 #ifdef __BIG_ENDIAN_BITFIELD
5550 uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
5551 For W1C bits, write 1 to clear the corresponding
5552 CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
5554 uint64_t workq : 64;
5557 struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xx;
5558 struct cvmx_ciu2_en_ppx_ip3_wrkq_w1c_s cn68xxp1;
5560 typedef union cvmx_ciu2_en_ppx_ip3_wrkq_w1c cvmx_ciu2_en_ppx_ip3_wrkq_w1c_t;
5563 * cvmx_ciu2_en_pp#_ip3_wrkq_w1s
5565 union cvmx_ciu2_en_ppx_ip3_wrkq_w1s {
5567 struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s {
5568 #ifdef __BIG_ENDIAN_BITFIELD
5569 uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
5570 1 bit/group. For all W1S bits, write 1 to enable
5571 corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
5572 writing 0 to retain previous value. */
5574 uint64_t workq : 64;
5577 struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xx;
5578 struct cvmx_ciu2_en_ppx_ip3_wrkq_w1s_s cn68xxp1;
5580 typedef union cvmx_ciu2_en_ppx_ip3_wrkq_w1s cvmx_ciu2_en_ppx_ip3_wrkq_w1s_t;
5583 * cvmx_ciu2_en_pp#_ip4_gpio
5585 union cvmx_ciu2_en_ppx_ip4_gpio {
5587 struct cvmx_ciu2_en_ppx_ip4_gpio_s {
5588 #ifdef __BIG_ENDIAN_BITFIELD
5589 uint64_t reserved_16_63 : 48;
5590 uint64_t gpio : 16; /**< 16 GPIO interrupt-enable */
5593 uint64_t reserved_16_63 : 48;
5596 struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xx;
5597 struct cvmx_ciu2_en_ppx_ip4_gpio_s cn68xxp1;
5599 typedef union cvmx_ciu2_en_ppx_ip4_gpio cvmx_ciu2_en_ppx_ip4_gpio_t;
5602 * cvmx_ciu2_en_pp#_ip4_gpio_w1c
5604 union cvmx_ciu2_en_ppx_ip4_gpio_w1c {
5606 struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s {
5607 #ifdef __BIG_ENDIAN_BITFIELD
5608 uint64_t reserved_16_63 : 48;
5609 uint64_t gpio : 16; /**< Write 1 to clear CIU2_EN_xx_yy_GPIO[GPIO] */
5612 uint64_t reserved_16_63 : 48;
5615 struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xx;
5616 struct cvmx_ciu2_en_ppx_ip4_gpio_w1c_s cn68xxp1;
5618 typedef union cvmx_ciu2_en_ppx_ip4_gpio_w1c cvmx_ciu2_en_ppx_ip4_gpio_w1c_t;
5621 * cvmx_ciu2_en_pp#_ip4_gpio_w1s
5623 union cvmx_ciu2_en_ppx_ip4_gpio_w1s {
5625 struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s {
5626 #ifdef __BIG_ENDIAN_BITFIELD
5627 uint64_t reserved_16_63 : 48;
5628 uint64_t gpio : 16; /**< 16 GPIO interrupt enable,write 1 to enable CIU2_EN */
5631 uint64_t reserved_16_63 : 48;
5634 struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xx;
5635 struct cvmx_ciu2_en_ppx_ip4_gpio_w1s_s cn68xxp1;
5637 typedef union cvmx_ciu2_en_ppx_ip4_gpio_w1s cvmx_ciu2_en_ppx_ip4_gpio_w1s_t;
5640 * cvmx_ciu2_en_pp#_ip4_io
5642 union cvmx_ciu2_en_ppx_ip4_io {
5644 struct cvmx_ciu2_en_ppx_ip4_io_s {
5645 #ifdef __BIG_ENDIAN_BITFIELD
5646 uint64_t reserved_34_63 : 30;
5647 uint64_t pem : 2; /**< PEMx interrupt-enable */
5648 uint64_t reserved_18_31 : 14;
5649 uint64_t pci_inta : 2; /**< PCI_INTA interrupt-enable */
5650 uint64_t reserved_13_15 : 3;
5651 uint64_t msired : 1; /**< MSI summary bit interrupt-enable
5652 This bit may not be functional in pass 1. */
5653 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI interrupt-enable */
5654 uint64_t reserved_4_7 : 4;
5655 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt-enable */
5657 uint64_t pci_intr : 4;
5658 uint64_t reserved_4_7 : 4;
5659 uint64_t pci_msi : 4;
5660 uint64_t msired : 1;
5661 uint64_t reserved_13_15 : 3;
5662 uint64_t pci_inta : 2;
5663 uint64_t reserved_18_31 : 14;
5665 uint64_t reserved_34_63 : 30;
5668 struct cvmx_ciu2_en_ppx_ip4_io_s cn68xx;
5669 struct cvmx_ciu2_en_ppx_ip4_io_s cn68xxp1;
5671 typedef union cvmx_ciu2_en_ppx_ip4_io cvmx_ciu2_en_ppx_ip4_io_t;
5674 * cvmx_ciu2_en_pp#_ip4_io_w1c
5676 union cvmx_ciu2_en_ppx_ip4_io_w1c {
5678 struct cvmx_ciu2_en_ppx_ip4_io_w1c_s {
5679 #ifdef __BIG_ENDIAN_BITFIELD
5680 uint64_t reserved_34_63 : 30;
5681 uint64_t pem : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PEM] */
5682 uint64_t reserved_18_31 : 14;
5683 uint64_t pci_inta : 2; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTA] */
5684 uint64_t reserved_13_15 : 3;
5685 uint64_t msired : 1; /**< Write 1 to clear CIU2_EN_xx_yy_IO[MSIRED]
5686 This bit may not be functional in pass 1. */
5687 uint64_t pci_msi : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_MSI] */
5688 uint64_t reserved_4_7 : 4;
5689 uint64_t pci_intr : 4; /**< Write 1 to clear CIU2_EN_xx_yy_IO[PCI_INTR] */
5691 uint64_t pci_intr : 4;
5692 uint64_t reserved_4_7 : 4;
5693 uint64_t pci_msi : 4;
5694 uint64_t msired : 1;
5695 uint64_t reserved_13_15 : 3;
5696 uint64_t pci_inta : 2;
5697 uint64_t reserved_18_31 : 14;
5699 uint64_t reserved_34_63 : 30;
5702 struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xx;
5703 struct cvmx_ciu2_en_ppx_ip4_io_w1c_s cn68xxp1;
5705 typedef union cvmx_ciu2_en_ppx_ip4_io_w1c cvmx_ciu2_en_ppx_ip4_io_w1c_t;
5708 * cvmx_ciu2_en_pp#_ip4_io_w1s
5710 union cvmx_ciu2_en_ppx_ip4_io_w1s {
5712 struct cvmx_ciu2_en_ppx_ip4_io_w1s_s {
5713 #ifdef __BIG_ENDIAN_BITFIELD
5714 uint64_t reserved_34_63 : 30;
5715 uint64_t pem : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PEM] */
5716 uint64_t reserved_18_31 : 14;
5717 uint64_t pci_inta : 2; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTA] */
5718 uint64_t reserved_13_15 : 3;
5719 uint64_t msired : 1; /**< Write 1 to enable CIU2_EN_xx_yy_IO[MSIRED]
5720 This bit may not be functional in pass 1. */
5721 uint64_t pci_msi : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_MSI] */
5722 uint64_t reserved_4_7 : 4;
5723 uint64_t pci_intr : 4; /**< Write 1 to enable CIU2_EN_xx_yy_IO[PCI_INTR] */
5725 uint64_t pci_intr : 4;
5726 uint64_t reserved_4_7 : 4;
5727 uint64_t pci_msi : 4;
5728 uint64_t msired : 1;
5729 uint64_t reserved_13_15 : 3;
5730 uint64_t pci_inta : 2;
5731 uint64_t reserved_18_31 : 14;
5733 uint64_t reserved_34_63 : 30;
5736 struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xx;
5737 struct cvmx_ciu2_en_ppx_ip4_io_w1s_s cn68xxp1;
5739 typedef union cvmx_ciu2_en_ppx_ip4_io_w1s cvmx_ciu2_en_ppx_ip4_io_w1s_t;
5742 * cvmx_ciu2_en_pp#_ip4_mbox
5744 union cvmx_ciu2_en_ppx_ip4_mbox {
5746 struct cvmx_ciu2_en_ppx_ip4_mbox_s {
5747 #ifdef __BIG_ENDIAN_BITFIELD
5748 uint64_t reserved_4_63 : 60;
5749 uint64_t mbox : 4; /**< Mailbox interrupt-enable, use with CIU2_MBOX
5750 to generate CIU2_SRC_xx_yy_MBOX */
5753 uint64_t reserved_4_63 : 60;
5756 struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xx;
5757 struct cvmx_ciu2_en_ppx_ip4_mbox_s cn68xxp1;
5759 typedef union cvmx_ciu2_en_ppx_ip4_mbox cvmx_ciu2_en_ppx_ip4_mbox_t;
5762 * cvmx_ciu2_en_pp#_ip4_mbox_w1c
5764 union cvmx_ciu2_en_ppx_ip4_mbox_w1c {
5766 struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s {
5767 #ifdef __BIG_ENDIAN_BITFIELD
5768 uint64_t reserved_4_63 : 60;
5769 uint64_t mbox : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MBOX[MBOX] */
5772 uint64_t reserved_4_63 : 60;
5775 struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xx;
5776 struct cvmx_ciu2_en_ppx_ip4_mbox_w1c_s cn68xxp1;
5778 typedef union cvmx_ciu2_en_ppx_ip4_mbox_w1c cvmx_ciu2_en_ppx_ip4_mbox_w1c_t;
5781 * cvmx_ciu2_en_pp#_ip4_mbox_w1s
5783 union cvmx_ciu2_en_ppx_ip4_mbox_w1s {
5785 struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s {
5786 #ifdef __BIG_ENDIAN_BITFIELD
5787 uint64_t reserved_4_63 : 60;
5788 uint64_t mbox : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MBOX[MBOX] */
5791 uint64_t reserved_4_63 : 60;
5794 struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xx;
5795 struct cvmx_ciu2_en_ppx_ip4_mbox_w1s_s cn68xxp1;
5797 typedef union cvmx_ciu2_en_ppx_ip4_mbox_w1s cvmx_ciu2_en_ppx_ip4_mbox_w1s_t;
5800 * cvmx_ciu2_en_pp#_ip4_mem
5802 union cvmx_ciu2_en_ppx_ip4_mem {
5804 struct cvmx_ciu2_en_ppx_ip4_mem_s {
5805 #ifdef __BIG_ENDIAN_BITFIELD
5806 uint64_t reserved_4_63 : 60;
5807 uint64_t lmc : 4; /**< LMC* interrupt-enable */
5810 uint64_t reserved_4_63 : 60;
5813 struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xx;
5814 struct cvmx_ciu2_en_ppx_ip4_mem_s cn68xxp1;
5816 typedef union cvmx_ciu2_en_ppx_ip4_mem cvmx_ciu2_en_ppx_ip4_mem_t;
5819 * cvmx_ciu2_en_pp#_ip4_mem_w1c
5821 union cvmx_ciu2_en_ppx_ip4_mem_w1c {
5823 struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s {
5824 #ifdef __BIG_ENDIAN_BITFIELD
5825 uint64_t reserved_4_63 : 60;
5826 uint64_t lmc : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MEM[LMC] */
5829 uint64_t reserved_4_63 : 60;
5832 struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xx;
5833 struct cvmx_ciu2_en_ppx_ip4_mem_w1c_s cn68xxp1;
5835 typedef union cvmx_ciu2_en_ppx_ip4_mem_w1c cvmx_ciu2_en_ppx_ip4_mem_w1c_t;
5838 * cvmx_ciu2_en_pp#_ip4_mem_w1s
5840 union cvmx_ciu2_en_ppx_ip4_mem_w1s {
5842 struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s {
5843 #ifdef __BIG_ENDIAN_BITFIELD
5844 uint64_t reserved_4_63 : 60;
5845 uint64_t lmc : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MEM[LMC] */
5848 uint64_t reserved_4_63 : 60;
5851 struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xx;
5852 struct cvmx_ciu2_en_ppx_ip4_mem_w1s_s cn68xxp1;
5854 typedef union cvmx_ciu2_en_ppx_ip4_mem_w1s cvmx_ciu2_en_ppx_ip4_mem_w1s_t;
5857 * cvmx_ciu2_en_pp#_ip4_mio
5859 union cvmx_ciu2_en_ppx_ip4_mio {
5861 struct cvmx_ciu2_en_ppx_ip4_mio_s {
5862 #ifdef __BIG_ENDIAN_BITFIELD
5863 uint64_t rst : 1; /**< MIO RST interrupt-enable */
5864 uint64_t reserved_49_62 : 14;
5865 uint64_t ptp : 1; /**< PTP interrupt-enable */
5866 uint64_t reserved_45_47 : 3;
5867 uint64_t usb_hci : 1; /**< USB HCI Interrupt-enable */
5868 uint64_t reserved_41_43 : 3;
5869 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt-enable */
5870 uint64_t reserved_38_39 : 2;
5871 uint64_t uart : 2; /**< Two UART interrupt-enable */
5872 uint64_t reserved_34_35 : 2;
5873 uint64_t twsi : 2; /**< TWSI x interrupt-enable */
5874 uint64_t reserved_19_31 : 13;
5875 uint64_t bootdma : 1; /**< Boot bus DMA engines interrupt-enable */
5876 uint64_t mio : 1; /**< MIO boot interrupt-enable */
5877 uint64_t nand : 1; /**< NAND Flash Controller interrupt-enable */
5878 uint64_t reserved_12_15 : 4;
5879 uint64_t timer : 4; /**< General timer interrupt-enable */
5880 uint64_t reserved_3_7 : 5;
5881 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt-enable */
5882 uint64_t ssoiq : 1; /**< SSO IQ interrupt-enable */
5883 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt-enable */
5885 uint64_t ipdppthr : 1;
5887 uint64_t ipd_drp : 1;
5888 uint64_t reserved_3_7 : 5;
5890 uint64_t reserved_12_15 : 4;
5893 uint64_t bootdma : 1;
5894 uint64_t reserved_19_31 : 13;
5896 uint64_t reserved_34_35 : 2;
5898 uint64_t reserved_38_39 : 2;
5899 uint64_t usb_uctl : 1;
5900 uint64_t reserved_41_43 : 3;
5901 uint64_t usb_hci : 1;
5902 uint64_t reserved_45_47 : 3;
5904 uint64_t reserved_49_62 : 14;
5908 struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xx;
5909 struct cvmx_ciu2_en_ppx_ip4_mio_s cn68xxp1;
5911 typedef union cvmx_ciu2_en_ppx_ip4_mio cvmx_ciu2_en_ppx_ip4_mio_t;
5914 * cvmx_ciu2_en_pp#_ip4_mio_w1c
5916 union cvmx_ciu2_en_ppx_ip4_mio_w1c {
5918 struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s {
5919 #ifdef __BIG_ENDIAN_BITFIELD
5920 uint64_t rst : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[RST] */
5921 uint64_t reserved_49_62 : 14;
5922 uint64_t ptp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[PTP] */
5923 uint64_t reserved_45_47 : 3;
5924 uint64_t usb_hci : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_HCI] */
5925 uint64_t reserved_41_43 : 3;
5926 uint64_t usb_uctl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[USB_UCTL] */
5927 uint64_t reserved_38_39 : 2;
5928 uint64_t uart : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[UART] */
5929 uint64_t reserved_34_35 : 2;
5930 uint64_t twsi : 2; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TWSI] */
5931 uint64_t reserved_19_31 : 13;
5932 uint64_t bootdma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[BOOTDMA] */
5933 uint64_t mio : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[MIO] */
5934 uint64_t nand : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[NAND] */
5935 uint64_t reserved_12_15 : 4;
5936 uint64_t timer : 4; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[TIMER] */
5937 uint64_t reserved_3_7 : 5;
5938 uint64_t ipd_drp : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPD_DRP] */
5939 uint64_t ssoiq : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[SSQIQ] */
5940 uint64_t ipdppthr : 1; /**< Write 1 to clear CIU2_EN_xx_yy_MIO[IPDPPTHR] */
5942 uint64_t ipdppthr : 1;
5944 uint64_t ipd_drp : 1;
5945 uint64_t reserved_3_7 : 5;
5947 uint64_t reserved_12_15 : 4;
5950 uint64_t bootdma : 1;
5951 uint64_t reserved_19_31 : 13;
5953 uint64_t reserved_34_35 : 2;
5955 uint64_t reserved_38_39 : 2;
5956 uint64_t usb_uctl : 1;
5957 uint64_t reserved_41_43 : 3;
5958 uint64_t usb_hci : 1;
5959 uint64_t reserved_45_47 : 3;
5961 uint64_t reserved_49_62 : 14;
5965 struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xx;
5966 struct cvmx_ciu2_en_ppx_ip4_mio_w1c_s cn68xxp1;
5968 typedef union cvmx_ciu2_en_ppx_ip4_mio_w1c cvmx_ciu2_en_ppx_ip4_mio_w1c_t;
5971 * cvmx_ciu2_en_pp#_ip4_mio_w1s
5973 union cvmx_ciu2_en_ppx_ip4_mio_w1s {
5975 struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s {
5976 #ifdef __BIG_ENDIAN_BITFIELD
5977 uint64_t rst : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[RST] */
5978 uint64_t reserved_49_62 : 14;
5979 uint64_t ptp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[PTP] */
5980 uint64_t reserved_45_47 : 3;
5981 uint64_t usb_hci : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_HCI] */
5982 uint64_t reserved_41_43 : 3;
5983 uint64_t usb_uctl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[USB_UCTL] */
5984 uint64_t reserved_38_39 : 2;
5985 uint64_t uart : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[UART] */
5986 uint64_t reserved_34_35 : 2;
5987 uint64_t twsi : 2; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TWSI] */
5988 uint64_t reserved_19_31 : 13;
5989 uint64_t bootdma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[BOOTDMA] */
5990 uint64_t mio : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[MIO] */
5991 uint64_t nand : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[NAND] */
5992 uint64_t reserved_12_15 : 4;
5993 uint64_t timer : 4; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[TIMER] */
5994 uint64_t reserved_3_7 : 5;
5995 uint64_t ipd_drp : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPD_DRP] */
5996 uint64_t ssoiq : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[SSQIQ] */
5997 uint64_t ipdppthr : 1; /**< Write 1 to enable CIU2_EN_xx_yy_MIO[IPDPPTHR] */
5999 uint64_t ipdppthr : 1;
6001 uint64_t ipd_drp : 1;
6002 uint64_t reserved_3_7 : 5;
6004 uint64_t reserved_12_15 : 4;
6007 uint64_t bootdma : 1;
6008 uint64_t reserved_19_31 : 13;
6010 uint64_t reserved_34_35 : 2;
6012 uint64_t reserved_38_39 : 2;
6013 uint64_t usb_uctl : 1;
6014 uint64_t reserved_41_43 : 3;
6015 uint64_t usb_hci : 1;
6016 uint64_t reserved_45_47 : 3;
6018 uint64_t reserved_49_62 : 14;
6022 struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xx;
6023 struct cvmx_ciu2_en_ppx_ip4_mio_w1s_s cn68xxp1;
6025 typedef union cvmx_ciu2_en_ppx_ip4_mio_w1s cvmx_ciu2_en_ppx_ip4_mio_w1s_t;
6028 * cvmx_ciu2_en_pp#_ip4_pkt
6030 union cvmx_ciu2_en_ppx_ip4_pkt {
6032 struct cvmx_ciu2_en_ppx_ip4_pkt_s {
6033 #ifdef __BIG_ENDIAN_BITFIELD
6034 uint64_t reserved_54_63 : 10;
6035 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt-enable */
6036 uint64_t reserved_49_51 : 3;
6037 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
6038 uint64_t reserved_41_47 : 7;
6039 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
6040 uint64_t reserved_33_39 : 7;
6041 uint64_t agl : 1; /**< AGL interrupt-enable */
6042 uint64_t reserved_13_31 : 19;
6043 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
6044 uint64_t reserved_5_7 : 3;
6045 uint64_t agx : 5; /**< GMX interrupt-enable */
6048 uint64_t reserved_5_7 : 3;
6049 uint64_t gmx_drp : 5;
6050 uint64_t reserved_13_31 : 19;
6052 uint64_t reserved_33_39 : 7;
6054 uint64_t reserved_41_47 : 7;
6056 uint64_t reserved_49_51 : 3;
6057 uint64_t ilk_drp : 2;
6058 uint64_t reserved_54_63 : 10;
6061 struct cvmx_ciu2_en_ppx_ip4_pkt_s cn68xx;
6062 struct cvmx_ciu2_en_ppx_ip4_pkt_cn68xxp1 {
6063 #ifdef __BIG_ENDIAN_BITFIELD
6064 uint64_t reserved_49_63 : 15;
6065 uint64_t ilk : 1; /**< ILK interface interrupt-enable */
6066 uint64_t reserved_41_47 : 7;
6067 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x interrupt-enable */
6068 uint64_t reserved_33_39 : 7;
6069 uint64_t agl : 1; /**< AGL interrupt-enable */
6070 uint64_t reserved_13_31 : 19;
6071 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt-enable */
6072 uint64_t reserved_5_7 : 3;
6073 uint64_t agx : 5; /**< GMX interrupt-enable */
6076 uint64_t reserved_5_7 : 3;
6077 uint64_t gmx_drp : 5;
6078 uint64_t reserved_13_31 : 19;
6080 uint64_t reserved_33_39 : 7;
6082 uint64_t reserved_41_47 : 7;
6084 uint64_t reserved_49_63 : 15;
6088 typedef union cvmx_ciu2_en_ppx_ip4_pkt cvmx_ciu2_en_ppx_ip4_pkt_t;
6091 * cvmx_ciu2_en_pp#_ip4_pkt_w1c
6093 union cvmx_ciu2_en_ppx_ip4_pkt_w1c {
6095 struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s {
6096 #ifdef __BIG_ENDIAN_BITFIELD
6097 uint64_t reserved_54_63 : 10;
6098 uint64_t ilk_drp : 2; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK_DRP] */
6099 uint64_t reserved_49_51 : 3;
6100 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
6101 uint64_t reserved_41_47 : 7;
6102 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
6103 uint64_t reserved_33_39 : 7;
6104 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
6105 uint64_t reserved_13_31 : 19;
6106 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
6107 uint64_t reserved_5_7 : 3;
6108 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
6111 uint64_t reserved_5_7 : 3;
6112 uint64_t gmx_drp : 5;
6113 uint64_t reserved_13_31 : 19;
6115 uint64_t reserved_33_39 : 7;
6117 uint64_t reserved_41_47 : 7;
6119 uint64_t reserved_49_51 : 3;
6120 uint64_t ilk_drp : 2;
6121 uint64_t reserved_54_63 : 10;
6124 struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_s cn68xx;
6125 struct cvmx_ciu2_en_ppx_ip4_pkt_w1c_cn68xxp1 {
6126 #ifdef __BIG_ENDIAN_BITFIELD
6127 uint64_t reserved_49_63 : 15;
6128 uint64_t ilk : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[ILK] */
6129 uint64_t reserved_41_47 : 7;
6130 uint64_t mii : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[MII] */
6131 uint64_t reserved_33_39 : 7;
6132 uint64_t agl : 1; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGL] */
6133 uint64_t reserved_13_31 : 19;
6134 uint64_t gmx_drp : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[GMX_DRP] */
6135 uint64_t reserved_5_7 : 3;
6136 uint64_t agx : 5; /**< Write 1 to clear CIU2_EN_xx_yy_PKT[AGX] */
6139 uint64_t reserved_5_7 : 3;
6140 uint64_t gmx_drp : 5;
6141 uint64_t reserved_13_31 : 19;
6143 uint64_t reserved_33_39 : 7;
6145 uint64_t reserved_41_47 : 7;
6147 uint64_t reserved_49_63 : 15;
6151 typedef union cvmx_ciu2_en_ppx_ip4_pkt_w1c cvmx_ciu2_en_ppx_ip4_pkt_w1c_t;
6154 * cvmx_ciu2_en_pp#_ip4_pkt_w1s
6156 union cvmx_ciu2_en_ppx_ip4_pkt_w1s {
6158 struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s {
6159 #ifdef __BIG_ENDIAN_BITFIELD
6160 uint64_t reserved_54_63 : 10;
6161 uint64_t ilk_drp : 2; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK_DRP] */
6162 uint64_t reserved_49_51 : 3;
6163 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
6164 uint64_t reserved_41_47 : 7;
6165 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
6166 uint64_t reserved_33_39 : 7;
6167 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
6168 uint64_t reserved_13_31 : 19;
6169 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
6170 uint64_t reserved_5_7 : 3;
6171 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
6174 uint64_t reserved_5_7 : 3;
6175 uint64_t gmx_drp : 5;
6176 uint64_t reserved_13_31 : 19;
6178 uint64_t reserved_33_39 : 7;
6180 uint64_t reserved_41_47 : 7;
6182 uint64_t reserved_49_51 : 3;
6183 uint64_t ilk_drp : 2;
6184 uint64_t reserved_54_63 : 10;
6187 struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_s cn68xx;
6188 struct cvmx_ciu2_en_ppx_ip4_pkt_w1s_cn68xxp1 {
6189 #ifdef __BIG_ENDIAN_BITFIELD
6190 uint64_t reserved_49_63 : 15;
6191 uint64_t ilk : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[ILK] */
6192 uint64_t reserved_41_47 : 7;
6193 uint64_t mii : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[MII] */
6194 uint64_t reserved_33_39 : 7;
6195 uint64_t agl : 1; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGL] */
6196 uint64_t reserved_13_31 : 19;
6197 uint64_t gmx_drp : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[GMX_DRP] */
6198 uint64_t reserved_5_7 : 3;
6199 uint64_t agx : 5; /**< Write 1 to enable CIU2_EN_xx_yy_PKT[AGX] */
6202 uint64_t reserved_5_7 : 3;
6203 uint64_t gmx_drp : 5;
6204 uint64_t reserved_13_31 : 19;
6206 uint64_t reserved_33_39 : 7;
6208 uint64_t reserved_41_47 : 7;
6210 uint64_t reserved_49_63 : 15;
6214 typedef union cvmx_ciu2_en_ppx_ip4_pkt_w1s cvmx_ciu2_en_ppx_ip4_pkt_w1s_t;
6217 * cvmx_ciu2_en_pp#_ip4_rml
6219 union cvmx_ciu2_en_ppx_ip4_rml {
6221 struct cvmx_ciu2_en_ppx_ip4_rml_s {
6222 #ifdef __BIG_ENDIAN_BITFIELD
6223 uint64_t reserved_56_63 : 8;
6224 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
6225 uint64_t reserved_49_51 : 3;
6226 uint64_t l2c : 1; /**< L2C interrupt-enable */
6227 uint64_t reserved_41_47 : 7;
6228 uint64_t dfa : 1; /**< DFA interrupt-enable */
6229 uint64_t reserved_37_39 : 3;
6230 uint64_t dpi_dma : 1; /**< DPI DMA interrupt-enable */
6231 uint64_t reserved_34_35 : 2;
6232 uint64_t dpi : 1; /**< DPI interrupt-enable */
6233 uint64_t sli : 1; /**< SLI interrupt-enable */
6234 uint64_t reserved_31_31 : 1;
6235 uint64_t key : 1; /**< KEY interrupt-enable */
6236 uint64_t rad : 1; /**< RAD interrupt-enable */
6237 uint64_t tim : 1; /**< TIM interrupt-enable */
6238 uint64_t reserved_25_27 : 3;
6239 uint64_t zip : 1; /**< ZIP interrupt-enable */
6240 uint64_t reserved_17_23 : 7;
6241 uint64_t sso : 1; /**< SSO err interrupt-enable */
6242 uint64_t reserved_8_15 : 8;
6243 uint64_t pko : 1; /**< PKO interrupt-enable */
6244 uint64_t pip : 1; /**< PIP interrupt-enable */
6245 uint64_t ipd : 1; /**< IPD interrupt-enable */
6246 uint64_t fpa : 1; /**< FPA interrupt-enable */
6247 uint64_t reserved_1_3 : 3;
6248 uint64_t iob : 1; /**< IOB interrupt-enable */
6251 uint64_t reserved_1_3 : 3;
6256 uint64_t reserved_8_15 : 8;
6258 uint64_t reserved_17_23 : 7;
6260 uint64_t reserved_25_27 : 3;
6264 uint64_t reserved_31_31 : 1;
6267 uint64_t reserved_34_35 : 2;
6268 uint64_t dpi_dma : 1;
6269 uint64_t reserved_37_39 : 3;
6271 uint64_t reserved_41_47 : 7;
6273 uint64_t reserved_49_51 : 3;
6275 uint64_t reserved_56_63 : 8;
6278 struct cvmx_ciu2_en_ppx_ip4_rml_s cn68xx;
6279 struct cvmx_ciu2_en_ppx_ip4_rml_cn68xxp1 {
6280 #ifdef __BIG_ENDIAN_BITFIELD
6281 uint64_t reserved_56_63 : 8;
6282 uint64_t trace : 4; /**< Trace buffer interrupt-enable */
6283 uint64_t reserved_49_51 : 3;
6284 uint64_t l2c : 1; /**< L2C interrupt-enable */
6285 uint64_t reserved_41_47 : 7;
6286 uint64_t dfa : 1; /**< DFA interrupt-enable */
6287 uint64_t reserved_34_39 : 6;
6288 uint64_t dpi : 1; /**< DPI interrupt-enable */
6289 uint64_t sli : 1; /**< SLI interrupt-enable */
6290 uint64_t reserved_31_31 : 1;
6291 uint64_t key : 1; /**< KEY interrupt-enable */
6292 uint64_t rad : 1; /**< RAD interrupt-enable */
6293 uint64_t tim : 1; /**< TIM interrupt-enable */
6294 uint64_t reserved_25_27 : 3;
6295 uint64_t zip : 1; /**< ZIP interrupt-enable */
6296 uint64_t reserved_17_23 : 7;
6297 uint64_t sso : 1; /**< SSO err interrupt-enable */
6298 uint64_t reserved_8_15 : 8;
6299 uint64_t pko : 1; /**< PKO interrupt-enable */
6300 uint64_t pip : 1; /**< PIP interrupt-enable */
6301 uint64_t ipd : 1; /**< IPD interrupt-enable */
6302 uint64_t fpa : 1; /**< FPA interrupt-enable */
6303 uint64_t reserved_1_3 : 3;
6304 uint64_t iob : 1; /**< IOB interrupt-enable */
6307 uint64_t reserved_1_3 : 3;
6312 uint64_t reserved_8_15 : 8;
6314 uint64_t reserved_17_23 : 7;
6316 uint64_t reserved_25_27 : 3;
6320 uint64_t reserved_31_31 : 1;
6323 uint64_t reserved_34_39 : 6;
6325 uint64_t reserved_41_47 : 7;
6327 uint64_t reserved_49_51 : 3;
6329 uint64_t reserved_56_63 : 8;
6333 typedef union cvmx_ciu2_en_ppx_ip4_rml cvmx_ciu2_en_ppx_ip4_rml_t;
6336 * cvmx_ciu2_en_pp#_ip4_rml_w1c
6338 union cvmx_ciu2_en_ppx_ip4_rml_w1c {
6340 struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s {
6341 #ifdef __BIG_ENDIAN_BITFIELD
6342 uint64_t reserved_56_63 : 8;
6343 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
6344 uint64_t reserved_49_51 : 3;
6345 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
6346 uint64_t reserved_41_47 : 7;
6347 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
6348 uint64_t reserved_37_39 : 3;
6349 uint64_t dpi_dma : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI_DMA] */
6350 uint64_t reserved_34_35 : 2;
6351 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
6352 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
6353 uint64_t reserved_31_31 : 1;
6354 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
6355 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
6356 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
6357 uint64_t reserved_25_27 : 3;
6358 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
6359 uint64_t reserved_17_23 : 7;
6360 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
6361 uint64_t reserved_8_15 : 8;
6362 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
6363 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
6364 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
6365 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
6366 uint64_t reserved_1_3 : 3;
6367 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
6370 uint64_t reserved_1_3 : 3;
6375 uint64_t reserved_8_15 : 8;
6377 uint64_t reserved_17_23 : 7;
6379 uint64_t reserved_25_27 : 3;
6383 uint64_t reserved_31_31 : 1;
6386 uint64_t reserved_34_35 : 2;
6387 uint64_t dpi_dma : 1;
6388 uint64_t reserved_37_39 : 3;
6390 uint64_t reserved_41_47 : 7;
6392 uint64_t reserved_49_51 : 3;
6394 uint64_t reserved_56_63 : 8;
6397 struct cvmx_ciu2_en_ppx_ip4_rml_w1c_s cn68xx;
6398 struct cvmx_ciu2_en_ppx_ip4_rml_w1c_cn68xxp1 {
6399 #ifdef __BIG_ENDIAN_BITFIELD
6400 uint64_t reserved_56_63 : 8;
6401 uint64_t trace : 4; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TRACE] */
6402 uint64_t reserved_49_51 : 3;
6403 uint64_t l2c : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[L2C] */
6404 uint64_t reserved_41_47 : 7;
6405 uint64_t dfa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DFA] */
6406 uint64_t reserved_34_39 : 6;
6407 uint64_t dpi : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[DPI] */
6408 uint64_t sli : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SLI] */
6409 uint64_t reserved_31_31 : 1;
6410 uint64_t key : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[KEY] */
6411 uint64_t rad : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[RAD] */
6412 uint64_t tim : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[TIM] */
6413 uint64_t reserved_25_27 : 3;
6414 uint64_t zip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[ZIP] */
6415 uint64_t reserved_17_23 : 7;
6416 uint64_t sso : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[SSO] */
6417 uint64_t reserved_8_15 : 8;
6418 uint64_t pko : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PKO] */
6419 uint64_t pip : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[PIP] */
6420 uint64_t ipd : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IPD] */
6421 uint64_t fpa : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[FPA] */
6422 uint64_t reserved_1_3 : 3;
6423 uint64_t iob : 1; /**< Write 1 to clear CIU2_EN_xx_yy_RML[IOB] */
6426 uint64_t reserved_1_3 : 3;
6431 uint64_t reserved_8_15 : 8;
6433 uint64_t reserved_17_23 : 7;
6435 uint64_t reserved_25_27 : 3;
6439 uint64_t reserved_31_31 : 1;
6442 uint64_t reserved_34_39 : 6;
6444 uint64_t reserved_41_47 : 7;
6446 uint64_t reserved_49_51 : 3;
6448 uint64_t reserved_56_63 : 8;
6452 typedef union cvmx_ciu2_en_ppx_ip4_rml_w1c cvmx_ciu2_en_ppx_ip4_rml_w1c_t;
6455 * cvmx_ciu2_en_pp#_ip4_rml_w1s
6457 union cvmx_ciu2_en_ppx_ip4_rml_w1s {
6459 struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s {
6460 #ifdef __BIG_ENDIAN_BITFIELD
6461 uint64_t reserved_56_63 : 8;
6462 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
6463 uint64_t reserved_49_51 : 3;
6464 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
6465 uint64_t reserved_41_47 : 7;
6466 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
6467 uint64_t reserved_37_39 : 3;
6468 uint64_t dpi_dma : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI_DMA] */
6469 uint64_t reserved_34_35 : 2;
6470 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
6471 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
6472 uint64_t reserved_31_31 : 1;
6473 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
6474 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
6475 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
6476 uint64_t reserved_25_27 : 3;
6477 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
6478 uint64_t reserved_17_23 : 7;
6479 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
6480 uint64_t reserved_8_15 : 8;
6481 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
6482 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
6483 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
6484 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
6485 uint64_t reserved_1_3 : 3;
6486 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
6489 uint64_t reserved_1_3 : 3;
6494 uint64_t reserved_8_15 : 8;
6496 uint64_t reserved_17_23 : 7;
6498 uint64_t reserved_25_27 : 3;
6502 uint64_t reserved_31_31 : 1;
6505 uint64_t reserved_34_35 : 2;
6506 uint64_t dpi_dma : 1;
6507 uint64_t reserved_37_39 : 3;
6509 uint64_t reserved_41_47 : 7;
6511 uint64_t reserved_49_51 : 3;
6513 uint64_t reserved_56_63 : 8;
6516 struct cvmx_ciu2_en_ppx_ip4_rml_w1s_s cn68xx;
6517 struct cvmx_ciu2_en_ppx_ip4_rml_w1s_cn68xxp1 {
6518 #ifdef __BIG_ENDIAN_BITFIELD
6519 uint64_t reserved_56_63 : 8;
6520 uint64_t trace : 4; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TRACE] */
6521 uint64_t reserved_49_51 : 3;
6522 uint64_t l2c : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[L2C] */
6523 uint64_t reserved_41_47 : 7;
6524 uint64_t dfa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DFA] */
6525 uint64_t reserved_34_39 : 6;
6526 uint64_t dpi : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[DPI] */
6527 uint64_t sli : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SLI] */
6528 uint64_t reserved_31_31 : 1;
6529 uint64_t key : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[KEY] */
6530 uint64_t rad : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[RAD] */
6531 uint64_t tim : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[TIM] */
6532 uint64_t reserved_25_27 : 3;
6533 uint64_t zip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[ZIP] */
6534 uint64_t reserved_17_23 : 7;
6535 uint64_t sso : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[SSO] */
6536 uint64_t reserved_8_15 : 8;
6537 uint64_t pko : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PKO] */
6538 uint64_t pip : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[PIP] */
6539 uint64_t ipd : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IPD] */
6540 uint64_t fpa : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[FPA] */
6541 uint64_t reserved_1_3 : 3;
6542 uint64_t iob : 1; /**< Write 1 to enable CIU2_EN_xx_yy_RML[IOB] */
6545 uint64_t reserved_1_3 : 3;
6550 uint64_t reserved_8_15 : 8;
6552 uint64_t reserved_17_23 : 7;
6554 uint64_t reserved_25_27 : 3;
6558 uint64_t reserved_31_31 : 1;
6561 uint64_t reserved_34_39 : 6;
6563 uint64_t reserved_41_47 : 7;
6565 uint64_t reserved_49_51 : 3;
6567 uint64_t reserved_56_63 : 8;
6571 typedef union cvmx_ciu2_en_ppx_ip4_rml_w1s cvmx_ciu2_en_ppx_ip4_rml_w1s_t;
6574 * cvmx_ciu2_en_pp#_ip4_wdog
6576 union cvmx_ciu2_en_ppx_ip4_wdog {
6578 struct cvmx_ciu2_en_ppx_ip4_wdog_s {
6579 #ifdef __BIG_ENDIAN_BITFIELD
6580 uint64_t reserved_32_63 : 32;
6581 uint64_t wdog : 32; /**< 32 watchdog interrupt-enable */
6584 uint64_t reserved_32_63 : 32;
6587 struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xx;
6588 struct cvmx_ciu2_en_ppx_ip4_wdog_s cn68xxp1;
6590 typedef union cvmx_ciu2_en_ppx_ip4_wdog cvmx_ciu2_en_ppx_ip4_wdog_t;
6593 * cvmx_ciu2_en_pp#_ip4_wdog_w1c
6595 union cvmx_ciu2_en_ppx_ip4_wdog_w1c {
6597 struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s {
6598 #ifdef __BIG_ENDIAN_BITFIELD
6599 uint64_t reserved_32_63 : 32;
6600 uint64_t wdog : 32; /**< write 1 to clear CIU2_EN_xx_yy_WDOG */
6603 uint64_t reserved_32_63 : 32;
6606 struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xx;
6607 struct cvmx_ciu2_en_ppx_ip4_wdog_w1c_s cn68xxp1;
6609 typedef union cvmx_ciu2_en_ppx_ip4_wdog_w1c cvmx_ciu2_en_ppx_ip4_wdog_w1c_t;
6612 * cvmx_ciu2_en_pp#_ip4_wdog_w1s
6614 union cvmx_ciu2_en_ppx_ip4_wdog_w1s {
6616 struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s {
6617 #ifdef __BIG_ENDIAN_BITFIELD
6618 uint64_t reserved_32_63 : 32;
6619 uint64_t wdog : 32; /**< Write 1 to enable CIU2_EN_xx_yy_WDOG[WDOG] */
6622 uint64_t reserved_32_63 : 32;
6625 struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xx;
6626 struct cvmx_ciu2_en_ppx_ip4_wdog_w1s_s cn68xxp1;
6628 typedef union cvmx_ciu2_en_ppx_ip4_wdog_w1s cvmx_ciu2_en_ppx_ip4_wdog_w1s_t;
6631 * cvmx_ciu2_en_pp#_ip4_wrkq
6633 union cvmx_ciu2_en_ppx_ip4_wrkq {
6635 struct cvmx_ciu2_en_ppx_ip4_wrkq_s {
6636 #ifdef __BIG_ENDIAN_BITFIELD
6637 uint64_t workq : 64; /**< 64 work queue interrupt-enable */
6639 uint64_t workq : 64;
6642 struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xx;
6643 struct cvmx_ciu2_en_ppx_ip4_wrkq_s cn68xxp1;
6645 typedef union cvmx_ciu2_en_ppx_ip4_wrkq cvmx_ciu2_en_ppx_ip4_wrkq_t;
6648 * cvmx_ciu2_en_pp#_ip4_wrkq_w1c
6650 union cvmx_ciu2_en_ppx_ip4_wrkq_w1c {
6652 struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s {
6653 #ifdef __BIG_ENDIAN_BITFIELD
6654 uint64_t workq : 64; /**< Write 1 to clear CIU2_EN_xx_yy_WRKQ[WORKQ]
6655 For W1C bits, write 1 to clear the corresponding
6656 CIU2_EN_xx_yy_WRKQ,write 0 to retain previous value */
6658 uint64_t workq : 64;
6661 struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xx;
6662 struct cvmx_ciu2_en_ppx_ip4_wrkq_w1c_s cn68xxp1;
6664 typedef union cvmx_ciu2_en_ppx_ip4_wrkq_w1c cvmx_ciu2_en_ppx_ip4_wrkq_w1c_t;
6667 * cvmx_ciu2_en_pp#_ip4_wrkq_w1s
6669 union cvmx_ciu2_en_ppx_ip4_wrkq_w1s {
6671 struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s {
6672 #ifdef __BIG_ENDIAN_BITFIELD
6673 uint64_t workq : 64; /**< Write 1 to enable CIU2_EN_xx_yy_WRKQ[WORKQ]
6674 1 bit/group. For all W1S bits, write 1 to enable
6675 corresponding CIU2_EN_xx_yy_WRKQ[WORKQ] bit,
6676 writing 0 to retain previous value. */
6678 uint64_t workq : 64;
6681 struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xx;
6682 struct cvmx_ciu2_en_ppx_ip4_wrkq_w1s_s cn68xxp1;
6684 typedef union cvmx_ciu2_en_ppx_ip4_wrkq_w1s cvmx_ciu2_en_ppx_ip4_wrkq_w1s_t;
6687 * cvmx_ciu2_intr_ciu_ready
6689 union cvmx_ciu2_intr_ciu_ready {
6691 struct cvmx_ciu2_intr_ciu_ready_s {
6692 #ifdef __BIG_ENDIAN_BITFIELD
6693 uint64_t reserved_1_63 : 63;
6694 uint64_t ready : 1; /**< Because of the delay of the IRQ updates which may
6695 take about 200 sclk cycles, software should read
6696 this register after servicing interrupts and wait
6697 for response before enabling interrupt watching.
6698 Or, the outdated interrupt will show up again.
6699 The read back data return when all interrupts have
6700 been serviced, and read back data is always zero.
6701 In o68 pass2, CIU_READY gets replaced by CIU2_ACK
6702 This becomes an internal debug feature. */
6705 uint64_t reserved_1_63 : 63;
6708 struct cvmx_ciu2_intr_ciu_ready_s cn68xx;
6709 struct cvmx_ciu2_intr_ciu_ready_s cn68xxp1;
6711 typedef union cvmx_ciu2_intr_ciu_ready cvmx_ciu2_intr_ciu_ready_t;
6714 * cvmx_ciu2_intr_ram_ecc_ctl
6716 union cvmx_ciu2_intr_ram_ecc_ctl {
6718 struct cvmx_ciu2_intr_ram_ecc_ctl_s {
6719 #ifdef __BIG_ENDIAN_BITFIELD
6720 uint64_t reserved_3_63 : 61;
6721 uint64_t flip_synd : 2; /**< Testing feature. Flip Syndrom to generate single or
6722 double bit error. FLIP_SYND[0] generate even number
6723 -ed bits error,FLIP_SYND[1] generate odd bits error */
6724 uint64_t ecc_ena : 1; /**< ECC Enable: When set will enable the 9bit ECC
6725 check/correct logic for CIU interrupt enable RAM.
6726 With ECC enabled, the ECC code will be generated
6727 and written in the memory and then later on reads,
6728 used to check and correct Single bit error and
6729 detect Double Bit error. */
6731 uint64_t ecc_ena : 1;
6732 uint64_t flip_synd : 2;
6733 uint64_t reserved_3_63 : 61;
6736 struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xx;
6737 struct cvmx_ciu2_intr_ram_ecc_ctl_s cn68xxp1;
6739 typedef union cvmx_ciu2_intr_ram_ecc_ctl cvmx_ciu2_intr_ram_ecc_ctl_t;
6742 * cvmx_ciu2_intr_ram_ecc_st
6744 union cvmx_ciu2_intr_ram_ecc_st {
6746 struct cvmx_ciu2_intr_ram_ecc_st_s {
6747 #ifdef __BIG_ENDIAN_BITFIELD
6748 uint64_t reserved_23_63 : 41;
6749 uint64_t addr : 7; /**< Latch the address for latest sde/dde occured
6750 The value only 0-98 indicates the different 98 IRQs
6751 Software can read all corresponding corrected value
6752 from CIU2_EN_PPX_IPx_*** or CIU2_EN_IOX_INT_*** and
6753 rewite to the same address to corrected the bit err */
6754 uint64_t reserved_13_15 : 3;
6755 uint64_t syndrom : 9; /**< Report the latest error syndrom */
6756 uint64_t reserved_2_3 : 2;
6757 uint64_t dbe : 1; /**< Double bit error observed. Write '1' to clear */
6758 uint64_t sbe : 1; /**< Single bit error observed. Write '1' to clear */
6762 uint64_t reserved_2_3 : 2;
6763 uint64_t syndrom : 9;
6764 uint64_t reserved_13_15 : 3;
6766 uint64_t reserved_23_63 : 41;
6769 struct cvmx_ciu2_intr_ram_ecc_st_s cn68xx;
6770 struct cvmx_ciu2_intr_ram_ecc_st_s cn68xxp1;
6772 typedef union cvmx_ciu2_intr_ram_ecc_st cvmx_ciu2_intr_ram_ecc_st_t;
6775 * cvmx_ciu2_intr_slowdown
6777 union cvmx_ciu2_intr_slowdown {
6779 struct cvmx_ciu2_intr_slowdown_s {
6780 #ifdef __BIG_ENDIAN_BITFIELD
6781 uint64_t reserved_3_63 : 61;
6782 uint64_t ctl : 3; /**< Slowdown CIU interrupt walker processing time.
6783 IRQ2/3/4 for all 32 PPs are sent to PP (MRC) in
6784 a serial bus to reduce global routing. There is
6785 no backpressure mechanism designed for this scheme.
6786 It will be only a problem when sclk is faster, this
6787 Control will process 1 interrupt in 2^(CTL) sclks
6788 With different setting, clock rate ratio can handle
6789 SLOWDOWN sclk_freq/aclk_freq ratio
6795 uint64_t reserved_3_63 : 61;
6798 struct cvmx_ciu2_intr_slowdown_s cn68xx;
6799 struct cvmx_ciu2_intr_slowdown_s cn68xxp1;
6801 typedef union cvmx_ciu2_intr_slowdown cvmx_ciu2_intr_slowdown_t;
6804 * cvmx_ciu2_msi_rcv#
6806 * CIU2_MSI_RCV Received MSI state bits (Pass 2)
6809 union cvmx_ciu2_msi_rcvx {
6811 struct cvmx_ciu2_msi_rcvx_s {
6812 #ifdef __BIG_ENDIAN_BITFIELD
6813 uint64_t reserved_1_63 : 63;
6814 uint64_t msi_rcv : 1; /**< MSI state bit, set on MSI delivery or by software
6815 "write 1" to set or "write 0" to clear.
6816 This register is used to create the
6817 CIU2_RAW_xx_yy_IO[MSIRED] interrupt. See also
6820 uint64_t msi_rcv : 1;
6821 uint64_t reserved_1_63 : 63;
6824 struct cvmx_ciu2_msi_rcvx_s cn68xx;
6825 struct cvmx_ciu2_msi_rcvx_s cn68xxp1;
6827 typedef union cvmx_ciu2_msi_rcvx cvmx_ciu2_msi_rcvx_t;
6830 * cvmx_ciu2_msi_sel#
6832 * CIU2_MSI_SEL Received MSI SEL enable (Pass 2)
6835 union cvmx_ciu2_msi_selx {
6837 struct cvmx_ciu2_msi_selx_s {
6838 #ifdef __BIG_ENDIAN_BITFIELD
6839 uint64_t reserved_13_63 : 51;
6840 uint64_t pp_num : 5; /**< Processor number to receive this MSI interrupt */
6841 uint64_t reserved_6_7 : 2;
6842 uint64_t ip_num : 2; /**< Interrupt priority level to receive this MSI
6843 interrupt (00=IP2, 01=IP3, 10=IP4, 11=rsvd) */
6844 uint64_t reserved_1_3 : 3;
6845 uint64_t en : 1; /**< Enable interrupt delivery.
6846 Must be set for PP_NUM and IP_NUM to have effect. */
6849 uint64_t reserved_1_3 : 3;
6850 uint64_t ip_num : 2;
6851 uint64_t reserved_6_7 : 2;
6852 uint64_t pp_num : 5;
6853 uint64_t reserved_13_63 : 51;
6856 struct cvmx_ciu2_msi_selx_s cn68xx;
6857 struct cvmx_ciu2_msi_selx_s cn68xxp1;
6859 typedef union cvmx_ciu2_msi_selx cvmx_ciu2_msi_selx_t;
6862 * cvmx_ciu2_msired_pp#_ip2
6864 * CIU2_MSIRED_PPX_IPx (Pass 2)
6865 * Contains reduced MSI interrupt numbers for delivery to software.
6866 * Note MSIRED delivery can only be made to PPs, not to IO; thus there are no CIU2_MSIRED_IO registers.
6868 union cvmx_ciu2_msired_ppx_ip2 {
6870 struct cvmx_ciu2_msired_ppx_ip2_s {
6871 #ifdef __BIG_ENDIAN_BITFIELD
6872 uint64_t reserved_21_63 : 43;
6873 uint64_t intr : 1; /**< Interrupt pending */
6874 uint64_t reserved_17_19 : 3;
6875 uint64_t newint : 1; /**< New interrupt to be delivered.
6876 Internal state, for diagnostic use only. | $PR */
6877 uint64_t reserved_8_15 : 8;
6878 uint64_t msi_num : 8; /**< MSI number causing this interrupt.
6879 If multiple MSIs are pending to the same PP and IP,
6880 then this contains the numerically lowest MSI number */
6882 uint64_t msi_num : 8;
6883 uint64_t reserved_8_15 : 8;
6884 uint64_t newint : 1;
6885 uint64_t reserved_17_19 : 3;
6887 uint64_t reserved_21_63 : 43;
6890 struct cvmx_ciu2_msired_ppx_ip2_s cn68xx;
6891 struct cvmx_ciu2_msired_ppx_ip2_s cn68xxp1;
6893 typedef union cvmx_ciu2_msired_ppx_ip2 cvmx_ciu2_msired_ppx_ip2_t;
6896 * cvmx_ciu2_msired_pp#_ip3
6898 union cvmx_ciu2_msired_ppx_ip3 {
6900 struct cvmx_ciu2_msired_ppx_ip3_s {
6901 #ifdef __BIG_ENDIAN_BITFIELD
6902 uint64_t reserved_21_63 : 43;
6903 uint64_t intr : 1; /**< Interrupt pending */
6904 uint64_t reserved_17_19 : 3;
6905 uint64_t newint : 1; /**< New interrupt to be delivered.
6906 Internal state, for diagnostic use only. | $PR */
6907 uint64_t reserved_8_15 : 8;
6908 uint64_t msi_num : 8; /**< MSI number causing this interrupt.
6909 If multiple MSIs are pending to the same PP and IP,
6910 then this contains the numerically lowest MSI number */
6912 uint64_t msi_num : 8;
6913 uint64_t reserved_8_15 : 8;
6914 uint64_t newint : 1;
6915 uint64_t reserved_17_19 : 3;
6917 uint64_t reserved_21_63 : 43;
6920 struct cvmx_ciu2_msired_ppx_ip3_s cn68xx;
6921 struct cvmx_ciu2_msired_ppx_ip3_s cn68xxp1;
6923 typedef union cvmx_ciu2_msired_ppx_ip3 cvmx_ciu2_msired_ppx_ip3_t;
6926 * cvmx_ciu2_msired_pp#_ip4
6928 union cvmx_ciu2_msired_ppx_ip4 {
6930 struct cvmx_ciu2_msired_ppx_ip4_s {
6931 #ifdef __BIG_ENDIAN_BITFIELD
6932 uint64_t reserved_21_63 : 43;
6933 uint64_t intr : 1; /**< Interrupt pending */
6934 uint64_t reserved_17_19 : 3;
6935 uint64_t newint : 1; /**< New interrupt to be delivered.
6936 Internal state, for diagnostic use only. | $PR */
6937 uint64_t reserved_8_15 : 8;
6938 uint64_t msi_num : 8; /**< MSI number causing this interrupt.
6939 If multiple MSIs are pending to the same PP and IP,
6940 then this contains the numerically lowest MSI number */
6942 uint64_t msi_num : 8;
6943 uint64_t reserved_8_15 : 8;
6944 uint64_t newint : 1;
6945 uint64_t reserved_17_19 : 3;
6947 uint64_t reserved_21_63 : 43;
6950 struct cvmx_ciu2_msired_ppx_ip4_s cn68xx;
6951 struct cvmx_ciu2_msired_ppx_ip4_s cn68xxp1;
6953 typedef union cvmx_ciu2_msired_ppx_ip4 cvmx_ciu2_msired_ppx_ip4_t;
6956 * cvmx_ciu2_raw_io#_int_gpio
6958 union cvmx_ciu2_raw_iox_int_gpio {
6960 struct cvmx_ciu2_raw_iox_int_gpio_s {
6961 #ifdef __BIG_ENDIAN_BITFIELD
6962 uint64_t reserved_16_63 : 48;
6963 uint64_t gpio : 16; /**< 16 GPIO interrupts
6964 For GPIO, all 98 RAW readout will be same value */
6967 uint64_t reserved_16_63 : 48;
6970 struct cvmx_ciu2_raw_iox_int_gpio_s cn68xx;
6971 struct cvmx_ciu2_raw_iox_int_gpio_s cn68xxp1;
6973 typedef union cvmx_ciu2_raw_iox_int_gpio cvmx_ciu2_raw_iox_int_gpio_t;
6976 * cvmx_ciu2_raw_io#_int_io
6978 union cvmx_ciu2_raw_iox_int_io {
6980 struct cvmx_ciu2_raw_iox_int_io_s {
6981 #ifdef __BIG_ENDIAN_BITFIELD
6982 uint64_t reserved_34_63 : 30;
6983 uint64_t pem : 2; /**< PEMx interrupt
6984 See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
6985 uint64_t reserved_18_31 : 14;
6986 uint64_t pci_inta : 2; /**< PCI_INTA software enable
6988 uint64_t reserved_13_15 : 3;
6989 uint64_t msired : 1; /**< MSI summary bit, copy of
6990 CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
6991 CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
6992 This bit may not be functional in pass 1. */
6993 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
6994 See SLI_MSI_RCVn for bit <40+n> */
6995 uint64_t reserved_4_7 : 4;
6996 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D
7001 Refer to "Receiving Emulated INTA/INTB/
7002 INTC/INTD" in the SLI chapter of the spec
7003 For IO, all 98 RAW readout will be different */
7005 uint64_t pci_intr : 4;
7006 uint64_t reserved_4_7 : 4;
7007 uint64_t pci_msi : 4;
7008 uint64_t msired : 1;
7009 uint64_t reserved_13_15 : 3;
7010 uint64_t pci_inta : 2;
7011 uint64_t reserved_18_31 : 14;
7013 uint64_t reserved_34_63 : 30;
7016 struct cvmx_ciu2_raw_iox_int_io_s cn68xx;
7017 struct cvmx_ciu2_raw_iox_int_io_s cn68xxp1;
7019 typedef union cvmx_ciu2_raw_iox_int_io cvmx_ciu2_raw_iox_int_io_t;
7022 * cvmx_ciu2_raw_io#_int_mem
7024 union cvmx_ciu2_raw_iox_int_mem {
7026 struct cvmx_ciu2_raw_iox_int_mem_s {
7027 #ifdef __BIG_ENDIAN_BITFIELD
7028 uint64_t reserved_4_63 : 60;
7029 uint64_t lmc : 4; /**< LMC* interrupt
7031 For MEM, all 98 RAW readout will be same value */
7034 uint64_t reserved_4_63 : 60;
7037 struct cvmx_ciu2_raw_iox_int_mem_s cn68xx;
7038 struct cvmx_ciu2_raw_iox_int_mem_s cn68xxp1;
7040 typedef union cvmx_ciu2_raw_iox_int_mem cvmx_ciu2_raw_iox_int_mem_t;
7043 * cvmx_ciu2_raw_io#_int_mio
7045 union cvmx_ciu2_raw_iox_int_mio {
7047 struct cvmx_ciu2_raw_iox_int_mio_s {
7048 #ifdef __BIG_ENDIAN_BITFIELD
7049 uint64_t rst : 1; /**< MIO RST interrupt
7051 uint64_t reserved_49_62 : 14;
7052 uint64_t ptp : 1; /**< PTP interrupt
7053 Set when HW decrements MIO_PTP_EVT_CNT to zero */
7054 uint64_t reserved_45_47 : 3;
7055 uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt
7056 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7057 uint64_t reserved_41_43 : 3;
7058 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt
7059 See UCTL*_INT_REG */
7060 uint64_t reserved_38_39 : 2;
7061 uint64_t uart : 2; /**< Two UART interrupts
7062 See MIO_UARTn_IIR[IID] for bit <34+n> */
7063 uint64_t reserved_34_35 : 2;
7064 uint64_t twsi : 2; /**< TWSI x Interrupt
7066 uint64_t reserved_19_31 : 13;
7067 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7068 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7069 uint64_t mio : 1; /**< MIO boot interrupt
7071 uint64_t nand : 1; /**< NAND Flash Controller interrupt
7073 uint64_t reserved_12_15 : 4;
7074 uint64_t timer : 4; /**< General timer interrupts
7075 Set any time the corresponding CIU timer expires */
7076 uint64_t reserved_3_7 : 5;
7077 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7078 Set any time PIP/IPD drops a packet */
7079 uint64_t ssoiq : 1; /**< SSO IQ interrupt
7081 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7082 See IPD_PORT_QOS_INT*
7083 For MIO, all 98 RAW readout will be same value */
7085 uint64_t ipdppthr : 1;
7087 uint64_t ipd_drp : 1;
7088 uint64_t reserved_3_7 : 5;
7090 uint64_t reserved_12_15 : 4;
7093 uint64_t bootdma : 1;
7094 uint64_t reserved_19_31 : 13;
7096 uint64_t reserved_34_35 : 2;
7098 uint64_t reserved_38_39 : 2;
7099 uint64_t usb_uctl : 1;
7100 uint64_t reserved_41_43 : 3;
7101 uint64_t usb_hci : 1;
7102 uint64_t reserved_45_47 : 3;
7104 uint64_t reserved_49_62 : 14;
7108 struct cvmx_ciu2_raw_iox_int_mio_s cn68xx;
7109 struct cvmx_ciu2_raw_iox_int_mio_s cn68xxp1;
7111 typedef union cvmx_ciu2_raw_iox_int_mio cvmx_ciu2_raw_iox_int_mio_t;
7114 * cvmx_ciu2_raw_io#_int_pkt
7116 union cvmx_ciu2_raw_iox_int_pkt {
7118 struct cvmx_ciu2_raw_iox_int_pkt_s {
7119 #ifdef __BIG_ENDIAN_BITFIELD
7120 uint64_t reserved_54_63 : 10;
7121 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */
7122 uint64_t reserved_49_51 : 3;
7123 uint64_t ilk : 1; /**< ILK interface interrupts */
7124 uint64_t reserved_41_47 : 7;
7125 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
7127 uint64_t reserved_33_39 : 7;
7128 uint64_t agl : 1; /**< AGL interrupt
7129 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
7130 uint64_t reserved_13_31 : 19;
7131 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
7132 Set any time corresponding GMX drops a packet */
7133 uint64_t reserved_5_7 : 3;
7134 uint64_t agx : 5; /**< GMX 0-4 interrupt
7135 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
7136 PCS0_INT*_REG, PCSX*_INT_REG
7137 For PKT, all 98 RAW readout will be same value */
7140 uint64_t reserved_5_7 : 3;
7141 uint64_t gmx_drp : 5;
7142 uint64_t reserved_13_31 : 19;
7144 uint64_t reserved_33_39 : 7;
7146 uint64_t reserved_41_47 : 7;
7148 uint64_t reserved_49_51 : 3;
7149 uint64_t ilk_drp : 2;
7150 uint64_t reserved_54_63 : 10;
7153 struct cvmx_ciu2_raw_iox_int_pkt_s cn68xx;
7154 struct cvmx_ciu2_raw_iox_int_pkt_cn68xxp1 {
7155 #ifdef __BIG_ENDIAN_BITFIELD
7156 uint64_t reserved_49_63 : 15;
7157 uint64_t ilk : 1; /**< ILK interface interrupts */
7158 uint64_t reserved_41_47 : 7;
7159 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
7161 uint64_t reserved_33_39 : 7;
7162 uint64_t agl : 1; /**< AGL interrupt
7163 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
7164 uint64_t reserved_13_31 : 19;
7165 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
7166 Set any time corresponding GMX drops a packet */
7167 uint64_t reserved_5_7 : 3;
7168 uint64_t agx : 5; /**< GMX 0-4 interrupt
7169 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
7170 PCS0_INT*_REG, PCSX*_INT_REG
7171 For PKT, all 98 RAW readout will be same value */
7174 uint64_t reserved_5_7 : 3;
7175 uint64_t gmx_drp : 5;
7176 uint64_t reserved_13_31 : 19;
7178 uint64_t reserved_33_39 : 7;
7180 uint64_t reserved_41_47 : 7;
7182 uint64_t reserved_49_63 : 15;
7186 typedef union cvmx_ciu2_raw_iox_int_pkt cvmx_ciu2_raw_iox_int_pkt_t;
7189 * cvmx_ciu2_raw_io#_int_rml
7191 union cvmx_ciu2_raw_iox_int_rml {
7193 struct cvmx_ciu2_raw_iox_int_rml_s {
7194 #ifdef __BIG_ENDIAN_BITFIELD
7195 uint64_t reserved_56_63 : 8;
7196 uint64_t trace : 4; /**< Trace buffer interrupt
7197 See TRA_INT_STATUS */
7198 uint64_t reserved_49_51 : 3;
7199 uint64_t l2c : 1; /**< L2C interrupt
7201 uint64_t reserved_41_47 : 7;
7202 uint64_t dfa : 1; /**< DFA interrupt
7204 uint64_t reserved_37_39 : 3;
7205 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
7206 See DPI DMA instruction completion */
7207 uint64_t reserved_34_35 : 2;
7208 uint64_t dpi : 1; /**< DPI interrupt
7210 uint64_t sli : 1; /**< SLI interrupt
7211 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
7212 uint64_t reserved_31_31 : 1;
7213 uint64_t key : 1; /**< KEY interrupt
7215 uint64_t rad : 1; /**< RAD interrupt
7216 See RAD_REG_ERROR */
7217 uint64_t tim : 1; /**< TIM interrupt
7218 See TIM_INT_ECCERR, TIM_INT0 */
7219 uint64_t reserved_25_27 : 3;
7220 uint64_t zip : 1; /**< ZIP interrupt
7222 uint64_t reserved_17_23 : 7;
7223 uint64_t sso : 1; /**< SSO err interrupt
7225 uint64_t reserved_8_15 : 8;
7226 uint64_t pko : 1; /**< PKO interrupt
7227 See PKO_REG_ERROR */
7228 uint64_t pip : 1; /**< PIP interrupt
7230 uint64_t ipd : 1; /**< IPD interrupt
7232 uint64_t fpa : 1; /**< FPA interrupt
7234 uint64_t reserved_1_3 : 3;
7235 uint64_t iob : 1; /**< IOB interrupt
7237 For RML, all 98 RAW readout will be same value */
7240 uint64_t reserved_1_3 : 3;
7245 uint64_t reserved_8_15 : 8;
7247 uint64_t reserved_17_23 : 7;
7249 uint64_t reserved_25_27 : 3;
7253 uint64_t reserved_31_31 : 1;
7256 uint64_t reserved_34_35 : 2;
7257 uint64_t dpi_dma : 1;
7258 uint64_t reserved_37_39 : 3;
7260 uint64_t reserved_41_47 : 7;
7262 uint64_t reserved_49_51 : 3;
7264 uint64_t reserved_56_63 : 8;
7267 struct cvmx_ciu2_raw_iox_int_rml_s cn68xx;
7268 struct cvmx_ciu2_raw_iox_int_rml_cn68xxp1 {
7269 #ifdef __BIG_ENDIAN_BITFIELD
7270 uint64_t reserved_56_63 : 8;
7271 uint64_t trace : 4; /**< Trace buffer interrupt
7272 See TRA_INT_STATUS */
7273 uint64_t reserved_49_51 : 3;
7274 uint64_t l2c : 1; /**< L2C interrupt
7276 uint64_t reserved_41_47 : 7;
7277 uint64_t dfa : 1; /**< DFA interrupt
7279 uint64_t reserved_34_39 : 6;
7280 uint64_t dpi : 1; /**< DPI interrupt
7282 uint64_t sli : 1; /**< SLI interrupt
7283 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
7284 uint64_t reserved_31_31 : 1;
7285 uint64_t key : 1; /**< KEY interrupt
7287 uint64_t rad : 1; /**< RAD interrupt
7288 See RAD_REG_ERROR */
7289 uint64_t tim : 1; /**< TIM interrupt
7290 See TIM_INT_ECCERR, TIM_INT0 */
7291 uint64_t reserved_25_27 : 3;
7292 uint64_t zip : 1; /**< ZIP interrupt
7294 uint64_t reserved_17_23 : 7;
7295 uint64_t sso : 1; /**< SSO err interrupt
7297 uint64_t reserved_8_15 : 8;
7298 uint64_t pko : 1; /**< PKO interrupt
7299 See PKO_REG_ERROR */
7300 uint64_t pip : 1; /**< PIP interrupt
7302 uint64_t ipd : 1; /**< IPD interrupt
7304 uint64_t fpa : 1; /**< FPA interrupt
7306 uint64_t reserved_1_3 : 3;
7307 uint64_t iob : 1; /**< IOB interrupt
7309 For RML, all 98 RAW readout will be same value */
7312 uint64_t reserved_1_3 : 3;
7317 uint64_t reserved_8_15 : 8;
7319 uint64_t reserved_17_23 : 7;
7321 uint64_t reserved_25_27 : 3;
7325 uint64_t reserved_31_31 : 1;
7328 uint64_t reserved_34_39 : 6;
7330 uint64_t reserved_41_47 : 7;
7332 uint64_t reserved_49_51 : 3;
7334 uint64_t reserved_56_63 : 8;
7338 typedef union cvmx_ciu2_raw_iox_int_rml cvmx_ciu2_raw_iox_int_rml_t;
7341 * cvmx_ciu2_raw_io#_int_wdog
7343 union cvmx_ciu2_raw_iox_int_wdog {
7345 struct cvmx_ciu2_raw_iox_int_wdog_s {
7346 #ifdef __BIG_ENDIAN_BITFIELD
7347 uint64_t reserved_32_63 : 32;
7348 uint64_t wdog : 32; /**< 32 watchdog interrupts
7349 For WDOG, all 98 RAW readout will be same value */
7352 uint64_t reserved_32_63 : 32;
7355 struct cvmx_ciu2_raw_iox_int_wdog_s cn68xx;
7356 struct cvmx_ciu2_raw_iox_int_wdog_s cn68xxp1;
7358 typedef union cvmx_ciu2_raw_iox_int_wdog cvmx_ciu2_raw_iox_int_wdog_t;
7361 * cvmx_ciu2_raw_io#_int_wrkq
7363 union cvmx_ciu2_raw_iox_int_wrkq {
7365 struct cvmx_ciu2_raw_iox_int_wrkq_s {
7366 #ifdef __BIG_ENDIAN_BITFIELD
7367 uint64_t workq : 64; /**< 64 work queue interrupts
7368 See SSO_WQ_INT[WQ_INT]
7369 1 bit/group. A copy of the R/W1C bit in the SSO.
7370 For WRKQ, all 98 RAW readout will be same value */
7372 uint64_t workq : 64;
7375 struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xx;
7376 struct cvmx_ciu2_raw_iox_int_wrkq_s cn68xxp1;
7378 typedef union cvmx_ciu2_raw_iox_int_wrkq cvmx_ciu2_raw_iox_int_wrkq_t;
7381 * cvmx_ciu2_raw_pp#_ip2_gpio
7383 union cvmx_ciu2_raw_ppx_ip2_gpio {
7385 struct cvmx_ciu2_raw_ppx_ip2_gpio_s {
7386 #ifdef __BIG_ENDIAN_BITFIELD
7387 uint64_t reserved_16_63 : 48;
7388 uint64_t gpio : 16; /**< 16 GPIO interrupts
7389 For GPIO, all 98 RAW readout will be same value */
7392 uint64_t reserved_16_63 : 48;
7395 struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xx;
7396 struct cvmx_ciu2_raw_ppx_ip2_gpio_s cn68xxp1;
7398 typedef union cvmx_ciu2_raw_ppx_ip2_gpio cvmx_ciu2_raw_ppx_ip2_gpio_t;
7401 * cvmx_ciu2_raw_pp#_ip2_io
7403 union cvmx_ciu2_raw_ppx_ip2_io {
7405 struct cvmx_ciu2_raw_ppx_ip2_io_s {
7406 #ifdef __BIG_ENDIAN_BITFIELD
7407 uint64_t reserved_34_63 : 30;
7408 uint64_t pem : 2; /**< PEMx interrupt
7409 See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
7410 uint64_t reserved_18_31 : 14;
7411 uint64_t pci_inta : 2; /**< PCI_INTA software enable
7413 uint64_t reserved_13_15 : 3;
7414 uint64_t msired : 1; /**< MSI summary bit, copy of
7415 CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
7416 CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
7417 This bit may not be functional in pass 1. */
7418 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
7419 See SLI_MSI_RCVn for bit <40+n> */
7420 uint64_t reserved_4_7 : 4;
7421 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D
7426 Refer to "Receiving Emulated INTA/INTB/
7427 INTC/INTD" in the SLI chapter of the spec
7428 For IO, all 98 RAW readout will be different */
7430 uint64_t pci_intr : 4;
7431 uint64_t reserved_4_7 : 4;
7432 uint64_t pci_msi : 4;
7433 uint64_t msired : 1;
7434 uint64_t reserved_13_15 : 3;
7435 uint64_t pci_inta : 2;
7436 uint64_t reserved_18_31 : 14;
7438 uint64_t reserved_34_63 : 30;
7441 struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xx;
7442 struct cvmx_ciu2_raw_ppx_ip2_io_s cn68xxp1;
7444 typedef union cvmx_ciu2_raw_ppx_ip2_io cvmx_ciu2_raw_ppx_ip2_io_t;
7447 * cvmx_ciu2_raw_pp#_ip2_mem
7449 union cvmx_ciu2_raw_ppx_ip2_mem {
7451 struct cvmx_ciu2_raw_ppx_ip2_mem_s {
7452 #ifdef __BIG_ENDIAN_BITFIELD
7453 uint64_t reserved_4_63 : 60;
7454 uint64_t lmc : 4; /**< LMC* interrupt
7456 For MEM, all 98 RAW readout will be same value */
7459 uint64_t reserved_4_63 : 60;
7462 struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xx;
7463 struct cvmx_ciu2_raw_ppx_ip2_mem_s cn68xxp1;
7465 typedef union cvmx_ciu2_raw_ppx_ip2_mem cvmx_ciu2_raw_ppx_ip2_mem_t;
7468 * cvmx_ciu2_raw_pp#_ip2_mio
7470 union cvmx_ciu2_raw_ppx_ip2_mio {
7472 struct cvmx_ciu2_raw_ppx_ip2_mio_s {
7473 #ifdef __BIG_ENDIAN_BITFIELD
7474 uint64_t rst : 1; /**< MIO RST interrupt
7476 uint64_t reserved_49_62 : 14;
7477 uint64_t ptp : 1; /**< PTP interrupt
7478 Set when HW decrements MIO_PTP_EVT_CNT to zero */
7479 uint64_t reserved_45_47 : 3;
7480 uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt
7481 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7482 uint64_t reserved_41_43 : 3;
7483 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt
7484 See UCTL*_INT_REG */
7485 uint64_t reserved_38_39 : 2;
7486 uint64_t uart : 2; /**< Two UART interrupts
7487 See MIO_UARTn_IIR[IID] for bit <34+n> */
7488 uint64_t reserved_34_35 : 2;
7489 uint64_t twsi : 2; /**< TWSI x Interrupt
7491 uint64_t reserved_19_31 : 13;
7492 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7493 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7494 uint64_t mio : 1; /**< MIO boot interrupt
7496 uint64_t nand : 1; /**< NAND Flash Controller interrupt
7498 uint64_t reserved_12_15 : 4;
7499 uint64_t timer : 4; /**< General timer interrupts
7500 Set any time the corresponding CIU timer expires */
7501 uint64_t reserved_3_7 : 5;
7502 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7503 Set any time PIP/IPD drops a packet */
7504 uint64_t ssoiq : 1; /**< SSO IQ interrupt
7506 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7507 See IPD_PORT_QOS_INT*
7508 For MIO, all 98 RAW readout will be same value */
7510 uint64_t ipdppthr : 1;
7512 uint64_t ipd_drp : 1;
7513 uint64_t reserved_3_7 : 5;
7515 uint64_t reserved_12_15 : 4;
7518 uint64_t bootdma : 1;
7519 uint64_t reserved_19_31 : 13;
7521 uint64_t reserved_34_35 : 2;
7523 uint64_t reserved_38_39 : 2;
7524 uint64_t usb_uctl : 1;
7525 uint64_t reserved_41_43 : 3;
7526 uint64_t usb_hci : 1;
7527 uint64_t reserved_45_47 : 3;
7529 uint64_t reserved_49_62 : 14;
7533 struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xx;
7534 struct cvmx_ciu2_raw_ppx_ip2_mio_s cn68xxp1;
7536 typedef union cvmx_ciu2_raw_ppx_ip2_mio cvmx_ciu2_raw_ppx_ip2_mio_t;
7539 * cvmx_ciu2_raw_pp#_ip2_pkt
7541 union cvmx_ciu2_raw_ppx_ip2_pkt {
7543 struct cvmx_ciu2_raw_ppx_ip2_pkt_s {
7544 #ifdef __BIG_ENDIAN_BITFIELD
7545 uint64_t reserved_54_63 : 10;
7546 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */
7547 uint64_t reserved_49_51 : 3;
7548 uint64_t ilk : 1; /**< ILK interface interrupts */
7549 uint64_t reserved_41_47 : 7;
7550 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
7552 uint64_t reserved_33_39 : 7;
7553 uint64_t agl : 1; /**< AGL interrupt
7554 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
7555 uint64_t reserved_13_31 : 19;
7556 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
7557 Set any time corresponding GMX drops a packet */
7558 uint64_t reserved_5_7 : 3;
7559 uint64_t agx : 5; /**< GMX 0-4 interrupt
7560 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
7561 PCS0_INT*_REG, PCSX*_INT_REG
7562 For PKT, all 98 RAW readout will be same value */
7565 uint64_t reserved_5_7 : 3;
7566 uint64_t gmx_drp : 5;
7567 uint64_t reserved_13_31 : 19;
7569 uint64_t reserved_33_39 : 7;
7571 uint64_t reserved_41_47 : 7;
7573 uint64_t reserved_49_51 : 3;
7574 uint64_t ilk_drp : 2;
7575 uint64_t reserved_54_63 : 10;
7578 struct cvmx_ciu2_raw_ppx_ip2_pkt_s cn68xx;
7579 struct cvmx_ciu2_raw_ppx_ip2_pkt_cn68xxp1 {
7580 #ifdef __BIG_ENDIAN_BITFIELD
7581 uint64_t reserved_49_63 : 15;
7582 uint64_t ilk : 1; /**< ILK interface interrupts */
7583 uint64_t reserved_41_47 : 7;
7584 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
7586 uint64_t reserved_33_39 : 7;
7587 uint64_t agl : 1; /**< AGL interrupt
7588 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
7589 uint64_t reserved_13_31 : 19;
7590 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
7591 Set any time corresponding GMX drops a packet */
7592 uint64_t reserved_5_7 : 3;
7593 uint64_t agx : 5; /**< GMX 0-4 interrupt
7594 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
7595 PCS0_INT*_REG, PCSX*_INT_REG
7596 For PKT, all 98 RAW readout will be same value */
7599 uint64_t reserved_5_7 : 3;
7600 uint64_t gmx_drp : 5;
7601 uint64_t reserved_13_31 : 19;
7603 uint64_t reserved_33_39 : 7;
7605 uint64_t reserved_41_47 : 7;
7607 uint64_t reserved_49_63 : 15;
7611 typedef union cvmx_ciu2_raw_ppx_ip2_pkt cvmx_ciu2_raw_ppx_ip2_pkt_t;
7614 * cvmx_ciu2_raw_pp#_ip2_rml
7616 union cvmx_ciu2_raw_ppx_ip2_rml {
7618 struct cvmx_ciu2_raw_ppx_ip2_rml_s {
7619 #ifdef __BIG_ENDIAN_BITFIELD
7620 uint64_t reserved_56_63 : 8;
7621 uint64_t trace : 4; /**< Trace buffer interrupt
7622 See TRA_INT_STATUS */
7623 uint64_t reserved_49_51 : 3;
7624 uint64_t l2c : 1; /**< L2C interrupt
7626 uint64_t reserved_41_47 : 7;
7627 uint64_t dfa : 1; /**< DFA interrupt
7629 uint64_t reserved_37_39 : 3;
7630 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
7631 See DPI DMA instruction completion */
7632 uint64_t reserved_34_35 : 2;
7633 uint64_t dpi : 1; /**< DPI interrupt
7635 uint64_t sli : 1; /**< SLI interrupt
7636 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
7637 uint64_t reserved_31_31 : 1;
7638 uint64_t key : 1; /**< KEY interrupt
7640 uint64_t rad : 1; /**< RAD interrupt
7641 See RAD_REG_ERROR */
7642 uint64_t tim : 1; /**< TIM interrupt
7643 See TIM_INT_ECCERR, TIM_INT0 */
7644 uint64_t reserved_25_27 : 3;
7645 uint64_t zip : 1; /**< ZIP interrupt
7647 uint64_t reserved_17_23 : 7;
7648 uint64_t sso : 1; /**< SSO err interrupt
7650 uint64_t reserved_8_15 : 8;
7651 uint64_t pko : 1; /**< PKO interrupt
7652 See PKO_REG_ERROR */
7653 uint64_t pip : 1; /**< PIP interrupt
7655 uint64_t ipd : 1; /**< IPD interrupt
7657 uint64_t fpa : 1; /**< FPA interrupt
7659 uint64_t reserved_1_3 : 3;
7660 uint64_t iob : 1; /**< IOB interrupt
7662 For RML, all 98 RAW readout will be same value */
7665 uint64_t reserved_1_3 : 3;
7670 uint64_t reserved_8_15 : 8;
7672 uint64_t reserved_17_23 : 7;
7674 uint64_t reserved_25_27 : 3;
7678 uint64_t reserved_31_31 : 1;
7681 uint64_t reserved_34_35 : 2;
7682 uint64_t dpi_dma : 1;
7683 uint64_t reserved_37_39 : 3;
7685 uint64_t reserved_41_47 : 7;
7687 uint64_t reserved_49_51 : 3;
7689 uint64_t reserved_56_63 : 8;
7692 struct cvmx_ciu2_raw_ppx_ip2_rml_s cn68xx;
7693 struct cvmx_ciu2_raw_ppx_ip2_rml_cn68xxp1 {
7694 #ifdef __BIG_ENDIAN_BITFIELD
7695 uint64_t reserved_56_63 : 8;
7696 uint64_t trace : 4; /**< Trace buffer interrupt
7697 See TRA_INT_STATUS */
7698 uint64_t reserved_49_51 : 3;
7699 uint64_t l2c : 1; /**< L2C interrupt
7701 uint64_t reserved_41_47 : 7;
7702 uint64_t dfa : 1; /**< DFA interrupt
7704 uint64_t reserved_34_39 : 6;
7705 uint64_t dpi : 1; /**< DPI interrupt
7707 uint64_t sli : 1; /**< SLI interrupt
7708 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
7709 uint64_t reserved_31_31 : 1;
7710 uint64_t key : 1; /**< KEY interrupt
7712 uint64_t rad : 1; /**< RAD interrupt
7713 See RAD_REG_ERROR */
7714 uint64_t tim : 1; /**< TIM interrupt
7715 See TIM_INT_ECCERR, TIM_INT0 */
7716 uint64_t reserved_25_27 : 3;
7717 uint64_t zip : 1; /**< ZIP interrupt
7719 uint64_t reserved_17_23 : 7;
7720 uint64_t sso : 1; /**< SSO err interrupt
7722 uint64_t reserved_8_15 : 8;
7723 uint64_t pko : 1; /**< PKO interrupt
7724 See PKO_REG_ERROR */
7725 uint64_t pip : 1; /**< PIP interrupt
7727 uint64_t ipd : 1; /**< IPD interrupt
7729 uint64_t fpa : 1; /**< FPA interrupt
7731 uint64_t reserved_1_3 : 3;
7732 uint64_t iob : 1; /**< IOB interrupt
7734 For RML, all 98 RAW readout will be same value */
7737 uint64_t reserved_1_3 : 3;
7742 uint64_t reserved_8_15 : 8;
7744 uint64_t reserved_17_23 : 7;
7746 uint64_t reserved_25_27 : 3;
7750 uint64_t reserved_31_31 : 1;
7753 uint64_t reserved_34_39 : 6;
7755 uint64_t reserved_41_47 : 7;
7757 uint64_t reserved_49_51 : 3;
7759 uint64_t reserved_56_63 : 8;
7763 typedef union cvmx_ciu2_raw_ppx_ip2_rml cvmx_ciu2_raw_ppx_ip2_rml_t;
7766 * cvmx_ciu2_raw_pp#_ip2_wdog
7768 union cvmx_ciu2_raw_ppx_ip2_wdog {
7770 struct cvmx_ciu2_raw_ppx_ip2_wdog_s {
7771 #ifdef __BIG_ENDIAN_BITFIELD
7772 uint64_t reserved_32_63 : 32;
7773 uint64_t wdog : 32; /**< 32 watchdog interrupts
7774 For WDOG, all 98 RAW readout will be same value */
7777 uint64_t reserved_32_63 : 32;
7780 struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xx;
7781 struct cvmx_ciu2_raw_ppx_ip2_wdog_s cn68xxp1;
7783 typedef union cvmx_ciu2_raw_ppx_ip2_wdog cvmx_ciu2_raw_ppx_ip2_wdog_t;
7786 * cvmx_ciu2_raw_pp#_ip2_wrkq
7788 union cvmx_ciu2_raw_ppx_ip2_wrkq {
7790 struct cvmx_ciu2_raw_ppx_ip2_wrkq_s {
7791 #ifdef __BIG_ENDIAN_BITFIELD
7792 uint64_t workq : 64; /**< 64 work queue interrupts
7793 See SSO_WQ_INT[WQ_INT]
7794 1 bit/group. A copy of the R/W1C bit in the SSO.
7795 For WRKQ, all 98 RAW readout will be same value */
7797 uint64_t workq : 64;
7800 struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xx;
7801 struct cvmx_ciu2_raw_ppx_ip2_wrkq_s cn68xxp1;
7803 typedef union cvmx_ciu2_raw_ppx_ip2_wrkq cvmx_ciu2_raw_ppx_ip2_wrkq_t;
7806 * cvmx_ciu2_raw_pp#_ip3_gpio
7808 union cvmx_ciu2_raw_ppx_ip3_gpio {
7810 struct cvmx_ciu2_raw_ppx_ip3_gpio_s {
7811 #ifdef __BIG_ENDIAN_BITFIELD
7812 uint64_t reserved_16_63 : 48;
7813 uint64_t gpio : 16; /**< 16 GPIO interrupts
7814 For GPIO, all 98 RAW readout will be same value */
7817 uint64_t reserved_16_63 : 48;
7820 struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xx;
7821 struct cvmx_ciu2_raw_ppx_ip3_gpio_s cn68xxp1;
7823 typedef union cvmx_ciu2_raw_ppx_ip3_gpio cvmx_ciu2_raw_ppx_ip3_gpio_t;
7826 * cvmx_ciu2_raw_pp#_ip3_io
7828 union cvmx_ciu2_raw_ppx_ip3_io {
7830 struct cvmx_ciu2_raw_ppx_ip3_io_s {
7831 #ifdef __BIG_ENDIAN_BITFIELD
7832 uint64_t reserved_34_63 : 30;
7833 uint64_t pem : 2; /**< PEMx interrupt
7834 See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
7835 uint64_t reserved_18_31 : 14;
7836 uint64_t pci_inta : 2; /**< PCI_INTA software enable
7838 uint64_t reserved_13_15 : 3;
7839 uint64_t msired : 1; /**< MSI summary bit, copy of
7840 CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
7841 CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
7842 This bit may not be functional in pass 1. */
7843 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
7844 See SLI_MSI_RCVn for bit <40+n> */
7845 uint64_t reserved_4_7 : 4;
7846 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D
7851 Refer to "Receiving Emulated INTA/INTB/
7852 INTC/INTD" in the SLI chapter of the spec
7853 For IO, all 98 RAW readout will be different */
7855 uint64_t pci_intr : 4;
7856 uint64_t reserved_4_7 : 4;
7857 uint64_t pci_msi : 4;
7858 uint64_t msired : 1;
7859 uint64_t reserved_13_15 : 3;
7860 uint64_t pci_inta : 2;
7861 uint64_t reserved_18_31 : 14;
7863 uint64_t reserved_34_63 : 30;
7866 struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xx;
7867 struct cvmx_ciu2_raw_ppx_ip3_io_s cn68xxp1;
7869 typedef union cvmx_ciu2_raw_ppx_ip3_io cvmx_ciu2_raw_ppx_ip3_io_t;
7872 * cvmx_ciu2_raw_pp#_ip3_mem
7874 union cvmx_ciu2_raw_ppx_ip3_mem {
7876 struct cvmx_ciu2_raw_ppx_ip3_mem_s {
7877 #ifdef __BIG_ENDIAN_BITFIELD
7878 uint64_t reserved_4_63 : 60;
7879 uint64_t lmc : 4; /**< LMC* interrupt
7881 For MEM, all 98 RAW readout will be same value */
7884 uint64_t reserved_4_63 : 60;
7887 struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xx;
7888 struct cvmx_ciu2_raw_ppx_ip3_mem_s cn68xxp1;
7890 typedef union cvmx_ciu2_raw_ppx_ip3_mem cvmx_ciu2_raw_ppx_ip3_mem_t;
7893 * cvmx_ciu2_raw_pp#_ip3_mio
7895 union cvmx_ciu2_raw_ppx_ip3_mio {
7897 struct cvmx_ciu2_raw_ppx_ip3_mio_s {
7898 #ifdef __BIG_ENDIAN_BITFIELD
7899 uint64_t rst : 1; /**< MIO RST interrupt
7901 uint64_t reserved_49_62 : 14;
7902 uint64_t ptp : 1; /**< PTP interrupt
7903 Set when HW decrements MIO_PTP_EVT_CNT to zero */
7904 uint64_t reserved_45_47 : 3;
7905 uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt
7906 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
7907 uint64_t reserved_41_43 : 3;
7908 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt
7909 See UCTL*_INT_REG */
7910 uint64_t reserved_38_39 : 2;
7911 uint64_t uart : 2; /**< Two UART interrupts
7912 See MIO_UARTn_IIR[IID] for bit <34+n> */
7913 uint64_t reserved_34_35 : 2;
7914 uint64_t twsi : 2; /**< TWSI x Interrupt
7916 uint64_t reserved_19_31 : 13;
7917 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
7918 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
7919 uint64_t mio : 1; /**< MIO boot interrupt
7921 uint64_t nand : 1; /**< NAND Flash Controller interrupt
7923 uint64_t reserved_12_15 : 4;
7924 uint64_t timer : 4; /**< General timer interrupts
7925 Set any time the corresponding CIU timer expires */
7926 uint64_t reserved_3_7 : 5;
7927 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
7928 Set any time PIP/IPD drops a packet */
7929 uint64_t ssoiq : 1; /**< SSO IQ interrupt
7931 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
7932 See IPD_PORT_QOS_INT*
7933 For MIO, all 98 RAW readout will be same value */
7935 uint64_t ipdppthr : 1;
7937 uint64_t ipd_drp : 1;
7938 uint64_t reserved_3_7 : 5;
7940 uint64_t reserved_12_15 : 4;
7943 uint64_t bootdma : 1;
7944 uint64_t reserved_19_31 : 13;
7946 uint64_t reserved_34_35 : 2;
7948 uint64_t reserved_38_39 : 2;
7949 uint64_t usb_uctl : 1;
7950 uint64_t reserved_41_43 : 3;
7951 uint64_t usb_hci : 1;
7952 uint64_t reserved_45_47 : 3;
7954 uint64_t reserved_49_62 : 14;
7958 struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xx;
7959 struct cvmx_ciu2_raw_ppx_ip3_mio_s cn68xxp1;
7961 typedef union cvmx_ciu2_raw_ppx_ip3_mio cvmx_ciu2_raw_ppx_ip3_mio_t;
7964 * cvmx_ciu2_raw_pp#_ip3_pkt
7966 union cvmx_ciu2_raw_ppx_ip3_pkt {
7968 struct cvmx_ciu2_raw_ppx_ip3_pkt_s {
7969 #ifdef __BIG_ENDIAN_BITFIELD
7970 uint64_t reserved_54_63 : 10;
7971 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */
7972 uint64_t reserved_49_51 : 3;
7973 uint64_t ilk : 1; /**< ILK interface interrupts */
7974 uint64_t reserved_41_47 : 7;
7975 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
7977 uint64_t reserved_33_39 : 7;
7978 uint64_t agl : 1; /**< AGL interrupt
7979 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
7980 uint64_t reserved_13_31 : 19;
7981 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
7982 Set any time corresponding GMX drops a packet */
7983 uint64_t reserved_5_7 : 3;
7984 uint64_t agx : 5; /**< GMX 0-4 interrupt
7985 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
7986 PCS0_INT*_REG, PCSX*_INT_REG
7987 For PKT, all 98 RAW readout will be same value */
7990 uint64_t reserved_5_7 : 3;
7991 uint64_t gmx_drp : 5;
7992 uint64_t reserved_13_31 : 19;
7994 uint64_t reserved_33_39 : 7;
7996 uint64_t reserved_41_47 : 7;
7998 uint64_t reserved_49_51 : 3;
7999 uint64_t ilk_drp : 2;
8000 uint64_t reserved_54_63 : 10;
8003 struct cvmx_ciu2_raw_ppx_ip3_pkt_s cn68xx;
8004 struct cvmx_ciu2_raw_ppx_ip3_pkt_cn68xxp1 {
8005 #ifdef __BIG_ENDIAN_BITFIELD
8006 uint64_t reserved_49_63 : 15;
8007 uint64_t ilk : 1; /**< ILK interface interrupts */
8008 uint64_t reserved_41_47 : 7;
8009 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
8011 uint64_t reserved_33_39 : 7;
8012 uint64_t agl : 1; /**< AGL interrupt
8013 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
8014 uint64_t reserved_13_31 : 19;
8015 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
8016 Set any time corresponding GMX drops a packet */
8017 uint64_t reserved_5_7 : 3;
8018 uint64_t agx : 5; /**< GMX 0-4 interrupt
8019 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
8020 PCS0_INT*_REG, PCSX*_INT_REG
8021 For PKT, all 98 RAW readout will be same value */
8024 uint64_t reserved_5_7 : 3;
8025 uint64_t gmx_drp : 5;
8026 uint64_t reserved_13_31 : 19;
8028 uint64_t reserved_33_39 : 7;
8030 uint64_t reserved_41_47 : 7;
8032 uint64_t reserved_49_63 : 15;
8036 typedef union cvmx_ciu2_raw_ppx_ip3_pkt cvmx_ciu2_raw_ppx_ip3_pkt_t;
8039 * cvmx_ciu2_raw_pp#_ip3_rml
8041 union cvmx_ciu2_raw_ppx_ip3_rml {
8043 struct cvmx_ciu2_raw_ppx_ip3_rml_s {
8044 #ifdef __BIG_ENDIAN_BITFIELD
8045 uint64_t reserved_56_63 : 8;
8046 uint64_t trace : 4; /**< Trace buffer interrupt
8047 See TRA_INT_STATUS */
8048 uint64_t reserved_49_51 : 3;
8049 uint64_t l2c : 1; /**< L2C interrupt
8051 uint64_t reserved_41_47 : 7;
8052 uint64_t dfa : 1; /**< DFA interrupt
8054 uint64_t reserved_37_39 : 3;
8055 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
8056 See DPI DMA instruction completion */
8057 uint64_t reserved_34_35 : 2;
8058 uint64_t dpi : 1; /**< DPI interrupt
8060 uint64_t sli : 1; /**< SLI interrupt
8061 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
8062 uint64_t reserved_31_31 : 1;
8063 uint64_t key : 1; /**< KEY interrupt
8065 uint64_t rad : 1; /**< RAD interrupt
8066 See RAD_REG_ERROR */
8067 uint64_t tim : 1; /**< TIM interrupt
8068 See TIM_INT_ECCERR, TIM_INT0 */
8069 uint64_t reserved_25_27 : 3;
8070 uint64_t zip : 1; /**< ZIP interrupt
8072 uint64_t reserved_17_23 : 7;
8073 uint64_t sso : 1; /**< SSO err interrupt
8075 uint64_t reserved_8_15 : 8;
8076 uint64_t pko : 1; /**< PKO interrupt
8077 See PKO_REG_ERROR */
8078 uint64_t pip : 1; /**< PIP interrupt
8080 uint64_t ipd : 1; /**< IPD interrupt
8082 uint64_t fpa : 1; /**< FPA interrupt
8084 uint64_t reserved_1_3 : 3;
8085 uint64_t iob : 1; /**< IOB interrupt
8087 For RML, all 98 RAW readout will be same value */
8090 uint64_t reserved_1_3 : 3;
8095 uint64_t reserved_8_15 : 8;
8097 uint64_t reserved_17_23 : 7;
8099 uint64_t reserved_25_27 : 3;
8103 uint64_t reserved_31_31 : 1;
8106 uint64_t reserved_34_35 : 2;
8107 uint64_t dpi_dma : 1;
8108 uint64_t reserved_37_39 : 3;
8110 uint64_t reserved_41_47 : 7;
8112 uint64_t reserved_49_51 : 3;
8114 uint64_t reserved_56_63 : 8;
8117 struct cvmx_ciu2_raw_ppx_ip3_rml_s cn68xx;
8118 struct cvmx_ciu2_raw_ppx_ip3_rml_cn68xxp1 {
8119 #ifdef __BIG_ENDIAN_BITFIELD
8120 uint64_t reserved_56_63 : 8;
8121 uint64_t trace : 4; /**< Trace buffer interrupt
8122 See TRA_INT_STATUS */
8123 uint64_t reserved_49_51 : 3;
8124 uint64_t l2c : 1; /**< L2C interrupt
8126 uint64_t reserved_41_47 : 7;
8127 uint64_t dfa : 1; /**< DFA interrupt
8129 uint64_t reserved_34_39 : 6;
8130 uint64_t dpi : 1; /**< DPI interrupt
8132 uint64_t sli : 1; /**< SLI interrupt
8133 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
8134 uint64_t reserved_31_31 : 1;
8135 uint64_t key : 1; /**< KEY interrupt
8137 uint64_t rad : 1; /**< RAD interrupt
8138 See RAD_REG_ERROR */
8139 uint64_t tim : 1; /**< TIM interrupt
8140 See TIM_INT_ECCERR, TIM_INT0 */
8141 uint64_t reserved_25_27 : 3;
8142 uint64_t zip : 1; /**< ZIP interrupt
8144 uint64_t reserved_17_23 : 7;
8145 uint64_t sso : 1; /**< SSO err interrupt
8147 uint64_t reserved_8_15 : 8;
8148 uint64_t pko : 1; /**< PKO interrupt
8149 See PKO_REG_ERROR */
8150 uint64_t pip : 1; /**< PIP interrupt
8152 uint64_t ipd : 1; /**< IPD interrupt
8154 uint64_t fpa : 1; /**< FPA interrupt
8156 uint64_t reserved_1_3 : 3;
8157 uint64_t iob : 1; /**< IOB interrupt
8159 For RML, all 98 RAW readout will be same value */
8162 uint64_t reserved_1_3 : 3;
8167 uint64_t reserved_8_15 : 8;
8169 uint64_t reserved_17_23 : 7;
8171 uint64_t reserved_25_27 : 3;
8175 uint64_t reserved_31_31 : 1;
8178 uint64_t reserved_34_39 : 6;
8180 uint64_t reserved_41_47 : 7;
8182 uint64_t reserved_49_51 : 3;
8184 uint64_t reserved_56_63 : 8;
8188 typedef union cvmx_ciu2_raw_ppx_ip3_rml cvmx_ciu2_raw_ppx_ip3_rml_t;
8191 * cvmx_ciu2_raw_pp#_ip3_wdog
8193 union cvmx_ciu2_raw_ppx_ip3_wdog {
8195 struct cvmx_ciu2_raw_ppx_ip3_wdog_s {
8196 #ifdef __BIG_ENDIAN_BITFIELD
8197 uint64_t reserved_32_63 : 32;
8198 uint64_t wdog : 32; /**< 32 watchdog interrupts
8199 For WDOG, all 98 RAW readout will be same value */
8202 uint64_t reserved_32_63 : 32;
8205 struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xx;
8206 struct cvmx_ciu2_raw_ppx_ip3_wdog_s cn68xxp1;
8208 typedef union cvmx_ciu2_raw_ppx_ip3_wdog cvmx_ciu2_raw_ppx_ip3_wdog_t;
8211 * cvmx_ciu2_raw_pp#_ip3_wrkq
8213 union cvmx_ciu2_raw_ppx_ip3_wrkq {
8215 struct cvmx_ciu2_raw_ppx_ip3_wrkq_s {
8216 #ifdef __BIG_ENDIAN_BITFIELD
8217 uint64_t workq : 64; /**< 64 work queue interrupts
8218 See SSO_WQ_INT[WQ_INT]
8219 1 bit/group. A copy of the R/W1C bit in the SSO.
8220 For WRKQ, all 98 RAW readout will be same value */
8222 uint64_t workq : 64;
8225 struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xx;
8226 struct cvmx_ciu2_raw_ppx_ip3_wrkq_s cn68xxp1;
8228 typedef union cvmx_ciu2_raw_ppx_ip3_wrkq cvmx_ciu2_raw_ppx_ip3_wrkq_t;
8231 * cvmx_ciu2_raw_pp#_ip4_gpio
8233 union cvmx_ciu2_raw_ppx_ip4_gpio {
8235 struct cvmx_ciu2_raw_ppx_ip4_gpio_s {
8236 #ifdef __BIG_ENDIAN_BITFIELD
8237 uint64_t reserved_16_63 : 48;
8238 uint64_t gpio : 16; /**< 16 GPIO interrupts
8239 For GPIO, all 98 RAW readout will be same value */
8242 uint64_t reserved_16_63 : 48;
8245 struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xx;
8246 struct cvmx_ciu2_raw_ppx_ip4_gpio_s cn68xxp1;
8248 typedef union cvmx_ciu2_raw_ppx_ip4_gpio cvmx_ciu2_raw_ppx_ip4_gpio_t;
8251 * cvmx_ciu2_raw_pp#_ip4_io
8253 union cvmx_ciu2_raw_ppx_ip4_io {
8255 struct cvmx_ciu2_raw_ppx_ip4_io_s {
8256 #ifdef __BIG_ENDIAN_BITFIELD
8257 uint64_t reserved_34_63 : 30;
8258 uint64_t pem : 2; /**< PEMx interrupt
8259 See PEMx_INT_SUM (enabled by PEMx_INT_ENB) */
8260 uint64_t reserved_18_31 : 14;
8261 uint64_t pci_inta : 2; /**< PCI_INTA software enable
8263 uint64_t reserved_13_15 : 3;
8264 uint64_t msired : 1; /**< MSI summary bit, copy of
8265 CIU2_MSIRED_PPx_IPy.INT, all IO interrupts
8266 CIU2_RAW_IOX_INT_IO[MSIRED] always zero.
8267 This bit may not be functional in pass 1. */
8268 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI
8269 See SLI_MSI_RCVn for bit <40+n> */
8270 uint64_t reserved_4_7 : 4;
8271 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D
8276 Refer to "Receiving Emulated INTA/INTB/
8277 INTC/INTD" in the SLI chapter of the spec
8278 For IO, all 98 RAW readout will be different */
8280 uint64_t pci_intr : 4;
8281 uint64_t reserved_4_7 : 4;
8282 uint64_t pci_msi : 4;
8283 uint64_t msired : 1;
8284 uint64_t reserved_13_15 : 3;
8285 uint64_t pci_inta : 2;
8286 uint64_t reserved_18_31 : 14;
8288 uint64_t reserved_34_63 : 30;
8291 struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xx;
8292 struct cvmx_ciu2_raw_ppx_ip4_io_s cn68xxp1;
8294 typedef union cvmx_ciu2_raw_ppx_ip4_io cvmx_ciu2_raw_ppx_ip4_io_t;
8297 * cvmx_ciu2_raw_pp#_ip4_mem
8299 union cvmx_ciu2_raw_ppx_ip4_mem {
8301 struct cvmx_ciu2_raw_ppx_ip4_mem_s {
8302 #ifdef __BIG_ENDIAN_BITFIELD
8303 uint64_t reserved_4_63 : 60;
8304 uint64_t lmc : 4; /**< LMC* interrupt
8306 For MEM, all 98 RAW readout will be same value */
8309 uint64_t reserved_4_63 : 60;
8312 struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xx;
8313 struct cvmx_ciu2_raw_ppx_ip4_mem_s cn68xxp1;
8315 typedef union cvmx_ciu2_raw_ppx_ip4_mem cvmx_ciu2_raw_ppx_ip4_mem_t;
8318 * cvmx_ciu2_raw_pp#_ip4_mio
8320 union cvmx_ciu2_raw_ppx_ip4_mio {
8322 struct cvmx_ciu2_raw_ppx_ip4_mio_s {
8323 #ifdef __BIG_ENDIAN_BITFIELD
8324 uint64_t rst : 1; /**< MIO RST interrupt
8326 uint64_t reserved_49_62 : 14;
8327 uint64_t ptp : 1; /**< PTP interrupt
8328 Set when HW decrements MIO_PTP_EVT_CNT to zero */
8329 uint64_t reserved_45_47 : 3;
8330 uint64_t usb_hci : 1; /**< USB EHCI or OHCI Interrupt
8331 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */
8332 uint64_t reserved_41_43 : 3;
8333 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt
8334 See UCTL*_INT_REG */
8335 uint64_t reserved_38_39 : 2;
8336 uint64_t uart : 2; /**< Two UART interrupts
8337 See MIO_UARTn_IIR[IID] for bit <34+n> */
8338 uint64_t reserved_34_35 : 2;
8339 uint64_t twsi : 2; /**< TWSI x Interrupt
8341 uint64_t reserved_19_31 : 13;
8342 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt
8343 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */
8344 uint64_t mio : 1; /**< MIO boot interrupt
8346 uint64_t nand : 1; /**< NAND Flash Controller interrupt
8348 uint64_t reserved_12_15 : 4;
8349 uint64_t timer : 4; /**< General timer interrupts
8350 Set any time the corresponding CIU timer expires */
8351 uint64_t reserved_3_7 : 5;
8352 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt
8353 Set any time PIP/IPD drops a packet */
8354 uint64_t ssoiq : 1; /**< SSO IQ interrupt
8356 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt
8357 See IPD_PORT_QOS_INT*
8358 For MIO, all 98 RAW readout will be same value */
8360 uint64_t ipdppthr : 1;
8362 uint64_t ipd_drp : 1;
8363 uint64_t reserved_3_7 : 5;
8365 uint64_t reserved_12_15 : 4;
8368 uint64_t bootdma : 1;
8369 uint64_t reserved_19_31 : 13;
8371 uint64_t reserved_34_35 : 2;
8373 uint64_t reserved_38_39 : 2;
8374 uint64_t usb_uctl : 1;
8375 uint64_t reserved_41_43 : 3;
8376 uint64_t usb_hci : 1;
8377 uint64_t reserved_45_47 : 3;
8379 uint64_t reserved_49_62 : 14;
8383 struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xx;
8384 struct cvmx_ciu2_raw_ppx_ip4_mio_s cn68xxp1;
8386 typedef union cvmx_ciu2_raw_ppx_ip4_mio cvmx_ciu2_raw_ppx_ip4_mio_t;
8389 * cvmx_ciu2_raw_pp#_ip4_pkt
8391 union cvmx_ciu2_raw_ppx_ip4_pkt {
8393 struct cvmx_ciu2_raw_ppx_ip4_pkt_s {
8394 #ifdef __BIG_ENDIAN_BITFIELD
8395 uint64_t reserved_54_63 : 10;
8396 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupt pulse */
8397 uint64_t reserved_49_51 : 3;
8398 uint64_t ilk : 1; /**< ILK interface interrupts */
8399 uint64_t reserved_41_47 : 7;
8400 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
8402 uint64_t reserved_33_39 : 7;
8403 uint64_t agl : 1; /**< AGL interrupt
8404 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
8405 uint64_t reserved_13_31 : 19;
8406 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
8407 Set any time corresponding GMX drops a packet */
8408 uint64_t reserved_5_7 : 3;
8409 uint64_t agx : 5; /**< GMX 0-4 interrupt
8410 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
8411 PCS0_INT*_REG, PCSX*_INT_REG
8412 For PKT, all 98 RAW readout will be same value */
8415 uint64_t reserved_5_7 : 3;
8416 uint64_t gmx_drp : 5;
8417 uint64_t reserved_13_31 : 19;
8419 uint64_t reserved_33_39 : 7;
8421 uint64_t reserved_41_47 : 7;
8423 uint64_t reserved_49_51 : 3;
8424 uint64_t ilk_drp : 2;
8425 uint64_t reserved_54_63 : 10;
8428 struct cvmx_ciu2_raw_ppx_ip4_pkt_s cn68xx;
8429 struct cvmx_ciu2_raw_ppx_ip4_pkt_cn68xxp1 {
8430 #ifdef __BIG_ENDIAN_BITFIELD
8431 uint64_t reserved_49_63 : 15;
8432 uint64_t ilk : 1; /**< ILK interface interrupts */
8433 uint64_t reserved_41_47 : 7;
8434 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts
8436 uint64_t reserved_33_39 : 7;
8437 uint64_t agl : 1; /**< AGL interrupt
8438 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */
8439 uint64_t reserved_13_31 : 19;
8440 uint64_t gmx_drp : 5; /**< GMX 0-4 packet drop interrupt pulse
8441 Set any time corresponding GMX drops a packet */
8442 uint64_t reserved_5_7 : 3;
8443 uint64_t agx : 5; /**< GMX 0-4 interrupt
8444 See GMX*_RX*_INT_REG, GMX*_TX_INT_REG,
8445 PCS0_INT*_REG, PCSX*_INT_REG
8446 For PKT, all 98 RAW readout will be same value */
8449 uint64_t reserved_5_7 : 3;
8450 uint64_t gmx_drp : 5;
8451 uint64_t reserved_13_31 : 19;
8453 uint64_t reserved_33_39 : 7;
8455 uint64_t reserved_41_47 : 7;
8457 uint64_t reserved_49_63 : 15;
8461 typedef union cvmx_ciu2_raw_ppx_ip4_pkt cvmx_ciu2_raw_ppx_ip4_pkt_t;
8464 * cvmx_ciu2_raw_pp#_ip4_rml
8466 union cvmx_ciu2_raw_ppx_ip4_rml {
8468 struct cvmx_ciu2_raw_ppx_ip4_rml_s {
8469 #ifdef __BIG_ENDIAN_BITFIELD
8470 uint64_t reserved_56_63 : 8;
8471 uint64_t trace : 4; /**< Trace buffer interrupt
8472 See TRA_INT_STATUS */
8473 uint64_t reserved_49_51 : 3;
8474 uint64_t l2c : 1; /**< L2C interrupt
8476 uint64_t reserved_41_47 : 7;
8477 uint64_t dfa : 1; /**< DFA interrupt
8479 uint64_t reserved_37_39 : 3;
8480 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
8481 See DPI DMA instruction completion */
8482 uint64_t reserved_34_35 : 2;
8483 uint64_t dpi : 1; /**< DPI interrupt
8485 uint64_t sli : 1; /**< SLI interrupt
8486 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
8487 uint64_t reserved_31_31 : 1;
8488 uint64_t key : 1; /**< KEY interrupt
8490 uint64_t rad : 1; /**< RAD interrupt
8491 See RAD_REG_ERROR */
8492 uint64_t tim : 1; /**< TIM interrupt
8493 See TIM_INT_ECCERR, TIM_INT0 */
8494 uint64_t reserved_25_27 : 3;
8495 uint64_t zip : 1; /**< ZIP interrupt
8497 uint64_t reserved_17_23 : 7;
8498 uint64_t sso : 1; /**< SSO err interrupt
8500 uint64_t reserved_8_15 : 8;
8501 uint64_t pko : 1; /**< PKO interrupt
8502 See PKO_REG_ERROR */
8503 uint64_t pip : 1; /**< PIP interrupt
8505 uint64_t ipd : 1; /**< IPD interrupt
8507 uint64_t fpa : 1; /**< FPA interrupt
8509 uint64_t reserved_1_3 : 3;
8510 uint64_t iob : 1; /**< IOB interrupt
8512 For RML, all 98 RAW readout will be same value */
8515 uint64_t reserved_1_3 : 3;
8520 uint64_t reserved_8_15 : 8;
8522 uint64_t reserved_17_23 : 7;
8524 uint64_t reserved_25_27 : 3;
8528 uint64_t reserved_31_31 : 1;
8531 uint64_t reserved_34_35 : 2;
8532 uint64_t dpi_dma : 1;
8533 uint64_t reserved_37_39 : 3;
8535 uint64_t reserved_41_47 : 7;
8537 uint64_t reserved_49_51 : 3;
8539 uint64_t reserved_56_63 : 8;
8542 struct cvmx_ciu2_raw_ppx_ip4_rml_s cn68xx;
8543 struct cvmx_ciu2_raw_ppx_ip4_rml_cn68xxp1 {
8544 #ifdef __BIG_ENDIAN_BITFIELD
8545 uint64_t reserved_56_63 : 8;
8546 uint64_t trace : 4; /**< Trace buffer interrupt
8547 See TRA_INT_STATUS */
8548 uint64_t reserved_49_51 : 3;
8549 uint64_t l2c : 1; /**< L2C interrupt
8551 uint64_t reserved_41_47 : 7;
8552 uint64_t dfa : 1; /**< DFA interrupt
8554 uint64_t reserved_34_39 : 6;
8555 uint64_t dpi : 1; /**< DPI interrupt
8557 uint64_t sli : 1; /**< SLI interrupt
8558 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */
8559 uint64_t reserved_31_31 : 1;
8560 uint64_t key : 1; /**< KEY interrupt
8562 uint64_t rad : 1; /**< RAD interrupt
8563 See RAD_REG_ERROR */
8564 uint64_t tim : 1; /**< TIM interrupt
8565 See TIM_INT_ECCERR, TIM_INT0 */
8566 uint64_t reserved_25_27 : 3;
8567 uint64_t zip : 1; /**< ZIP interrupt
8569 uint64_t reserved_17_23 : 7;
8570 uint64_t sso : 1; /**< SSO err interrupt
8572 uint64_t reserved_8_15 : 8;
8573 uint64_t pko : 1; /**< PKO interrupt
8574 See PKO_REG_ERROR */
8575 uint64_t pip : 1; /**< PIP interrupt
8577 uint64_t ipd : 1; /**< IPD interrupt
8579 uint64_t fpa : 1; /**< FPA interrupt
8581 uint64_t reserved_1_3 : 3;
8582 uint64_t iob : 1; /**< IOB interrupt
8584 For RML, all 98 RAW readout will be same value */
8587 uint64_t reserved_1_3 : 3;
8592 uint64_t reserved_8_15 : 8;
8594 uint64_t reserved_17_23 : 7;
8596 uint64_t reserved_25_27 : 3;
8600 uint64_t reserved_31_31 : 1;
8603 uint64_t reserved_34_39 : 6;
8605 uint64_t reserved_41_47 : 7;
8607 uint64_t reserved_49_51 : 3;
8609 uint64_t reserved_56_63 : 8;
8613 typedef union cvmx_ciu2_raw_ppx_ip4_rml cvmx_ciu2_raw_ppx_ip4_rml_t;
8616 * cvmx_ciu2_raw_pp#_ip4_wdog
8618 union cvmx_ciu2_raw_ppx_ip4_wdog {
8620 struct cvmx_ciu2_raw_ppx_ip4_wdog_s {
8621 #ifdef __BIG_ENDIAN_BITFIELD
8622 uint64_t reserved_32_63 : 32;
8623 uint64_t wdog : 32; /**< 32 watchdog interrupts
8624 For WDOG, all 98 RAW readout will be same value */
8627 uint64_t reserved_32_63 : 32;
8630 struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xx;
8631 struct cvmx_ciu2_raw_ppx_ip4_wdog_s cn68xxp1;
8633 typedef union cvmx_ciu2_raw_ppx_ip4_wdog cvmx_ciu2_raw_ppx_ip4_wdog_t;
8636 * cvmx_ciu2_raw_pp#_ip4_wrkq
8638 union cvmx_ciu2_raw_ppx_ip4_wrkq {
8640 struct cvmx_ciu2_raw_ppx_ip4_wrkq_s {
8641 #ifdef __BIG_ENDIAN_BITFIELD
8642 uint64_t workq : 64; /**< 64 work queue interrupts
8643 See SSO_WQ_INT[WQ_INT]
8644 1 bit/group. A copy of the R/W1C bit in the SSO.
8645 For WRKQ, all 98 RAW readout will be same value */
8647 uint64_t workq : 64;
8650 struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xx;
8651 struct cvmx_ciu2_raw_ppx_ip4_wrkq_s cn68xxp1;
8653 typedef union cvmx_ciu2_raw_ppx_ip4_wrkq cvmx_ciu2_raw_ppx_ip4_wrkq_t;
8656 * cvmx_ciu2_src_io#_int_gpio
8658 union cvmx_ciu2_src_iox_int_gpio {
8660 struct cvmx_ciu2_src_iox_int_gpio_s {
8661 #ifdef __BIG_ENDIAN_BITFIELD
8662 uint64_t reserved_16_63 : 48;
8663 uint64_t gpio : 16; /**< 16 GPIO interrupts source */
8666 uint64_t reserved_16_63 : 48;
8669 struct cvmx_ciu2_src_iox_int_gpio_s cn68xx;
8670 struct cvmx_ciu2_src_iox_int_gpio_s cn68xxp1;
8672 typedef union cvmx_ciu2_src_iox_int_gpio cvmx_ciu2_src_iox_int_gpio_t;
8675 * cvmx_ciu2_src_io#_int_io
8677 union cvmx_ciu2_src_iox_int_io {
8679 struct cvmx_ciu2_src_iox_int_io_s {
8680 #ifdef __BIG_ENDIAN_BITFIELD
8681 uint64_t reserved_34_63 : 30;
8682 uint64_t pem : 2; /**< PEMx interrupt source
8683 CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
8684 uint64_t reserved_18_31 : 14;
8685 uint64_t pci_inta : 2; /**< PCI_INTA source
8686 CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
8687 uint64_t reserved_13_15 : 3;
8688 uint64_t msired : 1; /**< MSI summary bit source
8689 CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
8690 This bit may not be functional in pass 1. */
8691 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source
8692 CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
8693 uint64_t reserved_4_7 : 4;
8694 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source
8695 CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
8697 uint64_t pci_intr : 4;
8698 uint64_t reserved_4_7 : 4;
8699 uint64_t pci_msi : 4;
8700 uint64_t msired : 1;
8701 uint64_t reserved_13_15 : 3;
8702 uint64_t pci_inta : 2;
8703 uint64_t reserved_18_31 : 14;
8705 uint64_t reserved_34_63 : 30;
8708 struct cvmx_ciu2_src_iox_int_io_s cn68xx;
8709 struct cvmx_ciu2_src_iox_int_io_s cn68xxp1;
8711 typedef union cvmx_ciu2_src_iox_int_io cvmx_ciu2_src_iox_int_io_t;
8714 * cvmx_ciu2_src_io#_int_mbox
8716 union cvmx_ciu2_src_iox_int_mbox {
8718 struct cvmx_ciu2_src_iox_int_mbox_s {
8719 #ifdef __BIG_ENDIAN_BITFIELD
8720 uint64_t reserved_4_63 : 60;
8721 uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE)
8722 For CIU2_SRC_PPX_IPx_MBOX:
8723 Four mailbox interrupts for entries 0-31
8725 [3] is the or of <31:24> of CIU2_MBOX
8726 [2] is the or of <23:16> of CIU2_MBOX
8727 [1] is the or of <15:8> of CIU2_MBOX
8728 [0] is the or of <7:0> of CIU2_MBOX
8729 CIU2_MBOX value can be read out via CSR address
8731 For CIU2_SRC_IOX_INT_MBOX:
8735 uint64_t reserved_4_63 : 60;
8738 struct cvmx_ciu2_src_iox_int_mbox_s cn68xx;
8739 struct cvmx_ciu2_src_iox_int_mbox_s cn68xxp1;
8741 typedef union cvmx_ciu2_src_iox_int_mbox cvmx_ciu2_src_iox_int_mbox_t;
8744 * cvmx_ciu2_src_io#_int_mem
8746 union cvmx_ciu2_src_iox_int_mem {
8748 struct cvmx_ciu2_src_iox_int_mem_s {
8749 #ifdef __BIG_ENDIAN_BITFIELD
8750 uint64_t reserved_4_63 : 60;
8751 uint64_t lmc : 4; /**< LMC* interrupt source
8752 CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
8755 uint64_t reserved_4_63 : 60;
8758 struct cvmx_ciu2_src_iox_int_mem_s cn68xx;
8759 struct cvmx_ciu2_src_iox_int_mem_s cn68xxp1;
8761 typedef union cvmx_ciu2_src_iox_int_mem cvmx_ciu2_src_iox_int_mem_t;
8764 * cvmx_ciu2_src_io#_int_mio
8766 union cvmx_ciu2_src_iox_int_mio {
8768 struct cvmx_ciu2_src_iox_int_mio_s {
8769 #ifdef __BIG_ENDIAN_BITFIELD
8770 uint64_t rst : 1; /**< MIO RST interrupt source
8771 CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
8772 uint64_t reserved_49_62 : 14;
8773 uint64_t ptp : 1; /**< PTP interrupt source
8774 CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
8775 uint64_t reserved_45_47 : 3;
8776 uint64_t usb_hci : 1; /**< USB HCI Interrupt source
8777 CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
8778 uint64_t reserved_41_43 : 3;
8779 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source
8780 CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
8781 uint64_t reserved_38_39 : 2;
8782 uint64_t uart : 2; /**< Two UART interrupts source
8783 CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
8784 uint64_t reserved_34_35 : 2;
8785 uint64_t twsi : 2; /**< TWSI x Interrupt source
8786 CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
8787 uint64_t reserved_19_31 : 13;
8788 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source
8789 CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
8790 uint64_t mio : 1; /**< MIO boot interrupt source
8791 CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
8792 uint64_t nand : 1; /**< NAND Flash Controller interrupt source
8793 CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
8794 uint64_t reserved_12_15 : 4;
8795 uint64_t timer : 4; /**< General timer interrupts source
8796 CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
8797 uint64_t reserved_3_7 : 5;
8798 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source
8799 CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
8800 uint64_t ssoiq : 1; /**< SSO IQ interrupt source
8801 CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
8802 uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source
8803 CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
8805 uint64_t ipdppthr : 1;
8807 uint64_t ipd_drp : 1;
8808 uint64_t reserved_3_7 : 5;
8810 uint64_t reserved_12_15 : 4;
8813 uint64_t bootdma : 1;
8814 uint64_t reserved_19_31 : 13;
8816 uint64_t reserved_34_35 : 2;
8818 uint64_t reserved_38_39 : 2;
8819 uint64_t usb_uctl : 1;
8820 uint64_t reserved_41_43 : 3;
8821 uint64_t usb_hci : 1;
8822 uint64_t reserved_45_47 : 3;
8824 uint64_t reserved_49_62 : 14;
8828 struct cvmx_ciu2_src_iox_int_mio_s cn68xx;
8829 struct cvmx_ciu2_src_iox_int_mio_s cn68xxp1;
8831 typedef union cvmx_ciu2_src_iox_int_mio cvmx_ciu2_src_iox_int_mio_t;
8834 * cvmx_ciu2_src_io#_int_pkt
8836 union cvmx_ciu2_src_iox_int_pkt {
8838 struct cvmx_ciu2_src_iox_int_pkt_s {
8839 #ifdef __BIG_ENDIAN_BITFIELD
8840 uint64_t reserved_54_63 : 10;
8841 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source
8842 CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
8843 uint64_t reserved_49_51 : 3;
8844 uint64_t ilk : 1; /**< ILK interface interrupts source
8845 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
8846 uint64_t reserved_41_47 : 7;
8847 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
8848 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
8849 uint64_t reserved_33_39 : 7;
8850 uint64_t agl : 1; /**< AGL interrupt source
8851 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
8852 uint64_t reserved_13_31 : 19;
8853 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
8854 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
8855 uint64_t reserved_5_7 : 3;
8856 uint64_t agx : 5; /**< GMX interrupt source
8857 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
8860 uint64_t reserved_5_7 : 3;
8861 uint64_t gmx_drp : 5;
8862 uint64_t reserved_13_31 : 19;
8864 uint64_t reserved_33_39 : 7;
8866 uint64_t reserved_41_47 : 7;
8868 uint64_t reserved_49_51 : 3;
8869 uint64_t ilk_drp : 2;
8870 uint64_t reserved_54_63 : 10;
8873 struct cvmx_ciu2_src_iox_int_pkt_s cn68xx;
8874 struct cvmx_ciu2_src_iox_int_pkt_cn68xxp1 {
8875 #ifdef __BIG_ENDIAN_BITFIELD
8876 uint64_t reserved_49_63 : 15;
8877 uint64_t ilk : 1; /**< ILK interface interrupts source
8878 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
8879 uint64_t reserved_41_47 : 7;
8880 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
8881 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
8882 uint64_t reserved_33_39 : 7;
8883 uint64_t agl : 1; /**< AGL interrupt source
8884 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
8885 uint64_t reserved_13_31 : 19;
8886 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
8887 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
8888 uint64_t reserved_5_7 : 3;
8889 uint64_t agx : 5; /**< GMX interrupt source
8890 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
8893 uint64_t reserved_5_7 : 3;
8894 uint64_t gmx_drp : 5;
8895 uint64_t reserved_13_31 : 19;
8897 uint64_t reserved_33_39 : 7;
8899 uint64_t reserved_41_47 : 7;
8901 uint64_t reserved_49_63 : 15;
8905 typedef union cvmx_ciu2_src_iox_int_pkt cvmx_ciu2_src_iox_int_pkt_t;
8908 * cvmx_ciu2_src_io#_int_rml
8910 union cvmx_ciu2_src_iox_int_rml {
8912 struct cvmx_ciu2_src_iox_int_rml_s {
8913 #ifdef __BIG_ENDIAN_BITFIELD
8914 uint64_t reserved_56_63 : 8;
8915 uint64_t trace : 4; /**< Trace buffer interrupt source
8916 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
8917 uint64_t reserved_49_51 : 3;
8918 uint64_t l2c : 1; /**< L2C interrupt source
8919 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
8920 uint64_t reserved_41_47 : 7;
8921 uint64_t dfa : 1; /**< DFA interrupt source
8922 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
8923 uint64_t reserved_37_39 : 3;
8924 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
8925 See DPI DMA instruction completion */
8926 uint64_t reserved_34_35 : 2;
8927 uint64_t dpi : 1; /**< DPI interrupt source
8928 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
8929 uint64_t sli : 1; /**< SLI interrupt source
8930 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
8931 uint64_t reserved_31_31 : 1;
8932 uint64_t key : 1; /**< KEY interrupt source
8933 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
8934 uint64_t rad : 1; /**< RAD interrupt source
8935 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
8936 uint64_t tim : 1; /**< TIM interrupt source
8937 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
8938 uint64_t reserved_25_27 : 3;
8939 uint64_t zip : 1; /**< ZIP interrupt source
8940 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
8941 uint64_t reserved_17_23 : 7;
8942 uint64_t sso : 1; /**< SSO err interrupt source
8943 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
8944 uint64_t reserved_8_15 : 8;
8945 uint64_t pko : 1; /**< PKO interrupt source
8946 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
8947 uint64_t pip : 1; /**< PIP interrupt source
8948 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
8949 uint64_t ipd : 1; /**< IPD interrupt source
8950 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
8951 uint64_t fpa : 1; /**< FPA interrupt source
8952 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
8953 uint64_t reserved_1_3 : 3;
8954 uint64_t iob : 1; /**< IOB interrupt source
8955 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
8958 uint64_t reserved_1_3 : 3;
8963 uint64_t reserved_8_15 : 8;
8965 uint64_t reserved_17_23 : 7;
8967 uint64_t reserved_25_27 : 3;
8971 uint64_t reserved_31_31 : 1;
8974 uint64_t reserved_34_35 : 2;
8975 uint64_t dpi_dma : 1;
8976 uint64_t reserved_37_39 : 3;
8978 uint64_t reserved_41_47 : 7;
8980 uint64_t reserved_49_51 : 3;
8982 uint64_t reserved_56_63 : 8;
8985 struct cvmx_ciu2_src_iox_int_rml_s cn68xx;
8986 struct cvmx_ciu2_src_iox_int_rml_cn68xxp1 {
8987 #ifdef __BIG_ENDIAN_BITFIELD
8988 uint64_t reserved_56_63 : 8;
8989 uint64_t trace : 4; /**< Trace buffer interrupt source
8990 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
8991 uint64_t reserved_49_51 : 3;
8992 uint64_t l2c : 1; /**< L2C interrupt source
8993 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
8994 uint64_t reserved_41_47 : 7;
8995 uint64_t dfa : 1; /**< DFA interrupt source
8996 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
8997 uint64_t reserved_34_39 : 6;
8998 uint64_t dpi : 1; /**< DPI interrupt source
8999 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
9000 uint64_t sli : 1; /**< SLI interrupt source
9001 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
9002 uint64_t reserved_31_31 : 1;
9003 uint64_t key : 1; /**< KEY interrupt source
9004 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
9005 uint64_t rad : 1; /**< RAD interrupt source
9006 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
9007 uint64_t tim : 1; /**< TIM interrupt source
9008 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
9009 uint64_t reserved_25_27 : 3;
9010 uint64_t zip : 1; /**< ZIP interrupt source
9011 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
9012 uint64_t reserved_17_23 : 7;
9013 uint64_t sso : 1; /**< SSO err interrupt source
9014 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
9015 uint64_t reserved_8_15 : 8;
9016 uint64_t pko : 1; /**< PKO interrupt source
9017 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
9018 uint64_t pip : 1; /**< PIP interrupt source
9019 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
9020 uint64_t ipd : 1; /**< IPD interrupt source
9021 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
9022 uint64_t fpa : 1; /**< FPA interrupt source
9023 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
9024 uint64_t reserved_1_3 : 3;
9025 uint64_t iob : 1; /**< IOB interrupt source
9026 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
9029 uint64_t reserved_1_3 : 3;
9034 uint64_t reserved_8_15 : 8;
9036 uint64_t reserved_17_23 : 7;
9038 uint64_t reserved_25_27 : 3;
9042 uint64_t reserved_31_31 : 1;
9045 uint64_t reserved_34_39 : 6;
9047 uint64_t reserved_41_47 : 7;
9049 uint64_t reserved_49_51 : 3;
9051 uint64_t reserved_56_63 : 8;
9055 typedef union cvmx_ciu2_src_iox_int_rml cvmx_ciu2_src_iox_int_rml_t;
9058 * cvmx_ciu2_src_io#_int_wdog
9060 union cvmx_ciu2_src_iox_int_wdog {
9062 struct cvmx_ciu2_src_iox_int_wdog_s {
9063 #ifdef __BIG_ENDIAN_BITFIELD
9064 uint64_t reserved_32_63 : 32;
9065 uint64_t wdog : 32; /**< 32 watchdog interrupts source
9066 CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
9069 uint64_t reserved_32_63 : 32;
9072 struct cvmx_ciu2_src_iox_int_wdog_s cn68xx;
9073 struct cvmx_ciu2_src_iox_int_wdog_s cn68xxp1;
9075 typedef union cvmx_ciu2_src_iox_int_wdog cvmx_ciu2_src_iox_int_wdog_t;
9078 * cvmx_ciu2_src_io#_int_wrkq
9080 union cvmx_ciu2_src_iox_int_wrkq {
9082 struct cvmx_ciu2_src_iox_int_wrkq_s {
9083 #ifdef __BIG_ENDIAN_BITFIELD
9084 uint64_t workq : 64; /**< 64 work queue intr source,
9085 CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
9087 uint64_t workq : 64;
9090 struct cvmx_ciu2_src_iox_int_wrkq_s cn68xx;
9091 struct cvmx_ciu2_src_iox_int_wrkq_s cn68xxp1;
9093 typedef union cvmx_ciu2_src_iox_int_wrkq cvmx_ciu2_src_iox_int_wrkq_t;
9096 * cvmx_ciu2_src_pp#_ip2_gpio
9098 union cvmx_ciu2_src_ppx_ip2_gpio {
9100 struct cvmx_ciu2_src_ppx_ip2_gpio_s {
9101 #ifdef __BIG_ENDIAN_BITFIELD
9102 uint64_t reserved_16_63 : 48;
9103 uint64_t gpio : 16; /**< 16 GPIO interrupts source */
9106 uint64_t reserved_16_63 : 48;
9109 struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xx;
9110 struct cvmx_ciu2_src_ppx_ip2_gpio_s cn68xxp1;
9112 typedef union cvmx_ciu2_src_ppx_ip2_gpio cvmx_ciu2_src_ppx_ip2_gpio_t;
9115 * cvmx_ciu2_src_pp#_ip2_io
9117 union cvmx_ciu2_src_ppx_ip2_io {
9119 struct cvmx_ciu2_src_ppx_ip2_io_s {
9120 #ifdef __BIG_ENDIAN_BITFIELD
9121 uint64_t reserved_34_63 : 30;
9122 uint64_t pem : 2; /**< PEMx interrupt source
9123 CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
9124 uint64_t reserved_18_31 : 14;
9125 uint64_t pci_inta : 2; /**< PCI_INTA source
9126 CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
9127 uint64_t reserved_13_15 : 3;
9128 uint64_t msired : 1; /**< MSI summary bit source
9129 CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
9130 This bit may not be functional in pass 1. */
9131 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source
9132 CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
9133 uint64_t reserved_4_7 : 4;
9134 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source
9135 CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
9137 uint64_t pci_intr : 4;
9138 uint64_t reserved_4_7 : 4;
9139 uint64_t pci_msi : 4;
9140 uint64_t msired : 1;
9141 uint64_t reserved_13_15 : 3;
9142 uint64_t pci_inta : 2;
9143 uint64_t reserved_18_31 : 14;
9145 uint64_t reserved_34_63 : 30;
9148 struct cvmx_ciu2_src_ppx_ip2_io_s cn68xx;
9149 struct cvmx_ciu2_src_ppx_ip2_io_s cn68xxp1;
9151 typedef union cvmx_ciu2_src_ppx_ip2_io cvmx_ciu2_src_ppx_ip2_io_t;
9154 * cvmx_ciu2_src_pp#_ip2_mbox
9156 union cvmx_ciu2_src_ppx_ip2_mbox {
9158 struct cvmx_ciu2_src_ppx_ip2_mbox_s {
9159 #ifdef __BIG_ENDIAN_BITFIELD
9160 uint64_t reserved_4_63 : 60;
9161 uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE)
9162 For CIU2_SRC_PPX_IPx_MBOX:
9163 Four mailbox interrupts for entries 0-31
9165 [3] is the or of <31:24> of CIU2_MBOX
9166 [2] is the or of <23:16> of CIU2_MBOX
9167 [1] is the or of <15:8> of CIU2_MBOX
9168 [0] is the or of <7:0> of CIU2_MBOX
9169 CIU2_MBOX value can be read out via CSR address
9171 For CIU2_SRC_IOX_INT_MBOX:
9175 uint64_t reserved_4_63 : 60;
9178 struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xx;
9179 struct cvmx_ciu2_src_ppx_ip2_mbox_s cn68xxp1;
9181 typedef union cvmx_ciu2_src_ppx_ip2_mbox cvmx_ciu2_src_ppx_ip2_mbox_t;
9184 * cvmx_ciu2_src_pp#_ip2_mem
9186 union cvmx_ciu2_src_ppx_ip2_mem {
9188 struct cvmx_ciu2_src_ppx_ip2_mem_s {
9189 #ifdef __BIG_ENDIAN_BITFIELD
9190 uint64_t reserved_4_63 : 60;
9191 uint64_t lmc : 4; /**< LMC* interrupt source
9192 CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
9195 uint64_t reserved_4_63 : 60;
9198 struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xx;
9199 struct cvmx_ciu2_src_ppx_ip2_mem_s cn68xxp1;
9201 typedef union cvmx_ciu2_src_ppx_ip2_mem cvmx_ciu2_src_ppx_ip2_mem_t;
9204 * cvmx_ciu2_src_pp#_ip2_mio
9206 union cvmx_ciu2_src_ppx_ip2_mio {
9208 struct cvmx_ciu2_src_ppx_ip2_mio_s {
9209 #ifdef __BIG_ENDIAN_BITFIELD
9210 uint64_t rst : 1; /**< MIO RST interrupt source
9211 CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
9212 uint64_t reserved_49_62 : 14;
9213 uint64_t ptp : 1; /**< PTP interrupt source
9214 CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
9215 uint64_t reserved_45_47 : 3;
9216 uint64_t usb_hci : 1; /**< USB HCI Interrupt source
9217 CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
9218 uint64_t reserved_41_43 : 3;
9219 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source
9220 CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
9221 uint64_t reserved_38_39 : 2;
9222 uint64_t uart : 2; /**< Two UART interrupts source
9223 CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
9224 uint64_t reserved_34_35 : 2;
9225 uint64_t twsi : 2; /**< TWSI x Interrupt source
9226 CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
9227 uint64_t reserved_19_31 : 13;
9228 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source
9229 CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
9230 uint64_t mio : 1; /**< MIO boot interrupt source
9231 CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
9232 uint64_t nand : 1; /**< NAND Flash Controller interrupt source
9233 CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
9234 uint64_t reserved_12_15 : 4;
9235 uint64_t timer : 4; /**< General timer interrupts source
9236 CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
9237 uint64_t reserved_3_7 : 5;
9238 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source
9239 CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
9240 uint64_t ssoiq : 1; /**< SSO IQ interrupt source
9241 CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
9242 uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source
9243 CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
9245 uint64_t ipdppthr : 1;
9247 uint64_t ipd_drp : 1;
9248 uint64_t reserved_3_7 : 5;
9250 uint64_t reserved_12_15 : 4;
9253 uint64_t bootdma : 1;
9254 uint64_t reserved_19_31 : 13;
9256 uint64_t reserved_34_35 : 2;
9258 uint64_t reserved_38_39 : 2;
9259 uint64_t usb_uctl : 1;
9260 uint64_t reserved_41_43 : 3;
9261 uint64_t usb_hci : 1;
9262 uint64_t reserved_45_47 : 3;
9264 uint64_t reserved_49_62 : 14;
9268 struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xx;
9269 struct cvmx_ciu2_src_ppx_ip2_mio_s cn68xxp1;
9271 typedef union cvmx_ciu2_src_ppx_ip2_mio cvmx_ciu2_src_ppx_ip2_mio_t;
9274 * cvmx_ciu2_src_pp#_ip2_pkt
9276 union cvmx_ciu2_src_ppx_ip2_pkt {
9278 struct cvmx_ciu2_src_ppx_ip2_pkt_s {
9279 #ifdef __BIG_ENDIAN_BITFIELD
9280 uint64_t reserved_54_63 : 10;
9281 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source
9282 CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
9283 uint64_t reserved_49_51 : 3;
9284 uint64_t ilk : 1; /**< ILK interface interrupts source
9285 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
9286 uint64_t reserved_41_47 : 7;
9287 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
9288 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
9289 uint64_t reserved_33_39 : 7;
9290 uint64_t agl : 1; /**< AGL interrupt source
9291 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
9292 uint64_t reserved_13_31 : 19;
9293 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
9294 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
9295 uint64_t reserved_5_7 : 3;
9296 uint64_t agx : 5; /**< GMX interrupt source
9297 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
9300 uint64_t reserved_5_7 : 3;
9301 uint64_t gmx_drp : 5;
9302 uint64_t reserved_13_31 : 19;
9304 uint64_t reserved_33_39 : 7;
9306 uint64_t reserved_41_47 : 7;
9308 uint64_t reserved_49_51 : 3;
9309 uint64_t ilk_drp : 2;
9310 uint64_t reserved_54_63 : 10;
9313 struct cvmx_ciu2_src_ppx_ip2_pkt_s cn68xx;
9314 struct cvmx_ciu2_src_ppx_ip2_pkt_cn68xxp1 {
9315 #ifdef __BIG_ENDIAN_BITFIELD
9316 uint64_t reserved_49_63 : 15;
9317 uint64_t ilk : 1; /**< ILK interface interrupts source
9318 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
9319 uint64_t reserved_41_47 : 7;
9320 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
9321 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
9322 uint64_t reserved_33_39 : 7;
9323 uint64_t agl : 1; /**< AGL interrupt source
9324 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
9325 uint64_t reserved_13_31 : 19;
9326 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
9327 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
9328 uint64_t reserved_5_7 : 3;
9329 uint64_t agx : 5; /**< GMX interrupt source
9330 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
9333 uint64_t reserved_5_7 : 3;
9334 uint64_t gmx_drp : 5;
9335 uint64_t reserved_13_31 : 19;
9337 uint64_t reserved_33_39 : 7;
9339 uint64_t reserved_41_47 : 7;
9341 uint64_t reserved_49_63 : 15;
9345 typedef union cvmx_ciu2_src_ppx_ip2_pkt cvmx_ciu2_src_ppx_ip2_pkt_t;
9348 * cvmx_ciu2_src_pp#_ip2_rml
9350 union cvmx_ciu2_src_ppx_ip2_rml {
9352 struct cvmx_ciu2_src_ppx_ip2_rml_s {
9353 #ifdef __BIG_ENDIAN_BITFIELD
9354 uint64_t reserved_56_63 : 8;
9355 uint64_t trace : 4; /**< Trace buffer interrupt source
9356 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
9357 uint64_t reserved_49_51 : 3;
9358 uint64_t l2c : 1; /**< L2C interrupt source
9359 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
9360 uint64_t reserved_41_47 : 7;
9361 uint64_t dfa : 1; /**< DFA interrupt source
9362 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
9363 uint64_t reserved_37_39 : 3;
9364 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
9365 See DPI DMA instruction completion */
9366 uint64_t reserved_34_35 : 2;
9367 uint64_t dpi : 1; /**< DPI interrupt source
9368 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
9369 uint64_t sli : 1; /**< SLI interrupt source
9370 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
9371 uint64_t reserved_31_31 : 1;
9372 uint64_t key : 1; /**< KEY interrupt source
9373 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
9374 uint64_t rad : 1; /**< RAD interrupt source
9375 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
9376 uint64_t tim : 1; /**< TIM interrupt source
9377 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
9378 uint64_t reserved_25_27 : 3;
9379 uint64_t zip : 1; /**< ZIP interrupt source
9380 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
9381 uint64_t reserved_17_23 : 7;
9382 uint64_t sso : 1; /**< SSO err interrupt source
9383 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
9384 uint64_t reserved_8_15 : 8;
9385 uint64_t pko : 1; /**< PKO interrupt source
9386 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
9387 uint64_t pip : 1; /**< PIP interrupt source
9388 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
9389 uint64_t ipd : 1; /**< IPD interrupt source
9390 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
9391 uint64_t fpa : 1; /**< FPA interrupt source
9392 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
9393 uint64_t reserved_1_3 : 3;
9394 uint64_t iob : 1; /**< IOB interrupt source
9395 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
9398 uint64_t reserved_1_3 : 3;
9403 uint64_t reserved_8_15 : 8;
9405 uint64_t reserved_17_23 : 7;
9407 uint64_t reserved_25_27 : 3;
9411 uint64_t reserved_31_31 : 1;
9414 uint64_t reserved_34_35 : 2;
9415 uint64_t dpi_dma : 1;
9416 uint64_t reserved_37_39 : 3;
9418 uint64_t reserved_41_47 : 7;
9420 uint64_t reserved_49_51 : 3;
9422 uint64_t reserved_56_63 : 8;
9425 struct cvmx_ciu2_src_ppx_ip2_rml_s cn68xx;
9426 struct cvmx_ciu2_src_ppx_ip2_rml_cn68xxp1 {
9427 #ifdef __BIG_ENDIAN_BITFIELD
9428 uint64_t reserved_56_63 : 8;
9429 uint64_t trace : 4; /**< Trace buffer interrupt source
9430 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
9431 uint64_t reserved_49_51 : 3;
9432 uint64_t l2c : 1; /**< L2C interrupt source
9433 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
9434 uint64_t reserved_41_47 : 7;
9435 uint64_t dfa : 1; /**< DFA interrupt source
9436 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
9437 uint64_t reserved_34_39 : 6;
9438 uint64_t dpi : 1; /**< DPI interrupt source
9439 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
9440 uint64_t sli : 1; /**< SLI interrupt source
9441 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
9442 uint64_t reserved_31_31 : 1;
9443 uint64_t key : 1; /**< KEY interrupt source
9444 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
9445 uint64_t rad : 1; /**< RAD interrupt source
9446 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
9447 uint64_t tim : 1; /**< TIM interrupt source
9448 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
9449 uint64_t reserved_25_27 : 3;
9450 uint64_t zip : 1; /**< ZIP interrupt source
9451 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
9452 uint64_t reserved_17_23 : 7;
9453 uint64_t sso : 1; /**< SSO err interrupt source
9454 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
9455 uint64_t reserved_8_15 : 8;
9456 uint64_t pko : 1; /**< PKO interrupt source
9457 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
9458 uint64_t pip : 1; /**< PIP interrupt source
9459 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
9460 uint64_t ipd : 1; /**< IPD interrupt source
9461 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
9462 uint64_t fpa : 1; /**< FPA interrupt source
9463 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
9464 uint64_t reserved_1_3 : 3;
9465 uint64_t iob : 1; /**< IOB interrupt source
9466 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
9469 uint64_t reserved_1_3 : 3;
9474 uint64_t reserved_8_15 : 8;
9476 uint64_t reserved_17_23 : 7;
9478 uint64_t reserved_25_27 : 3;
9482 uint64_t reserved_31_31 : 1;
9485 uint64_t reserved_34_39 : 6;
9487 uint64_t reserved_41_47 : 7;
9489 uint64_t reserved_49_51 : 3;
9491 uint64_t reserved_56_63 : 8;
9495 typedef union cvmx_ciu2_src_ppx_ip2_rml cvmx_ciu2_src_ppx_ip2_rml_t;
9498 * cvmx_ciu2_src_pp#_ip2_wdog
9500 union cvmx_ciu2_src_ppx_ip2_wdog {
9502 struct cvmx_ciu2_src_ppx_ip2_wdog_s {
9503 #ifdef __BIG_ENDIAN_BITFIELD
9504 uint64_t reserved_32_63 : 32;
9505 uint64_t wdog : 32; /**< 32 watchdog interrupts source
9506 CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
9509 uint64_t reserved_32_63 : 32;
9512 struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xx;
9513 struct cvmx_ciu2_src_ppx_ip2_wdog_s cn68xxp1;
9515 typedef union cvmx_ciu2_src_ppx_ip2_wdog cvmx_ciu2_src_ppx_ip2_wdog_t;
9518 * cvmx_ciu2_src_pp#_ip2_wrkq
9520 * All SRC values is generated by AND Raw value (CIU2_RAW_XXX) with CIU2_EN_PPX_IPx_XXX
9523 union cvmx_ciu2_src_ppx_ip2_wrkq {
9525 struct cvmx_ciu2_src_ppx_ip2_wrkq_s {
9526 #ifdef __BIG_ENDIAN_BITFIELD
9527 uint64_t workq : 64; /**< 64 work queue intr source,
9528 CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
9530 uint64_t workq : 64;
9533 struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xx;
9534 struct cvmx_ciu2_src_ppx_ip2_wrkq_s cn68xxp1;
9536 typedef union cvmx_ciu2_src_ppx_ip2_wrkq cvmx_ciu2_src_ppx_ip2_wrkq_t;
9539 * cvmx_ciu2_src_pp#_ip3_gpio
9541 union cvmx_ciu2_src_ppx_ip3_gpio {
9543 struct cvmx_ciu2_src_ppx_ip3_gpio_s {
9544 #ifdef __BIG_ENDIAN_BITFIELD
9545 uint64_t reserved_16_63 : 48;
9546 uint64_t gpio : 16; /**< 16 GPIO interrupts source */
9549 uint64_t reserved_16_63 : 48;
9552 struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xx;
9553 struct cvmx_ciu2_src_ppx_ip3_gpio_s cn68xxp1;
9555 typedef union cvmx_ciu2_src_ppx_ip3_gpio cvmx_ciu2_src_ppx_ip3_gpio_t;
9558 * cvmx_ciu2_src_pp#_ip3_io
9560 union cvmx_ciu2_src_ppx_ip3_io {
9562 struct cvmx_ciu2_src_ppx_ip3_io_s {
9563 #ifdef __BIG_ENDIAN_BITFIELD
9564 uint64_t reserved_34_63 : 30;
9565 uint64_t pem : 2; /**< PEMx interrupt source
9566 CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
9567 uint64_t reserved_18_31 : 14;
9568 uint64_t pci_inta : 2; /**< PCI_INTA source
9569 CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
9570 uint64_t reserved_13_15 : 3;
9571 uint64_t msired : 1; /**< MSI summary bit source
9572 CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
9573 This bit may not be functional in pass 1. */
9574 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source
9575 CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
9576 uint64_t reserved_4_7 : 4;
9577 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source
9578 CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
9580 uint64_t pci_intr : 4;
9581 uint64_t reserved_4_7 : 4;
9582 uint64_t pci_msi : 4;
9583 uint64_t msired : 1;
9584 uint64_t reserved_13_15 : 3;
9585 uint64_t pci_inta : 2;
9586 uint64_t reserved_18_31 : 14;
9588 uint64_t reserved_34_63 : 30;
9591 struct cvmx_ciu2_src_ppx_ip3_io_s cn68xx;
9592 struct cvmx_ciu2_src_ppx_ip3_io_s cn68xxp1;
9594 typedef union cvmx_ciu2_src_ppx_ip3_io cvmx_ciu2_src_ppx_ip3_io_t;
9597 * cvmx_ciu2_src_pp#_ip3_mbox
9599 union cvmx_ciu2_src_ppx_ip3_mbox {
9601 struct cvmx_ciu2_src_ppx_ip3_mbox_s {
9602 #ifdef __BIG_ENDIAN_BITFIELD
9603 uint64_t reserved_4_63 : 60;
9604 uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE)
9605 For CIU2_SRC_PPX_IPx_MBOX:
9606 Four mailbox interrupts for entries 0-31
9608 [3] is the or of <31:24> of CIU2_MBOX
9609 [2] is the or of <23:16> of CIU2_MBOX
9610 [1] is the or of <15:8> of CIU2_MBOX
9611 [0] is the or of <7:0> of CIU2_MBOX
9612 CIU2_MBOX value can be read out via CSR address
9614 For CIU2_SRC_IOX_INT_MBOX:
9618 uint64_t reserved_4_63 : 60;
9621 struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xx;
9622 struct cvmx_ciu2_src_ppx_ip3_mbox_s cn68xxp1;
9624 typedef union cvmx_ciu2_src_ppx_ip3_mbox cvmx_ciu2_src_ppx_ip3_mbox_t;
9627 * cvmx_ciu2_src_pp#_ip3_mem
9629 union cvmx_ciu2_src_ppx_ip3_mem {
9631 struct cvmx_ciu2_src_ppx_ip3_mem_s {
9632 #ifdef __BIG_ENDIAN_BITFIELD
9633 uint64_t reserved_4_63 : 60;
9634 uint64_t lmc : 4; /**< LMC* interrupt source
9635 CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
9638 uint64_t reserved_4_63 : 60;
9641 struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xx;
9642 struct cvmx_ciu2_src_ppx_ip3_mem_s cn68xxp1;
9644 typedef union cvmx_ciu2_src_ppx_ip3_mem cvmx_ciu2_src_ppx_ip3_mem_t;
9647 * cvmx_ciu2_src_pp#_ip3_mio
9649 union cvmx_ciu2_src_ppx_ip3_mio {
9651 struct cvmx_ciu2_src_ppx_ip3_mio_s {
9652 #ifdef __BIG_ENDIAN_BITFIELD
9653 uint64_t rst : 1; /**< MIO RST interrupt source
9654 CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
9655 uint64_t reserved_49_62 : 14;
9656 uint64_t ptp : 1; /**< PTP interrupt source
9657 CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
9658 uint64_t reserved_45_47 : 3;
9659 uint64_t usb_hci : 1; /**< USB HCI Interrupt source
9660 CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
9661 uint64_t reserved_41_43 : 3;
9662 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source
9663 CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
9664 uint64_t reserved_38_39 : 2;
9665 uint64_t uart : 2; /**< Two UART interrupts source
9666 CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
9667 uint64_t reserved_34_35 : 2;
9668 uint64_t twsi : 2; /**< TWSI x Interrupt source
9669 CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
9670 uint64_t reserved_19_31 : 13;
9671 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source
9672 CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
9673 uint64_t mio : 1; /**< MIO boot interrupt source
9674 CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
9675 uint64_t nand : 1; /**< NAND Flash Controller interrupt source
9676 CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
9677 uint64_t reserved_12_15 : 4;
9678 uint64_t timer : 4; /**< General timer interrupts source
9679 CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
9680 uint64_t reserved_3_7 : 5;
9681 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source
9682 CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
9683 uint64_t ssoiq : 1; /**< SSO IQ interrupt source
9684 CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
9685 uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source
9686 CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
9688 uint64_t ipdppthr : 1;
9690 uint64_t ipd_drp : 1;
9691 uint64_t reserved_3_7 : 5;
9693 uint64_t reserved_12_15 : 4;
9696 uint64_t bootdma : 1;
9697 uint64_t reserved_19_31 : 13;
9699 uint64_t reserved_34_35 : 2;
9701 uint64_t reserved_38_39 : 2;
9702 uint64_t usb_uctl : 1;
9703 uint64_t reserved_41_43 : 3;
9704 uint64_t usb_hci : 1;
9705 uint64_t reserved_45_47 : 3;
9707 uint64_t reserved_49_62 : 14;
9711 struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xx;
9712 struct cvmx_ciu2_src_ppx_ip3_mio_s cn68xxp1;
9714 typedef union cvmx_ciu2_src_ppx_ip3_mio cvmx_ciu2_src_ppx_ip3_mio_t;
9717 * cvmx_ciu2_src_pp#_ip3_pkt
9719 union cvmx_ciu2_src_ppx_ip3_pkt {
9721 struct cvmx_ciu2_src_ppx_ip3_pkt_s {
9722 #ifdef __BIG_ENDIAN_BITFIELD
9723 uint64_t reserved_54_63 : 10;
9724 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source
9725 CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
9726 uint64_t reserved_49_51 : 3;
9727 uint64_t ilk : 1; /**< ILK interface interrupts source
9728 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
9729 uint64_t reserved_41_47 : 7;
9730 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
9731 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
9732 uint64_t reserved_33_39 : 7;
9733 uint64_t agl : 1; /**< AGL interrupt source
9734 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
9735 uint64_t reserved_13_31 : 19;
9736 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
9737 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
9738 uint64_t reserved_5_7 : 3;
9739 uint64_t agx : 5; /**< GMX interrupt source
9740 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
9743 uint64_t reserved_5_7 : 3;
9744 uint64_t gmx_drp : 5;
9745 uint64_t reserved_13_31 : 19;
9747 uint64_t reserved_33_39 : 7;
9749 uint64_t reserved_41_47 : 7;
9751 uint64_t reserved_49_51 : 3;
9752 uint64_t ilk_drp : 2;
9753 uint64_t reserved_54_63 : 10;
9756 struct cvmx_ciu2_src_ppx_ip3_pkt_s cn68xx;
9757 struct cvmx_ciu2_src_ppx_ip3_pkt_cn68xxp1 {
9758 #ifdef __BIG_ENDIAN_BITFIELD
9759 uint64_t reserved_49_63 : 15;
9760 uint64_t ilk : 1; /**< ILK interface interrupts source
9761 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
9762 uint64_t reserved_41_47 : 7;
9763 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
9764 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
9765 uint64_t reserved_33_39 : 7;
9766 uint64_t agl : 1; /**< AGL interrupt source
9767 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
9768 uint64_t reserved_13_31 : 19;
9769 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
9770 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
9771 uint64_t reserved_5_7 : 3;
9772 uint64_t agx : 5; /**< GMX interrupt source
9773 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
9776 uint64_t reserved_5_7 : 3;
9777 uint64_t gmx_drp : 5;
9778 uint64_t reserved_13_31 : 19;
9780 uint64_t reserved_33_39 : 7;
9782 uint64_t reserved_41_47 : 7;
9784 uint64_t reserved_49_63 : 15;
9788 typedef union cvmx_ciu2_src_ppx_ip3_pkt cvmx_ciu2_src_ppx_ip3_pkt_t;
9791 * cvmx_ciu2_src_pp#_ip3_rml
9793 union cvmx_ciu2_src_ppx_ip3_rml {
9795 struct cvmx_ciu2_src_ppx_ip3_rml_s {
9796 #ifdef __BIG_ENDIAN_BITFIELD
9797 uint64_t reserved_56_63 : 8;
9798 uint64_t trace : 4; /**< Trace buffer interrupt source
9799 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
9800 uint64_t reserved_49_51 : 3;
9801 uint64_t l2c : 1; /**< L2C interrupt source
9802 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
9803 uint64_t reserved_41_47 : 7;
9804 uint64_t dfa : 1; /**< DFA interrupt source
9805 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
9806 uint64_t reserved_37_39 : 3;
9807 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
9808 See DPI DMA instruction completion */
9809 uint64_t reserved_34_35 : 2;
9810 uint64_t dpi : 1; /**< DPI interrupt source
9811 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
9812 uint64_t sli : 1; /**< SLI interrupt source
9813 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
9814 uint64_t reserved_31_31 : 1;
9815 uint64_t key : 1; /**< KEY interrupt source
9816 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
9817 uint64_t rad : 1; /**< RAD interrupt source
9818 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
9819 uint64_t tim : 1; /**< TIM interrupt source
9820 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
9821 uint64_t reserved_25_27 : 3;
9822 uint64_t zip : 1; /**< ZIP interrupt source
9823 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
9824 uint64_t reserved_17_23 : 7;
9825 uint64_t sso : 1; /**< SSO err interrupt source
9826 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
9827 uint64_t reserved_8_15 : 8;
9828 uint64_t pko : 1; /**< PKO interrupt source
9829 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
9830 uint64_t pip : 1; /**< PIP interrupt source
9831 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
9832 uint64_t ipd : 1; /**< IPD interrupt source
9833 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
9834 uint64_t fpa : 1; /**< FPA interrupt source
9835 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
9836 uint64_t reserved_1_3 : 3;
9837 uint64_t iob : 1; /**< IOB interrupt source
9838 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
9841 uint64_t reserved_1_3 : 3;
9846 uint64_t reserved_8_15 : 8;
9848 uint64_t reserved_17_23 : 7;
9850 uint64_t reserved_25_27 : 3;
9854 uint64_t reserved_31_31 : 1;
9857 uint64_t reserved_34_35 : 2;
9858 uint64_t dpi_dma : 1;
9859 uint64_t reserved_37_39 : 3;
9861 uint64_t reserved_41_47 : 7;
9863 uint64_t reserved_49_51 : 3;
9865 uint64_t reserved_56_63 : 8;
9868 struct cvmx_ciu2_src_ppx_ip3_rml_s cn68xx;
9869 struct cvmx_ciu2_src_ppx_ip3_rml_cn68xxp1 {
9870 #ifdef __BIG_ENDIAN_BITFIELD
9871 uint64_t reserved_56_63 : 8;
9872 uint64_t trace : 4; /**< Trace buffer interrupt source
9873 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
9874 uint64_t reserved_49_51 : 3;
9875 uint64_t l2c : 1; /**< L2C interrupt source
9876 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
9877 uint64_t reserved_41_47 : 7;
9878 uint64_t dfa : 1; /**< DFA interrupt source
9879 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
9880 uint64_t reserved_34_39 : 6;
9881 uint64_t dpi : 1; /**< DPI interrupt source
9882 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
9883 uint64_t sli : 1; /**< SLI interrupt source
9884 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
9885 uint64_t reserved_31_31 : 1;
9886 uint64_t key : 1; /**< KEY interrupt source
9887 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
9888 uint64_t rad : 1; /**< RAD interrupt source
9889 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
9890 uint64_t tim : 1; /**< TIM interrupt source
9891 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
9892 uint64_t reserved_25_27 : 3;
9893 uint64_t zip : 1; /**< ZIP interrupt source
9894 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
9895 uint64_t reserved_17_23 : 7;
9896 uint64_t sso : 1; /**< SSO err interrupt source
9897 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
9898 uint64_t reserved_8_15 : 8;
9899 uint64_t pko : 1; /**< PKO interrupt source
9900 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
9901 uint64_t pip : 1; /**< PIP interrupt source
9902 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
9903 uint64_t ipd : 1; /**< IPD interrupt source
9904 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
9905 uint64_t fpa : 1; /**< FPA interrupt source
9906 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
9907 uint64_t reserved_1_3 : 3;
9908 uint64_t iob : 1; /**< IOB interrupt source
9909 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
9912 uint64_t reserved_1_3 : 3;
9917 uint64_t reserved_8_15 : 8;
9919 uint64_t reserved_17_23 : 7;
9921 uint64_t reserved_25_27 : 3;
9925 uint64_t reserved_31_31 : 1;
9928 uint64_t reserved_34_39 : 6;
9930 uint64_t reserved_41_47 : 7;
9932 uint64_t reserved_49_51 : 3;
9934 uint64_t reserved_56_63 : 8;
9938 typedef union cvmx_ciu2_src_ppx_ip3_rml cvmx_ciu2_src_ppx_ip3_rml_t;
9941 * cvmx_ciu2_src_pp#_ip3_wdog
9943 union cvmx_ciu2_src_ppx_ip3_wdog {
9945 struct cvmx_ciu2_src_ppx_ip3_wdog_s {
9946 #ifdef __BIG_ENDIAN_BITFIELD
9947 uint64_t reserved_32_63 : 32;
9948 uint64_t wdog : 32; /**< 32 watchdog interrupts source
9949 CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
9952 uint64_t reserved_32_63 : 32;
9955 struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xx;
9956 struct cvmx_ciu2_src_ppx_ip3_wdog_s cn68xxp1;
9958 typedef union cvmx_ciu2_src_ppx_ip3_wdog cvmx_ciu2_src_ppx_ip3_wdog_t;
9961 * cvmx_ciu2_src_pp#_ip3_wrkq
9963 union cvmx_ciu2_src_ppx_ip3_wrkq {
9965 struct cvmx_ciu2_src_ppx_ip3_wrkq_s {
9966 #ifdef __BIG_ENDIAN_BITFIELD
9967 uint64_t workq : 64; /**< 64 work queue intr source,
9968 CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
9970 uint64_t workq : 64;
9973 struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xx;
9974 struct cvmx_ciu2_src_ppx_ip3_wrkq_s cn68xxp1;
9976 typedef union cvmx_ciu2_src_ppx_ip3_wrkq cvmx_ciu2_src_ppx_ip3_wrkq_t;
9979 * cvmx_ciu2_src_pp#_ip4_gpio
9981 union cvmx_ciu2_src_ppx_ip4_gpio {
9983 struct cvmx_ciu2_src_ppx_ip4_gpio_s {
9984 #ifdef __BIG_ENDIAN_BITFIELD
9985 uint64_t reserved_16_63 : 48;
9986 uint64_t gpio : 16; /**< 16 GPIO interrupts source */
9989 uint64_t reserved_16_63 : 48;
9992 struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xx;
9993 struct cvmx_ciu2_src_ppx_ip4_gpio_s cn68xxp1;
9995 typedef union cvmx_ciu2_src_ppx_ip4_gpio cvmx_ciu2_src_ppx_ip4_gpio_t;
9998 * cvmx_ciu2_src_pp#_ip4_io
10000 union cvmx_ciu2_src_ppx_ip4_io {
10002 struct cvmx_ciu2_src_ppx_ip4_io_s {
10003 #ifdef __BIG_ENDIAN_BITFIELD
10004 uint64_t reserved_34_63 : 30;
10005 uint64_t pem : 2; /**< PEMx interrupt source
10006 CIU2_RAW_IO[PEM] & CIU2_EN_xx_yy_IO[PEM] */
10007 uint64_t reserved_18_31 : 14;
10008 uint64_t pci_inta : 2; /**< PCI_INTA source
10009 CIU2_RAW_IO[PCI_INTA] & CIU2_EN_xx_yy_IO[PCI_INTA] */
10010 uint64_t reserved_13_15 : 3;
10011 uint64_t msired : 1; /**< MSI summary bit source
10012 CIU2_RAW_IO[MSIRED] & CIU2_EN_xx_yy_IO[MSIRED]
10013 This bit may not be functional in pass 1. */
10014 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI source
10015 CIU2_RAW_IO[PCI_MSI] & CIU2_EN_xx_yy_IO[PCI_MSI] */
10016 uint64_t reserved_4_7 : 4;
10017 uint64_t pci_intr : 4; /**< PCIe INTA/B/C/D interrupt source
10018 CIU2_RAW_IO[PCI_INTR] &CIU2_EN_xx_yy_IO[PCI_INTR] */
10020 uint64_t pci_intr : 4;
10021 uint64_t reserved_4_7 : 4;
10022 uint64_t pci_msi : 4;
10023 uint64_t msired : 1;
10024 uint64_t reserved_13_15 : 3;
10025 uint64_t pci_inta : 2;
10026 uint64_t reserved_18_31 : 14;
10028 uint64_t reserved_34_63 : 30;
10031 struct cvmx_ciu2_src_ppx_ip4_io_s cn68xx;
10032 struct cvmx_ciu2_src_ppx_ip4_io_s cn68xxp1;
10034 typedef union cvmx_ciu2_src_ppx_ip4_io cvmx_ciu2_src_ppx_ip4_io_t;
10037 * cvmx_ciu2_src_pp#_ip4_mbox
10039 union cvmx_ciu2_src_ppx_ip4_mbox {
10041 struct cvmx_ciu2_src_ppx_ip4_mbox_s {
10042 #ifdef __BIG_ENDIAN_BITFIELD
10043 uint64_t reserved_4_63 : 60;
10044 uint64_t mbox : 4; /**< Mailbox interrupt Source (RAW & ENABLE)
10045 For CIU2_SRC_PPX_IPx_MBOX:
10046 Four mailbox interrupts for entries 0-31
10048 [3] is the or of <31:24> of CIU2_MBOX
10049 [2] is the or of <23:16> of CIU2_MBOX
10050 [1] is the or of <15:8> of CIU2_MBOX
10051 [0] is the or of <7:0> of CIU2_MBOX
10052 CIU2_MBOX value can be read out via CSR address
10054 For CIU2_SRC_IOX_INT_MBOX:
10058 uint64_t reserved_4_63 : 60;
10061 struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xx;
10062 struct cvmx_ciu2_src_ppx_ip4_mbox_s cn68xxp1;
10064 typedef union cvmx_ciu2_src_ppx_ip4_mbox cvmx_ciu2_src_ppx_ip4_mbox_t;
10067 * cvmx_ciu2_src_pp#_ip4_mem
10069 union cvmx_ciu2_src_ppx_ip4_mem {
10071 struct cvmx_ciu2_src_ppx_ip4_mem_s {
10072 #ifdef __BIG_ENDIAN_BITFIELD
10073 uint64_t reserved_4_63 : 60;
10074 uint64_t lmc : 4; /**< LMC* interrupt source
10075 CIU2_RAW_MEM[LMC] & CIU2_EN_xx_yy_MEM[LMC] */
10078 uint64_t reserved_4_63 : 60;
10081 struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xx;
10082 struct cvmx_ciu2_src_ppx_ip4_mem_s cn68xxp1;
10084 typedef union cvmx_ciu2_src_ppx_ip4_mem cvmx_ciu2_src_ppx_ip4_mem_t;
10087 * cvmx_ciu2_src_pp#_ip4_mio
10089 union cvmx_ciu2_src_ppx_ip4_mio {
10091 struct cvmx_ciu2_src_ppx_ip4_mio_s {
10092 #ifdef __BIG_ENDIAN_BITFIELD
10093 uint64_t rst : 1; /**< MIO RST interrupt source
10094 CIU2_RAW_MIO[RST] & CIU2_EN_xx_yy_MIO[RST] */
10095 uint64_t reserved_49_62 : 14;
10096 uint64_t ptp : 1; /**< PTP interrupt source
10097 CIU2_RAW_MIO[PTP] & CIU2_EN_xx_yy_MIO[PTP] */
10098 uint64_t reserved_45_47 : 3;
10099 uint64_t usb_hci : 1; /**< USB HCI Interrupt source
10100 CIU2_RAW_MIO[USB_HCI] & CIU2_EN_xx_yy_MIO[USB_HCI] */
10101 uint64_t reserved_41_43 : 3;
10102 uint64_t usb_uctl : 1; /**< USB UCTL* interrupt source
10103 CIU2_RAW_MIO[USB_UCTL] &CIU2_EN_xx_yy_MIO[USB_UCTL] */
10104 uint64_t reserved_38_39 : 2;
10105 uint64_t uart : 2; /**< Two UART interrupts source
10106 CIU2_RAW_MIO[UART] & CIU2_EN_xx_yy_MIO[UART] */
10107 uint64_t reserved_34_35 : 2;
10108 uint64_t twsi : 2; /**< TWSI x Interrupt source
10109 CIU2_RAW_MIO[TWSI] & CIU2_EN_xx_yy_MIO[TWSI] */
10110 uint64_t reserved_19_31 : 13;
10111 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt source
10112 CIU2_RAW_MIO[BOOTDMA] & CIU2_EN_xx_yy_MIO[BOOTDMA] */
10113 uint64_t mio : 1; /**< MIO boot interrupt source
10114 CIU2_RAW_MIO[MIO] & CIU2_EN_xx_yy_MIO[MIO] */
10115 uint64_t nand : 1; /**< NAND Flash Controller interrupt source
10116 CIU2_RAW_MIO[NAND] & CIU2_EN_xx_yy_MIO[NANAD] */
10117 uint64_t reserved_12_15 : 4;
10118 uint64_t timer : 4; /**< General timer interrupts source
10119 CIU2_RAW_MIO[TIMER] & CIU2_EN_xx_yy_MIO[TIMER] */
10120 uint64_t reserved_3_7 : 5;
10121 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt source
10122 CIU2_RAW_MIO[IPD_DRP] & CIU2_EN_xx_yy_MIO[IPD_DRP] */
10123 uint64_t ssoiq : 1; /**< SSO IQ interrupt source
10124 CIU2_RAW_MIO[SSOIQ] & CIU2_EN_xx_yy_MIO[SSOIQ] */
10125 uint64_t ipdppthr : 1; /**< IPD per-port cnt threshold interrupt source
10126 CIU2_RAW_MIO[IPDPPTHR] &CIU2_EN_xx_yy_MIO[IPDPPTHR] */
10128 uint64_t ipdppthr : 1;
10129 uint64_t ssoiq : 1;
10130 uint64_t ipd_drp : 1;
10131 uint64_t reserved_3_7 : 5;
10132 uint64_t timer : 4;
10133 uint64_t reserved_12_15 : 4;
10136 uint64_t bootdma : 1;
10137 uint64_t reserved_19_31 : 13;
10139 uint64_t reserved_34_35 : 2;
10141 uint64_t reserved_38_39 : 2;
10142 uint64_t usb_uctl : 1;
10143 uint64_t reserved_41_43 : 3;
10144 uint64_t usb_hci : 1;
10145 uint64_t reserved_45_47 : 3;
10147 uint64_t reserved_49_62 : 14;
10151 struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xx;
10152 struct cvmx_ciu2_src_ppx_ip4_mio_s cn68xxp1;
10154 typedef union cvmx_ciu2_src_ppx_ip4_mio cvmx_ciu2_src_ppx_ip4_mio_t;
10157 * cvmx_ciu2_src_pp#_ip4_pkt
10159 union cvmx_ciu2_src_ppx_ip4_pkt {
10161 struct cvmx_ciu2_src_ppx_ip4_pkt_s {
10162 #ifdef __BIG_ENDIAN_BITFIELD
10163 uint64_t reserved_54_63 : 10;
10164 uint64_t ilk_drp : 2; /**< ILK Packet Drop interrupts source
10165 CIU2_RAW_PKT[ILK_DRP] & CIU2_EN_xx_yy_PKT[ILK_DRP] */
10166 uint64_t reserved_49_51 : 3;
10167 uint64_t ilk : 1; /**< ILK interface interrupts source
10168 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
10169 uint64_t reserved_41_47 : 7;
10170 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
10171 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
10172 uint64_t reserved_33_39 : 7;
10173 uint64_t agl : 1; /**< AGL interrupt source
10174 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
10175 uint64_t reserved_13_31 : 19;
10176 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
10177 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
10178 uint64_t reserved_5_7 : 3;
10179 uint64_t agx : 5; /**< GMX interrupt source
10180 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
10183 uint64_t reserved_5_7 : 3;
10184 uint64_t gmx_drp : 5;
10185 uint64_t reserved_13_31 : 19;
10187 uint64_t reserved_33_39 : 7;
10189 uint64_t reserved_41_47 : 7;
10191 uint64_t reserved_49_51 : 3;
10192 uint64_t ilk_drp : 2;
10193 uint64_t reserved_54_63 : 10;
10196 struct cvmx_ciu2_src_ppx_ip4_pkt_s cn68xx;
10197 struct cvmx_ciu2_src_ppx_ip4_pkt_cn68xxp1 {
10198 #ifdef __BIG_ENDIAN_BITFIELD
10199 uint64_t reserved_49_63 : 15;
10200 uint64_t ilk : 1; /**< ILK interface interrupts source
10201 CIU2_RAW_PKT[ILK] & CIU2_EN_xx_yy_PKT[ILK] */
10202 uint64_t reserved_41_47 : 7;
10203 uint64_t mii : 1; /**< RGMII/MII/MIX Interface x Interrupts source
10204 CIU2_RAW_PKT[MII] & CIU2_EN_xx_yy_PKT[MII] */
10205 uint64_t reserved_33_39 : 7;
10206 uint64_t agl : 1; /**< AGL interrupt source
10207 CIU2_RAW_PKT[AGL] & CIU2_EN_xx_yy_PKT[AGL] */
10208 uint64_t reserved_13_31 : 19;
10209 uint64_t gmx_drp : 5; /**< GMX packet drop interrupt, RAW & ENABLE
10210 CIU2_RAW_PKT[GMX_DRP] & CIU2_EN_xx_yy_PKT[GMX_DRP] */
10211 uint64_t reserved_5_7 : 3;
10212 uint64_t agx : 5; /**< GMX interrupt source
10213 CIU2_RAW_PKT[AGX] & CIU2_EN_xx_yy_PKT[AGX] */
10216 uint64_t reserved_5_7 : 3;
10217 uint64_t gmx_drp : 5;
10218 uint64_t reserved_13_31 : 19;
10220 uint64_t reserved_33_39 : 7;
10222 uint64_t reserved_41_47 : 7;
10224 uint64_t reserved_49_63 : 15;
10228 typedef union cvmx_ciu2_src_ppx_ip4_pkt cvmx_ciu2_src_ppx_ip4_pkt_t;
10231 * cvmx_ciu2_src_pp#_ip4_rml
10233 union cvmx_ciu2_src_ppx_ip4_rml {
10235 struct cvmx_ciu2_src_ppx_ip4_rml_s {
10236 #ifdef __BIG_ENDIAN_BITFIELD
10237 uint64_t reserved_56_63 : 8;
10238 uint64_t trace : 4; /**< Trace buffer interrupt source
10239 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
10240 uint64_t reserved_49_51 : 3;
10241 uint64_t l2c : 1; /**< L2C interrupt source
10242 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
10243 uint64_t reserved_41_47 : 7;
10244 uint64_t dfa : 1; /**< DFA interrupt source
10245 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
10246 uint64_t reserved_37_39 : 3;
10247 uint64_t dpi_dma : 1; /**< DPI DMA instruction completion interrupt
10248 See DPI DMA instruction completion */
10249 uint64_t reserved_34_35 : 2;
10250 uint64_t dpi : 1; /**< DPI interrupt source
10251 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
10252 uint64_t sli : 1; /**< SLI interrupt source
10253 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
10254 uint64_t reserved_31_31 : 1;
10255 uint64_t key : 1; /**< KEY interrupt source
10256 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
10257 uint64_t rad : 1; /**< RAD interrupt source
10258 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
10259 uint64_t tim : 1; /**< TIM interrupt source
10260 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
10261 uint64_t reserved_25_27 : 3;
10262 uint64_t zip : 1; /**< ZIP interrupt source
10263 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
10264 uint64_t reserved_17_23 : 7;
10265 uint64_t sso : 1; /**< SSO err interrupt source
10266 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
10267 uint64_t reserved_8_15 : 8;
10268 uint64_t pko : 1; /**< PKO interrupt source
10269 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
10270 uint64_t pip : 1; /**< PIP interrupt source
10271 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
10272 uint64_t ipd : 1; /**< IPD interrupt source
10273 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
10274 uint64_t fpa : 1; /**< FPA interrupt source
10275 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
10276 uint64_t reserved_1_3 : 3;
10277 uint64_t iob : 1; /**< IOB interrupt source
10278 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
10281 uint64_t reserved_1_3 : 3;
10286 uint64_t reserved_8_15 : 8;
10288 uint64_t reserved_17_23 : 7;
10290 uint64_t reserved_25_27 : 3;
10294 uint64_t reserved_31_31 : 1;
10297 uint64_t reserved_34_35 : 2;
10298 uint64_t dpi_dma : 1;
10299 uint64_t reserved_37_39 : 3;
10301 uint64_t reserved_41_47 : 7;
10303 uint64_t reserved_49_51 : 3;
10304 uint64_t trace : 4;
10305 uint64_t reserved_56_63 : 8;
10308 struct cvmx_ciu2_src_ppx_ip4_rml_s cn68xx;
10309 struct cvmx_ciu2_src_ppx_ip4_rml_cn68xxp1 {
10310 #ifdef __BIG_ENDIAN_BITFIELD
10311 uint64_t reserved_56_63 : 8;
10312 uint64_t trace : 4; /**< Trace buffer interrupt source
10313 CIU2_RAW_RML[TRACE] & CIU2_EN_xx_yy_RML[TRACE] */
10314 uint64_t reserved_49_51 : 3;
10315 uint64_t l2c : 1; /**< L2C interrupt source
10316 CIU2_RAW_RML[L2C] & CIU2_EN_xx_yy_RML[L2C] */
10317 uint64_t reserved_41_47 : 7;
10318 uint64_t dfa : 1; /**< DFA interrupt source
10319 CIU2_RAW_RML[DFA] & CIU2_EN_xx_yy_RML[DFA] */
10320 uint64_t reserved_34_39 : 6;
10321 uint64_t dpi : 1; /**< DPI interrupt source
10322 CIU2_RAW_RML[DPI] & CIU2_EN_xx_yy_RML[DPI] */
10323 uint64_t sli : 1; /**< SLI interrupt source
10324 CIU2_RAW_RML[SLI] & CIU2_EN_xx_yy_RML[SLI] */
10325 uint64_t reserved_31_31 : 1;
10326 uint64_t key : 1; /**< KEY interrupt source
10327 CIU2_RAW_RML[KEY] & CIU2_EN_xx_yy_RML[KEY] */
10328 uint64_t rad : 1; /**< RAD interrupt source
10329 CIU2_RAW_RML[RAD] & CIU2_EN_xx_yy_RML[RAD] */
10330 uint64_t tim : 1; /**< TIM interrupt source
10331 CIU2_RAW_RML[TIM] & CIU2_EN_xx_yy_RML[TIM] */
10332 uint64_t reserved_25_27 : 3;
10333 uint64_t zip : 1; /**< ZIP interrupt source
10334 CIU2_RAW_RML[ZIP] & CIU2_EN_xx_yy_RML[ZIP] */
10335 uint64_t reserved_17_23 : 7;
10336 uint64_t sso : 1; /**< SSO err interrupt source
10337 CIU2_RAW_RML[SSO] & CIU2_EN_xx_yy_RML[SSO] */
10338 uint64_t reserved_8_15 : 8;
10339 uint64_t pko : 1; /**< PKO interrupt source
10340 CIU2_RAW_RML[PKO] & CIU2_EN_xx_yy_RML[PKO] */
10341 uint64_t pip : 1; /**< PIP interrupt source
10342 CIU2_RAW_RML[PIP] & CIU2_EN_xx_yy_RML[PIP] */
10343 uint64_t ipd : 1; /**< IPD interrupt source
10344 CIU2_RAW_RML[IPD] & CIU2_EN_xx_yy_RML[IPD] */
10345 uint64_t fpa : 1; /**< FPA interrupt source
10346 CIU2_RAW_RML[FPA] & CIU2_EN_xx_yy_RML[FPA] */
10347 uint64_t reserved_1_3 : 3;
10348 uint64_t iob : 1; /**< IOB interrupt source
10349 CIU2_RAW_RML[IOB] & CIU2_EN_xx_yy_RML[IOB] */
10352 uint64_t reserved_1_3 : 3;
10357 uint64_t reserved_8_15 : 8;
10359 uint64_t reserved_17_23 : 7;
10361 uint64_t reserved_25_27 : 3;
10365 uint64_t reserved_31_31 : 1;
10368 uint64_t reserved_34_39 : 6;
10370 uint64_t reserved_41_47 : 7;
10372 uint64_t reserved_49_51 : 3;
10373 uint64_t trace : 4;
10374 uint64_t reserved_56_63 : 8;
10378 typedef union cvmx_ciu2_src_ppx_ip4_rml cvmx_ciu2_src_ppx_ip4_rml_t;
10381 * cvmx_ciu2_src_pp#_ip4_wdog
10383 union cvmx_ciu2_src_ppx_ip4_wdog {
10385 struct cvmx_ciu2_src_ppx_ip4_wdog_s {
10386 #ifdef __BIG_ENDIAN_BITFIELD
10387 uint64_t reserved_32_63 : 32;
10388 uint64_t wdog : 32; /**< 32 watchdog interrupts source
10389 CIU2_RAW_WDOG & CIU2_EN_xx_yy_WDOG */
10391 uint64_t wdog : 32;
10392 uint64_t reserved_32_63 : 32;
10395 struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xx;
10396 struct cvmx_ciu2_src_ppx_ip4_wdog_s cn68xxp1;
10398 typedef union cvmx_ciu2_src_ppx_ip4_wdog cvmx_ciu2_src_ppx_ip4_wdog_t;
10401 * cvmx_ciu2_src_pp#_ip4_wrkq
10403 union cvmx_ciu2_src_ppx_ip4_wrkq {
10405 struct cvmx_ciu2_src_ppx_ip4_wrkq_s {
10406 #ifdef __BIG_ENDIAN_BITFIELD
10407 uint64_t workq : 64; /**< 64 work queue intr source,
10408 CIU2_RAW_WRKQ & CIU2_EN_xx_yy_WRKQ */
10410 uint64_t workq : 64;
10413 struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xx;
10414 struct cvmx_ciu2_src_ppx_ip4_wrkq_s cn68xxp1;
10416 typedef union cvmx_ciu2_src_ppx_ip4_wrkq cvmx_ciu2_src_ppx_ip4_wrkq_t;
10419 * cvmx_ciu2_sum_io#_int
10421 union cvmx_ciu2_sum_iox_int {
10423 struct cvmx_ciu2_sum_iox_int_s {
10424 #ifdef __BIG_ENDIAN_BITFIELD
10425 uint64_t mbox : 4; /**< MBOX interrupt summary
10426 Direct connect to CIU2_SRC_*_MBOX[MBOX]
10427 See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
10428 uint64_t reserved_8_59 : 52;
10429 uint64_t gpio : 1; /**< GPIO interrupt summary,
10430 Report ORed result of CIU2_SRC_*_GPIO[63:0]
10431 See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
10432 uint64_t pkt : 1; /**< Packet I/O interrupt summary
10433 Report ORed result of CIU2_SRC_*_PKT[63:0]
10434 See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
10435 uint64_t mem : 1; /**< MEM interrupt Summary
10436 Report ORed result of CIU2_SRC_*_MEM[63:0]
10437 See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
10438 uint64_t io : 1; /**< I/O interrupt summary
10439 Report ORed result of CIU2_SRC_*_IO[63:0]
10440 See CIU2_RAW_IO / CIU2_SRC_*_IO */
10441 uint64_t mio : 1; /**< MIO interrupt summary
10442 Report ORed result of CIU2_SRC_*_MIO[63:0]
10443 See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
10444 uint64_t rml : 1; /**< RML Interrupt
10445 Report ORed result of CIU2_SRC_*_RML[63:0]
10446 See CIU2_RAW_RML / CIU2_SRC_*_RML */
10447 uint64_t wdog : 1; /**< WDOG summary bit
10448 Report ORed result of CIU2_SRC_*_WDOG[63:0]
10449 See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
10450 This read-only bit reads as a one whenever
10451 CIU2_RAW_WDOG bit is set and corresponding
10452 enable bit in CIU2_EN_PPx_IPy_WDOG or
10453 CIU2_EN_IOx_INT_WDOG is set, where x and y are
10454 the same x and y in the CIU2_SUM_PPx_IPy or
10455 CIU2_SUM_IOx_INT registers.
10456 Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
10457 CIU2_SRC_IOx_INT_WDOG registers can be used. */
10458 uint64_t workq : 1; /**< 64 work queue interrupts
10459 Report ORed result of CIU2_SRC_*_WRKQ[63:0]
10460 See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
10461 See SSO_WQ_INT[WQ_INT]
10462 1 bit/group. A copy of the R/W1C bit in the SSO. */
10464 uint64_t workq : 1;
10472 uint64_t reserved_8_59 : 52;
10476 struct cvmx_ciu2_sum_iox_int_s cn68xx;
10477 struct cvmx_ciu2_sum_iox_int_s cn68xxp1;
10479 typedef union cvmx_ciu2_sum_iox_int cvmx_ciu2_sum_iox_int_t;
10482 * cvmx_ciu2_sum_pp#_ip2
10484 union cvmx_ciu2_sum_ppx_ip2 {
10486 struct cvmx_ciu2_sum_ppx_ip2_s {
10487 #ifdef __BIG_ENDIAN_BITFIELD
10488 uint64_t mbox : 4; /**< MBOX interrupt summary
10489 Direct connect to CIU2_SRC_*_MBOX[MBOX]
10490 See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
10491 uint64_t reserved_8_59 : 52;
10492 uint64_t gpio : 1; /**< GPIO interrupt summary,
10493 Report ORed result of CIU2_SRC_*_GPIO[63:0]
10494 See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
10495 uint64_t pkt : 1; /**< Packet I/O interrupt summary
10496 Report ORed result of CIU2_SRC_*_PKT[63:0]
10497 See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
10498 uint64_t mem : 1; /**< MEM interrupt Summary
10499 Report ORed result of CIU2_SRC_*_MEM[63:0]
10500 See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
10501 uint64_t io : 1; /**< I/O interrupt summary
10502 Report ORed result of CIU2_SRC_*_IO[63:0]
10503 See CIU2_RAW_IO / CIU2_SRC_*_IO */
10504 uint64_t mio : 1; /**< MIO interrupt summary
10505 Report ORed result of CIU2_SRC_*_MIO[63:0]
10506 See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
10507 uint64_t rml : 1; /**< RML Interrupt
10508 Report ORed result of CIU2_SRC_*_RML[63:0]
10509 See CIU2_RAW_RML / CIU2_SRC_*_RML */
10510 uint64_t wdog : 1; /**< WDOG summary bit
10511 Report ORed result of CIU2_SRC_*_WDOG[63:0]
10512 See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
10513 This read-only bit reads as a one whenever
10514 CIU2_RAW_WDOG bit is set and corresponding
10515 enable bit in CIU2_EN_PPx_IPy_WDOG or
10516 CIU2_EN_IOx_INT_WDOG is set, where x and y are
10517 the same x and y in the CIU2_SUM_PPx_IPy or
10518 CIU2_SUM_IOx_INT registers.
10519 Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
10520 CIU2_SRC_IOx_INT_WDOG registers can be used. */
10521 uint64_t workq : 1; /**< 64 work queue interrupts
10522 Report ORed result of CIU2_SRC_*_WRKQ[63:0]
10523 See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
10524 See SSO_WQ_INT[WQ_INT]
10525 1 bit/group. A copy of the R/W1C bit in the SSO. */
10527 uint64_t workq : 1;
10535 uint64_t reserved_8_59 : 52;
10539 struct cvmx_ciu2_sum_ppx_ip2_s cn68xx;
10540 struct cvmx_ciu2_sum_ppx_ip2_s cn68xxp1;
10542 typedef union cvmx_ciu2_sum_ppx_ip2 cvmx_ciu2_sum_ppx_ip2_t;
10545 * cvmx_ciu2_sum_pp#_ip3
10547 union cvmx_ciu2_sum_ppx_ip3 {
10549 struct cvmx_ciu2_sum_ppx_ip3_s {
10550 #ifdef __BIG_ENDIAN_BITFIELD
10551 uint64_t mbox : 4; /**< MBOX interrupt summary
10552 Direct connect to CIU2_SRC_*_MBOX[MBOX]
10553 See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
10554 uint64_t reserved_8_59 : 52;
10555 uint64_t gpio : 1; /**< GPIO interrupt summary,
10556 Report ORed result of CIU2_SRC_*_GPIO[63:0]
10557 See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
10558 uint64_t pkt : 1; /**< Packet I/O interrupt summary
10559 Report ORed result of CIU2_SRC_*_PKT[63:0]
10560 See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
10561 uint64_t mem : 1; /**< MEM interrupt Summary
10562 Report ORed result of CIU2_SRC_*_MEM[63:0]
10563 See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
10564 uint64_t io : 1; /**< I/O interrupt summary
10565 Report ORed result of CIU2_SRC_*_IO[63:0]
10566 See CIU2_RAW_IO / CIU2_SRC_*_IO */
10567 uint64_t mio : 1; /**< MIO interrupt summary
10568 Report ORed result of CIU2_SRC_*_MIO[63:0]
10569 See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
10570 uint64_t rml : 1; /**< RML Interrupt
10571 Report ORed result of CIU2_SRC_*_RML[63:0]
10572 See CIU2_RAW_RML / CIU2_SRC_*_RML */
10573 uint64_t wdog : 1; /**< WDOG summary bit
10574 Report ORed result of CIU2_SRC_*_WDOG[63:0]
10575 See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
10576 This read-only bit reads as a one whenever
10577 CIU2_RAW_WDOG bit is set and corresponding
10578 enable bit in CIU2_EN_PPx_IPy_WDOG or
10579 CIU2_EN_IOx_INT_WDOG is set, where x and y are
10580 the same x and y in the CIU2_SUM_PPx_IPy or
10581 CIU2_SUM_IOx_INT registers.
10582 Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
10583 CIU2_SRC_IOx_INT_WDOG registers can be used. */
10584 uint64_t workq : 1; /**< 64 work queue interrupts
10585 Report ORed result of CIU2_SRC_*_WRKQ[63:0]
10586 See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
10587 See SSO_WQ_INT[WQ_INT]
10588 1 bit/group. A copy of the R/W1C bit in the SSO. */
10590 uint64_t workq : 1;
10598 uint64_t reserved_8_59 : 52;
10602 struct cvmx_ciu2_sum_ppx_ip3_s cn68xx;
10603 struct cvmx_ciu2_sum_ppx_ip3_s cn68xxp1;
10605 typedef union cvmx_ciu2_sum_ppx_ip3 cvmx_ciu2_sum_ppx_ip3_t;
10608 * cvmx_ciu2_sum_pp#_ip4
10610 union cvmx_ciu2_sum_ppx_ip4 {
10612 struct cvmx_ciu2_sum_ppx_ip4_s {
10613 #ifdef __BIG_ENDIAN_BITFIELD
10614 uint64_t mbox : 4; /**< MBOX interrupt summary
10615 Direct connect to CIU2_SRC_*_MBOX[MBOX]
10616 See CIU_MBOX_SET/CLR / CIU2_SRC_*_MBOX */
10617 uint64_t reserved_8_59 : 52;
10618 uint64_t gpio : 1; /**< GPIO interrupt summary,
10619 Report ORed result of CIU2_SRC_*_GPIO[63:0]
10620 See CIU2_RAW_GPIO / CIU2_SRC_*_GPIO */
10621 uint64_t pkt : 1; /**< Packet I/O interrupt summary
10622 Report ORed result of CIU2_SRC_*_PKT[63:0]
10623 See CIU2_RAW_PKT / CIU2_SRC_*_PKT */
10624 uint64_t mem : 1; /**< MEM interrupt Summary
10625 Report ORed result of CIU2_SRC_*_MEM[63:0]
10626 See CIU2_RAW_MEM / CIU2_SRC_*_MEM */
10627 uint64_t io : 1; /**< I/O interrupt summary
10628 Report ORed result of CIU2_SRC_*_IO[63:0]
10629 See CIU2_RAW_IO / CIU2_SRC_*_IO */
10630 uint64_t mio : 1; /**< MIO interrupt summary
10631 Report ORed result of CIU2_SRC_*_MIO[63:0]
10632 See CIU2_RAW_MIO / CIU2_SRC_*_MIO */
10633 uint64_t rml : 1; /**< RML Interrupt
10634 Report ORed result of CIU2_SRC_*_RML[63:0]
10635 See CIU2_RAW_RML / CIU2_SRC_*_RML */
10636 uint64_t wdog : 1; /**< WDOG summary bit
10637 Report ORed result of CIU2_SRC_*_WDOG[63:0]
10638 See CIU2_RAW_WDOG / CIU2_SRC_*_WDOG
10639 This read-only bit reads as a one whenever
10640 CIU2_RAW_WDOG bit is set and corresponding
10641 enable bit in CIU2_EN_PPx_IPy_WDOG or
10642 CIU2_EN_IOx_INT_WDOG is set, where x and y are
10643 the same x and y in the CIU2_SUM_PPx_IPy or
10644 CIU2_SUM_IOx_INT registers.
10645 Alternatively, the CIU2_SRC_PPx_IPy_WDOG and
10646 CIU2_SRC_IOx_INT_WDOG registers can be used. */
10647 uint64_t workq : 1; /**< 64 work queue interrupts
10648 Report ORed result of CIU2_SRC_*_WRKQ[63:0]
10649 See CIU2_RAW_WRKQ / CIU2_SRC_*_WRKQ
10650 See SSO_WQ_INT[WQ_INT]
10651 1 bit/group. A copy of the R/W1C bit in the SSO. */
10653 uint64_t workq : 1;
10661 uint64_t reserved_8_59 : 52;
10665 struct cvmx_ciu2_sum_ppx_ip4_s cn68xx;
10666 struct cvmx_ciu2_sum_ppx_ip4_s cn68xxp1;
10668 typedef union cvmx_ciu2_sum_ppx_ip4 cvmx_ciu2_sum_ppx_ip4_t;