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49 * Interface to Core, IO and DDR Clock.
51 * <hr>$Revision: 45089 $<hr>
54 #ifndef __CVMX_CLOCK_H__
55 #define __CVMX_CLOCK_H__
57 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
58 #include <asm/octeon/octeon.h>
59 #include <asm/octeon/cvmx-lmcx-defs.h>
69 * Enumeration of different Clocks in Octeon.
72 CVMX_CLOCK_RCLK, /**< Clock used by cores, coherent bus and L2 cache. */
73 CVMX_CLOCK_SCLK, /**< Clock used by IO blocks. */
74 CVMX_CLOCK_DDR, /**< Clock used by DRAM */
75 CVMX_CLOCK_CORE, /**< Alias for CVMX_CLOCK_RCLK */
76 CVMX_CLOCK_TIM, /**< Alias for CVMX_CLOCK_SCLK */
77 CVMX_CLOCK_IPD, /**< Alias for CVMX_CLOCK_SCLK */
81 * Get cycle count based on the clock type.
83 * @param clock - Enumeration of the clock type.
84 * @return - Get the number of cycles executed so far.
86 static inline uint64_t cvmx_clock_get_count(cvmx_clock_t clock)
94 return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
95 #elif defined(CVMX_ABI_O32)
96 uint32_t tmp_low, tmp_hi;
102 " rdhwr %[tmpl], $31 \n"
103 " dsrl %[tmph], %[tmpl], 32 \n"
107 : [tmpl] "=&r" (tmp_low), [tmph] "=&r" (tmp_hi) : );
109 return(((uint64_t)tmp_hi << 32) + tmp_low);
112 CVMX_RDHWR(cycle, 31);
117 case CVMX_CLOCK_SCLK:
120 return cvmx_read_csr(CVMX_IPD_CLK_COUNT);
123 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
124 return cvmx_read_csr(CVMX_LMCX_DCLK_CNT(0));
126 return ((cvmx_read_csr(CVMX_LMCX_DCLK_CNT_HI(0)) << 32) | cvmx_read_csr(CVMX_LMCX_DCLK_CNT_LO(0)));
129 cvmx_dprintf("cvmx_clock_get_count: Unknown clock type\n");
133 extern uint64_t cvmx_clock_get_rate(cvmx_clock_t clock);
139 #endif /* __CVMX_CLOCK_H__ */