1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Inc. nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
43 #include "cvmx-sysinfo.h"
44 #include "cvmx-compactflash.h"
48 #define MAX(a,b) (((a)>(b))?(a):(b))
50 #define FLASH_RoundUP(_Dividend, _Divisor) (((_Dividend)+(_Divisor-1))/(_Divisor))
52 * Convert nanosecond based time to setting used in the
53 * boot bus timing register, based on timing multiple
57 static uint32_t ns_to_tim_reg(int tim_mult, uint32_t nsecs)
61 /* Compute # of eclock periods to get desired duration in nanoseconds */
62 val = FLASH_RoundUP(nsecs * (cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000), 1000);
64 /* Factor in timing multiple, if not 1 */
66 val = FLASH_RoundUP(val, tim_mult);
71 uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data, int *mwdma_mode_ptr)
74 cvmx_mio_boot_dma_timx_t dma_tim;
83 uint16_t word53_field_valid;
84 uint16_t word63_mwdma;
85 uint16_t word163_adv_timing_info;
90 word53_field_valid = ident_data[53];
91 word63_mwdma = ident_data[63];
92 word163_adv_timing_info = ident_data[163];
96 /* Check for basic MWDMA modes */
97 if (word53_field_valid & 0x2)
99 if (word63_mwdma & 0x4)
101 else if (word63_mwdma & 0x2)
103 else if (word63_mwdma & 0x1)
107 /* Check for advanced MWDMA modes */
108 switch ((word163_adv_timing_info >> 3) & 0x7)
120 /* DMA is not supported by this card */
124 /* Now set up the DMA timing */
128 dma_tim.s.tim_mult = 1;
131 dma_tim.s.tim_mult = 2;
134 dma_tim.s.tim_mult = 0;
137 dma_tim.s.tim_mult = 3;
140 cvmx_dprintf("ERROR: invalid boot bus dma tim_mult setting\n");
152 oe_a = Td + 20; // Td (Seem to need more margin here....
153 oe_n = MAX(To - oe_a, Tkr); // Tkr from cf spec, lengthened to meet To
155 // oe_n + oe_h must be >= To (cycle time)
159 dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
160 pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
167 oe_a = Td + 20; // Td (Seem to need more margin here....
168 oe_n = MAX(To - oe_a, Tkr); // Tkr from cf spec, lengthened to meet To
170 // oe_n + oe_h must be >= To (cycle time)
174 dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
175 pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
186 // oe_a 0 fudge doesn't work; 10 seems to
187 oe_a = Td + 20 + 10; // Td (Seem to need more margin here....
188 oe_n = MAX(To - oe_a, Tkr) + 10; // Tkr from cf spec, lengthened to meet To
189 // oe_n 0 fudge fails;;; 10 boots
191 // 20 ns fudge needed on dma_acks
192 // oe_n + oe_h must be >= To (cycle time)
193 dma_acks = 0 + 20; //Ti
196 dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
197 pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
198 // no fudge needed on pause
204 cvmx_dprintf("ERROR: Unsupported DMA mode: %d\n", mwdma_mode);
210 *mwdma_mode_ptr = mwdma_mode;
212 dma_tim.s.dmack_pi = 1;
214 dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
215 dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
217 dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, dma_acks);
218 dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
220 dma_tim.s.dmarq = dma_arq;
221 dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
223 dma_tim.s.rd_dly = 0; /* Sample right on edge */
226 dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
227 dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
230 cvmx_dprintf("ns to ticks (mult %d) of %d is: %d\n", TIM_MULT, 60, ns_to_tim_reg(60));
231 cvmx_dprintf("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
232 dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
242 * Setup timing and region config to support a specific IDE PIO
243 * mode over the bootbus.
245 * @param cs0 Bootbus region number connected to CS0 on the IDE device
246 * @param cs1 Bootbus region number connected to CS1 on the IDE device
247 * @param pio_mode PIO mode to set (0-6)
249 void cvmx_compactflash_set_piomode(int cs0, int cs1, int pio_mode)
251 cvmx_mio_boot_reg_cfgx_t mio_boot_reg_cfg;
252 cvmx_mio_boot_reg_timx_t mio_boot_reg_tim;
254 int clocks_us; /* Number of clock cycles per microsec */
256 int use_iordy; /* Set for PIO0-4, not set for PIO5-6 */
257 int t1; /* These t names are timing parameters from the ATA spec */
265 /* PIO modes 0-4 all allow the device to deassert IORDY to slow down
269 /* Use the PIO mode to determine timing parameters */
272 /* CF spec say IORDY should be ignore in PIO 5 */
283 /* CF spec say IORDY should be ignore in PIO 6 */
339 /* Convert times in ns to clock cycles, rounding up */
340 clocks_us = FLASH_RoundUP(cvmx_clock_get_rate(CVMX_CLOCK_SCLK), 1000000);
342 /* Convert times in clock cycles, rounding up. Octeon parameters are in
343 minus one notation, so take off one after the conversion */
344 t1 = FLASH_RoundUP(t1 * clocks_us, 1000);
347 t2 = FLASH_RoundUP(t2 * clocks_us, 1000);
350 t2i = FLASH_RoundUP(t2i * clocks_us, 1000);
353 t4 = FLASH_RoundUP(t4 * clocks_us, 1000);
356 t6 = FLASH_RoundUP(t6 * clocks_us, 1000);
359 t6z = FLASH_RoundUP(t6z * clocks_us, 1000);
362 t9 = FLASH_RoundUP(t9 * clocks_us, 1000);
366 /* Start using a scale factor of one cycle. Keep doubling it until
367 the parameters fit in their fields. Since t2 is the largest number,
368 we only need to check it */
372 t1 = FLASH_RoundUP(t1, 2);
373 t2 = FLASH_RoundUP(t2, 2);
374 t2i = FLASH_RoundUP(t2i, 2);
375 t4 = FLASH_RoundUP(t4, 2);
376 t6 = FLASH_RoundUP(t6, 2);
377 t6z = FLASH_RoundUP(t6z, 2);
378 t9 = FLASH_RoundUP(t9, 2);
384 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
385 mio_boot_reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
388 mio_boot_reg_cfg.s.tim_mult = 1;
391 mio_boot_reg_cfg.s.tim_mult = 2;
394 mio_boot_reg_cfg.s.tim_mult = 0;
398 mio_boot_reg_cfg.s.tim_mult = 3;
401 mio_boot_reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
402 mio_boot_reg_cfg.s.sam = 0; /* Don't combine write and output enable */
403 mio_boot_reg_cfg.s.we_ext = 0; /* No write enable extension */
404 mio_boot_reg_cfg.s.oe_ext = 0; /* No read enable extension */
405 mio_boot_reg_cfg.s.en = 1; /* Enable this region */
406 mio_boot_reg_cfg.s.orbit = 0; /* Don't combine with previos region */
407 mio_boot_reg_cfg.s.width = 1; /* 16 bits wide */
408 cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), mio_boot_reg_cfg.u64);
415 mio_boot_reg_tim.u64 = 0;
416 mio_boot_reg_tim.s.pagem = 0; /* Disable page mode */
417 mio_boot_reg_tim.s.waitm = use_iordy; /* Enable dynamic timing */
418 mio_boot_reg_tim.s.pages = 0; /* Pages are disabled */
419 mio_boot_reg_tim.s.ale = 8; /* If someone uses ALE, this seems to work */
420 mio_boot_reg_tim.s.page = 0; /* Not used */
421 mio_boot_reg_tim.s.wait = 0; /* Time after IORDY to coninue to assert the data */
422 mio_boot_reg_tim.s.pause = 0; /* Time after CE that signals stay valid */
423 mio_boot_reg_tim.s.wr_hld = t9; /* How long to hold after a write */
424 mio_boot_reg_tim.s.rd_hld = t9; /* How long to wait after a read for device to tristate */
425 mio_boot_reg_tim.s.we = t2; /* How long write enable is asserted */
426 mio_boot_reg_tim.s.oe = t2; /* How long read enable is asserted */
427 mio_boot_reg_tim.s.ce = t1; /* Time after CE that read/write starts */
428 mio_boot_reg_tim.s.adr = 1; /* Time before CE that address is valid */
430 /* Program the bootbus region timing for both chip selects */
431 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs0), mio_boot_reg_tim.u64);
432 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs1), mio_boot_reg_tim.u64);