sys/contrib/octeon-sdk/cvmx-dpi-defs.h

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  40
  41 /**
  42  * cvmx-dpi-defs.h
  43  *
  44  * Configuration and status register (CSR) type definitions for
  45  * Octeon dpi.
  46  *
  47  * This file is auto generated. Do not edit.
  48  *
  49  * <hr>$Revision$<hr>
  50  *
  51  */
  52 #ifndef __CVMX_DPI_DEFS_H__
  53 #define __CVMX_DPI_DEFS_H__
  54
  55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  56 #define CVMX_DPI_BIST_STATUS CVMX_DPI_BIST_STATUS_FUNC()
  57 static inline uint64_t CVMX_DPI_BIST_STATUS_FUNC(void)
  58 {
  59         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
  60                 cvmx_warn("CVMX_DPI_BIST_STATUS not supported on this chip\n");
  61         return CVMX_ADD_IO_SEG(0x0001DF0000000000ull);
  62 }
  63 #else
  64 #define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
  65 #endif
  66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  67 #define CVMX_DPI_CTL CVMX_DPI_CTL_FUNC()
  68 static inline uint64_t CVMX_DPI_CTL_FUNC(void)
  69 {
  70         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
  71                 cvmx_warn("CVMX_DPI_CTL not supported on this chip\n");
  72         return CVMX_ADD_IO_SEG(0x0001DF0000000040ull);
  73 }
  74 #else
  75 #define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
  76 #endif
  77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  78 static inline uint64_t CVMX_DPI_DMAX_COUNTS(unsigned long offset)
  79 {
  80         if (!(
  81               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
  82               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
  83               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
  84               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
  85               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
  86                 cvmx_warn("CVMX_DPI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
  87         return CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8;
  88 }
  89 #else
  90 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
  91 #endif
  92 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
  93 static inline uint64_t CVMX_DPI_DMAX_DBELL(unsigned long offset)
  94 {
  95         if (!(
  96               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
  97               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
  98               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
  99               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
 100               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 101                 cvmx_warn("CVMX_DPI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
 102         return CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8;
 103 }
 104 #else
 105 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
 106 #endif
 107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 108 static inline uint64_t CVMX_DPI_DMAX_ERR_RSP_STATUS(unsigned long offset)
 109 {
 110         if (!(
 111               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
 112               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
 113               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
 114               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 115                 cvmx_warn("CVMX_DPI_DMAX_ERR_RSP_STATUS(%lu) is invalid on this chip\n", offset);
 116         return CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8;
 117 }
 118 #else
 119 #define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
 120 #endif
 121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 122 static inline uint64_t CVMX_DPI_DMAX_IBUFF_SADDR(unsigned long offset)
 123 {
 124         if (!(
 125               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
 126               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
 127               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
 128               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
 129               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 130                 cvmx_warn("CVMX_DPI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
 131         return CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8;
 132 }
 133 #else
 134 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
 135 #endif
 136 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 137 static inline uint64_t CVMX_DPI_DMAX_IFLIGHT(unsigned long offset)
 138 {
 139         if (!(
 140               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
 141               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
 142               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
 143               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 144                 cvmx_warn("CVMX_DPI_DMAX_IFLIGHT(%lu) is invalid on this chip\n", offset);
 145         return CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8;
 146 }
 147 #else
 148 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
 149 #endif
 150 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 151 static inline uint64_t CVMX_DPI_DMAX_NADDR(unsigned long offset)
 152 {
 153         if (!(
 154               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
 155               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
 156               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
 157               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
 158               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 159                 cvmx_warn("CVMX_DPI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
 160         return CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8;
 161 }
 162 #else
 163 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
 164 #endif
 165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 166 static inline uint64_t CVMX_DPI_DMAX_REQBNK0(unsigned long offset)
 167 {
 168         if (!(
 169               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
 170               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
 171               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
 172               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
 173               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 174                 cvmx_warn("CVMX_DPI_DMAX_REQBNK0(%lu) is invalid on this chip\n", offset);
 175         return CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8;
 176 }
 177 #else
 178 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
 179 #endif
 180 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 181 static inline uint64_t CVMX_DPI_DMAX_REQBNK1(unsigned long offset)
 182 {
 183         if (!(
 184               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
 185               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
 186               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
 187               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
 188               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
 189                 cvmx_warn("CVMX_DPI_DMAX_REQBNK1(%lu) is invalid on this chip\n", offset);
 190         return CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8;
 191 }
 192 #else
 193 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
 194 #endif
 195 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 196 #define CVMX_DPI_DMA_CONTROL CVMX_DPI_DMA_CONTROL_FUNC()
 197 static inline uint64_t CVMX_DPI_DMA_CONTROL_FUNC(void)
 198 {
 199         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 200                 cvmx_warn("CVMX_DPI_DMA_CONTROL not supported on this chip\n");
 201         return CVMX_ADD_IO_SEG(0x0001DF0000000048ull);
 202 }
 203 #else
 204 #define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
 205 #endif
 206 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 207 static inline uint64_t CVMX_DPI_DMA_ENGX_EN(unsigned long offset)
 208 {
 209         if (!(
 210               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) ||
 211               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
 212               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) ||
 213               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) ||
 214               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5)))))
 215                 cvmx_warn("CVMX_DPI_DMA_ENGX_EN(%lu) is invalid on this chip\n", offset);
 216         return CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8;
 217 }
 218 #else
 219 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
 220 #endif
 221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 222 static inline uint64_t CVMX_DPI_DMA_PPX_CNT(unsigned long offset)
 223 {
 224         if (!(
 225               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
 226               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
 227               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
 228                 cvmx_warn("CVMX_DPI_DMA_PPX_CNT(%lu) is invalid on this chip\n", offset);
 229         return CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8;
 230 }
 231 #else
 232 #define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
 233 #endif
 234 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 235 static inline uint64_t CVMX_DPI_ENGX_BUF(unsigned long offset)
 236 {
 237         if (!(
 238               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 5))) ||
 239               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
 240               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 5))) ||
 241               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 5))) ||
 242               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 5)))))
 243                 cvmx_warn("CVMX_DPI_ENGX_BUF(%lu) is invalid on this chip\n", offset);
 244         return CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8;
 245 }
 246 #else
 247 #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
 248 #endif
 249 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 250 #define CVMX_DPI_INFO_REG CVMX_DPI_INFO_REG_FUNC()
 251 static inline uint64_t CVMX_DPI_INFO_REG_FUNC(void)
 252 {
 253         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 254                 cvmx_warn("CVMX_DPI_INFO_REG not supported on this chip\n");
 255         return CVMX_ADD_IO_SEG(0x0001DF0000000980ull);
 256 }
 257 #else
 258 #define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
 259 #endif
 260 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 261 #define CVMX_DPI_INT_EN CVMX_DPI_INT_EN_FUNC()
 262 static inline uint64_t CVMX_DPI_INT_EN_FUNC(void)
 263 {
 264         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 265                 cvmx_warn("CVMX_DPI_INT_EN not supported on this chip\n");
 266         return CVMX_ADD_IO_SEG(0x0001DF0000000010ull);
 267 }
 268 #else
 269 #define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
 270 #endif
 271 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 272 #define CVMX_DPI_INT_REG CVMX_DPI_INT_REG_FUNC()
 273 static inline uint64_t CVMX_DPI_INT_REG_FUNC(void)
 274 {
 275         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 276                 cvmx_warn("CVMX_DPI_INT_REG not supported on this chip\n");
 277         return CVMX_ADD_IO_SEG(0x0001DF0000000008ull);
 278 }
 279 #else
 280 #define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
 281 #endif
 282 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 283 static inline uint64_t CVMX_DPI_NCBX_CFG(unsigned long block_id)
 284 {
 285         if (!(
 286               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) ||
 287               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) ||
 288               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) ||
 289               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0)))))
 290                 cvmx_warn("CVMX_DPI_NCBX_CFG(%lu) is invalid on this chip\n", block_id);
 291         return CVMX_ADD_IO_SEG(0x0001DF0000000800ull);
 292 }
 293 #else
 294 #define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
 295 #endif
 296 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 297 #define CVMX_DPI_PINT_INFO CVMX_DPI_PINT_INFO_FUNC()
 298 static inline uint64_t CVMX_DPI_PINT_INFO_FUNC(void)
 299 {
 300         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 301                 cvmx_warn("CVMX_DPI_PINT_INFO not supported on this chip\n");
 302         return CVMX_ADD_IO_SEG(0x0001DF0000000830ull);
 303 }
 304 #else
 305 #define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
 306 #endif
 307 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 308 #define CVMX_DPI_PKT_ERR_RSP CVMX_DPI_PKT_ERR_RSP_FUNC()
 309 static inline uint64_t CVMX_DPI_PKT_ERR_RSP_FUNC(void)
 310 {
 311         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 312                 cvmx_warn("CVMX_DPI_PKT_ERR_RSP not supported on this chip\n");
 313         return CVMX_ADD_IO_SEG(0x0001DF0000000078ull);
 314 }
 315 #else
 316 #define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
 317 #endif
 318 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 319 #define CVMX_DPI_REQ_ERR_RSP CVMX_DPI_REQ_ERR_RSP_FUNC()
 320 static inline uint64_t CVMX_DPI_REQ_ERR_RSP_FUNC(void)
 321 {
 322         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 323                 cvmx_warn("CVMX_DPI_REQ_ERR_RSP not supported on this chip\n");
 324         return CVMX_ADD_IO_SEG(0x0001DF0000000058ull);
 325 }
 326 #else
 327 #define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
 328 #endif
 329 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 330 #define CVMX_DPI_REQ_ERR_RSP_EN CVMX_DPI_REQ_ERR_RSP_EN_FUNC()
 331 static inline uint64_t CVMX_DPI_REQ_ERR_RSP_EN_FUNC(void)
 332 {
 333         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 334                 cvmx_warn("CVMX_DPI_REQ_ERR_RSP_EN not supported on this chip\n");
 335         return CVMX_ADD_IO_SEG(0x0001DF0000000068ull);
 336 }
 337 #else
 338 #define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
 339 #endif
 340 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 341 #define CVMX_DPI_REQ_ERR_RST CVMX_DPI_REQ_ERR_RST_FUNC()
 342 static inline uint64_t CVMX_DPI_REQ_ERR_RST_FUNC(void)
 343 {
 344         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 345                 cvmx_warn("CVMX_DPI_REQ_ERR_RST not supported on this chip\n");
 346         return CVMX_ADD_IO_SEG(0x0001DF0000000060ull);
 347 }
 348 #else
 349 #define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
 350 #endif
 351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 352 #define CVMX_DPI_REQ_ERR_RST_EN CVMX_DPI_REQ_ERR_RST_EN_FUNC()
 353 static inline uint64_t CVMX_DPI_REQ_ERR_RST_EN_FUNC(void)
 354 {
 355         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 356                 cvmx_warn("CVMX_DPI_REQ_ERR_RST_EN not supported on this chip\n");
 357         return CVMX_ADD_IO_SEG(0x0001DF0000000070ull);
 358 }
 359 #else
 360 #define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
 361 #endif
 362 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 363 #define CVMX_DPI_REQ_ERR_SKIP_COMP CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC()
 364 static inline uint64_t CVMX_DPI_REQ_ERR_SKIP_COMP_FUNC(void)
 365 {
 366         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 367                 cvmx_warn("CVMX_DPI_REQ_ERR_SKIP_COMP not supported on this chip\n");
 368         return CVMX_ADD_IO_SEG(0x0001DF0000000838ull);
 369 }
 370 #else
 371 #define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
 372 #endif
 373 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 374 #define CVMX_DPI_REQ_GBL_EN CVMX_DPI_REQ_GBL_EN_FUNC()
 375 static inline uint64_t CVMX_DPI_REQ_GBL_EN_FUNC(void)
 376 {
 377         if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
 378                 cvmx_warn("CVMX_DPI_REQ_GBL_EN not supported on this chip\n");
 379         return CVMX_ADD_IO_SEG(0x0001DF0000000050ull);
 380 }
 381 #else
 382 #define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
 383 #endif
 384 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 385 static inline uint64_t CVMX_DPI_SLI_PRTX_CFG(unsigned long offset)
 386 {
 387         if (!(
 388               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 389               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 390               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
 391               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
 392               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 393                 cvmx_warn("CVMX_DPI_SLI_PRTX_CFG(%lu) is invalid on this chip\n", offset);
 394         return CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8;
 395 }
 396 #else
 397 #define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
 398 #endif
 399 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR(unsigned long offset)
 400 {
 401         switch(cvmx_get_octeon_family()) {
 402                 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 403                         if ((offset <= 3))
 404                                 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 3) * 8;
 405                         break;
 406                 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 407                 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 408                 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 409
 410                         if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
 411                                 if ((offset <= 1))
 412                                         return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8;
 413                         if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2))
 414                                 if ((offset <= 1))
 415                                         return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8;
 416                         if ((offset <= 1))
 417                                 return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8;
 418                         break;
 419                 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 420                         if ((offset <= 1))
 421                                 return CVMX_ADD_IO_SEG(0x0001DF0000000928ull) + ((offset) & 1) * 8;
 422                         break;
 423         }
 424         cvmx_warn("CVMX_DPI_SLI_PRTX_ERR (offset = %lu) not supported on this chip\n", offset);
 425         return CVMX_ADD_IO_SEG(0x0001DF0000000920ull) + ((offset) & 1) * 8;
 426 }
 427 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
 428 static inline uint64_t CVMX_DPI_SLI_PRTX_ERR_INFO(unsigned long offset)
 429 {
 430         if (!(
 431               (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
 432               (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
 433               (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
 434               (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
 435               (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
 436                 cvmx_warn("CVMX_DPI_SLI_PRTX_ERR_INFO(%lu) is invalid on this chip\n", offset);
 437         return CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8;
 438 }
 439 #else
 440 #define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
 441 #endif
 442
 443 /**
 444  * cvmx_dpi_bist_status
 445  */
 446 union cvmx_dpi_bist_status {
 447         uint64_t u64;
 448         struct cvmx_dpi_bist_status_s {
 449 #ifdef __BIG_ENDIAN_BITFIELD
 450         uint64_t reserved_47_63               : 17;
 451         uint64_t bist                         : 47; /**< BIST Results.
 452                                                          HW sets a bit in BIST for for memory that fails
 453                                                          BIST. */
 454 #else
 455         uint64_t bist                         : 47;
 456         uint64_t reserved_47_63               : 17;
 457 #endif
 458         } s;
 459         struct cvmx_dpi_bist_status_s         cn61xx;
 460         struct cvmx_dpi_bist_status_cn63xx {
 461 #ifdef __BIG_ENDIAN_BITFIELD
 462         uint64_t reserved_45_63               : 19;
 463         uint64_t bist                         : 45; /**< BIST Results.
 464                                                          HW sets a bit in BIST for for memory that fails
 465                                                          BIST. */
 466 #else
 467         uint64_t bist                         : 45;
 468         uint64_t reserved_45_63               : 19;
 469 #endif
 470         } cn63xx;
 471         struct cvmx_dpi_bist_status_cn63xxp1 {
 472 #ifdef __BIG_ENDIAN_BITFIELD
 473         uint64_t reserved_37_63               : 27;
 474         uint64_t bist                         : 37; /**< BIST Results.
 475                                                          HW sets a bit in BIST for for memory that fails
 476                                                          BIST. */
 477 #else
 478         uint64_t bist                         : 37;
 479         uint64_t reserved_37_63               : 27;
 480 #endif
 481         } cn63xxp1;
 482         struct cvmx_dpi_bist_status_s         cn66xx;
 483         struct cvmx_dpi_bist_status_cn63xx    cn68xx;
 484         struct cvmx_dpi_bist_status_cn63xx    cn68xxp1;
 485         struct cvmx_dpi_bist_status_s         cnf71xx;
 486 };
 487 typedef union cvmx_dpi_bist_status cvmx_dpi_bist_status_t;
 488
 489 /**
 490  * cvmx_dpi_ctl
 491  */
 492 union cvmx_dpi_ctl {
 493         uint64_t u64;
 494         struct cvmx_dpi_ctl_s {
 495 #ifdef __BIG_ENDIAN_BITFIELD
 496         uint64_t reserved_2_63                : 62;
 497         uint64_t clk                          : 1;  /**< Status bit that indicates that the clks are running */
 498         uint64_t en                           : 1;  /**< Turns on the DMA and Packet state machines */
 499 #else
 500         uint64_t en                           : 1;
 501         uint64_t clk                          : 1;
 502         uint64_t reserved_2_63                : 62;
 503 #endif
 504         } s;
 505         struct cvmx_dpi_ctl_cn61xx {
 506 #ifdef __BIG_ENDIAN_BITFIELD
 507         uint64_t reserved_1_63                : 63;
 508         uint64_t en                           : 1;  /**< Turns on the DMA and Packet state machines */
 509 #else
 510         uint64_t en                           : 1;
 511         uint64_t reserved_1_63                : 63;
 512 #endif
 513         } cn61xx;
 514         struct cvmx_dpi_ctl_s                 cn63xx;
 515         struct cvmx_dpi_ctl_s                 cn63xxp1;
 516         struct cvmx_dpi_ctl_s                 cn66xx;
 517         struct cvmx_dpi_ctl_s                 cn68xx;
 518         struct cvmx_dpi_ctl_s                 cn68xxp1;
 519         struct cvmx_dpi_ctl_cn61xx            cnf71xx;
 520 };
 521 typedef union cvmx_dpi_ctl cvmx_dpi_ctl_t;
 522
 523 /**
 524  * cvmx_dpi_dma#_counts
 525  *
 526  * DPI_DMA[0..7]_COUNTS = DMA Instruction Counts
 527  *
 528  * Values for determing the number of instructions for DMA[0..7] in the DPI.
 529  */
 530 union cvmx_dpi_dmax_counts {
 531         uint64_t u64;
 532         struct cvmx_dpi_dmax_counts_s {
 533 #ifdef __BIG_ENDIAN_BITFIELD
 534         uint64_t reserved_39_63               : 25;
 535         uint64_t fcnt                         : 7;  /**< Number of words in the Instruction FIFO locally
 536                                                          cached within DPI. */
 537         uint64_t dbell                        : 32; /**< Number of available words of Instructions to read. */
 538 #else
 539         uint64_t dbell                        : 32;
 540         uint64_t fcnt                         : 7;
 541         uint64_t reserved_39_63               : 25;
 542 #endif
 543         } s;
 544         struct cvmx_dpi_dmax_counts_s         cn61xx;
 545         struct cvmx_dpi_dmax_counts_s         cn63xx;
 546         struct cvmx_dpi_dmax_counts_s         cn63xxp1;
 547         struct cvmx_dpi_dmax_counts_s         cn66xx;
 548         struct cvmx_dpi_dmax_counts_s         cn68xx;
 549         struct cvmx_dpi_dmax_counts_s         cn68xxp1;
 550         struct cvmx_dpi_dmax_counts_s         cnf71xx;
 551 };
 552 typedef union cvmx_dpi_dmax_counts cvmx_dpi_dmax_counts_t;
 553
 554 /**
 555  * cvmx_dpi_dma#_dbell
 556  *
 557  * DPI_DMA_DBELL[0..7] = DMA Door Bell
 558  *
 559  * The door bell register for DMA[0..7] queue.
 560  */
 561 union cvmx_dpi_dmax_dbell {
 562         uint64_t u64;
 563         struct cvmx_dpi_dmax_dbell_s {
 564 #ifdef __BIG_ENDIAN_BITFIELD
 565         uint64_t reserved_16_63               : 48;
 566         uint64_t dbell                        : 16; /**< The value written to this register is added to the
 567                                                          number of 8byte words to be read and processes for
 568                                                          the low priority dma queue. */
 569 #else
 570         uint64_t dbell                        : 16;
 571         uint64_t reserved_16_63               : 48;
 572 #endif
 573         } s;
 574         struct cvmx_dpi_dmax_dbell_s          cn61xx;
 575         struct cvmx_dpi_dmax_dbell_s          cn63xx;
 576         struct cvmx_dpi_dmax_dbell_s          cn63xxp1;
 577         struct cvmx_dpi_dmax_dbell_s          cn66xx;
 578         struct cvmx_dpi_dmax_dbell_s          cn68xx;
 579         struct cvmx_dpi_dmax_dbell_s          cn68xxp1;
 580         struct cvmx_dpi_dmax_dbell_s          cnf71xx;
 581 };
 582 typedef union cvmx_dpi_dmax_dbell cvmx_dpi_dmax_dbell_t;
 583
 584 /**
 585  * cvmx_dpi_dma#_err_rsp_status
 586  */
 587 union cvmx_dpi_dmax_err_rsp_status {
 588         uint64_t u64;
 589         struct cvmx_dpi_dmax_err_rsp_status_s {
 590 #ifdef __BIG_ENDIAN_BITFIELD
 591         uint64_t reserved_6_63                : 58;
 592         uint64_t status                       : 6;  /**< QUE captures the ErrorResponse status of the last
 593                                                          6 instructions for each instruction queue.
 594                                                          STATUS<5> represents the status for first
 595                                                          instruction in instruction order while STATUS<0>
 596                                                          represents the last or most recent instruction.
 597                                                          If STATUS<n> is set, then the nth instruction in
 598                                                          the given queue experienced an ErrorResponse.
 599                                                          Otherwise, it completed normally. */
 600 #else
 601         uint64_t status                       : 6;
 602         uint64_t reserved_6_63                : 58;
 603 #endif
 604         } s;
 605         struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
 606         struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
 607         struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
 608         struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
 609         struct cvmx_dpi_dmax_err_rsp_status_s cnf71xx;
 610 };
 611 typedef union cvmx_dpi_dmax_err_rsp_status cvmx_dpi_dmax_err_rsp_status_t;
 612
 613 /**
 614  * cvmx_dpi_dma#_ibuff_saddr
 615  *
 616  * DPI_DMA[0..7]_IBUFF_SADDR = DMA Instruction Buffer Starting Address
 617  *
 618  * The address to start reading Instructions from for DMA[0..7].
 619  */
 620 union cvmx_dpi_dmax_ibuff_saddr {
 621         uint64_t u64;
 622         struct cvmx_dpi_dmax_ibuff_saddr_s {
 623 #ifdef __BIG_ENDIAN_BITFIELD
 624         uint64_t reserved_62_63               : 2;
 625         uint64_t csize                        : 14; /**< The size in 8B words of the DMA Instruction Chunk.
 626                                                          This value should only be written at known times
 627                                                          in order to prevent corruption of the instruction
 628                                                          queue.  The minimum CSIZE is 16 (one cacheblock). */
 629         uint64_t reserved_41_47               : 7;
 630         uint64_t idle                         : 1;  /**< DMA Request Queue is IDLE */
 631         uint64_t saddr                        : 33; /**< The 128 byte aligned starting or chunk address.
 632                                                          SADDR is address bit 35:7 of the starting
 633                                                          instructions address. When new chunks are fetched
 634                                                          by the HW, SADDR will be updated to reflect the
 635                                                          address of the current chunk.
 636                                                          A write to SADDR resets both the queue's doorbell
 637                                                          (DPI_DMAx_COUNTS[DBELL) and its tail pointer
 638                                                          (DPI_DMAx_NADDR[ADDR]). */
 639         uint64_t reserved_0_6                 : 7;
 640 #else
 641         uint64_t reserved_0_6                 : 7;
 642         uint64_t saddr                        : 33;
 643         uint64_t idle                         : 1;
 644         uint64_t reserved_41_47               : 7;
 645         uint64_t csize                        : 14;
 646         uint64_t reserved_62_63               : 2;
 647 #endif
 648         } s;
 649         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
 650 #ifdef __BIG_ENDIAN_BITFIELD
 651         uint64_t reserved_62_63               : 2;
 652         uint64_t csize                        : 14; /**< The size in 8B words of the DMA Instruction Chunk.
 653                                                          This value should only be written at known times
 654                                                          in order to prevent corruption of the instruction
 655                                                          queue.  The minimum CSIZE is 16 (one cacheblock). */
 656         uint64_t reserved_41_47               : 7;
 657         uint64_t idle                         : 1;  /**< DMA Request Queue is IDLE */
 658         uint64_t reserved_36_39               : 4;
 659         uint64_t saddr                        : 29; /**< The 128 byte aligned starting or chunk address.
 660                                                          SADDR is address bit 35:7 of the starting
 661                                                          instructions address. When new chunks are fetched
 662                                                          by the HW, SADDR will be updated to reflect the
 663                                                          address of the current chunk.
 664                                                          A write to SADDR resets both the queue's doorbell
 665                                                          (DPI_DMAx_COUNTS[DBELL) and its tail pointer
 666                                                          (DPI_DMAx_NADDR[ADDR]). */
 667         uint64_t reserved_0_6                 : 7;
 668 #else
 669         uint64_t reserved_0_6                 : 7;
 670         uint64_t saddr                        : 29;
 671         uint64_t reserved_36_39               : 4;
 672         uint64_t idle                         : 1;
 673         uint64_t reserved_41_47               : 7;
 674         uint64_t csize                        : 14;
 675         uint64_t reserved_62_63               : 2;
 676 #endif
 677         } cn61xx;
 678         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
 679         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
 680         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
 681         struct cvmx_dpi_dmax_ibuff_saddr_s    cn68xx;
 682         struct cvmx_dpi_dmax_ibuff_saddr_s    cn68xxp1;
 683         struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cnf71xx;
 684 };
 685 typedef union cvmx_dpi_dmax_ibuff_saddr cvmx_dpi_dmax_ibuff_saddr_t;
 686
 687 /**
 688  * cvmx_dpi_dma#_iflight
 689  */
 690 union cvmx_dpi_dmax_iflight {
 691         uint64_t u64;
 692         struct cvmx_dpi_dmax_iflight_s {
 693 #ifdef __BIG_ENDIAN_BITFIELD
 694         uint64_t reserved_3_63                : 61;
 695         uint64_t cnt                          : 3;  /**< The number of instructions from a given queue that
 696                                                          can be inflight to the DMA engines at a time.
 697                                                          Reset value matches the number of DMA engines. */
 698 #else
 699         uint64_t cnt                          : 3;
 700         uint64_t reserved_3_63                : 61;
 701 #endif
 702         } s;
 703         struct cvmx_dpi_dmax_iflight_s        cn61xx;
 704         struct cvmx_dpi_dmax_iflight_s        cn66xx;
 705         struct cvmx_dpi_dmax_iflight_s        cn68xx;
 706         struct cvmx_dpi_dmax_iflight_s        cn68xxp1;
 707         struct cvmx_dpi_dmax_iflight_s        cnf71xx;
 708 };
 709 typedef union cvmx_dpi_dmax_iflight cvmx_dpi_dmax_iflight_t;
 710
 711 /**
 712  * cvmx_dpi_dma#_naddr
 713  *
 714  * DPI_DMA[0..7]_NADDR = DMA Next Ichunk Address
 715  *
 716  * Place DPI will read the next Ichunk data from.
 717  */
 718 union cvmx_dpi_dmax_naddr {
 719         uint64_t u64;
 720         struct cvmx_dpi_dmax_naddr_s {
 721 #ifdef __BIG_ENDIAN_BITFIELD
 722         uint64_t reserved_40_63               : 24;
 723         uint64_t addr                         : 40; /**< The next L2C address to read DMA# instructions
 724                                                          from. */
 725 #else
 726         uint64_t addr                         : 40;
 727         uint64_t reserved_40_63               : 24;
 728 #endif
 729         } s;
 730         struct cvmx_dpi_dmax_naddr_cn61xx {
 731 #ifdef __BIG_ENDIAN_BITFIELD
 732         uint64_t reserved_36_63               : 28;
 733         uint64_t addr                         : 36; /**< The next L2C address to read DMA# instructions
 734                                                          from. */
 735 #else
 736         uint64_t addr                         : 36;
 737         uint64_t reserved_36_63               : 28;
 738 #endif
 739         } cn61xx;
 740         struct cvmx_dpi_dmax_naddr_cn61xx     cn63xx;
 741         struct cvmx_dpi_dmax_naddr_cn61xx     cn63xxp1;
 742         struct cvmx_dpi_dmax_naddr_cn61xx     cn66xx;
 743         struct cvmx_dpi_dmax_naddr_s          cn68xx;
 744         struct cvmx_dpi_dmax_naddr_s          cn68xxp1;
 745         struct cvmx_dpi_dmax_naddr_cn61xx     cnf71xx;
 746 };
 747 typedef union cvmx_dpi_dmax_naddr cvmx_dpi_dmax_naddr_t;
 748
 749 /**
 750  * cvmx_dpi_dma#_reqbnk0
 751  *
 752  * DPI_DMA[0..7]_REQBNK0 = DMA Request State Bank0
 753  *
 754  * Current contents of the request state machine - bank0
 755  */
 756 union cvmx_dpi_dmax_reqbnk0 {
 757         uint64_t u64;
 758         struct cvmx_dpi_dmax_reqbnk0_s {
 759 #ifdef __BIG_ENDIAN_BITFIELD
 760         uint64_t state                        : 64; /**< State */
 761 #else
 762         uint64_t state                        : 64;
 763 #endif
 764         } s;
 765         struct cvmx_dpi_dmax_reqbnk0_s        cn61xx;
 766         struct cvmx_dpi_dmax_reqbnk0_s        cn63xx;
 767         struct cvmx_dpi_dmax_reqbnk0_s        cn63xxp1;
 768         struct cvmx_dpi_dmax_reqbnk0_s        cn66xx;
 769         struct cvmx_dpi_dmax_reqbnk0_s        cn68xx;
 770         struct cvmx_dpi_dmax_reqbnk0_s        cn68xxp1;
 771         struct cvmx_dpi_dmax_reqbnk0_s        cnf71xx;
 772 };
 773 typedef union cvmx_dpi_dmax_reqbnk0 cvmx_dpi_dmax_reqbnk0_t;
 774
 775 /**
 776  * cvmx_dpi_dma#_reqbnk1
 777  *
 778  * DPI_DMA[0..7]_REQBNK1 = DMA Request State Bank1
 779  *
 780  * Current contents of the request state machine - bank1
 781  */
 782 union cvmx_dpi_dmax_reqbnk1 {
 783         uint64_t u64;
 784         struct cvmx_dpi_dmax_reqbnk1_s {
 785 #ifdef __BIG_ENDIAN_BITFIELD
 786         uint64_t state                        : 64; /**< State */
 787 #else
 788         uint64_t state                        : 64;
 789 #endif
 790         } s;
 791         struct cvmx_dpi_dmax_reqbnk1_s        cn61xx;
 792         struct cvmx_dpi_dmax_reqbnk1_s        cn63xx;
 793         struct cvmx_dpi_dmax_reqbnk1_s        cn63xxp1;
 794         struct cvmx_dpi_dmax_reqbnk1_s        cn66xx;
 795         struct cvmx_dpi_dmax_reqbnk1_s        cn68xx;
 796         struct cvmx_dpi_dmax_reqbnk1_s        cn68xxp1;
 797         struct cvmx_dpi_dmax_reqbnk1_s        cnf71xx;
 798 };
 799 typedef union cvmx_dpi_dmax_reqbnk1 cvmx_dpi_dmax_reqbnk1_t;
 800
 801 /**
 802  * cvmx_dpi_dma_control
 803  *
 804  * DPI_DMA_CONTROL = DMA Control Register
 805  *
 806  * Controls operation of the DMA IN/OUT.
 807  */
 808 union cvmx_dpi_dma_control {
 809         uint64_t u64;
 810         struct cvmx_dpi_dma_control_s {
 811 #ifdef __BIG_ENDIAN_BITFIELD
 812         uint64_t reserved_62_63               : 2;
 813         uint64_t dici_mode                    : 1;  /**< DMA Instruction Completion Interrupt Mode
 814                                                          turns on mode to increment DPI_DMA_PPx_CNT
 815                                                          counters. */
 816         uint64_t pkt_en1                      : 1;  /**< Enables the 2nd packet interface.
 817                                                          When the packet interface is enabled, engine 4
 818                                                          is used for packets and is not available for DMA.
 819                                                          The packet interfaces must be enabled in order.
 820                                                          When PKT_EN1=1, then PKT_EN=1.
 821                                                          When PKT_EN1=1, then DMA_ENB<4>=0. */
 822         uint64_t ffp_dis                      : 1;  /**< Force forward progress disable
 823                                                          The DMA engines will compete for shared resources.
 824                                                          If the HW detects that particular engines are not
 825                                                          able to make requests to an interface, the HW
 826                                                          will periodically trade-off throughput for
 827                                                          fairness. */
 828         uint64_t commit_mode                  : 1;  /**< DMA Engine Commit Mode
 829
 830                                                          When COMMIT_MODE=0, DPI considers an instruction
 831                                                          complete when the HW internally generates the
 832                                                          final write for the current instruction.
 833
 834                                                          When COMMIT_MODE=1, DPI additionally waits for
 835                                                          the final write to reach the interface coherency
 836                                                          point to declare the instructions complete.
 837
 838                                                          Please note: when COMMIT_MODE == 0, DPI may not
 839                                                          follow the HRM ordering rules.
 840
 841                                                          DPI hardware performance may be better with
 842                                                          COMMIT_MODE == 0 than with COMMIT_MODE == 1 due
 843                                                          to the relaxed ordering rules.
 844
 845                                                          If the HRM ordering rules are required, set
 846                                                          COMMIT_MODE == 1. */
 847         uint64_t pkt_hp                       : 1;  /**< High-Priority Mode for Packet Interface.
 848                                                          This mode has been deprecated. */
 849         uint64_t pkt_en                       : 1;  /**< Enables 1st the packet interface.
 850                                                          When the packet interface is enabled, engine 5
 851                                                          is used for packets and is not available for DMA.
 852                                                          When PKT_EN=1, then DMA_ENB<5>=0.
 853                                                          When PKT_EN1=1, then PKT_EN=1. */
 854         uint64_t reserved_54_55               : 2;
 855         uint64_t dma_enb                      : 6;  /**< DMA engine enable. Enables the operation of the
 856                                                          DMA engine. After being enabled an engine should
 857                                                          not be disabled while processing instructions.
 858                                                          When PKT_EN=1,  then DMA_ENB<5>=0.
 859                                                          When PKT_EN1=1, then DMA_ENB<4>=0. */
 860         uint64_t reserved_34_47               : 14;
 861         uint64_t b0_lend                      : 1;  /**< When set '1' and the DPI is in the mode to write
 862                                                          0 to L2C memory when a DMA is done, the address
 863                                                          to be written to will be treated as a Little
 864                                                          Endian address. */
 865         uint64_t dwb_denb                     : 1;  /**< When set '1', DPI will send a value in the DWB
 866                                                          field for a free page operation for the memory
 867                                                          that contained the data. */
 868         uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are
 869                                                          freed this value is used for the DWB field of the
 870                                                          operation. */
 871         uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
 872                                                          be returned to when used. */
 873         uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the SLI_DMAX_CNT
 874                                                          DMA counters, if '0' then the number of bytes
 875                                                          in the dma transfer will be added to the
 876                                                          SLI_DMAX_CNT count register. */
 877         uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
 878         uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
 879         uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
 880         uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
 881                                                          0=DPTR format 1 is used
 882                                                            use register values for address and pointer
 883                                                            values for ES, NS, RO
 884                                                          1=DPTR format 0 is used
 885                                                            use pointer values for address and register
 886                                                            values for ES, NS, RO */
 887         uint64_t reserved_0_13                : 14;
 888 #else
 889         uint64_t reserved_0_13                : 14;
 890         uint64_t o_mode                       : 1;
 891         uint64_t o_es                         : 2;
 892         uint64_t o_ns                         : 1;
 893         uint64_t o_ro                         : 1;
 894         uint64_t o_add1                       : 1;
 895         uint64_t fpa_que                      : 3;
 896         uint64_t dwb_ichk                     : 9;
 897         uint64_t dwb_denb                     : 1;
 898         uint64_t b0_lend                      : 1;
 899         uint64_t reserved_34_47               : 14;
 900         uint64_t dma_enb                      : 6;
 901         uint64_t reserved_54_55               : 2;
 902         uint64_t pkt_en                       : 1;
 903         uint64_t pkt_hp                       : 1;
 904         uint64_t commit_mode                  : 1;
 905         uint64_t ffp_dis                      : 1;
 906         uint64_t pkt_en1                      : 1;
 907         uint64_t dici_mode                    : 1;
 908         uint64_t reserved_62_63               : 2;
 909 #endif
 910         } s;
 911         struct cvmx_dpi_dma_control_s         cn61xx;
 912         struct cvmx_dpi_dma_control_cn63xx {
 913 #ifdef __BIG_ENDIAN_BITFIELD
 914         uint64_t reserved_61_63               : 3;
 915         uint64_t pkt_en1                      : 1;  /**< Enables the 2nd packet interface.
 916                                                          When the packet interface is enabled, engine 4
 917                                                          is used for packets and is not available for DMA.
 918                                                          The packet interfaces must be enabled in order.
 919                                                          When PKT_EN1=1, then PKT_EN=1.
 920                                                          When PKT_EN1=1, then DMA_ENB<4>=0. */
 921         uint64_t ffp_dis                      : 1;  /**< Force forward progress disable
 922                                                          The DMA engines will compete for shared resources.
 923                                                          If the HW detects that particular engines are not
 924                                                          able to make requests to an interface, the HW
 925                                                          will periodically trade-off throughput for
 926                                                          fairness. */
 927         uint64_t commit_mode                  : 1;  /**< DMA Engine Commit Mode
 928
 929                                                          When COMMIT_MODE=0, DPI considers an instruction
 930                                                          complete when the HW internally generates the
 931                                                          final write for the current instruction.
 932
 933                                                          When COMMIT_MODE=1, DPI additionally waits for
 934                                                          the final write to reach the interface coherency
 935                                                          point to declare the instructions complete.
 936
 937                                                          Please note: when COMMIT_MODE == 0, DPI may not
 938                                                          follow the HRM ordering rules.
 939
 940                                                          DPI hardware performance may be better with
 941                                                          COMMIT_MODE == 0 than with COMMIT_MODE == 1 due
 942                                                          to the relaxed ordering rules.
 943
 944                                                          If the HRM ordering rules are required, set
 945                                                          COMMIT_MODE == 1. */
 946         uint64_t pkt_hp                       : 1;  /**< High-Priority Mode for Packet Interface.
 947                                                          This mode has been deprecated. */
 948         uint64_t pkt_en                       : 1;  /**< Enables 1st the packet interface.
 949                                                          When the packet interface is enabled, engine 5
 950                                                          is used for packets and is not available for DMA.
 951                                                          When PKT_EN=1, then DMA_ENB<5>=0.
 952                                                          When PKT_EN1=1, then PKT_EN=1. */
 953         uint64_t reserved_54_55               : 2;
 954         uint64_t dma_enb                      : 6;  /**< DMA engine enable. Enables the operation of the
 955                                                          DMA engine. After being enabled an engine should
 956                                                          not be disabled while processing instructions.
 957                                                          When PKT_EN=1,  then DMA_ENB<5>=0.
 958                                                          When PKT_EN1=1, then DMA_ENB<4>=0. */
 959         uint64_t reserved_34_47               : 14;
 960         uint64_t b0_lend                      : 1;  /**< When set '1' and the DPI is in the mode to write
 961                                                          0 to L2C memory when a DMA is done, the address
 962                                                          to be written to will be treated as a Little
 963                                                          Endian address. */
 964         uint64_t dwb_denb                     : 1;  /**< When set '1', DPI will send a value in the DWB
 965                                                          field for a free page operation for the memory
 966                                                          that contained the data. */
 967         uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are
 968                                                          freed this value is used for the DWB field of the
 969                                                          operation. */
 970         uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
 971                                                          be returned to when used. */
 972         uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
 973                                                          if '0' then the number of bytes in the dma
 974                                                          transfer will be added to the count register. */
 975         uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
 976         uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
 977         uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
 978         uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
 979                                                          0=DPTR format 1 is used
 980                                                            use register values for address and pointer
 981                                                            values for ES, NS, RO
 982                                                          1=DPTR format 0 is used
 983                                                            use pointer values for address and register
 984                                                            values for ES, NS, RO */
 985         uint64_t reserved_0_13                : 14;
 986 #else
 987         uint64_t reserved_0_13                : 14;
 988         uint64_t o_mode                       : 1;
 989         uint64_t o_es                         : 2;
 990         uint64_t o_ns                         : 1;
 991         uint64_t o_ro                         : 1;
 992         uint64_t o_add1                       : 1;
 993         uint64_t fpa_que                      : 3;
 994         uint64_t dwb_ichk                     : 9;
 995         uint64_t dwb_denb                     : 1;
 996         uint64_t b0_lend                      : 1;
 997         uint64_t reserved_34_47               : 14;
 998         uint64_t dma_enb                      : 6;
 999         uint64_t reserved_54_55               : 2;
1000         uint64_t pkt_en                       : 1;
1001         uint64_t pkt_hp                       : 1;
1002         uint64_t commit_mode                  : 1;
1003         uint64_t ffp_dis                      : 1;
1004         uint64_t pkt_en1                      : 1;
1005         uint64_t reserved_61_63               : 3;
1006 #endif
1007         } cn63xx;
1008         struct cvmx_dpi_dma_control_cn63xxp1 {
1009 #ifdef __BIG_ENDIAN_BITFIELD
1010         uint64_t reserved_59_63               : 5;
1011         uint64_t commit_mode                  : 1;  /**< DMA Engine Commit Mode
1012
1013                                                          When COMMIT_MODE=0, DPI considers an instruction
1014                                                          complete when the HW internally generates the
1015                                                          final write for the current instruction.
1016
1017                                                          When COMMIT_MODE=1, DPI additionally waits for
1018                                                          the final write to reach the interface coherency
1019                                                          point to declare the instructions complete.
1020
1021                                                          Please note: when COMMIT_MODE == 0, DPI may not
1022                                                          follow the HRM ordering rules.
1023
1024                                                          DPI hardware performance may be better with
1025                                                          COMMIT_MODE == 0 than with COMMIT_MODE == 1 due
1026                                                          to the relaxed ordering rules.
1027
1028                                                          If the HRM ordering rules are required, set
1029                                                          COMMIT_MODE == 1. */
1030         uint64_t pkt_hp                       : 1;  /**< High-Priority Mode for Packet Interface.
1031                                                          Engine 5 will be serviced more frequently to
1032                                                          deliver more bandwidth to packet interface.
1033                                                          When PKT_EN=0, then PKT_HP=0. */
1034         uint64_t pkt_en                       : 1;  /**< Enables the packet interface.
1035                                                          When the packet interface is enabled, engine 5
1036                                                          is used for packets and is not available for DMA.
1037                                                          When PKT_EN=1, then DMA_ENB<5>=0.
1038                                                          When PKT_EN=0, then PKT_HP=0. */
1039         uint64_t reserved_54_55               : 2;
1040         uint64_t dma_enb                      : 6;  /**< DMA engine enable. Enables the operation of the
1041                                                          DMA engine. After being enabled an engine should
1042                                                          not be disabled while processing instructions.
1043                                                          When PKT_EN=1, then DMA_ENB<5>=0. */
1044         uint64_t reserved_34_47               : 14;
1045         uint64_t b0_lend                      : 1;  /**< When set '1' and the DPI is in the mode to write
1046                                                          0 to L2C memory when a DMA is done, the address
1047                                                          to be written to will be treated as a Little
1048                                                          Endian address. */
1049         uint64_t dwb_denb                     : 1;  /**< When set '1', DPI will send a value in the DWB
1050                                                          field for a free page operation for the memory
1051                                                          that contained the data. */
1052         uint64_t dwb_ichk                     : 9;  /**< When Instruction Chunks for DMA operations are
1053                                                          freed this value is used for the DWB field of the
1054                                                          operation. */
1055         uint64_t fpa_que                      : 3;  /**< The FPA queue that the instruction-chunk page will
1056                                                          be returned to when used. */
1057         uint64_t o_add1                       : 1;  /**< When set '1' 1 will be added to the DMA counters,
1058                                                          if '0' then the number of bytes in the dma
1059                                                          transfer will be added to the count register. */
1060         uint64_t o_ro                         : 1;  /**< Relaxed Ordering Mode for DMA. */
1061         uint64_t o_ns                         : 1;  /**< Nosnoop For DMA. */
1062         uint64_t o_es                         : 2;  /**< Endian Swap Mode for DMA. */
1063         uint64_t o_mode                       : 1;  /**< Select PCI_POINTER MODE to be used.
1064                                                          0=DPTR format 1 is used
1065                                                            use register values for address and pointer
1066                                                            values for ES, NS, RO
1067                                                          1=DPTR format 0 is used
1068                                                            use pointer values for address and register
1069                                                            values for ES, NS, RO */
1070         uint64_t reserved_0_13                : 14;
1071 #else
1072         uint64_t reserved_0_13                : 14;
1073         uint64_t o_mode                       : 1;
1074         uint64_t o_es                         : 2;
1075         uint64_t o_ns                         : 1;
1076         uint64_t o_ro                         : 1;
1077         uint64_t o_add1                       : 1;
1078         uint64_t fpa_que                      : 3;
1079         uint64_t dwb_ichk                     : 9;
1080         uint64_t dwb_denb                     : 1;
1081         uint64_t b0_lend                      : 1;
1082         uint64_t reserved_34_47               : 14;
1083         uint64_t dma_enb                      : 6;
1084         uint64_t reserved_54_55               : 2;
1085         uint64_t pkt_en                       : 1;
1086         uint64_t pkt_hp                       : 1;
1087         uint64_t commit_mode                  : 1;
1088         uint64_t reserved_59_63               : 5;
1089 #endif
1090         } cn63xxp1;
1091         struct cvmx_dpi_dma_control_cn63xx    cn66xx;
1092         struct cvmx_dpi_dma_control_s         cn68xx;
1093         struct cvmx_dpi_dma_control_cn63xx    cn68xxp1;
1094         struct cvmx_dpi_dma_control_s         cnf71xx;
1095 };
1096 typedef union cvmx_dpi_dma_control cvmx_dpi_dma_control_t;
1097
1098 /**
1099  * cvmx_dpi_dma_eng#_en
1100  */
1101 union cvmx_dpi_dma_engx_en {
1102         uint64_t u64;
1103         struct cvmx_dpi_dma_engx_en_s {
1104 #ifdef __BIG_ENDIAN_BITFIELD
1105         uint64_t reserved_8_63                : 56;
1106         uint64_t qen                          : 8;  /**< Controls which logical instruction queues can be
1107                                                          serviced by the DMA engine. Setting QEN==0
1108                                                          effectively disables the engine.
1109                                                          When DPI_DMA_CONTROL[PKT_EN] = 1, then
1110                                                          DPI_DMA_ENG5_EN[QEN] must be zero.
1111                                                          When DPI_DMA_CONTROL[PKT_EN1] = 1, then
1112                                                          DPI_DMA_ENG4_EN[QEN] must be zero. */
1113 #else
1114         uint64_t qen                          : 8;
1115         uint64_t reserved_8_63                : 56;
1116 #endif
1117         } s;
1118         struct cvmx_dpi_dma_engx_en_s         cn61xx;
1119         struct cvmx_dpi_dma_engx_en_s         cn63xx;
1120         struct cvmx_dpi_dma_engx_en_s         cn63xxp1;
1121         struct cvmx_dpi_dma_engx_en_s         cn66xx;
1122         struct cvmx_dpi_dma_engx_en_s         cn68xx;
1123         struct cvmx_dpi_dma_engx_en_s         cn68xxp1;
1124         struct cvmx_dpi_dma_engx_en_s         cnf71xx;
1125 };
1126 typedef union cvmx_dpi_dma_engx_en cvmx_dpi_dma_engx_en_t;
1127
1128 /**
1129  * cvmx_dpi_dma_pp#_cnt
1130  *
1131  * DPI_DMA_PP[0..3]_CNT  = DMA per PP Instr Done Counter
1132  *
1133  * When DMA Instruction Completion Interrupt Mode DPI_DMA_CONTROL.DICI_MODE is enabled, every dma instruction
1134  * that has the WQP=0 and a PTR value of 1..4 will incremrement DPI_DMA_PPx_CNT value-1 counter.
1135  * Instructions with WQP=0 and PTR values higher then 0x3F will still send a zero byte write.
1136  * Hardware reserves that values 5..63 for future use and will treat them as a PTR of 0 and do nothing.
1137  */
1138 union cvmx_dpi_dma_ppx_cnt {
1139         uint64_t u64;
1140         struct cvmx_dpi_dma_ppx_cnt_s {
1141 #ifdef __BIG_ENDIAN_BITFIELD
1142         uint64_t reserved_16_63               : 48;
1143         uint64_t cnt                          : 16; /**< Counter incremented according to conditions
1144                                                          described above and decremented by values written
1145                                                          to this field.  A CNT of non zero, will cause
1146                                                          an interrupt in the CIU_SUM1_PPX_IPX register */
1147 #else
1148         uint64_t cnt                          : 16;
1149         uint64_t reserved_16_63               : 48;
1150 #endif
1151         } s;
1152         struct cvmx_dpi_dma_ppx_cnt_s         cn61xx;
1153         struct cvmx_dpi_dma_ppx_cnt_s         cn68xx;
1154         struct cvmx_dpi_dma_ppx_cnt_s         cnf71xx;
1155 };
1156 typedef union cvmx_dpi_dma_ppx_cnt cvmx_dpi_dma_ppx_cnt_t;
1157
1158 /**
1159  * cvmx_dpi_eng#_buf
1160  *
1161  * Notes:
1162  * The total amount of storage allocated to the 6 DPI DMA engines (via DPI_ENG*_BUF[BLKS]) must not exceed 8KB.
1163  *
1164  */
1165 union cvmx_dpi_engx_buf {
1166         uint64_t u64;
1167         struct cvmx_dpi_engx_buf_s {
1168 #ifdef __BIG_ENDIAN_BITFIELD
1169         uint64_t reserved_37_63               : 27;
1170         uint64_t compblks                     : 5;  /**< Computed engine block size */
1171         uint64_t reserved_9_31                : 23;
1172         uint64_t base                         : 5;  /**< The base address in 512B blocks of the engine fifo */
1173         uint64_t blks                         : 4;  /**< The size of the engine fifo
1174                                                          Legal values are 0-10.
1175                                                          0  = Engine is disabled
1176                                                          1  = 0.5KB buffer
1177                                                          2  = 1.0KB buffer
1178                                                          3  = 1.5KB buffer
1179                                                          4  = 2.0KB buffer
1180                                                          5  = 2.5KB buffer
1181                                                          6  = 3.0KB buffer
1182                                                          7  = 3.5KB buffer
1183                                                          8  = 4.0KB buffer
1184                                                          9  = 6.0KB buffer
1185                                                          10 = 8.0KB buffer */
1186 #else
1187         uint64_t blks                         : 4;
1188         uint64_t base                         : 5;
1189         uint64_t reserved_9_31                : 23;
1190         uint64_t compblks                     : 5;
1191         uint64_t reserved_37_63               : 27;
1192 #endif
1193         } s;
1194         struct cvmx_dpi_engx_buf_s            cn61xx;
1195         struct cvmx_dpi_engx_buf_cn63xx {
1196 #ifdef __BIG_ENDIAN_BITFIELD
1197         uint64_t reserved_8_63                : 56;
1198         uint64_t base                         : 4;  /**< The base address in 512B blocks of the engine fifo */
1199         uint64_t blks                         : 4;  /**< The size in 512B blocks of the engine fifo
1200                                                          Legal values are 0-8.
1201                                                          0 = Engine is disabled
1202                                                          1 = 0.5KB buffer
1203                                                          2 = 1.0KB buffer
1204                                                          3 = 1.5KB buffer
1205                                                          4 = 2.0KB buffer
1206                                                          5 = 2.5KB buffer
1207                                                          6 = 3.0KB buffer
1208                                                          7 = 3.5KB buffer
1209                                                          8 = 4.0KB buffer */
1210 #else
1211         uint64_t blks                         : 4;
1212         uint64_t base                         : 4;
1213         uint64_t reserved_8_63                : 56;
1214 #endif
1215         } cn63xx;
1216         struct cvmx_dpi_engx_buf_cn63xx       cn63xxp1;
1217         struct cvmx_dpi_engx_buf_s            cn66xx;
1218         struct cvmx_dpi_engx_buf_s            cn68xx;
1219         struct cvmx_dpi_engx_buf_s            cn68xxp1;
1220         struct cvmx_dpi_engx_buf_s            cnf71xx;
1221 };
1222 typedef union cvmx_dpi_engx_buf cvmx_dpi_engx_buf_t;
1223
1224 /**
1225  * cvmx_dpi_info_reg
1226  */
1227 union cvmx_dpi_info_reg {
1228         uint64_t u64;
1229         struct cvmx_dpi_info_reg_s {
1230 #ifdef __BIG_ENDIAN_BITFIELD
1231         uint64_t reserved_8_63                : 56;
1232         uint64_t ffp                          : 4;  /**< Force Forward Progress Indicator */
1233         uint64_t reserved_2_3                 : 2;
1234         uint64_t ncb                          : 1;  /**< NCB Register Access
1235                                                          This interrupt will fire in normal operation
1236                                                          when SW reads a DPI register through the NCB
1237                                                          interface. */
1238         uint64_t rsl                          : 1;  /**< RSL Register Access
1239                                                          This interrupt will fire in normal operation
1240                                                          when SW reads a DPI register through the RSL
1241                                                          interface. */
1242 #else
1243         uint64_t rsl                          : 1;
1244         uint64_t ncb                          : 1;
1245         uint64_t reserved_2_3                 : 2;
1246         uint64_t ffp                          : 4;
1247         uint64_t reserved_8_63                : 56;
1248 #endif
1249         } s;
1250         struct cvmx_dpi_info_reg_s            cn61xx;
1251         struct cvmx_dpi_info_reg_s            cn63xx;
1252         struct cvmx_dpi_info_reg_cn63xxp1 {
1253 #ifdef __BIG_ENDIAN_BITFIELD
1254         uint64_t reserved_2_63                : 62;
1255         uint64_t ncb                          : 1;  /**< NCB Register Access
1256                                                          This interrupt will fire in normal operation
1257                                                          when SW reads a DPI register through the NCB
1258                                                          interface. */
1259         uint64_t rsl                          : 1;  /**< RSL Register Access
1260                                                          This interrupt will fire in normal operation
1261                                                          when SW reads a DPI register through the RSL
1262                                                          interface. */
1263 #else
1264         uint64_t rsl                          : 1;
1265         uint64_t ncb                          : 1;
1266         uint64_t reserved_2_63                : 62;
1267 #endif
1268         } cn63xxp1;
1269         struct cvmx_dpi_info_reg_s            cn66xx;
1270         struct cvmx_dpi_info_reg_s            cn68xx;
1271         struct cvmx_dpi_info_reg_s            cn68xxp1;
1272         struct cvmx_dpi_info_reg_s            cnf71xx;
1273 };
1274 typedef union cvmx_dpi_info_reg cvmx_dpi_info_reg_t;
1275
1276 /**
1277  * cvmx_dpi_int_en
1278  */
1279 union cvmx_dpi_int_en {
1280         uint64_t u64;
1281         struct cvmx_dpi_int_en_s {
1282 #ifdef __BIG_ENDIAN_BITFIELD
1283         uint64_t reserved_28_63               : 36;
1284         uint64_t sprt3_rst                    : 1;  /**< DMA instruction was dropped because the source or
1285                                                           destination port was in reset.
1286                                                          this bit is set. */
1287         uint64_t sprt2_rst                    : 1;  /**< DMA instruction was dropped because the source or
1288                                                           destination port was in reset.
1289                                                          this bit is set. */
1290         uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
1291                                                           destination port was in reset.
1292                                                          this bit is set. */
1293         uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
1294                                                           destination port was in reset.
1295                                                          this bit is set. */
1296         uint64_t reserved_23_23               : 1;
1297         uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill */
1298         uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer */
1299         uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction */
1300         uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow */
1301         uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow */
1302         uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length */
1303         uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer */
1304         uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow. */
1305         uint64_t reserved_2_7                 : 6;
1306         uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow */
1307         uint64_t nderr                        : 1;  /**< NCB Decode Error */
1308 #else
1309         uint64_t nderr                        : 1;
1310         uint64_t nfovr                        : 1;
1311         uint64_t reserved_2_7                 : 6;
1312         uint64_t dmadbo                       : 8;
1313         uint64_t req_badadr                   : 1;
1314         uint64_t req_badlen                   : 1;
1315         uint64_t req_ovrflw                   : 1;
1316         uint64_t req_undflw                   : 1;
1317         uint64_t req_anull                    : 1;
1318         uint64_t req_inull                    : 1;
1319         uint64_t req_badfil                   : 1;
1320         uint64_t reserved_23_23               : 1;
1321         uint64_t sprt0_rst                    : 1;
1322         uint64_t sprt1_rst                    : 1;
1323         uint64_t sprt2_rst                    : 1;
1324         uint64_t sprt3_rst                    : 1;
1325         uint64_t reserved_28_63               : 36;
1326 #endif
1327         } s;
1328         struct cvmx_dpi_int_en_s              cn61xx;
1329         struct cvmx_dpi_int_en_cn63xx {
1330 #ifdef __BIG_ENDIAN_BITFIELD
1331         uint64_t reserved_26_63               : 38;
1332         uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
1333                                                           destination port was in reset.
1334                                                          this bit is set. */
1335         uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
1336                                                           destination port was in reset.
1337                                                          this bit is set. */
1338         uint64_t reserved_23_23               : 1;
1339         uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill */
1340         uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer */
1341         uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction */
1342         uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow */
1343         uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow */
1344         uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length */
1345         uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer */
1346         uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow. */
1347         uint64_t reserved_2_7                 : 6;
1348         uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow */
1349         uint64_t nderr                        : 1;  /**< NCB Decode Error */
1350 #else
1351         uint64_t nderr                        : 1;
1352         uint64_t nfovr                        : 1;
1353         uint64_t reserved_2_7                 : 6;
1354         uint64_t dmadbo                       : 8;
1355         uint64_t req_badadr                   : 1;
1356         uint64_t req_badlen                   : 1;
1357         uint64_t req_ovrflw                   : 1;
1358         uint64_t req_undflw                   : 1;
1359         uint64_t req_anull                    : 1;
1360         uint64_t req_inull                    : 1;
1361         uint64_t req_badfil                   : 1;
1362         uint64_t reserved_23_23               : 1;
1363         uint64_t sprt0_rst                    : 1;
1364         uint64_t sprt1_rst                    : 1;
1365         uint64_t reserved_26_63               : 38;
1366 #endif
1367         } cn63xx;
1368         struct cvmx_dpi_int_en_cn63xx         cn63xxp1;
1369         struct cvmx_dpi_int_en_s              cn66xx;
1370         struct cvmx_dpi_int_en_cn63xx         cn68xx;
1371         struct cvmx_dpi_int_en_cn63xx         cn68xxp1;
1372         struct cvmx_dpi_int_en_s              cnf71xx;
1373 };
1374 typedef union cvmx_dpi_int_en cvmx_dpi_int_en_t;
1375
1376 /**
1377  * cvmx_dpi_int_reg
1378  */
1379 union cvmx_dpi_int_reg {
1380         uint64_t u64;
1381         struct cvmx_dpi_int_reg_s {
1382 #ifdef __BIG_ENDIAN_BITFIELD
1383         uint64_t reserved_28_63               : 36;
1384         uint64_t sprt3_rst                    : 1;  /**< DMA instruction was dropped because the source or
1385                                                           destination port was in reset.
1386                                                          this bit is set. */
1387         uint64_t sprt2_rst                    : 1;  /**< DMA instruction was dropped because the source or
1388                                                           destination port was in reset.
1389                                                          this bit is set. */
1390         uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
1391                                                           destination port was in reset.
1392                                                          this bit is set. */
1393         uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
1394                                                           destination port was in reset.
1395                                                          this bit is set. */
1396         uint64_t reserved_23_23               : 1;
1397         uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill
1398                                                          Instruction fill when none outstanding. */
1399         uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer
1400                                                          Next pointer was NULL. */
1401         uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction
1402                                                          Fetched instruction word was 0. */
1403         uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow
1404                                                          DPI tracks outstanding instructions fetches.
1405                                                          Interrupt will fire when FIFO underflows. */
1406         uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow
1407                                                          DPI tracks outstanding instructions fetches.
1408                                                          Interrupt will fire when FIFO overflows. */
1409         uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length
1410                                                          Interrupt will fire if DPI forms an instruction
1411                                                          fetch with length of zero. */
1412         uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer
1413                                                          Interrupt will fire if DPI forms an instruction
1414                                                          fetch to the NULL pointer. */
1415         uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow.
1416                                                          DPI has a 32-bit counter for each request's queue
1417                                                          outstanding doorbell counts. Interrupt will fire
1418                                                          if the count overflows. */
1419         uint64_t reserved_2_7                 : 6;
1420         uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow
1421                                                          DPI can store upto 16 CSR request.  The FIFO will
1422                                                          overflow if that number is exceeded. */
1423         uint64_t nderr                        : 1;  /**< NCB Decode Error
1424                                                          DPI received a NCB transaction on the outbound
1425                                                          bus to the DPI deviceID, but the command was not
1426                                                          recognized. */
1427 #else
1428         uint64_t nderr                        : 1;
1429         uint64_t nfovr                        : 1;
1430         uint64_t reserved_2_7                 : 6;
1431         uint64_t dmadbo                       : 8;
1432         uint64_t req_badadr                   : 1;
1433         uint64_t req_badlen                   : 1;
1434         uint64_t req_ovrflw                   : 1;
1435         uint64_t req_undflw                   : 1;
1436         uint64_t req_anull                    : 1;
1437         uint64_t req_inull                    : 1;
1438         uint64_t req_badfil                   : 1;
1439         uint64_t reserved_23_23               : 1;
1440         uint64_t sprt0_rst                    : 1;
1441         uint64_t sprt1_rst                    : 1;
1442         uint64_t sprt2_rst                    : 1;
1443         uint64_t sprt3_rst                    : 1;
1444         uint64_t reserved_28_63               : 36;
1445 #endif
1446         } s;
1447         struct cvmx_dpi_int_reg_s             cn61xx;
1448         struct cvmx_dpi_int_reg_cn63xx {
1449 #ifdef __BIG_ENDIAN_BITFIELD
1450         uint64_t reserved_26_63               : 38;
1451         uint64_t sprt1_rst                    : 1;  /**< DMA instruction was dropped because the source or
1452                                                           destination port was in reset.
1453                                                          this bit is set. */
1454         uint64_t sprt0_rst                    : 1;  /**< DMA instruction was dropped because the source or
1455                                                           destination port was in reset.
1456                                                          this bit is set. */
1457         uint64_t reserved_23_23               : 1;
1458         uint64_t req_badfil                   : 1;  /**< DMA instruction unexpected fill
1459                                                          Instruction fill when none outstanding. */
1460         uint64_t req_inull                    : 1;  /**< DMA instruction filled with NULL pointer
1461                                                          Next pointer was NULL. */
1462         uint64_t req_anull                    : 1;  /**< DMA instruction filled with bad instruction
1463                                                          Fetched instruction word was 0. */
1464         uint64_t req_undflw                   : 1;  /**< DMA instruction FIFO underflow
1465                                                          DPI tracks outstanding instructions fetches.
1466                                                          Interrupt will fire when FIFO underflows. */
1467         uint64_t req_ovrflw                   : 1;  /**< DMA instruction FIFO overflow
1468                                                          DPI tracks outstanding instructions fetches.
1469                                                          Interrupt will fire when FIFO overflows. */
1470         uint64_t req_badlen                   : 1;  /**< DMA instruction fetch with length
1471                                                          Interrupt will fire if DPI forms an instruction
1472                                                          fetch with length of zero. */
1473         uint64_t req_badadr                   : 1;  /**< DMA instruction fetch with bad pointer
1474                                                          Interrupt will fire if DPI forms an instruction
1475                                                          fetch to the NULL pointer. */
1476         uint64_t dmadbo                       : 8;  /**< DMAx doorbell overflow.
1477                                                          DPI has a 32-bit counter for each request's queue
1478                                                          outstanding doorbell counts. Interrupt will fire
1479                                                          if the count overflows. */
1480         uint64_t reserved_2_7                 : 6;
1481         uint64_t nfovr                        : 1;  /**< CSR Fifo Overflow
1482                                                          DPI can store upto 16 CSR request.  The FIFO will
1483                                                          overflow if that number is exceeded. */
1484         uint64_t nderr                        : 1;  /**< NCB Decode Error
1485                                                          DPI received a NCB transaction on the outbound
1486                                                          bus to the DPI deviceID, but the command was not
1487                                                          recognized. */
1488 #else
1489         uint64_t nderr                        : 1;
1490         uint64_t nfovr                        : 1;
1491         uint64_t reserved_2_7                 : 6;
1492         uint64_t dmadbo                       : 8;
1493         uint64_t req_badadr                   : 1;
1494         uint64_t req_badlen                   : 1;
1495         uint64_t req_ovrflw                   : 1;
1496         uint64_t req_undflw                   : 1;
1497         uint64_t req_anull                    : 1;
1498         uint64_t req_inull                    : 1;
1499         uint64_t req_badfil                   : 1;
1500         uint64_t reserved_23_23               : 1;
1501         uint64_t sprt0_rst                    : 1;
1502         uint64_t sprt1_rst                    : 1;
1503         uint64_t reserved_26_63               : 38;
1504 #endif
1505         } cn63xx;
1506         struct cvmx_dpi_int_reg_cn63xx        cn63xxp1;
1507         struct cvmx_dpi_int_reg_s             cn66xx;
1508         struct cvmx_dpi_int_reg_cn63xx        cn68xx;
1509         struct cvmx_dpi_int_reg_cn63xx        cn68xxp1;
1510         struct cvmx_dpi_int_reg_s             cnf71xx;
1511 };
1512 typedef union cvmx_dpi_int_reg cvmx_dpi_int_reg_t;
1513
1514 /**
1515  * cvmx_dpi_ncb#_cfg
1516  */
1517 union cvmx_dpi_ncbx_cfg {
1518         uint64_t u64;
1519         struct cvmx_dpi_ncbx_cfg_s {
1520 #ifdef __BIG_ENDIAN_BITFIELD
1521         uint64_t reserved_6_63                : 58;
1522         uint64_t molr                         : 6;  /**< Max Outstanding Load Requests
1523                                                          Limits the number of oustanding load requests on
1524                                                          the NCB interface.  This value can range from 1
1525                                                          to 32. Setting a value of 0 will halt all read
1526                                                          traffic to the NCB interface.  There are no
1527                                                          restrictions on when this value can be changed. */
1528 #else
1529         uint64_t molr                         : 6;
1530         uint64_t reserved_6_63                : 58;
1531 #endif
1532         } s;
1533         struct cvmx_dpi_ncbx_cfg_s            cn61xx;
1534         struct cvmx_dpi_ncbx_cfg_s            cn66xx;
1535         struct cvmx_dpi_ncbx_cfg_s            cn68xx;
1536         struct cvmx_dpi_ncbx_cfg_s            cnf71xx;
1537 };
1538 typedef union cvmx_dpi_ncbx_cfg cvmx_dpi_ncbx_cfg_t;
1539
1540 /**
1541  * cvmx_dpi_pint_info
1542  *
1543  * DPI_PINT_INFO = DPI Packet Interrupt Info
1544  *
1545  * DPI Packet Interrupt Info.
1546  */
1547 union cvmx_dpi_pint_info {
1548         uint64_t u64;
1549         struct cvmx_dpi_pint_info_s {
1550 #ifdef __BIG_ENDIAN_BITFIELD
1551         uint64_t reserved_14_63               : 50;
1552         uint64_t iinfo                        : 6;  /**< Packet Instruction Doorbell count overflow info */
1553         uint64_t reserved_6_7                 : 2;
1554         uint64_t sinfo                        : 6;  /**< Packet Scatterlist Doorbell count overflow info */
1555 #else
1556         uint64_t sinfo                        : 6;
1557         uint64_t reserved_6_7                 : 2;
1558         uint64_t iinfo                        : 6;
1559         uint64_t reserved_14_63               : 50;
1560 #endif
1561         } s;
1562         struct cvmx_dpi_pint_info_s           cn61xx;
1563         struct cvmx_dpi_pint_info_s           cn63xx;
1564         struct cvmx_dpi_pint_info_s           cn63xxp1;
1565         struct cvmx_dpi_pint_info_s           cn66xx;
1566         struct cvmx_dpi_pint_info_s           cn68xx;
1567         struct cvmx_dpi_pint_info_s           cn68xxp1;
1568         struct cvmx_dpi_pint_info_s           cnf71xx;
1569 };
1570 typedef union cvmx_dpi_pint_info cvmx_dpi_pint_info_t;
1571
1572 /**
1573  * cvmx_dpi_pkt_err_rsp
1574  */
1575 union cvmx_dpi_pkt_err_rsp {
1576         uint64_t u64;
1577         struct cvmx_dpi_pkt_err_rsp_s {
1578 #ifdef __BIG_ENDIAN_BITFIELD
1579         uint64_t reserved_1_63                : 63;
1580         uint64_t pkterr                       : 1;  /**< Indicates that an ErrorResponse was received from
1581                                                          the I/O subsystem. */
1582 #else
1583         uint64_t pkterr                       : 1;
1584         uint64_t reserved_1_63                : 63;
1585 #endif
1586         } s;
1587         struct cvmx_dpi_pkt_err_rsp_s         cn61xx;
1588         struct cvmx_dpi_pkt_err_rsp_s         cn63xx;
1589         struct cvmx_dpi_pkt_err_rsp_s         cn63xxp1;
1590         struct cvmx_dpi_pkt_err_rsp_s         cn66xx;
1591         struct cvmx_dpi_pkt_err_rsp_s         cn68xx;
1592         struct cvmx_dpi_pkt_err_rsp_s         cn68xxp1;
1593         struct cvmx_dpi_pkt_err_rsp_s         cnf71xx;
1594 };
1595 typedef union cvmx_dpi_pkt_err_rsp cvmx_dpi_pkt_err_rsp_t;
1596
1597 /**
1598  * cvmx_dpi_req_err_rsp
1599  */
1600 union cvmx_dpi_req_err_rsp {
1601         uint64_t u64;
1602         struct cvmx_dpi_req_err_rsp_s {
1603 #ifdef __BIG_ENDIAN_BITFIELD
1604         uint64_t reserved_8_63                : 56;
1605         uint64_t qerr                         : 8;  /**< Indicates which instruction queue received an
1606                                                          ErrorResponse from the I/O subsystem.
1607                                                          SW must clear the bit before the the cooresponding
1608                                                          instruction queue will continue processing
1609                                                          instructions if DPI_REQ_ERR_RSP_EN[EN] is set. */
1610 #else
1611         uint64_t qerr                         : 8;
1612         uint64_t reserved_8_63                : 56;
1613 #endif
1614         } s;
1615         struct cvmx_dpi_req_err_rsp_s         cn61xx;
1616         struct cvmx_dpi_req_err_rsp_s         cn63xx;
1617         struct cvmx_dpi_req_err_rsp_s         cn63xxp1;
1618         struct cvmx_dpi_req_err_rsp_s         cn66xx;
1619         struct cvmx_dpi_req_err_rsp_s         cn68xx;
1620         struct cvmx_dpi_req_err_rsp_s         cn68xxp1;
1621         struct cvmx_dpi_req_err_rsp_s         cnf71xx;
1622 };
1623 typedef union cvmx_dpi_req_err_rsp cvmx_dpi_req_err_rsp_t;
1624
1625 /**
1626  * cvmx_dpi_req_err_rsp_en
1627  */
1628 union cvmx_dpi_req_err_rsp_en {
1629         uint64_t u64;
1630         struct cvmx_dpi_req_err_rsp_en_s {
1631 #ifdef __BIG_ENDIAN_BITFIELD
1632         uint64_t reserved_8_63                : 56;
1633         uint64_t en                           : 8;  /**< Indicates which instruction queues should stop
1634                                                          dispatching instructions when an  ErrorResponse
1635                                                          is received from the I/O subsystem. */
1636 #else
1637         uint64_t en                           : 8;
1638         uint64_t reserved_8_63                : 56;
1639 #endif
1640         } s;
1641         struct cvmx_dpi_req_err_rsp_en_s      cn61xx;
1642         struct cvmx_dpi_req_err_rsp_en_s      cn63xx;
1643         struct cvmx_dpi_req_err_rsp_en_s      cn63xxp1;
1644         struct cvmx_dpi_req_err_rsp_en_s      cn66xx;
1645         struct cvmx_dpi_req_err_rsp_en_s      cn68xx;
1646         struct cvmx_dpi_req_err_rsp_en_s      cn68xxp1;
1647         struct cvmx_dpi_req_err_rsp_en_s      cnf71xx;
1648 };
1649 typedef union cvmx_dpi_req_err_rsp_en cvmx_dpi_req_err_rsp_en_t;
1650
1651 /**
1652  * cvmx_dpi_req_err_rst
1653  */
1654 union cvmx_dpi_req_err_rst {
1655         uint64_t u64;
1656         struct cvmx_dpi_req_err_rst_s {
1657 #ifdef __BIG_ENDIAN_BITFIELD
1658         uint64_t reserved_8_63                : 56;
1659         uint64_t qerr                         : 8;  /**< Indicates which instruction queue dropped an
1660                                                          instruction because the source or destination
1661                                                          was in reset.
1662                                                          SW must clear the bit before the the cooresponding
1663                                                          instruction queue will continue processing
1664                                                          instructions if DPI_REQ_ERR_RST_EN[EN] is set. */
1665 #else
1666         uint64_t qerr                         : 8;
1667         uint64_t reserved_8_63                : 56;
1668 #endif
1669         } s;
1670         struct cvmx_dpi_req_err_rst_s         cn61xx;
1671         struct cvmx_dpi_req_err_rst_s         cn63xx;
1672         struct cvmx_dpi_req_err_rst_s         cn63xxp1;
1673         struct cvmx_dpi_req_err_rst_s         cn66xx;
1674         struct cvmx_dpi_req_err_rst_s         cn68xx;
1675         struct cvmx_dpi_req_err_rst_s         cn68xxp1;
1676         struct cvmx_dpi_req_err_rst_s         cnf71xx;
1677 };
1678 typedef union cvmx_dpi_req_err_rst cvmx_dpi_req_err_rst_t;
1679
1680 /**
1681  * cvmx_dpi_req_err_rst_en
1682  */
1683 union cvmx_dpi_req_err_rst_en {
1684         uint64_t u64;
1685         struct cvmx_dpi_req_err_rst_en_s {
1686 #ifdef __BIG_ENDIAN_BITFIELD
1687         uint64_t reserved_8_63                : 56;
1688         uint64_t en                           : 8;  /**< Indicates which instruction queues should stop
1689                                                          dispatching instructions when an instruction
1690                                                          is dropped because the source or destination port
1691                                                          is in reset. */
1692 #else
1693         uint64_t en                           : 8;
1694         uint64_t reserved_8_63                : 56;
1695 #endif
1696         } s;
1697         struct cvmx_dpi_req_err_rst_en_s      cn61xx;
1698         struct cvmx_dpi_req_err_rst_en_s      cn63xx;
1699         struct cvmx_dpi_req_err_rst_en_s      cn63xxp1;
1700         struct cvmx_dpi_req_err_rst_en_s      cn66xx;
1701         struct cvmx_dpi_req_err_rst_en_s      cn68xx;
1702         struct cvmx_dpi_req_err_rst_en_s      cn68xxp1;
1703         struct cvmx_dpi_req_err_rst_en_s      cnf71xx;
1704 };
1705 typedef union cvmx_dpi_req_err_rst_en cvmx_dpi_req_err_rst_en_t;
1706
1707 /**
1708  * cvmx_dpi_req_err_skip_comp
1709  */
1710 union cvmx_dpi_req_err_skip_comp {
1711         uint64_t u64;
1712         struct cvmx_dpi_req_err_skip_comp_s {
1713 #ifdef __BIG_ENDIAN_BITFIELD
1714         uint64_t reserved_24_63               : 40;
1715         uint64_t en_rst                       : 8;  /**< Indicates which instruction queue should skip the
1716                                                          completion  phase once an port reset is
1717                                                          detected as indicated by DPI_REQ_ERR_RST.  All
1718                                                          completions to the effected instruction queue
1719                                                          will be skipped as long as
1720                                                          DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or
1721                                                          DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are
1722                                                          set. */
1723         uint64_t reserved_8_15                : 8;
1724         uint64_t en_rsp                       : 8;  /**< Indicates which instruction queue should skip the
1725                                                          completion  phase once an ErrorResponse is
1726                                                          detected as indicated by DPI_REQ_ERR_RSP.  All
1727                                                          completions to the effected instruction queue
1728                                                          will be skipped as long as
1729                                                          DPI_REQ_ERR_RSP[QERR<ique>] & EN_RSP<ique> or
1730                                                          DPI_REQ_ERR_RST[QERR<ique>] & EN_RST<ique> are
1731                                                          set. */
1732 #else
1733         uint64_t en_rsp                       : 8;
1734         uint64_t reserved_8_15                : 8;
1735         uint64_t en_rst                       : 8;
1736         uint64_t reserved_24_63               : 40;
1737 #endif
1738         } s;
1739         struct cvmx_dpi_req_err_skip_comp_s   cn61xx;
1740         struct cvmx_dpi_req_err_skip_comp_s   cn66xx;
1741         struct cvmx_dpi_req_err_skip_comp_s   cn68xx;
1742         struct cvmx_dpi_req_err_skip_comp_s   cn68xxp1;
1743         struct cvmx_dpi_req_err_skip_comp_s   cnf71xx;
1744 };
1745 typedef union cvmx_dpi_req_err_skip_comp cvmx_dpi_req_err_skip_comp_t;
1746
1747 /**
1748  * cvmx_dpi_req_gbl_en
1749  */
1750 union cvmx_dpi_req_gbl_en {
1751         uint64_t u64;
1752         struct cvmx_dpi_req_gbl_en_s {
1753 #ifdef __BIG_ENDIAN_BITFIELD
1754         uint64_t reserved_8_63                : 56;
1755         uint64_t qen                          : 8;  /**< Indicates which instruction queues are enabled and
1756                                                          can dispatch instructions to a requesting engine. */
1757 #else
1758         uint64_t qen                          : 8;
1759         uint64_t reserved_8_63                : 56;
1760 #endif
1761         } s;
1762         struct cvmx_dpi_req_gbl_en_s          cn61xx;
1763         struct cvmx_dpi_req_gbl_en_s          cn63xx;
1764         struct cvmx_dpi_req_gbl_en_s          cn63xxp1;
1765         struct cvmx_dpi_req_gbl_en_s          cn66xx;
1766         struct cvmx_dpi_req_gbl_en_s          cn68xx;
1767         struct cvmx_dpi_req_gbl_en_s          cn68xxp1;
1768         struct cvmx_dpi_req_gbl_en_s          cnf71xx;
1769 };
1770 typedef union cvmx_dpi_req_gbl_en cvmx_dpi_req_gbl_en_t;
1771
1772 /**
1773  * cvmx_dpi_sli_prt#_cfg
1774  *
1775  * DPI_SLI_PRTx_CFG = DPI SLI Port Configuration
1776  *
1777  * Configures the Max Read Request Size, Max Paylod Size, and Max Number of SLI Tags in use
1778  */
1779 union cvmx_dpi_sli_prtx_cfg {
1780         uint64_t u64;
1781         struct cvmx_dpi_sli_prtx_cfg_s {
1782 #ifdef __BIG_ENDIAN_BITFIELD
1783         uint64_t reserved_25_63               : 39;
1784         uint64_t halt                         : 1;  /**< When set, HALT indicates that the MAC has detected
1785                                                          a reset condition. No further instructions that
1786                                                          reference the MAC from any instruction Q will be
1787                                                          issued until the MAC comes out of reset and HALT
1788                                                          is cleared in SLI_CTL_PORTx[DIS_PORT]. */
1789         uint64_t qlm_cfg                      : 4;  /**< QLM_CFG is a function of MIO_QLMx_CFG[QLM_CFG]
1790                                                          QLM_CFG may contain values that are not normally
1791                                                          used for DMA and/or packet operations.
1792                                                          QLM_CFG does not indicate if a port is disabled.
1793                                                          MIO_QLMx_CFG can be used for more complete QLM
1794                                                          configuration information.
1795                                                          0000 = MAC is PCIe 1x4 (QLM) or 1x2 (DLM)
1796                                                          0001 = MAC is PCIe 2x1 (DLM only)
1797                                                          0010 = MAC is SGMII
1798                                                          0011 = MAC is XAUI
1799                                                          all other encodings are RESERVED */
1800         uint64_t reserved_17_19               : 3;
1801         uint64_t rd_mode                      : 1;  /**< Read Mode
1802                                                          0=Exact Read Mode
1803                                                            If the port is a PCIe port, the HW reads on a
1804                                                            4B granularity.  In this mode, the HW may break
1805                                                            a given read into 3 operations to satisify
1806                                                            PCIe rules.
1807                                                            If the port is a SRIO port, the HW follows the
1808                                                            SRIO read rules from the SRIO specification and
1809                                                             only issues 32*n, 16, and 8 byte  operations
1810                                                             on the SRIO bus.
1811                                                          1=Block Mode
1812                                                            The HW will read more data than requested in
1813                                                            order to minimize the number of operations
1814                                                            necessary to complete the operation.
1815                                                            The memory region must be memory like. */
1816         uint64_t reserved_14_15               : 2;
1817         uint64_t molr                         : 6;  /**< Max Outstanding Load Requests
1818                                                          Limits the number of oustanding load requests on
1819                                                          the port by restricting the number of tags
1820                                                          used by the SLI to track load responses.  This
1821                                                          value can range from 1 to 32 depending on the MAC
1822                                                          type and number of lanes.
1823                                                          MAC == PCIe:           Max is 32
1824                                                          MAC == sRio / 4 lanes: Max is 32
1825                                                          MAC == sRio / 2 lanes: Max is 16
1826                                                          MAC == sRio / 1 lane:  Max is  8
1827                                                          Reset value is computed based on the MAC config.
1828                                                          Setting MOLR to a value of 0 will halt all read
1829                                                          traffic to the port.  There are no restrictions
1830                                                          on when this value can be changed. */
1831         uint64_t mps_lim                      : 1;  /**< MAC memory space write requests cannot cross the
1832                                                          (naturally-aligned) MPS boundary.
1833                                                          When clear, DPI is allowed to issue a MAC memory
1834                                                          space read that crosses the naturally-aligned
1835                                                          boundary of size defined by MPS. (DPI will still
1836                                                          only cross the boundary when it would eliminate a
1837                                                          write by doing so.)
1838                                                          When set, DPI will never issue a MAC memory space
1839                                                          write that crosses the naturally-aligned boundary
1840                                                          of size defined by MPS. */
1841         uint64_t reserved_5_6                 : 2;
1842         uint64_t mps                          : 1;  /**< Max Payload Size
1843                                                                  0 = 128B
1844                                                                  1 = 256B
1845                                                          For PCIe MACs, this MPS size must not exceed
1846                                                                the size selected by PCIE*_CFG030[MPS].
1847                                                          For sRIO MACs, all MPS values are allowed. */
1848         uint64_t mrrs_lim                     : 1;  /**< MAC memory space read requests cannot cross the
1849                                                          (naturally-aligned) MRRS boundary.
1850                                                          When clear, DPI is allowed to issue a MAC memory
1851                                                          space read that crosses the naturally-aligned
1852                                                          boundary of size defined by MRRS. (DPI will still
1853                                                          only cross the boundary when it would eliminate a
1854                                                          read by doing so.)
1855                                                          When set, DPI will never issue a MAC memory space
1856                                                          read that crosses the naturally-aligned boundary
1857                                                          of size defined by MRRS. */
1858         uint64_t reserved_2_2                 : 1;
1859         uint64_t mrrs                         : 2;  /**< Max Read Request Size
1860                                                                  0 = 128B
1861                                                                  1 = 256B
1862                                                                  2 = 512B
1863                                                                  3 = 1024B
1864                                                          For PCIe MACs, this MRRS size must not exceed
1865                                                                the size selected by PCIE*_CFG030[MRRS].
1866                                                          For sRIO MACs, this MRRS size must be <= 256B. */
1867 #else
1868         uint64_t mrrs                         : 2;
1869         uint64_t reserved_2_2                 : 1;
1870         uint64_t mrrs_lim                     : 1;
1871         uint64_t mps                          : 1;
1872         uint64_t reserved_5_6                 : 2;
1873         uint64_t mps_lim                      : 1;
1874         uint64_t molr                         : 6;
1875         uint64_t reserved_14_15               : 2;
1876         uint64_t rd_mode                      : 1;
1877         uint64_t reserved_17_19               : 3;
1878         uint64_t qlm_cfg                      : 4;
1879         uint64_t halt                         : 1;
1880         uint64_t reserved_25_63               : 39;
1881 #endif
1882         } s;
1883         struct cvmx_dpi_sli_prtx_cfg_s        cn61xx;
1884         struct cvmx_dpi_sli_prtx_cfg_cn63xx {
1885 #ifdef __BIG_ENDIAN_BITFIELD
1886         uint64_t reserved_25_63               : 39;
1887         uint64_t halt                         : 1;  /**< When set, HALT indicates that the MAC has detected
1888                                                          a reset condition. No further instructions that
1889                                                          reference the MAC from any instruction Q will be
1890                                                          issued until the MAC comes out of reset and HALT
1891                                                          is cleared in SLI_CTL_PORTx[DIS_PORT]. */
1892         uint64_t reserved_21_23               : 3;
1893         uint64_t qlm_cfg                      : 1;  /**< Read only copy of the QLM CFG pin
1894                                                          Since QLM_CFG is simply a copy of the QLM CFG
1895                                                          pins, it may reflect values that are not normal
1896                                                          for DMA or packet operations. QLM_CFG does not
1897                                                          indicate if a port is disabled.
1898                                                          0= MAC is PCIe
1899                                                          1= MAC is SRIO */
1900         uint64_t reserved_17_19               : 3;
1901         uint64_t rd_mode                      : 1;  /**< Read Mode
1902                                                          0=Exact Read Mode
1903                                                            If the port is a PCIe port, the HW reads on a
1904                                                            4B granularity.  In this mode, the HW may break
1905                                                            a given read into 3 operations to satisify
1906                                                            PCIe rules.
1907                                                            If the port is a SRIO port, the HW follows the
1908                                                            SRIO read rules from the SRIO specification and
1909                                                             only issues 32*n, 16, and 8 byte  operations
1910                                                             on the SRIO bus.
1911                                                          1=Block Mode
1912                                                            The HW will read more data than requested in
1913                                                            order to minimize the number of operations
1914                                                            necessary to complete the operation.
1915                                                            The memory region must be memory like. */
1916         uint64_t reserved_14_15               : 2;
1917         uint64_t molr                         : 6;  /**< Max Outstanding Load Requests
1918                                                          Limits the number of oustanding load requests on
1919                                                          the port by restricting the number of tags
1920                                                          used by the SLI to track load responses.  This
1921                                                          value can range from 1 to 32. Setting a value of
1922                                                          0 will halt all read traffic to the port.  There
1923                                                          are no restrictions on when this value
1924                                                          can be changed. */
1925         uint64_t mps_lim                      : 1;  /**< MAC memory space write requests cannot cross the
1926                                                          (naturally-aligned) MPS boundary.
1927                                                          When clear, DPI is allowed to issue a MAC memory
1928                                                          space read that crosses the naturally-aligned
1929                                                          boundary of size defined by MPS. (DPI will still
1930                                                          only cross the boundary when it would eliminate a
1931                                                          write by doing so.)
1932                                                          When set, DPI will never issue a MAC memory space
1933                                                          write that crosses the naturally-aligned boundary
1934                                                          of size defined by MPS. */
1935         uint64_t reserved_5_6                 : 2;
1936         uint64_t mps                          : 1;  /**< Max Payload Size
1937                                                                  0 = 128B
1938                                                                  1 = 256B
1939                                                          For PCIe MACs, this MPS size must not exceed
1940                                                                the size selected by PCIE*_CFG030[MPS].
1941                                                          For sRIO MACs, all MPS values are allowed. */
1942         uint64_t mrrs_lim                     : 1;  /**< MAC memory space read requests cannot cross the
1943                                                          (naturally-aligned) MRRS boundary.
1944                                                          When clear, DPI is allowed to issue a MAC memory
1945                                                          space read that crosses the naturally-aligned
1946                                                          boundary of size defined by MRRS. (DPI will still
1947                                                          only cross the boundary when it would eliminate a
1948                                                          read by doing so.)
1949                                                          When set, DPI will never issue a MAC memory space
1950                                                          read that crosses the naturally-aligned boundary
1951                                                          of size defined by MRRS. */
1952         uint64_t reserved_2_2                 : 1;
1953         uint64_t mrrs                         : 2;  /**< Max Read Request Size
1954                                                                  0 = 128B
1955                                                                  1 = 256B
1956                                                                  2 = 512B
1957                                                                  3 = 1024B
1958                                                          For PCIe MACs, this MRRS size must not exceed
1959                                                                the size selected by PCIE*_CFG030[MRRS].
1960                                                          For sRIO MACs, this MRRS size must be <= 256B. */
1961 #else
1962         uint64_t mrrs                         : 2;
1963         uint64_t reserved_2_2                 : 1;
1964         uint64_t mrrs_lim                     : 1;
1965         uint64_t mps                          : 1;
1966         uint64_t reserved_5_6                 : 2;
1967         uint64_t mps_lim                      : 1;
1968         uint64_t molr                         : 6;
1969         uint64_t reserved_14_15               : 2;
1970         uint64_t rd_mode                      : 1;
1971         uint64_t reserved_17_19               : 3;
1972         uint64_t qlm_cfg                      : 1;
1973         uint64_t reserved_21_23               : 3;
1974         uint64_t halt                         : 1;
1975         uint64_t reserved_25_63               : 39;
1976 #endif
1977         } cn63xx;
1978         struct cvmx_dpi_sli_prtx_cfg_cn63xx   cn63xxp1;
1979         struct cvmx_dpi_sli_prtx_cfg_s        cn66xx;
1980         struct cvmx_dpi_sli_prtx_cfg_cn63xx   cn68xx;
1981         struct cvmx_dpi_sli_prtx_cfg_cn63xx   cn68xxp1;
1982         struct cvmx_dpi_sli_prtx_cfg_s        cnf71xx;
1983 };
1984 typedef union cvmx_dpi_sli_prtx_cfg cvmx_dpi_sli_prtx_cfg_t;
1985
1986 /**
1987  * cvmx_dpi_sli_prt#_err
1988  *
1989  * DPI_SLI_PRTx_ERR = DPI SLI Port Error Info
1990  *
1991  * Logs the Address and Request Queue associated with the reported SLI error response
1992  */
1993 union cvmx_dpi_sli_prtx_err {
1994         uint64_t u64;
1995         struct cvmx_dpi_sli_prtx_err_s {
1996 #ifdef __BIG_ENDIAN_BITFIELD
1997         uint64_t addr                         : 61; /**< Address of the failed load request.
1998                                                          Address is locked along with the
1999                                                          DPI_SLI_PRTx_ERR_INFO register.
2000                                                          See the DPI_SLI_PRTx_ERR_INFO[LOCK] description
2001                                                          for further information. */
2002         uint64_t reserved_0_2                 : 3;
2003 #else
2004         uint64_t reserved_0_2                 : 3;
2005         uint64_t addr                         : 61;
2006 #endif
2007         } s;
2008         struct cvmx_dpi_sli_prtx_err_s        cn61xx;
2009         struct cvmx_dpi_sli_prtx_err_s        cn63xx;
2010         struct cvmx_dpi_sli_prtx_err_s        cn63xxp1;
2011         struct cvmx_dpi_sli_prtx_err_s        cn66xx;
2012         struct cvmx_dpi_sli_prtx_err_s        cn68xx;
2013         struct cvmx_dpi_sli_prtx_err_s        cn68xxp1;
2014         struct cvmx_dpi_sli_prtx_err_s        cnf71xx;
2015 };
2016 typedef union cvmx_dpi_sli_prtx_err cvmx_dpi_sli_prtx_err_t;
2017
2018 /**
2019  * cvmx_dpi_sli_prt#_err_info
2020  *
2021  * DPI_SLI_PRTx_ERR_INFO = DPI SLI Port Error Info
2022  *
2023  * Logs the Address and Request Queue associated with the reported SLI error response
2024  */
2025 union cvmx_dpi_sli_prtx_err_info {
2026         uint64_t u64;
2027         struct cvmx_dpi_sli_prtx_err_info_s {
2028 #ifdef __BIG_ENDIAN_BITFIELD
2029         uint64_t reserved_9_63                : 55;
2030         uint64_t lock                         : 1;  /**< DPI_SLI_PRTx_ERR and DPI_SLI_PRTx_ERR_INFO have
2031                                                          captured and locked contents.
2032                                                          When Octeon first detects an ErrorResponse, the
2033                                                          TYPE, REQQ, and ADDR of the error is saved and an
2034                                                          internal lock state is set so the data associated
2035                                                          with the initial error is perserved.
2036                                                          Subsequent ErrorResponses will optionally raise
2037                                                          an interrupt, but will not modify the TYPE, REQQ,
2038                                                          or ADDR fields until the internal lock state is
2039                                                          cleared.
2040                                                          SW can clear the internal lock state by writting
2041                                                          a '1' to the appropriate bit in either
2042                                                          DPI_REQ_ERR_RSP or DPI_PKT_ERR_RSP depending on
2043                                                          the TYPE field.
2044                                                          Once the internal lock state is cleared,
2045                                                          the next ErrorResponse will set the TYPE, REQQ,
2046                                                          and ADDR for the new transaction. */
2047         uint64_t reserved_5_7                 : 3;
2048         uint64_t type                         : 1;  /**< Type of transaction that caused the ErrorResponse.
2049                                                          0=DMA Instruction
2050                                                          1=PKT Instruction */
2051         uint64_t reserved_3_3                 : 1;
2052         uint64_t reqq                         : 3;  /**< Request queue that made the failed load request. */
2053 #else
2054         uint64_t reqq                         : 3;
2055         uint64_t reserved_3_3                 : 1;
2056         uint64_t type                         : 1;
2057         uint64_t reserved_5_7                 : 3;
2058         uint64_t lock                         : 1;
2059         uint64_t reserved_9_63                : 55;
2060 #endif
2061         } s;
2062         struct cvmx_dpi_sli_prtx_err_info_s   cn61xx;
2063         struct cvmx_dpi_sli_prtx_err_info_s   cn63xx;
2064         struct cvmx_dpi_sli_prtx_err_info_s   cn63xxp1;
2065         struct cvmx_dpi_sli_prtx_err_info_s   cn66xx;
2066         struct cvmx_dpi_sli_prtx_err_info_s   cn68xx;
2067         struct cvmx_dpi_sli_prtx_err_info_s   cn68xxp1;
2068         struct cvmx_dpi_sli_prtx_err_info_s   cnf71xx;
2069 };
2070 typedef union cvmx_dpi_sli_prtx_err_info cvmx_dpi_sli_prtx_err_info_t;
2071
2072 #endif