1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Inc. nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Automatically generated error messages for cn63xx.
46 * This file is auto generated. Do not edit.
50 * <hr><h2>Error tree for CN63XX</h2>
55 * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
56 * edge [fontsize=7, font=helvitica];
57 * cvmx_root [label="ROOT|<root>root"];
58 * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
59 * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
60 * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
61 * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
62 * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
63 * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
64 * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
65 * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
66 * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
67 * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
68 * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
69 * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
70 * cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
71 * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
72 * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
73 * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
74 * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
75 * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
76 * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
77 * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
78 * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
79 * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
80 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
81 * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
82 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
83 * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
84 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
85 * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
86 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
87 * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
88 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
89 * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
90 * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
91 * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
92 * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
93 * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
94 * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
95 * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
96 * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
97 * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
98 * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
99 * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
100 * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
101 * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7"];
102 * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
103 * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
104 * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
105 * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
106 * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
107 * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
108 * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
109 * cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
110 * cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
111 * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
112 * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
113 * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
114 * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
115 * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
116 * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
117 * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
118 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
119 * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
120 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
121 * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
122 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
123 * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
124 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
125 * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
126 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
127 * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
128 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
129 * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
130 * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
131 * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
132 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
133 * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
134 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
135 * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
136 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
137 * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
138 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
139 * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
140 * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
141 * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
142 * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
143 * cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
144 * cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
145 * cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
146 * cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
147 * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
148 * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
149 * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
150 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
151 * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
152 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
153 * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
154 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
155 * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
156 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
157 * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
158 * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
159 * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
160 * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
161 * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
162 * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
163 * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
164 * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
165 * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
166 * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
167 * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
168 * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
169 * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
170 * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
171 * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
172 * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
173 * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
177 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
178 #include <asm/octeon/cvmx.h>
179 #include <asm/octeon/cvmx-error.h>
180 #include <asm/octeon/cvmx-error-custom.h>
181 #include <asm/octeon/cvmx-csr-typedefs.h>
184 #include "cvmx-error.h"
185 #include "cvmx-error-custom.h"
188 int cvmx_error_initialize_cn63xx(void);
190 int cvmx_error_initialize_cn63xx(void)
192 cvmx_error_info_t info;
195 /* CVMX_CIU_INTX_SUM0(0) */
196 info.reg_type = CVMX_ERROR_REGISTER_IO64;
197 info.status_addr = CVMX_CIU_INTX_SUM0(0);
198 info.status_mask = 0;
199 info.enable_addr = 0;
200 info.enable_mask = 0;
202 info.group = CVMX_ERROR_GROUP_INTERNAL;
203 info.group_index = 0;
204 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
205 info.parent.status_addr = 0;
206 info.parent.status_mask = 0;
207 info.func = __cvmx_error_decode;
209 fail |= cvmx_error_add(&info);
211 /* CVMX_MIXX_ISR(0) */
212 info.reg_type = CVMX_ERROR_REGISTER_IO64;
213 info.status_addr = CVMX_MIXX_ISR(0);
214 info.status_mask = 1ull<<0 /* odblovf */;
215 info.enable_addr = CVMX_MIXX_INTENA(0);
216 info.enable_mask = 1ull<<0 /* ovfena */;
218 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
219 info.group_index = 0;
220 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
221 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
222 info.parent.status_mask = 1ull<<62 /* mii */;
223 info.func = __cvmx_error_display;
224 info.user_info = (long)
225 "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
226 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
227 " with a value greater than the remaining #of\n"
228 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
229 " the following occurs:\n"
230 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
231 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
232 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
233 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
234 " and the local interrupt mask bit(OVFENA) is set, than an\n"
235 " interrupt is reported for this event.\n"
236 " SW should keep track of the #I-Ring Entries in use\n"
237 " (ie: cumulative # of ODBELL writes), and ensure that\n"
238 " future ODBELL writes don't exceed the size of the\n"
239 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
240 " SW must reclaim O-Ring Entries by writing to the\n"
241 " MIX_ORCNT[ORCNT]. .\n"
242 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
243 " If it occurs, it's an indication that SW has\n"
244 " overwritten the O-Ring buffer, and the only recourse\n"
246 fail |= cvmx_error_add(&info);
248 info.reg_type = CVMX_ERROR_REGISTER_IO64;
249 info.status_addr = CVMX_MIXX_ISR(0);
250 info.status_mask = 1ull<<1 /* idblovf */;
251 info.enable_addr = CVMX_MIXX_INTENA(0);
252 info.enable_mask = 1ull<<1 /* ivfena */;
254 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
255 info.group_index = 0;
256 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
257 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
258 info.parent.status_mask = 1ull<<62 /* mii */;
259 info.func = __cvmx_error_display;
260 info.user_info = (long)
261 "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
262 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
263 " with a value greater than the remaining #of\n"
264 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
265 " the following occurs:\n"
266 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
267 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
268 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
269 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
270 " and the local interrupt mask bit(IVFENA) is set, than an\n"
271 " interrupt is reported for this event.\n"
272 " SW should keep track of the #I-Ring Entries in use\n"
273 " (ie: cumulative # of IDBELL writes), and ensure that\n"
274 " future IDBELL writes don't exceed the size of the\n"
275 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
276 " SW must reclaim I-Ring Entries by keeping track of the\n"
277 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
278 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
279 " total #packets(not IRing Entries) and SW must further\n"
280 " keep track of the # of I-Ring Entries associated with\n"
281 " each packet as they are processed.\n"
282 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
283 " If it occurs, it's an indication that SW has\n"
284 " overwritten the I-Ring buffer, and the only recourse\n"
286 fail |= cvmx_error_add(&info);
288 info.reg_type = CVMX_ERROR_REGISTER_IO64;
289 info.status_addr = CVMX_MIXX_ISR(0);
290 info.status_mask = 1ull<<4 /* data_drp */;
291 info.enable_addr = CVMX_MIXX_INTENA(0);
292 info.enable_mask = 1ull<<4 /* data_drpena */;
294 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
295 info.group_index = 0;
296 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
297 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
298 info.parent.status_mask = 1ull<<62 /* mii */;
299 info.func = __cvmx_error_display;
300 info.user_info = (long)
301 "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
302 " If this does occur, the DATA_DRP is set and the\n"
303 " CIU_INTx_SUM0,4[MII] bits are set.\n"
304 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
305 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
306 " interrupt is reported for this event.\n";
307 fail |= cvmx_error_add(&info);
309 info.reg_type = CVMX_ERROR_REGISTER_IO64;
310 info.status_addr = CVMX_MIXX_ISR(0);
311 info.status_mask = 1ull<<5 /* irun */;
312 info.enable_addr = CVMX_MIXX_INTENA(0);
313 info.enable_mask = 1ull<<5 /* irunena */;
315 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
316 info.group_index = 0;
317 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
318 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
319 info.parent.status_mask = 1ull<<62 /* mii */;
320 info.func = __cvmx_error_display;
321 info.user_info = (long)
322 "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
323 " If SW writes a larger value than what is currently\n"
324 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
325 " underflow condition.\n"
326 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
327 " NOTE: If an IRUN underflow condition is detected,\n"
328 " the integrity of the MIX/AGL HW state has\n"
329 " been compromised. To recover, SW must issue a\n"
330 " software reset sequence (see: MIX_CTL[RESET]\n";
331 fail |= cvmx_error_add(&info);
333 info.reg_type = CVMX_ERROR_REGISTER_IO64;
334 info.status_addr = CVMX_MIXX_ISR(0);
335 info.status_mask = 1ull<<6 /* orun */;
336 info.enable_addr = CVMX_MIXX_INTENA(0);
337 info.enable_mask = 1ull<<6 /* orunena */;
339 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
340 info.group_index = 0;
341 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
342 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
343 info.parent.status_mask = 1ull<<62 /* mii */;
344 info.func = __cvmx_error_display;
345 info.user_info = (long)
346 "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
347 " If SW writes a larger value than what is currently\n"
348 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
349 " underflow condition.\n"
350 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
351 " NOTE: If an ORUN underflow condition is detected,\n"
352 " the integrity of the MIX/AGL HW state has\n"
353 " been compromised. To recover, SW must issue a\n"
354 " software reset sequence (see: MIX_CTL[RESET]\n";
355 fail |= cvmx_error_add(&info);
357 /* CVMX_CIU_INT_SUM1 */
358 info.reg_type = CVMX_ERROR_REGISTER_IO64;
359 info.status_addr = CVMX_CIU_INT_SUM1;
360 info.status_mask = 0;
361 info.enable_addr = 0;
362 info.enable_mask = 0;
364 info.group = CVMX_ERROR_GROUP_INTERNAL;
365 info.group_index = 0;
366 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
367 info.parent.status_addr = 0;
368 info.parent.status_mask = 0;
369 info.func = __cvmx_error_decode;
371 fail |= cvmx_error_add(&info);
373 /* CVMX_MIXX_ISR(1) */
374 info.reg_type = CVMX_ERROR_REGISTER_IO64;
375 info.status_addr = CVMX_MIXX_ISR(1);
376 info.status_mask = 1ull<<0 /* odblovf */;
377 info.enable_addr = CVMX_MIXX_INTENA(1);
378 info.enable_mask = 1ull<<0 /* ovfena */;
380 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
381 info.group_index = 1;
382 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
383 info.parent.status_addr = CVMX_CIU_INT_SUM1;
384 info.parent.status_mask = 1ull<<18 /* mii1 */;
385 info.func = __cvmx_error_display;
386 info.user_info = (long)
387 "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
388 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
389 " with a value greater than the remaining #of\n"
390 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
391 " the following occurs:\n"
392 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
393 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
394 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
395 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
396 " and the local interrupt mask bit(OVFENA) is set, than an\n"
397 " interrupt is reported for this event.\n"
398 " SW should keep track of the #I-Ring Entries in use\n"
399 " (ie: cumulative # of ODBELL writes), and ensure that\n"
400 " future ODBELL writes don't exceed the size of the\n"
401 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
402 " SW must reclaim O-Ring Entries by writing to the\n"
403 " MIX_ORCNT[ORCNT]. .\n"
404 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
405 " If it occurs, it's an indication that SW has\n"
406 " overwritten the O-Ring buffer, and the only recourse\n"
408 fail |= cvmx_error_add(&info);
410 info.reg_type = CVMX_ERROR_REGISTER_IO64;
411 info.status_addr = CVMX_MIXX_ISR(1);
412 info.status_mask = 1ull<<1 /* idblovf */;
413 info.enable_addr = CVMX_MIXX_INTENA(1);
414 info.enable_mask = 1ull<<1 /* ivfena */;
416 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
417 info.group_index = 1;
418 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
419 info.parent.status_addr = CVMX_CIU_INT_SUM1;
420 info.parent.status_mask = 1ull<<18 /* mii1 */;
421 info.func = __cvmx_error_display;
422 info.user_info = (long)
423 "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
424 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
425 " with a value greater than the remaining #of\n"
426 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
427 " the following occurs:\n"
428 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
429 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
430 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
431 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
432 " and the local interrupt mask bit(IVFENA) is set, than an\n"
433 " interrupt is reported for this event.\n"
434 " SW should keep track of the #I-Ring Entries in use\n"
435 " (ie: cumulative # of IDBELL writes), and ensure that\n"
436 " future IDBELL writes don't exceed the size of the\n"
437 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
438 " SW must reclaim I-Ring Entries by keeping track of the\n"
439 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
440 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
441 " total #packets(not IRing Entries) and SW must further\n"
442 " keep track of the # of I-Ring Entries associated with\n"
443 " each packet as they are processed.\n"
444 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
445 " If it occurs, it's an indication that SW has\n"
446 " overwritten the I-Ring buffer, and the only recourse\n"
448 fail |= cvmx_error_add(&info);
450 info.reg_type = CVMX_ERROR_REGISTER_IO64;
451 info.status_addr = CVMX_MIXX_ISR(1);
452 info.status_mask = 1ull<<4 /* data_drp */;
453 info.enable_addr = CVMX_MIXX_INTENA(1);
454 info.enable_mask = 1ull<<4 /* data_drpena */;
456 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
457 info.group_index = 1;
458 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
459 info.parent.status_addr = CVMX_CIU_INT_SUM1;
460 info.parent.status_mask = 1ull<<18 /* mii1 */;
461 info.func = __cvmx_error_display;
462 info.user_info = (long)
463 "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
464 " If this does occur, the DATA_DRP is set and the\n"
465 " CIU_INTx_SUM0,4[MII] bits are set.\n"
466 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
467 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
468 " interrupt is reported for this event.\n";
469 fail |= cvmx_error_add(&info);
471 info.reg_type = CVMX_ERROR_REGISTER_IO64;
472 info.status_addr = CVMX_MIXX_ISR(1);
473 info.status_mask = 1ull<<5 /* irun */;
474 info.enable_addr = CVMX_MIXX_INTENA(1);
475 info.enable_mask = 1ull<<5 /* irunena */;
477 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
478 info.group_index = 1;
479 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
480 info.parent.status_addr = CVMX_CIU_INT_SUM1;
481 info.parent.status_mask = 1ull<<18 /* mii1 */;
482 info.func = __cvmx_error_display;
483 info.user_info = (long)
484 "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
485 " If SW writes a larger value than what is currently\n"
486 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
487 " underflow condition.\n"
488 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
489 " NOTE: If an IRUN underflow condition is detected,\n"
490 " the integrity of the MIX/AGL HW state has\n"
491 " been compromised. To recover, SW must issue a\n"
492 " software reset sequence (see: MIX_CTL[RESET]\n";
493 fail |= cvmx_error_add(&info);
495 info.reg_type = CVMX_ERROR_REGISTER_IO64;
496 info.status_addr = CVMX_MIXX_ISR(1);
497 info.status_mask = 1ull<<6 /* orun */;
498 info.enable_addr = CVMX_MIXX_INTENA(1);
499 info.enable_mask = 1ull<<6 /* orunena */;
501 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
502 info.group_index = 1;
503 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
504 info.parent.status_addr = CVMX_CIU_INT_SUM1;
505 info.parent.status_mask = 1ull<<18 /* mii1 */;
506 info.func = __cvmx_error_display;
507 info.user_info = (long)
508 "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
509 " If SW writes a larger value than what is currently\n"
510 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
511 " underflow condition.\n"
512 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
513 " NOTE: If an ORUN underflow condition is detected,\n"
514 " the integrity of the MIX/AGL HW state has\n"
515 " been compromised. To recover, SW must issue a\n"
516 " software reset sequence (see: MIX_CTL[RESET]\n";
517 fail |= cvmx_error_add(&info);
520 info.reg_type = CVMX_ERROR_REGISTER_IO64;
521 info.status_addr = CVMX_NDF_INT;
522 info.status_mask = 1ull<<2 /* wdog */;
523 info.enable_addr = CVMX_NDF_INT_EN;
524 info.enable_mask = 1ull<<2 /* wdog */;
526 info.group = CVMX_ERROR_GROUP_INTERNAL;
527 info.group_index = 0;
528 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
529 info.parent.status_addr = CVMX_CIU_INT_SUM1;
530 info.parent.status_mask = 1ull<<19 /* nand */;
531 info.func = __cvmx_error_display;
532 info.user_info = (long)
533 "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
534 fail |= cvmx_error_add(&info);
536 info.reg_type = CVMX_ERROR_REGISTER_IO64;
537 info.status_addr = CVMX_NDF_INT;
538 info.status_mask = 1ull<<3 /* sm_bad */;
539 info.enable_addr = CVMX_NDF_INT_EN;
540 info.enable_mask = 1ull<<3 /* sm_bad */;
542 info.group = CVMX_ERROR_GROUP_INTERNAL;
543 info.group_index = 0;
544 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
545 info.parent.status_addr = CVMX_CIU_INT_SUM1;
546 info.parent.status_mask = 1ull<<19 /* nand */;
547 info.func = __cvmx_error_display;
548 info.user_info = (long)
549 "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
550 fail |= cvmx_error_add(&info);
552 info.reg_type = CVMX_ERROR_REGISTER_IO64;
553 info.status_addr = CVMX_NDF_INT;
554 info.status_mask = 1ull<<4 /* ecc_1bit */;
555 info.enable_addr = CVMX_NDF_INT_EN;
556 info.enable_mask = 1ull<<4 /* ecc_1bit */;
558 info.group = CVMX_ERROR_GROUP_INTERNAL;
559 info.group_index = 0;
560 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
561 info.parent.status_addr = CVMX_CIU_INT_SUM1;
562 info.parent.status_mask = 1ull<<19 /* nand */;
563 info.func = __cvmx_error_display;
564 info.user_info = (long)
565 "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
566 fail |= cvmx_error_add(&info);
568 info.reg_type = CVMX_ERROR_REGISTER_IO64;
569 info.status_addr = CVMX_NDF_INT;
570 info.status_mask = 1ull<<5 /* ecc_mult */;
571 info.enable_addr = CVMX_NDF_INT_EN;
572 info.enable_mask = 1ull<<5 /* ecc_mult */;
574 info.group = CVMX_ERROR_GROUP_INTERNAL;
575 info.group_index = 0;
576 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
577 info.parent.status_addr = CVMX_CIU_INT_SUM1;
578 info.parent.status_mask = 1ull<<19 /* nand */;
579 info.func = __cvmx_error_display;
580 info.user_info = (long)
581 "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
582 fail |= cvmx_error_add(&info);
584 info.reg_type = CVMX_ERROR_REGISTER_IO64;
585 info.status_addr = CVMX_NDF_INT;
586 info.status_mask = 1ull<<6 /* ovrf */;
587 info.enable_addr = CVMX_NDF_INT_EN;
588 info.enable_mask = 1ull<<6 /* ovrf */;
590 info.group = CVMX_ERROR_GROUP_INTERNAL;
591 info.group_index = 0;
592 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
593 info.parent.status_addr = CVMX_CIU_INT_SUM1;
594 info.parent.status_mask = 1ull<<19 /* nand */;
595 info.func = __cvmx_error_display;
596 info.user_info = (long)
597 "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
599 fail |= cvmx_error_add(&info);
601 /* CVMX_CIU_BLOCK_INT */
602 info.reg_type = CVMX_ERROR_REGISTER_IO64;
603 info.status_addr = CVMX_CIU_BLOCK_INT;
604 info.status_mask = 0;
605 info.enable_addr = 0;
606 info.enable_mask = 0;
608 info.group = CVMX_ERROR_GROUP_INTERNAL;
609 info.group_index = 0;
610 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
611 info.parent.status_addr = 0;
612 info.parent.status_mask = 0;
613 info.func = __cvmx_error_decode;
615 fail |= cvmx_error_add(&info);
617 /* CVMX_L2C_INT_REG */
618 info.reg_type = CVMX_ERROR_REGISTER_IO64;
619 info.status_addr = CVMX_L2C_INT_REG;
620 info.status_mask = 1ull<<0 /* holerd */;
621 info.enable_addr = CVMX_L2C_INT_ENA;
622 info.enable_mask = 1ull<<0 /* holerd */;
624 info.group = CVMX_ERROR_GROUP_INTERNAL;
625 info.group_index = 0;
626 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
627 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
628 info.parent.status_mask = 1ull<<16 /* l2c */;
629 info.func = __cvmx_error_display;
630 info.user_info = (long)
631 "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
632 fail |= cvmx_error_add(&info);
634 info.reg_type = CVMX_ERROR_REGISTER_IO64;
635 info.status_addr = CVMX_L2C_INT_REG;
636 info.status_mask = 1ull<<1 /* holewr */;
637 info.enable_addr = CVMX_L2C_INT_ENA;
638 info.enable_mask = 1ull<<1 /* holewr */;
640 info.group = CVMX_ERROR_GROUP_INTERNAL;
641 info.group_index = 0;
642 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
643 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
644 info.parent.status_mask = 1ull<<16 /* l2c */;
645 info.func = __cvmx_error_display;
646 info.user_info = (long)
647 "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
648 fail |= cvmx_error_add(&info);
650 info.reg_type = CVMX_ERROR_REGISTER_IO64;
651 info.status_addr = CVMX_L2C_INT_REG;
652 info.status_mask = 1ull<<2 /* vrtwr */;
653 info.enable_addr = CVMX_L2C_INT_ENA;
654 info.enable_mask = 1ull<<2 /* vrtwr */;
656 info.group = CVMX_ERROR_GROUP_INTERNAL;
657 info.group_index = 0;
658 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
659 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
660 info.parent.status_mask = 1ull<<16 /* l2c */;
661 info.func = __cvmx_error_display;
662 info.user_info = (long)
663 "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
664 " Set when L2C_VRT_MEM blocked a store.\n";
665 fail |= cvmx_error_add(&info);
667 info.reg_type = CVMX_ERROR_REGISTER_IO64;
668 info.status_addr = CVMX_L2C_INT_REG;
669 info.status_mask = 1ull<<3 /* vrtidrng */;
670 info.enable_addr = CVMX_L2C_INT_ENA;
671 info.enable_mask = 1ull<<3 /* vrtidrng */;
673 info.group = CVMX_ERROR_GROUP_INTERNAL;
674 info.group_index = 0;
675 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
676 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
677 info.parent.status_mask = 1ull<<16 /* l2c */;
678 info.func = __cvmx_error_display;
679 info.user_info = (long)
680 "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
681 " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
683 fail |= cvmx_error_add(&info);
685 info.reg_type = CVMX_ERROR_REGISTER_IO64;
686 info.status_addr = CVMX_L2C_INT_REG;
687 info.status_mask = 1ull<<4 /* vrtadrng */;
688 info.enable_addr = CVMX_L2C_INT_ENA;
689 info.enable_mask = 1ull<<4 /* vrtadrng */;
691 info.group = CVMX_ERROR_GROUP_INTERNAL;
692 info.group_index = 0;
693 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
694 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
695 info.parent.status_mask = 1ull<<16 /* l2c */;
696 info.func = __cvmx_error_display;
697 info.user_info = (long)
698 "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
699 " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
701 " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
702 fail |= cvmx_error_add(&info);
704 info.reg_type = CVMX_ERROR_REGISTER_IO64;
705 info.status_addr = CVMX_L2C_INT_REG;
706 info.status_mask = 1ull<<5 /* vrtpe */;
707 info.enable_addr = CVMX_L2C_INT_ENA;
708 info.enable_mask = 1ull<<5 /* vrtpe */;
710 info.group = CVMX_ERROR_GROUP_INTERNAL;
711 info.group_index = 0;
712 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
713 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
714 info.parent.status_mask = 1ull<<16 /* l2c */;
715 info.func = __cvmx_error_display;
716 info.user_info = (long)
717 "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
718 " Whenever an L2C_VRT_MEM read finds a parity error,\n"
719 " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
720 " Software should correct the error.\n";
721 fail |= cvmx_error_add(&info);
723 info.reg_type = CVMX_ERROR_REGISTER_IO64;
724 info.status_addr = CVMX_L2C_INT_REG;
725 info.status_mask = 1ull<<6 /* bigwr */;
726 info.enable_addr = CVMX_L2C_INT_ENA;
727 info.enable_mask = 1ull<<6 /* bigwr */;
729 info.group = CVMX_ERROR_GROUP_INTERNAL;
730 info.group_index = 0;
731 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
732 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
733 info.parent.status_mask = 1ull<<16 /* l2c */;
734 info.func = __cvmx_error_display;
735 info.user_info = (long)
736 "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
737 fail |= cvmx_error_add(&info);
739 info.reg_type = CVMX_ERROR_REGISTER_IO64;
740 info.status_addr = CVMX_L2C_INT_REG;
741 info.status_mask = 1ull<<7 /* bigrd */;
742 info.enable_addr = CVMX_L2C_INT_ENA;
743 info.enable_mask = 1ull<<7 /* bigrd */;
745 info.group = CVMX_ERROR_GROUP_INTERNAL;
746 info.group_index = 0;
747 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
748 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
749 info.parent.status_mask = 1ull<<16 /* l2c */;
750 info.func = __cvmx_error_display;
751 info.user_info = (long)
752 "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
753 fail |= cvmx_error_add(&info);
755 info.reg_type = CVMX_ERROR_REGISTER_IO64;
756 info.status_addr = CVMX_L2C_INT_REG;
757 info.status_mask = 0;
758 info.enable_addr = 0;
759 info.enable_mask = 0;
761 info.group = CVMX_ERROR_GROUP_INTERNAL;
762 info.group_index = 0;
763 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
764 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
765 info.parent.status_mask = 1ull<<16 /* l2c */;
766 info.func = __cvmx_error_decode;
768 fail |= cvmx_error_add(&info);
770 /* CVMX_L2C_TADX_INT(0) */
771 info.reg_type = CVMX_ERROR_REGISTER_IO64;
772 info.status_addr = CVMX_L2C_TADX_INT(0);
773 info.status_mask = 1ull<<0 /* l2dsbe */;
774 info.enable_addr = CVMX_L2C_TADX_IEN(0);
775 info.enable_mask = 1ull<<0 /* l2dsbe */;
777 info.group = CVMX_ERROR_GROUP_INTERNAL;
778 info.group_index = 0;
779 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
780 info.parent.status_addr = CVMX_L2C_INT_REG;
781 info.parent.status_mask = 1ull<<16 /* tad0 */;
782 info.func = __cvmx_error_display;
783 info.user_info = (long)
784 "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
785 " Shadow copy of L2C_ERR_TDTX[SBE]\n"
786 " Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
787 fail |= cvmx_error_add(&info);
789 info.reg_type = CVMX_ERROR_REGISTER_IO64;
790 info.status_addr = CVMX_L2C_TADX_INT(0);
791 info.status_mask = 1ull<<1 /* l2ddbe */;
792 info.enable_addr = CVMX_L2C_TADX_IEN(0);
793 info.enable_mask = 1ull<<1 /* l2ddbe */;
795 info.group = CVMX_ERROR_GROUP_INTERNAL;
796 info.group_index = 0;
797 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
798 info.parent.status_addr = CVMX_L2C_INT_REG;
799 info.parent.status_mask = 1ull<<16 /* tad0 */;
800 info.func = __cvmx_error_display;
801 info.user_info = (long)
802 "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
803 " Shadow copy of L2C_ERR_TDTX[DBE]\n"
804 " Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
805 fail |= cvmx_error_add(&info);
807 info.reg_type = CVMX_ERROR_REGISTER_IO64;
808 info.status_addr = CVMX_L2C_TADX_INT(0);
809 info.status_mask = 1ull<<2 /* tagsbe */;
810 info.enable_addr = CVMX_L2C_TADX_IEN(0);
811 info.enable_mask = 1ull<<2 /* tagsbe */;
813 info.group = CVMX_ERROR_GROUP_INTERNAL;
814 info.group_index = 0;
815 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
816 info.parent.status_addr = CVMX_L2C_INT_REG;
817 info.parent.status_mask = 1ull<<16 /* tad0 */;
818 info.func = __cvmx_error_display;
819 info.user_info = (long)
820 "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
821 " Shadow copy of L2C_ERR_TTGX[SBE]\n"
822 " Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
823 fail |= cvmx_error_add(&info);
825 info.reg_type = CVMX_ERROR_REGISTER_IO64;
826 info.status_addr = CVMX_L2C_TADX_INT(0);
827 info.status_mask = 1ull<<3 /* tagdbe */;
828 info.enable_addr = CVMX_L2C_TADX_IEN(0);
829 info.enable_mask = 1ull<<3 /* tagdbe */;
831 info.group = CVMX_ERROR_GROUP_INTERNAL;
832 info.group_index = 0;
833 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
834 info.parent.status_addr = CVMX_L2C_INT_REG;
835 info.parent.status_mask = 1ull<<16 /* tad0 */;
836 info.func = __cvmx_error_display;
837 info.user_info = (long)
838 "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
839 " Shadow copy of L2C_ERR_TTGX[DBE]\n"
840 " Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
841 fail |= cvmx_error_add(&info);
843 info.reg_type = CVMX_ERROR_REGISTER_IO64;
844 info.status_addr = CVMX_L2C_TADX_INT(0);
845 info.status_mask = 1ull<<4 /* vbfsbe */;
846 info.enable_addr = CVMX_L2C_TADX_IEN(0);
847 info.enable_mask = 1ull<<4 /* vbfsbe */;
849 info.group = CVMX_ERROR_GROUP_INTERNAL;
850 info.group_index = 0;
851 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
852 info.parent.status_addr = CVMX_L2C_INT_REG;
853 info.parent.status_mask = 1ull<<16 /* tad0 */;
854 info.func = __cvmx_error_display;
855 info.user_info = (long)
856 "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
857 " Shadow copy of L2C_ERR_TDTX[VSBE]\n"
858 " Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
859 fail |= cvmx_error_add(&info);
861 info.reg_type = CVMX_ERROR_REGISTER_IO64;
862 info.status_addr = CVMX_L2C_TADX_INT(0);
863 info.status_mask = 1ull<<5 /* vbfdbe */;
864 info.enable_addr = CVMX_L2C_TADX_IEN(0);
865 info.enable_mask = 1ull<<5 /* vbfdbe */;
867 info.group = CVMX_ERROR_GROUP_INTERNAL;
868 info.group_index = 0;
869 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
870 info.parent.status_addr = CVMX_L2C_INT_REG;
871 info.parent.status_mask = 1ull<<16 /* tad0 */;
872 info.func = __cvmx_error_display;
873 info.user_info = (long)
874 "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
875 " Shadow copy of L2C_ERR_TDTX[VDBE]\n"
876 " Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
877 fail |= cvmx_error_add(&info);
879 info.reg_type = CVMX_ERROR_REGISTER_IO64;
880 info.status_addr = CVMX_L2C_TADX_INT(0);
881 info.status_mask = 1ull<<6 /* noway */;
882 info.enable_addr = CVMX_L2C_TADX_IEN(0);
883 info.enable_mask = 1ull<<6 /* noway */;
885 info.group = CVMX_ERROR_GROUP_INTERNAL;
886 info.group_index = 0;
887 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
888 info.parent.status_addr = CVMX_L2C_INT_REG;
889 info.parent.status_mask = 1ull<<16 /* tad0 */;
890 info.func = __cvmx_error_display;
891 info.user_info = (long)
892 "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
893 " Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
894 " Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
895 fail |= cvmx_error_add(&info);
897 info.reg_type = CVMX_ERROR_REGISTER_IO64;
898 info.status_addr = CVMX_L2C_TADX_INT(0);
899 info.status_mask = 1ull<<7 /* rddislmc */;
900 info.enable_addr = CVMX_L2C_TADX_IEN(0);
901 info.enable_mask = 1ull<<7 /* rddislmc */;
903 info.group = CVMX_ERROR_GROUP_INTERNAL;
904 info.group_index = 0;
905 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
906 info.parent.status_addr = CVMX_L2C_INT_REG;
907 info.parent.status_mask = 1ull<<16 /* tad0 */;
908 info.func = __cvmx_error_display;
909 info.user_info = (long)
910 "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read to Disabled LMC Error\n"
911 " A DRAM read arrived before the LMC(s) were enabled\n";
912 fail |= cvmx_error_add(&info);
914 info.reg_type = CVMX_ERROR_REGISTER_IO64;
915 info.status_addr = CVMX_L2C_TADX_INT(0);
916 info.status_mask = 1ull<<8 /* wrdislmc */;
917 info.enable_addr = CVMX_L2C_TADX_IEN(0);
918 info.enable_mask = 1ull<<8 /* wrdislmc */;
920 info.group = CVMX_ERROR_GROUP_INTERNAL;
921 info.group_index = 0;
922 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
923 info.parent.status_addr = CVMX_L2C_INT_REG;
924 info.parent.status_mask = 1ull<<16 /* tad0 */;
925 info.func = __cvmx_error_display;
926 info.user_info = (long)
927 "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
928 " A DRAM write arrived before the LMC(s) were enabled\n";
929 fail |= cvmx_error_add(&info);
931 /* CVMX_IPD_INT_SUM */
932 info.reg_type = CVMX_ERROR_REGISTER_IO64;
933 info.status_addr = CVMX_IPD_INT_SUM;
934 info.status_mask = 1ull<<0 /* prc_par0 */;
935 info.enable_addr = CVMX_IPD_INT_ENB;
936 info.enable_mask = 1ull<<0 /* prc_par0 */;
938 info.group = CVMX_ERROR_GROUP_INTERNAL;
939 info.group_index = 0;
940 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
941 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
942 info.parent.status_mask = 1ull<<9 /* ipd */;
943 info.func = __cvmx_error_display;
944 info.user_info = (long)
945 "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
946 " [31:0] of the PBM memory.\n";
947 fail |= cvmx_error_add(&info);
949 info.reg_type = CVMX_ERROR_REGISTER_IO64;
950 info.status_addr = CVMX_IPD_INT_SUM;
951 info.status_mask = 1ull<<1 /* prc_par1 */;
952 info.enable_addr = CVMX_IPD_INT_ENB;
953 info.enable_mask = 1ull<<1 /* prc_par1 */;
955 info.group = CVMX_ERROR_GROUP_INTERNAL;
956 info.group_index = 0;
957 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
958 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
959 info.parent.status_mask = 1ull<<9 /* ipd */;
960 info.func = __cvmx_error_display;
961 info.user_info = (long)
962 "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
963 " [63:32] of the PBM memory.\n";
964 fail |= cvmx_error_add(&info);
966 info.reg_type = CVMX_ERROR_REGISTER_IO64;
967 info.status_addr = CVMX_IPD_INT_SUM;
968 info.status_mask = 1ull<<2 /* prc_par2 */;
969 info.enable_addr = CVMX_IPD_INT_ENB;
970 info.enable_mask = 1ull<<2 /* prc_par2 */;
972 info.group = CVMX_ERROR_GROUP_INTERNAL;
973 info.group_index = 0;
974 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
975 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
976 info.parent.status_mask = 1ull<<9 /* ipd */;
977 info.func = __cvmx_error_display;
978 info.user_info = (long)
979 "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
980 " [95:64] of the PBM memory.\n";
981 fail |= cvmx_error_add(&info);
983 info.reg_type = CVMX_ERROR_REGISTER_IO64;
984 info.status_addr = CVMX_IPD_INT_SUM;
985 info.status_mask = 1ull<<3 /* prc_par3 */;
986 info.enable_addr = CVMX_IPD_INT_ENB;
987 info.enable_mask = 1ull<<3 /* prc_par3 */;
989 info.group = CVMX_ERROR_GROUP_INTERNAL;
990 info.group_index = 0;
991 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
992 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
993 info.parent.status_mask = 1ull<<9 /* ipd */;
994 info.func = __cvmx_error_display;
995 info.user_info = (long)
996 "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
997 " [127:96] of the PBM memory.\n";
998 fail |= cvmx_error_add(&info);
1000 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1001 info.status_addr = CVMX_IPD_INT_SUM;
1002 info.status_mask = 1ull<<4 /* bp_sub */;
1003 info.enable_addr = CVMX_IPD_INT_ENB;
1004 info.enable_mask = 1ull<<4 /* bp_sub */;
1006 info.group = CVMX_ERROR_GROUP_INTERNAL;
1007 info.group_index = 0;
1008 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1009 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1010 info.parent.status_mask = 1ull<<9 /* ipd */;
1011 info.func = __cvmx_error_display;
1012 info.user_info = (long)
1013 "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
1014 " supplied illegal value.\n";
1015 fail |= cvmx_error_add(&info);
1017 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1018 info.status_addr = CVMX_IPD_INT_SUM;
1019 info.status_mask = 1ull<<5 /* dc_ovr */;
1020 info.enable_addr = CVMX_IPD_INT_ENB;
1021 info.enable_mask = 1ull<<5 /* dc_ovr */;
1023 info.group = CVMX_ERROR_GROUP_INTERNAL;
1024 info.group_index = 0;
1025 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1026 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1027 info.parent.status_mask = 1ull<<9 /* ipd */;
1028 info.func = __cvmx_error_display;
1029 info.user_info = (long)
1030 "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
1031 fail |= cvmx_error_add(&info);
1033 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1034 info.status_addr = CVMX_IPD_INT_SUM;
1035 info.status_mask = 1ull<<6 /* cc_ovr */;
1036 info.enable_addr = CVMX_IPD_INT_ENB;
1037 info.enable_mask = 1ull<<6 /* cc_ovr */;
1039 info.group = CVMX_ERROR_GROUP_INTERNAL;
1040 info.group_index = 0;
1041 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1042 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1043 info.parent.status_mask = 1ull<<9 /* ipd */;
1044 info.func = __cvmx_error_display;
1045 info.user_info = (long)
1046 "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
1047 fail |= cvmx_error_add(&info);
1049 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1050 info.status_addr = CVMX_IPD_INT_SUM;
1051 info.status_mask = 1ull<<7 /* c_coll */;
1052 info.enable_addr = CVMX_IPD_INT_ENB;
1053 info.enable_mask = 1ull<<7 /* c_coll */;
1055 info.group = CVMX_ERROR_GROUP_INTERNAL;
1056 info.group_index = 0;
1057 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1058 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1059 info.parent.status_mask = 1ull<<9 /* ipd */;
1060 info.func = __cvmx_error_display;
1061 info.user_info = (long)
1062 "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
1064 fail |= cvmx_error_add(&info);
1066 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1067 info.status_addr = CVMX_IPD_INT_SUM;
1068 info.status_mask = 1ull<<8 /* d_coll */;
1069 info.enable_addr = CVMX_IPD_INT_ENB;
1070 info.enable_mask = 1ull<<8 /* d_coll */;
1072 info.group = CVMX_ERROR_GROUP_INTERNAL;
1073 info.group_index = 0;
1074 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1075 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1076 info.parent.status_mask = 1ull<<9 /* ipd */;
1077 info.func = __cvmx_error_display;
1078 info.user_info = (long)
1079 "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
1081 fail |= cvmx_error_add(&info);
1083 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1084 info.status_addr = CVMX_IPD_INT_SUM;
1085 info.status_mask = 1ull<<9 /* bc_ovr */;
1086 info.enable_addr = CVMX_IPD_INT_ENB;
1087 info.enable_mask = 1ull<<9 /* bc_ovr */;
1089 info.group = CVMX_ERROR_GROUP_INTERNAL;
1090 info.group_index = 0;
1091 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1092 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1093 info.parent.status_mask = 1ull<<9 /* ipd */;
1094 info.func = __cvmx_error_display;
1095 info.user_info = (long)
1096 "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
1097 fail |= cvmx_error_add(&info);
1099 /* CVMX_POW_ECC_ERR */
1100 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1101 info.status_addr = CVMX_POW_ECC_ERR;
1102 info.status_mask = 1ull<<0 /* sbe */;
1103 info.enable_addr = CVMX_POW_ECC_ERR;
1104 info.enable_mask = 1ull<<2 /* sbe_ie */;
1105 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
1106 info.group = CVMX_ERROR_GROUP_INTERNAL;
1107 info.group_index = 0;
1108 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1109 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1110 info.parent.status_mask = 1ull<<12 /* pow */;
1111 info.func = __cvmx_error_handle_pow_ecc_err_sbe;
1112 info.user_info = (long)
1113 "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
1114 fail |= cvmx_error_add(&info);
1116 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1117 info.status_addr = CVMX_POW_ECC_ERR;
1118 info.status_mask = 1ull<<1 /* dbe */;
1119 info.enable_addr = CVMX_POW_ECC_ERR;
1120 info.enable_mask = 1ull<<3 /* dbe_ie */;
1122 info.group = CVMX_ERROR_GROUP_INTERNAL;
1123 info.group_index = 0;
1124 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1125 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1126 info.parent.status_mask = 1ull<<12 /* pow */;
1127 info.func = __cvmx_error_handle_pow_ecc_err_dbe;
1128 info.user_info = (long)
1129 "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
1130 fail |= cvmx_error_add(&info);
1132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1133 info.status_addr = CVMX_POW_ECC_ERR;
1134 info.status_mask = 1ull<<12 /* rpe */;
1135 info.enable_addr = CVMX_POW_ECC_ERR;
1136 info.enable_mask = 1ull<<13 /* rpe_ie */;
1138 info.group = CVMX_ERROR_GROUP_INTERNAL;
1139 info.group_index = 0;
1140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1141 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1142 info.parent.status_mask = 1ull<<12 /* pow */;
1143 info.func = __cvmx_error_handle_pow_ecc_err_rpe;
1144 info.user_info = (long)
1145 "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
1146 fail |= cvmx_error_add(&info);
1148 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1149 info.status_addr = CVMX_POW_ECC_ERR;
1150 info.status_mask = 0x1fffull<<16 /* iop */;
1151 info.enable_addr = CVMX_POW_ECC_ERR;
1152 info.enable_mask = 0x1fffull<<32 /* iop_ie */;
1154 info.group = CVMX_ERROR_GROUP_INTERNAL;
1155 info.group_index = 0;
1156 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1157 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1158 info.parent.status_mask = 1ull<<12 /* pow */;
1159 info.func = __cvmx_error_handle_pow_ecc_err_iop;
1160 info.user_info = (long)
1161 "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
1162 fail |= cvmx_error_add(&info);
1164 /* CVMX_RAD_REG_ERROR */
1165 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1166 info.status_addr = CVMX_RAD_REG_ERROR;
1167 info.status_mask = 1ull<<0 /* doorbell */;
1168 info.enable_addr = CVMX_RAD_REG_INT_MASK;
1169 info.enable_mask = 1ull<<0 /* doorbell */;
1171 info.group = CVMX_ERROR_GROUP_INTERNAL;
1172 info.group_index = 0;
1173 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1174 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1175 info.parent.status_mask = 1ull<<14 /* rad */;
1176 info.func = __cvmx_error_display;
1177 info.user_info = (long)
1178 "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
1179 fail |= cvmx_error_add(&info);
1181 /* CVMX_PCSX_INTX_REG(0,0) */
1182 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1183 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1184 info.status_mask = 1ull<<2 /* an_err */;
1185 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1186 info.enable_mask = 1ull<<2 /* an_err_en */;
1188 info.group = CVMX_ERROR_GROUP_ETHERNET;
1189 info.group_index = 0;
1190 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1191 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1192 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1193 info.func = __cvmx_error_display;
1194 info.user_info = (long)
1195 "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1196 fail |= cvmx_error_add(&info);
1198 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1199 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1200 info.status_mask = 1ull<<3 /* txfifu */;
1201 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1202 info.enable_mask = 1ull<<3 /* txfifu_en */;
1204 info.group = CVMX_ERROR_GROUP_ETHERNET;
1205 info.group_index = 0;
1206 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1207 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1208 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1209 info.func = __cvmx_error_display;
1210 info.user_info = (long)
1211 "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1213 fail |= cvmx_error_add(&info);
1215 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1216 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1217 info.status_mask = 1ull<<4 /* txfifo */;
1218 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1219 info.enable_mask = 1ull<<4 /* txfifo_en */;
1221 info.group = CVMX_ERROR_GROUP_ETHERNET;
1222 info.group_index = 0;
1223 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1224 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1225 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1226 info.func = __cvmx_error_display;
1227 info.user_info = (long)
1228 "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1230 fail |= cvmx_error_add(&info);
1232 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1233 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1234 info.status_mask = 1ull<<5 /* txbad */;
1235 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1236 info.enable_mask = 1ull<<5 /* txbad_en */;
1238 info.group = CVMX_ERROR_GROUP_ETHERNET;
1239 info.group_index = 0;
1240 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1241 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1242 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1243 info.func = __cvmx_error_display;
1244 info.user_info = (long)
1245 "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1246 " state. Should never be set during normal operation\n";
1247 fail |= cvmx_error_add(&info);
1249 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1250 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1251 info.status_mask = 1ull<<7 /* rxbad */;
1252 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1253 info.enable_mask = 1ull<<7 /* rxbad_en */;
1255 info.group = CVMX_ERROR_GROUP_ETHERNET;
1256 info.group_index = 0;
1257 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1258 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1259 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1260 info.func = __cvmx_error_display;
1261 info.user_info = (long)
1262 "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1263 " state. Should never be set during normal operation\n";
1264 fail |= cvmx_error_add(&info);
1266 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1267 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1268 info.status_mask = 1ull<<8 /* rxlock */;
1269 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1270 info.enable_mask = 1ull<<8 /* rxlock_en */;
1272 info.group = CVMX_ERROR_GROUP_ETHERNET;
1273 info.group_index = 0;
1274 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1275 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1276 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1277 info.func = __cvmx_error_display;
1278 info.user_info = (long)
1279 "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1281 " Cannot fire in loopback1 mode\n";
1282 fail |= cvmx_error_add(&info);
1284 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1285 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1286 info.status_mask = 1ull<<9 /* an_bad */;
1287 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1288 info.enable_mask = 1ull<<9 /* an_bad_en */;
1290 info.group = CVMX_ERROR_GROUP_ETHERNET;
1291 info.group_index = 0;
1292 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1293 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1294 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1295 info.func = __cvmx_error_display;
1296 info.user_info = (long)
1297 "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1298 " state. Should never be set during normal operation\n";
1299 fail |= cvmx_error_add(&info);
1301 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1302 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1303 info.status_mask = 1ull<<10 /* sync_bad */;
1304 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1305 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1307 info.group = CVMX_ERROR_GROUP_ETHERNET;
1308 info.group_index = 0;
1309 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1310 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1311 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1312 info.func = __cvmx_error_display;
1313 info.user_info = (long)
1314 "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1315 " state. Should never be set during normal operation\n";
1316 fail |= cvmx_error_add(&info);
1318 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1319 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1320 info.status_mask = 1ull<<12 /* dbg_sync */;
1321 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1322 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1324 info.group = CVMX_ERROR_GROUP_ETHERNET;
1325 info.group_index = 0;
1326 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1327 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1328 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1329 info.func = __cvmx_error_display;
1330 info.user_info = (long)
1331 "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1332 fail |= cvmx_error_add(&info);
1334 /* CVMX_PCSX_INTX_REG(1,0) */
1335 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1336 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1337 info.status_mask = 1ull<<2 /* an_err */;
1338 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1339 info.enable_mask = 1ull<<2 /* an_err_en */;
1341 info.group = CVMX_ERROR_GROUP_ETHERNET;
1342 info.group_index = 1;
1343 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1344 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1345 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1346 info.func = __cvmx_error_display;
1347 info.user_info = (long)
1348 "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1349 fail |= cvmx_error_add(&info);
1351 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1352 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1353 info.status_mask = 1ull<<3 /* txfifu */;
1354 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1355 info.enable_mask = 1ull<<3 /* txfifu_en */;
1357 info.group = CVMX_ERROR_GROUP_ETHERNET;
1358 info.group_index = 1;
1359 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1360 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1361 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1362 info.func = __cvmx_error_display;
1363 info.user_info = (long)
1364 "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1366 fail |= cvmx_error_add(&info);
1368 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1369 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1370 info.status_mask = 1ull<<4 /* txfifo */;
1371 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1372 info.enable_mask = 1ull<<4 /* txfifo_en */;
1374 info.group = CVMX_ERROR_GROUP_ETHERNET;
1375 info.group_index = 1;
1376 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1377 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1378 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1379 info.func = __cvmx_error_display;
1380 info.user_info = (long)
1381 "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1383 fail |= cvmx_error_add(&info);
1385 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1386 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1387 info.status_mask = 1ull<<5 /* txbad */;
1388 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1389 info.enable_mask = 1ull<<5 /* txbad_en */;
1391 info.group = CVMX_ERROR_GROUP_ETHERNET;
1392 info.group_index = 1;
1393 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1394 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1395 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1396 info.func = __cvmx_error_display;
1397 info.user_info = (long)
1398 "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1399 " state. Should never be set during normal operation\n";
1400 fail |= cvmx_error_add(&info);
1402 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1403 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1404 info.status_mask = 1ull<<7 /* rxbad */;
1405 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1406 info.enable_mask = 1ull<<7 /* rxbad_en */;
1408 info.group = CVMX_ERROR_GROUP_ETHERNET;
1409 info.group_index = 1;
1410 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1411 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1412 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1413 info.func = __cvmx_error_display;
1414 info.user_info = (long)
1415 "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1416 " state. Should never be set during normal operation\n";
1417 fail |= cvmx_error_add(&info);
1419 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1420 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1421 info.status_mask = 1ull<<8 /* rxlock */;
1422 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1423 info.enable_mask = 1ull<<8 /* rxlock_en */;
1425 info.group = CVMX_ERROR_GROUP_ETHERNET;
1426 info.group_index = 1;
1427 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1428 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1429 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1430 info.func = __cvmx_error_display;
1431 info.user_info = (long)
1432 "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1434 " Cannot fire in loopback1 mode\n";
1435 fail |= cvmx_error_add(&info);
1437 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1438 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1439 info.status_mask = 1ull<<9 /* an_bad */;
1440 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1441 info.enable_mask = 1ull<<9 /* an_bad_en */;
1443 info.group = CVMX_ERROR_GROUP_ETHERNET;
1444 info.group_index = 1;
1445 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1446 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1447 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1448 info.func = __cvmx_error_display;
1449 info.user_info = (long)
1450 "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1451 " state. Should never be set during normal operation\n";
1452 fail |= cvmx_error_add(&info);
1454 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1455 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1456 info.status_mask = 1ull<<10 /* sync_bad */;
1457 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1458 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1460 info.group = CVMX_ERROR_GROUP_ETHERNET;
1461 info.group_index = 1;
1462 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1463 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1464 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1465 info.func = __cvmx_error_display;
1466 info.user_info = (long)
1467 "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1468 " state. Should never be set during normal operation\n";
1469 fail |= cvmx_error_add(&info);
1471 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1472 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1473 info.status_mask = 1ull<<12 /* dbg_sync */;
1474 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1475 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1477 info.group = CVMX_ERROR_GROUP_ETHERNET;
1478 info.group_index = 1;
1479 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1480 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1481 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1482 info.func = __cvmx_error_display;
1483 info.user_info = (long)
1484 "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1485 fail |= cvmx_error_add(&info);
1487 /* CVMX_PCSX_INTX_REG(2,0) */
1488 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1489 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1490 info.status_mask = 1ull<<2 /* an_err */;
1491 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1492 info.enable_mask = 1ull<<2 /* an_err_en */;
1494 info.group = CVMX_ERROR_GROUP_ETHERNET;
1495 info.group_index = 2;
1496 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1497 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1498 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1499 info.func = __cvmx_error_display;
1500 info.user_info = (long)
1501 "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1502 fail |= cvmx_error_add(&info);
1504 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1505 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1506 info.status_mask = 1ull<<3 /* txfifu */;
1507 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1508 info.enable_mask = 1ull<<3 /* txfifu_en */;
1510 info.group = CVMX_ERROR_GROUP_ETHERNET;
1511 info.group_index = 2;
1512 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1513 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1514 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1515 info.func = __cvmx_error_display;
1516 info.user_info = (long)
1517 "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1519 fail |= cvmx_error_add(&info);
1521 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1522 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1523 info.status_mask = 1ull<<4 /* txfifo */;
1524 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1525 info.enable_mask = 1ull<<4 /* txfifo_en */;
1527 info.group = CVMX_ERROR_GROUP_ETHERNET;
1528 info.group_index = 2;
1529 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1530 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1531 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1532 info.func = __cvmx_error_display;
1533 info.user_info = (long)
1534 "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1536 fail |= cvmx_error_add(&info);
1538 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1539 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1540 info.status_mask = 1ull<<5 /* txbad */;
1541 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1542 info.enable_mask = 1ull<<5 /* txbad_en */;
1544 info.group = CVMX_ERROR_GROUP_ETHERNET;
1545 info.group_index = 2;
1546 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1547 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1548 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1549 info.func = __cvmx_error_display;
1550 info.user_info = (long)
1551 "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1552 " state. Should never be set during normal operation\n";
1553 fail |= cvmx_error_add(&info);
1555 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1556 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1557 info.status_mask = 1ull<<7 /* rxbad */;
1558 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1559 info.enable_mask = 1ull<<7 /* rxbad_en */;
1561 info.group = CVMX_ERROR_GROUP_ETHERNET;
1562 info.group_index = 2;
1563 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1564 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1565 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1566 info.func = __cvmx_error_display;
1567 info.user_info = (long)
1568 "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1569 " state. Should never be set during normal operation\n";
1570 fail |= cvmx_error_add(&info);
1572 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1573 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1574 info.status_mask = 1ull<<8 /* rxlock */;
1575 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1576 info.enable_mask = 1ull<<8 /* rxlock_en */;
1578 info.group = CVMX_ERROR_GROUP_ETHERNET;
1579 info.group_index = 2;
1580 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1581 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1582 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1583 info.func = __cvmx_error_display;
1584 info.user_info = (long)
1585 "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1587 " Cannot fire in loopback1 mode\n";
1588 fail |= cvmx_error_add(&info);
1590 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1591 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1592 info.status_mask = 1ull<<9 /* an_bad */;
1593 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1594 info.enable_mask = 1ull<<9 /* an_bad_en */;
1596 info.group = CVMX_ERROR_GROUP_ETHERNET;
1597 info.group_index = 2;
1598 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1599 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1600 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1601 info.func = __cvmx_error_display;
1602 info.user_info = (long)
1603 "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1604 " state. Should never be set during normal operation\n";
1605 fail |= cvmx_error_add(&info);
1607 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1608 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1609 info.status_mask = 1ull<<10 /* sync_bad */;
1610 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1611 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1613 info.group = CVMX_ERROR_GROUP_ETHERNET;
1614 info.group_index = 2;
1615 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1616 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1617 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1618 info.func = __cvmx_error_display;
1619 info.user_info = (long)
1620 "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1621 " state. Should never be set during normal operation\n";
1622 fail |= cvmx_error_add(&info);
1624 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1625 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1626 info.status_mask = 1ull<<12 /* dbg_sync */;
1627 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1628 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1630 info.group = CVMX_ERROR_GROUP_ETHERNET;
1631 info.group_index = 2;
1632 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1633 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1634 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1635 info.func = __cvmx_error_display;
1636 info.user_info = (long)
1637 "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1638 fail |= cvmx_error_add(&info);
1640 /* CVMX_PCSX_INTX_REG(3,0) */
1641 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1642 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1643 info.status_mask = 1ull<<2 /* an_err */;
1644 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1645 info.enable_mask = 1ull<<2 /* an_err_en */;
1647 info.group = CVMX_ERROR_GROUP_ETHERNET;
1648 info.group_index = 3;
1649 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1650 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1651 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1652 info.func = __cvmx_error_display;
1653 info.user_info = (long)
1654 "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1655 fail |= cvmx_error_add(&info);
1657 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1658 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1659 info.status_mask = 1ull<<3 /* txfifu */;
1660 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1661 info.enable_mask = 1ull<<3 /* txfifu_en */;
1663 info.group = CVMX_ERROR_GROUP_ETHERNET;
1664 info.group_index = 3;
1665 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1666 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1667 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1668 info.func = __cvmx_error_display;
1669 info.user_info = (long)
1670 "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1672 fail |= cvmx_error_add(&info);
1674 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1675 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1676 info.status_mask = 1ull<<4 /* txfifo */;
1677 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1678 info.enable_mask = 1ull<<4 /* txfifo_en */;
1680 info.group = CVMX_ERROR_GROUP_ETHERNET;
1681 info.group_index = 3;
1682 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1683 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1684 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1685 info.func = __cvmx_error_display;
1686 info.user_info = (long)
1687 "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1689 fail |= cvmx_error_add(&info);
1691 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1692 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1693 info.status_mask = 1ull<<5 /* txbad */;
1694 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1695 info.enable_mask = 1ull<<5 /* txbad_en */;
1697 info.group = CVMX_ERROR_GROUP_ETHERNET;
1698 info.group_index = 3;
1699 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1700 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1701 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1702 info.func = __cvmx_error_display;
1703 info.user_info = (long)
1704 "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1705 " state. Should never be set during normal operation\n";
1706 fail |= cvmx_error_add(&info);
1708 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1709 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1710 info.status_mask = 1ull<<7 /* rxbad */;
1711 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1712 info.enable_mask = 1ull<<7 /* rxbad_en */;
1714 info.group = CVMX_ERROR_GROUP_ETHERNET;
1715 info.group_index = 3;
1716 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1717 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1718 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1719 info.func = __cvmx_error_display;
1720 info.user_info = (long)
1721 "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1722 " state. Should never be set during normal operation\n";
1723 fail |= cvmx_error_add(&info);
1725 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1726 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1727 info.status_mask = 1ull<<8 /* rxlock */;
1728 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1729 info.enable_mask = 1ull<<8 /* rxlock_en */;
1731 info.group = CVMX_ERROR_GROUP_ETHERNET;
1732 info.group_index = 3;
1733 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1734 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1735 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1736 info.func = __cvmx_error_display;
1737 info.user_info = (long)
1738 "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1740 " Cannot fire in loopback1 mode\n";
1741 fail |= cvmx_error_add(&info);
1743 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1744 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1745 info.status_mask = 1ull<<9 /* an_bad */;
1746 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1747 info.enable_mask = 1ull<<9 /* an_bad_en */;
1749 info.group = CVMX_ERROR_GROUP_ETHERNET;
1750 info.group_index = 3;
1751 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1752 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1753 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1754 info.func = __cvmx_error_display;
1755 info.user_info = (long)
1756 "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1757 " state. Should never be set during normal operation\n";
1758 fail |= cvmx_error_add(&info);
1760 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1761 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1762 info.status_mask = 1ull<<10 /* sync_bad */;
1763 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1764 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1766 info.group = CVMX_ERROR_GROUP_ETHERNET;
1767 info.group_index = 3;
1768 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1769 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1770 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1771 info.func = __cvmx_error_display;
1772 info.user_info = (long)
1773 "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1774 " state. Should never be set during normal operation\n";
1775 fail |= cvmx_error_add(&info);
1777 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1778 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1779 info.status_mask = 1ull<<12 /* dbg_sync */;
1780 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1781 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1783 info.group = CVMX_ERROR_GROUP_ETHERNET;
1784 info.group_index = 3;
1785 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1786 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1787 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1788 info.func = __cvmx_error_display;
1789 info.user_info = (long)
1790 "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1791 fail |= cvmx_error_add(&info);
1793 /* CVMX_PCSXX_INT_REG(0) */
1794 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1795 info.status_addr = CVMX_PCSXX_INT_REG(0);
1796 info.status_mask = 1ull<<0 /* txflt */;
1797 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1798 info.enable_mask = 1ull<<0 /* txflt_en */;
1800 info.group = CVMX_ERROR_GROUP_ETHERNET;
1801 info.group_index = 0;
1802 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1803 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1804 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1805 info.func = __cvmx_error_display;
1806 info.user_info = (long)
1807 "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
1808 fail |= cvmx_error_add(&info);
1810 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1811 info.status_addr = CVMX_PCSXX_INT_REG(0);
1812 info.status_mask = 1ull<<1 /* rxbad */;
1813 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1814 info.enable_mask = 1ull<<1 /* rxbad_en */;
1816 info.group = CVMX_ERROR_GROUP_ETHERNET;
1817 info.group_index = 0;
1818 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1819 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1820 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1821 info.func = __cvmx_error_display;
1822 info.user_info = (long)
1823 "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
1824 fail |= cvmx_error_add(&info);
1826 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1827 info.status_addr = CVMX_PCSXX_INT_REG(0);
1828 info.status_mask = 1ull<<2 /* rxsynbad */;
1829 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1830 info.enable_mask = 1ull<<2 /* rxsynbad_en */;
1832 info.group = CVMX_ERROR_GROUP_ETHERNET;
1833 info.group_index = 0;
1834 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1835 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1836 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1837 info.func = __cvmx_error_display;
1838 info.user_info = (long)
1839 "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
1840 " in one of the 4 xaui lanes\n";
1841 fail |= cvmx_error_add(&info);
1843 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1844 info.status_addr = CVMX_PCSXX_INT_REG(0);
1845 info.status_mask = 1ull<<3 /* bitlckls */;
1846 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1847 info.enable_mask = 1ull<<3 /* bitlckls_en */;
1849 info.group = CVMX_ERROR_GROUP_ETHERNET;
1850 info.group_index = 0;
1851 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1852 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1853 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1854 info.func = __cvmx_error_display;
1855 info.user_info = (long)
1856 "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
1857 fail |= cvmx_error_add(&info);
1859 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1860 info.status_addr = CVMX_PCSXX_INT_REG(0);
1861 info.status_mask = 1ull<<4 /* synlos */;
1862 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1863 info.enable_mask = 1ull<<4 /* synlos_en */;
1865 info.group = CVMX_ERROR_GROUP_ETHERNET;
1866 info.group_index = 0;
1867 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1868 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1869 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1870 info.func = __cvmx_error_display;
1871 info.user_info = (long)
1872 "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
1873 fail |= cvmx_error_add(&info);
1875 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1876 info.status_addr = CVMX_PCSXX_INT_REG(0);
1877 info.status_mask = 1ull<<5 /* algnlos */;
1878 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1879 info.enable_mask = 1ull<<5 /* algnlos_en */;
1881 info.group = CVMX_ERROR_GROUP_ETHERNET;
1882 info.group_index = 0;
1883 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1884 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1885 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1886 info.func = __cvmx_error_display;
1887 info.user_info = (long)
1888 "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
1889 fail |= cvmx_error_add(&info);
1891 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1892 info.status_addr = CVMX_PCSXX_INT_REG(0);
1893 info.status_mask = 1ull<<6 /* dbg_sync */;
1894 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1895 info.enable_mask = 1ull<<6 /* dbg_sync_en */;
1897 info.group = CVMX_ERROR_GROUP_ETHERNET;
1898 info.group_index = 0;
1899 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1900 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1901 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1902 info.func = __cvmx_error_display;
1903 info.user_info = (long)
1904 "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
1905 fail |= cvmx_error_add(&info);
1907 /* CVMX_PIP_INT_REG */
1908 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1909 info.status_addr = CVMX_PIP_INT_REG;
1910 info.status_mask = 1ull<<3 /* prtnxa */;
1911 info.enable_addr = CVMX_PIP_INT_EN;
1912 info.enable_mask = 1ull<<3 /* prtnxa */;
1914 info.group = CVMX_ERROR_GROUP_INTERNAL;
1915 info.group_index = 0;
1916 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1917 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1918 info.parent.status_mask = 1ull<<20 /* pip */;
1919 info.func = __cvmx_error_display;
1920 info.user_info = (long)
1921 "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
1922 fail |= cvmx_error_add(&info);
1924 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1925 info.status_addr = CVMX_PIP_INT_REG;
1926 info.status_mask = 1ull<<4 /* badtag */;
1927 info.enable_addr = CVMX_PIP_INT_EN;
1928 info.enable_mask = 1ull<<4 /* badtag */;
1930 info.group = CVMX_ERROR_GROUP_INTERNAL;
1931 info.group_index = 0;
1932 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1933 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1934 info.parent.status_mask = 1ull<<20 /* pip */;
1935 info.func = __cvmx_error_display;
1936 info.user_info = (long)
1937 "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
1938 fail |= cvmx_error_add(&info);
1940 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1941 info.status_addr = CVMX_PIP_INT_REG;
1942 info.status_mask = 1ull<<5 /* skprunt */;
1943 info.enable_addr = CVMX_PIP_INT_EN;
1944 info.enable_mask = 1ull<<5 /* skprunt */;
1946 info.group = CVMX_ERROR_GROUP_INTERNAL;
1947 info.group_index = 0;
1948 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1949 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1950 info.parent.status_mask = 1ull<<20 /* pip */;
1951 info.func = __cvmx_error_display;
1952 info.user_info = (long)
1953 "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
1954 " This interrupt can occur with received PARTIAL\n"
1955 " packets that are truncated to SKIP bytes or\n"
1957 fail |= cvmx_error_add(&info);
1959 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1960 info.status_addr = CVMX_PIP_INT_REG;
1961 info.status_mask = 1ull<<6 /* todoovr */;
1962 info.enable_addr = CVMX_PIP_INT_EN;
1963 info.enable_mask = 1ull<<6 /* todoovr */;
1965 info.group = CVMX_ERROR_GROUP_INTERNAL;
1966 info.group_index = 0;
1967 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1968 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1969 info.parent.status_mask = 1ull<<20 /* pip */;
1970 info.func = __cvmx_error_display;
1971 info.user_info = (long)
1972 "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
1973 fail |= cvmx_error_add(&info);
1975 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1976 info.status_addr = CVMX_PIP_INT_REG;
1977 info.status_mask = 1ull<<7 /* feperr */;
1978 info.enable_addr = CVMX_PIP_INT_EN;
1979 info.enable_mask = 1ull<<7 /* feperr */;
1981 info.group = CVMX_ERROR_GROUP_INTERNAL;
1982 info.group_index = 0;
1983 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1984 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1985 info.parent.status_mask = 1ull<<20 /* pip */;
1986 info.func = __cvmx_error_display;
1987 info.user_info = (long)
1988 "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
1989 fail |= cvmx_error_add(&info);
1991 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1992 info.status_addr = CVMX_PIP_INT_REG;
1993 info.status_mask = 1ull<<8 /* beperr */;
1994 info.enable_addr = CVMX_PIP_INT_EN;
1995 info.enable_mask = 1ull<<8 /* beperr */;
1997 info.group = CVMX_ERROR_GROUP_INTERNAL;
1998 info.group_index = 0;
1999 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2000 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2001 info.parent.status_mask = 1ull<<20 /* pip */;
2002 info.func = __cvmx_error_display;
2003 info.user_info = (long)
2004 "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
2005 fail |= cvmx_error_add(&info);
2007 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2008 info.status_addr = CVMX_PIP_INT_REG;
2009 info.status_mask = 1ull<<12 /* punyerr */;
2010 info.enable_addr = CVMX_PIP_INT_EN;
2011 info.enable_mask = 1ull<<12 /* punyerr */;
2013 info.group = CVMX_ERROR_GROUP_INTERNAL;
2014 info.group_index = 0;
2015 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2016 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2017 info.parent.status_mask = 1ull<<20 /* pip */;
2018 info.func = __cvmx_error_display;
2019 info.user_info = (long)
2020 "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
2021 " stripping in IPD is enable\n";
2022 fail |= cvmx_error_add(&info);
2024 /* CVMX_PKO_REG_ERROR */
2025 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2026 info.status_addr = CVMX_PKO_REG_ERROR;
2027 info.status_mask = 1ull<<0 /* parity */;
2028 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2029 info.enable_mask = 1ull<<0 /* parity */;
2031 info.group = CVMX_ERROR_GROUP_INTERNAL;
2032 info.group_index = 0;
2033 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2034 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2035 info.parent.status_mask = 1ull<<10 /* pko */;
2036 info.func = __cvmx_error_display;
2037 info.user_info = (long)
2038 "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
2039 fail |= cvmx_error_add(&info);
2041 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2042 info.status_addr = CVMX_PKO_REG_ERROR;
2043 info.status_mask = 1ull<<1 /* doorbell */;
2044 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2045 info.enable_mask = 1ull<<1 /* doorbell */;
2047 info.group = CVMX_ERROR_GROUP_INTERNAL;
2048 info.group_index = 0;
2049 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2050 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2051 info.parent.status_mask = 1ull<<10 /* pko */;
2052 info.func = __cvmx_error_display;
2053 info.user_info = (long)
2054 "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2055 fail |= cvmx_error_add(&info);
2057 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2058 info.status_addr = CVMX_PKO_REG_ERROR;
2059 info.status_mask = 1ull<<2 /* currzero */;
2060 info.enable_addr = CVMX_PKO_REG_INT_MASK;
2061 info.enable_mask = 1ull<<2 /* currzero */;
2063 info.group = CVMX_ERROR_GROUP_INTERNAL;
2064 info.group_index = 0;
2065 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2066 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2067 info.parent.status_mask = 1ull<<10 /* pko */;
2068 info.func = __cvmx_error_display;
2069 info.user_info = (long)
2070 "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
2071 fail |= cvmx_error_add(&info);
2073 /* CVMX_PEMX_INT_SUM(0) */
2074 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2075 info.status_addr = CVMX_PEMX_INT_SUM(0);
2076 info.status_mask = 1ull<<1 /* se */;
2077 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2078 info.enable_mask = 1ull<<1 /* se */;
2080 info.group = CVMX_ERROR_GROUP_PCI;
2081 info.group_index = 0;
2082 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2083 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2084 info.parent.status_mask = 1ull<<25 /* pem0 */;
2085 info.func = __cvmx_error_display;
2086 info.user_info = (long)
2087 "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
2088 " (cfg_sys_err_rc)\n";
2089 fail |= cvmx_error_add(&info);
2091 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2092 info.status_addr = CVMX_PEMX_INT_SUM(0);
2093 info.status_mask = 1ull<<4 /* up_b1 */;
2094 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2095 info.enable_mask = 1ull<<4 /* up_b1 */;
2097 info.group = CVMX_ERROR_GROUP_PCI;
2098 info.group_index = 0;
2099 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2100 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2101 info.parent.status_mask = 1ull<<25 /* pem0 */;
2102 info.func = __cvmx_error_display;
2103 info.user_info = (long)
2104 "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
2106 fail |= cvmx_error_add(&info);
2108 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2109 info.status_addr = CVMX_PEMX_INT_SUM(0);
2110 info.status_mask = 1ull<<5 /* up_b2 */;
2111 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2112 info.enable_mask = 1ull<<5 /* up_b2 */;
2114 info.group = CVMX_ERROR_GROUP_PCI;
2115 info.group_index = 0;
2116 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2117 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2118 info.parent.status_mask = 1ull<<25 /* pem0 */;
2119 info.func = __cvmx_error_display;
2120 info.user_info = (long)
2121 "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
2122 fail |= cvmx_error_add(&info);
2124 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2125 info.status_addr = CVMX_PEMX_INT_SUM(0);
2126 info.status_mask = 1ull<<6 /* up_bx */;
2127 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2128 info.enable_mask = 1ull<<6 /* up_bx */;
2130 info.group = CVMX_ERROR_GROUP_PCI;
2131 info.group_index = 0;
2132 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2133 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2134 info.parent.status_mask = 1ull<<25 /* pem0 */;
2135 info.func = __cvmx_error_display;
2136 info.user_info = (long)
2137 "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
2138 fail |= cvmx_error_add(&info);
2140 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2141 info.status_addr = CVMX_PEMX_INT_SUM(0);
2142 info.status_mask = 1ull<<7 /* un_b1 */;
2143 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2144 info.enable_mask = 1ull<<7 /* un_b1 */;
2146 info.group = CVMX_ERROR_GROUP_PCI;
2147 info.group_index = 0;
2148 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2149 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2150 info.parent.status_mask = 1ull<<25 /* pem0 */;
2151 info.func = __cvmx_error_display;
2152 info.user_info = (long)
2153 "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
2155 fail |= cvmx_error_add(&info);
2157 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2158 info.status_addr = CVMX_PEMX_INT_SUM(0);
2159 info.status_mask = 1ull<<8 /* un_b2 */;
2160 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2161 info.enable_mask = 1ull<<8 /* un_b2 */;
2163 info.group = CVMX_ERROR_GROUP_PCI;
2164 info.group_index = 0;
2165 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2166 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2167 info.parent.status_mask = 1ull<<25 /* pem0 */;
2168 info.func = __cvmx_error_display;
2169 info.user_info = (long)
2170 "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
2171 fail |= cvmx_error_add(&info);
2173 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2174 info.status_addr = CVMX_PEMX_INT_SUM(0);
2175 info.status_mask = 1ull<<9 /* un_bx */;
2176 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2177 info.enable_mask = 1ull<<9 /* un_bx */;
2179 info.group = CVMX_ERROR_GROUP_PCI;
2180 info.group_index = 0;
2181 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2182 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2183 info.parent.status_mask = 1ull<<25 /* pem0 */;
2184 info.func = __cvmx_error_display;
2185 info.user_info = (long)
2186 "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
2187 fail |= cvmx_error_add(&info);
2189 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2190 info.status_addr = CVMX_PEMX_INT_SUM(0);
2191 info.status_mask = 1ull<<11 /* rdlk */;
2192 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2193 info.enable_mask = 1ull<<11 /* rdlk */;
2195 info.group = CVMX_ERROR_GROUP_PCI;
2196 info.group_index = 0;
2197 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2198 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2199 info.parent.status_mask = 1ull<<25 /* pem0 */;
2200 info.func = __cvmx_error_display;
2201 info.user_info = (long)
2202 "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
2203 fail |= cvmx_error_add(&info);
2205 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2206 info.status_addr = CVMX_PEMX_INT_SUM(0);
2207 info.status_mask = 1ull<<12 /* crs_er */;
2208 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2209 info.enable_mask = 1ull<<12 /* crs_er */;
2211 info.group = CVMX_ERROR_GROUP_PCI;
2212 info.group_index = 0;
2213 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2214 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2215 info.parent.status_mask = 1ull<<25 /* pem0 */;
2216 info.func = __cvmx_error_display;
2217 info.user_info = (long)
2218 "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
2219 fail |= cvmx_error_add(&info);
2221 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2222 info.status_addr = CVMX_PEMX_INT_SUM(0);
2223 info.status_mask = 1ull<<13 /* crs_dr */;
2224 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2225 info.enable_mask = 1ull<<13 /* crs_dr */;
2227 info.group = CVMX_ERROR_GROUP_PCI;
2228 info.group_index = 0;
2229 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2230 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2231 info.parent.status_mask = 1ull<<25 /* pem0 */;
2232 info.func = __cvmx_error_display;
2233 info.user_info = (long)
2234 "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
2235 fail |= cvmx_error_add(&info);
2237 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2238 info.status_addr = CVMX_PEMX_INT_SUM(0);
2239 info.status_mask = 0;
2240 info.enable_addr = 0;
2241 info.enable_mask = 0;
2243 info.group = CVMX_ERROR_GROUP_INTERNAL;
2244 info.group_index = 0;
2245 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2246 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2247 info.parent.status_mask = 1ull<<25 /* pem0 */;
2248 info.func = __cvmx_error_decode;
2250 fail |= cvmx_error_add(&info);
2252 /* CVMX_PEMX_DBG_INFO(0) */
2253 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2254 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2255 info.status_mask = 1ull<<0 /* spoison */;
2256 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2257 info.enable_mask = 1ull<<0 /* spoison */;
2259 info.group = CVMX_ERROR_GROUP_PCI;
2260 info.group_index = 0;
2261 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2262 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2263 info.parent.status_mask = 1ull<<10 /* exc */;
2264 info.func = __cvmx_error_display;
2265 info.user_info = (long)
2266 "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
2267 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
2268 fail |= cvmx_error_add(&info);
2270 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2271 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2272 info.status_mask = 1ull<<2 /* rtlplle */;
2273 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2274 info.enable_mask = 1ull<<2 /* rtlplle */;
2276 info.group = CVMX_ERROR_GROUP_PCI;
2277 info.group_index = 0;
2278 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2279 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2280 info.parent.status_mask = 1ull<<10 /* exc */;
2281 info.func = __cvmx_error_display;
2282 info.user_info = (long)
2283 "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
2284 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
2285 fail |= cvmx_error_add(&info);
2287 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2288 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2289 info.status_mask = 1ull<<3 /* recrce */;
2290 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2291 info.enable_mask = 1ull<<3 /* recrce */;
2293 info.group = CVMX_ERROR_GROUP_PCI;
2294 info.group_index = 0;
2295 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2296 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2297 info.parent.status_mask = 1ull<<10 /* exc */;
2298 info.func = __cvmx_error_display;
2299 info.user_info = (long)
2300 "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
2301 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
2302 fail |= cvmx_error_add(&info);
2304 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2305 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2306 info.status_mask = 1ull<<4 /* rpoison */;
2307 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2308 info.enable_mask = 1ull<<4 /* rpoison */;
2310 info.group = CVMX_ERROR_GROUP_PCI;
2311 info.group_index = 0;
2312 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2313 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2314 info.parent.status_mask = 1ull<<10 /* exc */;
2315 info.func = __cvmx_error_display;
2316 info.user_info = (long)
2317 "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
2318 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
2319 fail |= cvmx_error_add(&info);
2321 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2322 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2323 info.status_mask = 1ull<<5 /* rcemrc */;
2324 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2325 info.enable_mask = 1ull<<5 /* rcemrc */;
2327 info.group = CVMX_ERROR_GROUP_PCI;
2328 info.group_index = 0;
2329 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2330 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2331 info.parent.status_mask = 1ull<<10 /* exc */;
2332 info.func = __cvmx_error_display;
2333 info.user_info = (long)
2334 "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
2335 " pedc_radm_correctable_err\n";
2336 fail |= cvmx_error_add(&info);
2338 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2339 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2340 info.status_mask = 1ull<<6 /* rnfemrc */;
2341 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2342 info.enable_mask = 1ull<<6 /* rnfemrc */;
2344 info.group = CVMX_ERROR_GROUP_PCI;
2345 info.group_index = 0;
2346 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2347 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2348 info.parent.status_mask = 1ull<<10 /* exc */;
2349 info.func = __cvmx_error_display;
2350 info.user_info = (long)
2351 "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
2352 " pedc_radm_nonfatal_err\n";
2353 fail |= cvmx_error_add(&info);
2355 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2356 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2357 info.status_mask = 1ull<<7 /* rfemrc */;
2358 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2359 info.enable_mask = 1ull<<7 /* rfemrc */;
2361 info.group = CVMX_ERROR_GROUP_PCI;
2362 info.group_index = 0;
2363 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2364 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2365 info.parent.status_mask = 1ull<<10 /* exc */;
2366 info.func = __cvmx_error_display;
2367 info.user_info = (long)
2368 "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
2369 " pedc_radm_fatal_err\n"
2370 " Bit set when a message with ERR_FATAL is set.\n";
2371 fail |= cvmx_error_add(&info);
2373 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2374 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2375 info.status_mask = 1ull<<8 /* rpmerc */;
2376 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2377 info.enable_mask = 1ull<<8 /* rpmerc */;
2379 info.group = CVMX_ERROR_GROUP_PCI;
2380 info.group_index = 0;
2381 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2382 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2383 info.parent.status_mask = 1ull<<10 /* exc */;
2384 info.func = __cvmx_error_display;
2385 info.user_info = (long)
2386 "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
2387 " pedc_radm_pm_pme\n";
2388 fail |= cvmx_error_add(&info);
2390 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2391 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2392 info.status_mask = 1ull<<9 /* rptamrc */;
2393 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2394 info.enable_mask = 1ull<<9 /* rptamrc */;
2396 info.group = CVMX_ERROR_GROUP_PCI;
2397 info.group_index = 0;
2398 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2399 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2400 info.parent.status_mask = 1ull<<10 /* exc */;
2401 info.func = __cvmx_error_display;
2402 info.user_info = (long)
2403 "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
2405 " pedc_radm_pm_to_ack\n";
2406 fail |= cvmx_error_add(&info);
2408 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2409 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2410 info.status_mask = 1ull<<10 /* rumep */;
2411 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2412 info.enable_mask = 1ull<<10 /* rumep */;
2414 info.group = CVMX_ERROR_GROUP_PCI;
2415 info.group_index = 0;
2416 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2417 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2418 info.parent.status_mask = 1ull<<10 /* exc */;
2419 info.func = __cvmx_error_display;
2420 info.user_info = (long)
2421 "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
2422 " pedc_radm_msg_unlock\n";
2423 fail |= cvmx_error_add(&info);
2425 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2426 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2427 info.status_mask = 1ull<<11 /* rvdm */;
2428 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2429 info.enable_mask = 1ull<<11 /* rvdm */;
2431 info.group = CVMX_ERROR_GROUP_PCI;
2432 info.group_index = 0;
2433 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2434 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2435 info.parent.status_mask = 1ull<<10 /* exc */;
2436 info.func = __cvmx_error_display;
2437 info.user_info = (long)
2438 "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
2439 " pedc_radm_vendor_msg\n";
2440 fail |= cvmx_error_add(&info);
2442 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2443 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2444 info.status_mask = 1ull<<12 /* acto */;
2445 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2446 info.enable_mask = 1ull<<12 /* acto */;
2448 info.group = CVMX_ERROR_GROUP_PCI;
2449 info.group_index = 0;
2450 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2451 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2452 info.parent.status_mask = 1ull<<10 /* exc */;
2453 info.func = __cvmx_error_display;
2454 info.user_info = (long)
2455 "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
2456 " pedc_radm_cpl_timeout\n";
2457 fail |= cvmx_error_add(&info);
2459 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2460 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2461 info.status_mask = 1ull<<13 /* rte */;
2462 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2463 info.enable_mask = 1ull<<13 /* rte */;
2465 info.group = CVMX_ERROR_GROUP_PCI;
2466 info.group_index = 0;
2467 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2468 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2469 info.parent.status_mask = 1ull<<10 /* exc */;
2470 info.func = __cvmx_error_display;
2471 info.user_info = (long)
2472 "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
2473 " xdlh_replay_timeout_err\n"
2474 " This bit is set when the REPLAY_TIMER expires in\n"
2475 " the PCIE core. The probability of this bit being\n"
2476 " set will increase with the traffic load.\n";
2477 fail |= cvmx_error_add(&info);
2479 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2480 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2481 info.status_mask = 1ull<<14 /* mre */;
2482 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2483 info.enable_mask = 1ull<<14 /* mre */;
2485 info.group = CVMX_ERROR_GROUP_PCI;
2486 info.group_index = 0;
2487 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2488 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2489 info.parent.status_mask = 1ull<<10 /* exc */;
2490 info.func = __cvmx_error_display;
2491 info.user_info = (long)
2492 "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
2493 " xdlh_replay_num_rlover_err\n";
2494 fail |= cvmx_error_add(&info);
2496 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2497 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2498 info.status_mask = 1ull<<15 /* rdwdle */;
2499 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2500 info.enable_mask = 1ull<<15 /* rdwdle */;
2502 info.group = CVMX_ERROR_GROUP_PCI;
2503 info.group_index = 0;
2504 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2505 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2506 info.parent.status_mask = 1ull<<10 /* exc */;
2507 info.func = __cvmx_error_display;
2508 info.user_info = (long)
2509 "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
2510 " rdlh_bad_dllp_err\n";
2511 fail |= cvmx_error_add(&info);
2513 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2514 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2515 info.status_mask = 1ull<<16 /* rtwdle */;
2516 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2517 info.enable_mask = 1ull<<16 /* rtwdle */;
2519 info.group = CVMX_ERROR_GROUP_PCI;
2520 info.group_index = 0;
2521 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2522 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2523 info.parent.status_mask = 1ull<<10 /* exc */;
2524 info.func = __cvmx_error_display;
2525 info.user_info = (long)
2526 "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
2527 " rdlh_bad_tlp_err\n";
2528 fail |= cvmx_error_add(&info);
2530 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2531 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2532 info.status_mask = 1ull<<17 /* dpeoosd */;
2533 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2534 info.enable_mask = 1ull<<17 /* dpeoosd */;
2536 info.group = CVMX_ERROR_GROUP_PCI;
2537 info.group_index = 0;
2538 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2539 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2540 info.parent.status_mask = 1ull<<10 /* exc */;
2541 info.func = __cvmx_error_display;
2542 info.user_info = (long)
2543 "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
2545 fail |= cvmx_error_add(&info);
2547 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2548 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2549 info.status_mask = 1ull<<18 /* fcpvwt */;
2550 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2551 info.enable_mask = 1ull<<18 /* fcpvwt */;
2553 info.group = CVMX_ERROR_GROUP_PCI;
2554 info.group_index = 0;
2555 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2556 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2557 info.parent.status_mask = 1ull<<10 /* exc */;
2558 info.func = __cvmx_error_display;
2559 info.user_info = (long)
2560 "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
2561 " rtlh_fc_prot_err\n";
2562 fail |= cvmx_error_add(&info);
2564 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2565 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2566 info.status_mask = 1ull<<19 /* rpe */;
2567 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2568 info.enable_mask = 1ull<<19 /* rpe */;
2570 info.group = CVMX_ERROR_GROUP_PCI;
2571 info.group_index = 0;
2572 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2573 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2574 info.parent.status_mask = 1ull<<10 /* exc */;
2575 info.func = __cvmx_error_display;
2576 info.user_info = (long)
2577 "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
2578 " (RxStatus = 3b100) or disparity error\n"
2579 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
2582 fail |= cvmx_error_add(&info);
2584 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2585 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2586 info.status_mask = 1ull<<20 /* fcuv */;
2587 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2588 info.enable_mask = 1ull<<20 /* fcuv */;
2590 info.group = CVMX_ERROR_GROUP_PCI;
2591 info.group_index = 0;
2592 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2593 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2594 info.parent.status_mask = 1ull<<10 /* exc */;
2595 info.func = __cvmx_error_display;
2596 info.user_info = (long)
2597 "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
2598 " int_xadm_fc_prot_err\n";
2599 fail |= cvmx_error_add(&info);
2601 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2602 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2603 info.status_mask = 1ull<<21 /* rqo */;
2604 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2605 info.enable_mask = 1ull<<21 /* rqo */;
2607 info.group = CVMX_ERROR_GROUP_PCI;
2608 info.group_index = 0;
2609 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2610 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2611 info.parent.status_mask = 1ull<<10 /* exc */;
2612 info.func = __cvmx_error_display;
2613 info.user_info = (long)
2614 "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
2615 " flow control advertisements are ignored\n"
2616 " radm_qoverflow\n";
2617 fail |= cvmx_error_add(&info);
2619 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2620 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2621 info.status_mask = 1ull<<22 /* rauc */;
2622 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2623 info.enable_mask = 1ull<<22 /* rauc */;
2625 info.group = CVMX_ERROR_GROUP_PCI;
2626 info.group_index = 0;
2627 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2628 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2629 info.parent.status_mask = 1ull<<10 /* exc */;
2630 info.func = __cvmx_error_display;
2631 info.user_info = (long)
2632 "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
2633 " radm_unexp_cpl_err\n";
2634 fail |= cvmx_error_add(&info);
2636 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2637 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2638 info.status_mask = 1ull<<23 /* racur */;
2639 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2640 info.enable_mask = 1ull<<23 /* racur */;
2642 info.group = CVMX_ERROR_GROUP_PCI;
2643 info.group_index = 0;
2644 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2645 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2646 info.parent.status_mask = 1ull<<10 /* exc */;
2647 info.func = __cvmx_error_display;
2648 info.user_info = (long)
2649 "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
2650 " radm_rcvd_cpl_ur\n";
2651 fail |= cvmx_error_add(&info);
2653 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2654 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2655 info.status_mask = 1ull<<24 /* racca */;
2656 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2657 info.enable_mask = 1ull<<24 /* racca */;
2659 info.group = CVMX_ERROR_GROUP_PCI;
2660 info.group_index = 0;
2661 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2662 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2663 info.parent.status_mask = 1ull<<10 /* exc */;
2664 info.func = __cvmx_error_display;
2665 info.user_info = (long)
2666 "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
2667 " radm_rcvd_cpl_ca\n";
2668 fail |= cvmx_error_add(&info);
2670 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2671 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2672 info.status_mask = 1ull<<25 /* caar */;
2673 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2674 info.enable_mask = 1ull<<25 /* caar */;
2676 info.group = CVMX_ERROR_GROUP_PCI;
2677 info.group_index = 0;
2678 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2679 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2680 info.parent.status_mask = 1ull<<10 /* exc */;
2681 info.func = __cvmx_error_display;
2682 info.user_info = (long)
2683 "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
2684 " radm_rcvd_ca_req\n"
2685 " This bit will never be set because Octeon does\n"
2686 " not generate Completer Aborts.\n";
2687 fail |= cvmx_error_add(&info);
2689 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2690 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2691 info.status_mask = 1ull<<26 /* rarwdns */;
2692 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2693 info.enable_mask = 1ull<<26 /* rarwdns */;
2695 info.group = CVMX_ERROR_GROUP_PCI;
2696 info.group_index = 0;
2697 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2698 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2699 info.parent.status_mask = 1ull<<10 /* exc */;
2700 info.func = __cvmx_error_display;
2701 info.user_info = (long)
2702 "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
2703 " radm_rcvd_ur_req\n";
2704 fail |= cvmx_error_add(&info);
2706 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2707 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2708 info.status_mask = 1ull<<27 /* ramtlp */;
2709 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2710 info.enable_mask = 1ull<<27 /* ramtlp */;
2712 info.group = CVMX_ERROR_GROUP_PCI;
2713 info.group_index = 0;
2714 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2715 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2716 info.parent.status_mask = 1ull<<10 /* exc */;
2717 info.func = __cvmx_error_display;
2718 info.user_info = (long)
2719 "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
2720 " radm_mlf_tlp_err\n";
2721 fail |= cvmx_error_add(&info);
2723 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2724 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2725 info.status_mask = 1ull<<28 /* racpp */;
2726 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2727 info.enable_mask = 1ull<<28 /* racpp */;
2729 info.group = CVMX_ERROR_GROUP_PCI;
2730 info.group_index = 0;
2731 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2732 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2733 info.parent.status_mask = 1ull<<10 /* exc */;
2734 info.func = __cvmx_error_display;
2735 info.user_info = (long)
2736 "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
2737 " radm_rcvd_cpl_poisoned\n";
2738 fail |= cvmx_error_add(&info);
2740 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2741 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2742 info.status_mask = 1ull<<29 /* rawwpp */;
2743 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2744 info.enable_mask = 1ull<<29 /* rawwpp */;
2746 info.group = CVMX_ERROR_GROUP_PCI;
2747 info.group_index = 0;
2748 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2749 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2750 info.parent.status_mask = 1ull<<10 /* exc */;
2751 info.func = __cvmx_error_display;
2752 info.user_info = (long)
2753 "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
2754 " radm_rcvd_wreq_poisoned\n";
2755 fail |= cvmx_error_add(&info);
2757 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2758 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2759 info.status_mask = 1ull<<30 /* ecrc_e */;
2760 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2761 info.enable_mask = 1ull<<30 /* ecrc_e */;
2763 info.group = CVMX_ERROR_GROUP_PCI;
2764 info.group_index = 0;
2765 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2766 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2767 info.parent.status_mask = 1ull<<10 /* exc */;
2768 info.func = __cvmx_error_display;
2769 info.user_info = (long)
2770 "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
2772 fail |= cvmx_error_add(&info);
2774 /* CVMX_PEMX_INT_SUM(1) */
2775 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2776 info.status_addr = CVMX_PEMX_INT_SUM(1);
2777 info.status_mask = 1ull<<1 /* se */;
2778 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2779 info.enable_mask = 1ull<<1 /* se */;
2781 info.group = CVMX_ERROR_GROUP_PCI;
2782 info.group_index = 1;
2783 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2784 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2785 info.parent.status_mask = 1ull<<26 /* pem1 */;
2786 info.func = __cvmx_error_display;
2787 info.user_info = (long)
2788 "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
2789 " (cfg_sys_err_rc)\n";
2790 fail |= cvmx_error_add(&info);
2792 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2793 info.status_addr = CVMX_PEMX_INT_SUM(1);
2794 info.status_mask = 1ull<<4 /* up_b1 */;
2795 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2796 info.enable_mask = 1ull<<4 /* up_b1 */;
2798 info.group = CVMX_ERROR_GROUP_PCI;
2799 info.group_index = 1;
2800 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2801 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2802 info.parent.status_mask = 1ull<<26 /* pem1 */;
2803 info.func = __cvmx_error_display;
2804 info.user_info = (long)
2805 "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
2807 fail |= cvmx_error_add(&info);
2809 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2810 info.status_addr = CVMX_PEMX_INT_SUM(1);
2811 info.status_mask = 1ull<<5 /* up_b2 */;
2812 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2813 info.enable_mask = 1ull<<5 /* up_b2 */;
2815 info.group = CVMX_ERROR_GROUP_PCI;
2816 info.group_index = 1;
2817 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2818 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2819 info.parent.status_mask = 1ull<<26 /* pem1 */;
2820 info.func = __cvmx_error_display;
2821 info.user_info = (long)
2822 "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
2823 fail |= cvmx_error_add(&info);
2825 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2826 info.status_addr = CVMX_PEMX_INT_SUM(1);
2827 info.status_mask = 1ull<<6 /* up_bx */;
2828 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2829 info.enable_mask = 1ull<<6 /* up_bx */;
2831 info.group = CVMX_ERROR_GROUP_PCI;
2832 info.group_index = 1;
2833 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2834 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2835 info.parent.status_mask = 1ull<<26 /* pem1 */;
2836 info.func = __cvmx_error_display;
2837 info.user_info = (long)
2838 "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
2839 fail |= cvmx_error_add(&info);
2841 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2842 info.status_addr = CVMX_PEMX_INT_SUM(1);
2843 info.status_mask = 1ull<<7 /* un_b1 */;
2844 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2845 info.enable_mask = 1ull<<7 /* un_b1 */;
2847 info.group = CVMX_ERROR_GROUP_PCI;
2848 info.group_index = 1;
2849 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2850 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2851 info.parent.status_mask = 1ull<<26 /* pem1 */;
2852 info.func = __cvmx_error_display;
2853 info.user_info = (long)
2854 "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
2856 fail |= cvmx_error_add(&info);
2858 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2859 info.status_addr = CVMX_PEMX_INT_SUM(1);
2860 info.status_mask = 1ull<<8 /* un_b2 */;
2861 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2862 info.enable_mask = 1ull<<8 /* un_b2 */;
2864 info.group = CVMX_ERROR_GROUP_PCI;
2865 info.group_index = 1;
2866 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2867 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2868 info.parent.status_mask = 1ull<<26 /* pem1 */;
2869 info.func = __cvmx_error_display;
2870 info.user_info = (long)
2871 "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
2872 fail |= cvmx_error_add(&info);
2874 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2875 info.status_addr = CVMX_PEMX_INT_SUM(1);
2876 info.status_mask = 1ull<<9 /* un_bx */;
2877 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2878 info.enable_mask = 1ull<<9 /* un_bx */;
2880 info.group = CVMX_ERROR_GROUP_PCI;
2881 info.group_index = 1;
2882 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2883 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2884 info.parent.status_mask = 1ull<<26 /* pem1 */;
2885 info.func = __cvmx_error_display;
2886 info.user_info = (long)
2887 "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
2888 fail |= cvmx_error_add(&info);
2890 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2891 info.status_addr = CVMX_PEMX_INT_SUM(1);
2892 info.status_mask = 1ull<<11 /* rdlk */;
2893 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2894 info.enable_mask = 1ull<<11 /* rdlk */;
2896 info.group = CVMX_ERROR_GROUP_PCI;
2897 info.group_index = 1;
2898 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2899 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2900 info.parent.status_mask = 1ull<<26 /* pem1 */;
2901 info.func = __cvmx_error_display;
2902 info.user_info = (long)
2903 "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
2904 fail |= cvmx_error_add(&info);
2906 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2907 info.status_addr = CVMX_PEMX_INT_SUM(1);
2908 info.status_mask = 1ull<<12 /* crs_er */;
2909 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2910 info.enable_mask = 1ull<<12 /* crs_er */;
2912 info.group = CVMX_ERROR_GROUP_PCI;
2913 info.group_index = 1;
2914 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2915 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2916 info.parent.status_mask = 1ull<<26 /* pem1 */;
2917 info.func = __cvmx_error_display;
2918 info.user_info = (long)
2919 "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
2920 fail |= cvmx_error_add(&info);
2922 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2923 info.status_addr = CVMX_PEMX_INT_SUM(1);
2924 info.status_mask = 1ull<<13 /* crs_dr */;
2925 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2926 info.enable_mask = 1ull<<13 /* crs_dr */;
2928 info.group = CVMX_ERROR_GROUP_PCI;
2929 info.group_index = 1;
2930 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2931 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2932 info.parent.status_mask = 1ull<<26 /* pem1 */;
2933 info.func = __cvmx_error_display;
2934 info.user_info = (long)
2935 "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
2936 fail |= cvmx_error_add(&info);
2938 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2939 info.status_addr = CVMX_PEMX_INT_SUM(1);
2940 info.status_mask = 0;
2941 info.enable_addr = 0;
2942 info.enable_mask = 0;
2944 info.group = CVMX_ERROR_GROUP_INTERNAL;
2945 info.group_index = 0;
2946 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2947 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2948 info.parent.status_mask = 1ull<<26 /* pem1 */;
2949 info.func = __cvmx_error_decode;
2951 fail |= cvmx_error_add(&info);
2953 /* CVMX_PEMX_DBG_INFO(1) */
2954 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2955 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2956 info.status_mask = 1ull<<0 /* spoison */;
2957 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2958 info.enable_mask = 1ull<<0 /* spoison */;
2960 info.group = CVMX_ERROR_GROUP_PCI;
2961 info.group_index = 1;
2962 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2963 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2964 info.parent.status_mask = 1ull<<10 /* exc */;
2965 info.func = __cvmx_error_display;
2966 info.user_info = (long)
2967 "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
2968 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
2969 fail |= cvmx_error_add(&info);
2971 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2972 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2973 info.status_mask = 1ull<<2 /* rtlplle */;
2974 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2975 info.enable_mask = 1ull<<2 /* rtlplle */;
2977 info.group = CVMX_ERROR_GROUP_PCI;
2978 info.group_index = 1;
2979 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2980 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2981 info.parent.status_mask = 1ull<<10 /* exc */;
2982 info.func = __cvmx_error_display;
2983 info.user_info = (long)
2984 "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
2985 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
2986 fail |= cvmx_error_add(&info);
2988 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2989 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2990 info.status_mask = 1ull<<3 /* recrce */;
2991 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2992 info.enable_mask = 1ull<<3 /* recrce */;
2994 info.group = CVMX_ERROR_GROUP_PCI;
2995 info.group_index = 1;
2996 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2997 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2998 info.parent.status_mask = 1ull<<10 /* exc */;
2999 info.func = __cvmx_error_display;
3000 info.user_info = (long)
3001 "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
3002 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3003 fail |= cvmx_error_add(&info);
3005 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3006 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3007 info.status_mask = 1ull<<4 /* rpoison */;
3008 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3009 info.enable_mask = 1ull<<4 /* rpoison */;
3011 info.group = CVMX_ERROR_GROUP_PCI;
3012 info.group_index = 1;
3013 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3014 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3015 info.parent.status_mask = 1ull<<10 /* exc */;
3016 info.func = __cvmx_error_display;
3017 info.user_info = (long)
3018 "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
3019 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3020 fail |= cvmx_error_add(&info);
3022 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3023 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3024 info.status_mask = 1ull<<5 /* rcemrc */;
3025 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3026 info.enable_mask = 1ull<<5 /* rcemrc */;
3028 info.group = CVMX_ERROR_GROUP_PCI;
3029 info.group_index = 1;
3030 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3031 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3032 info.parent.status_mask = 1ull<<10 /* exc */;
3033 info.func = __cvmx_error_display;
3034 info.user_info = (long)
3035 "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
3036 " pedc_radm_correctable_err\n";
3037 fail |= cvmx_error_add(&info);
3039 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3040 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3041 info.status_mask = 1ull<<6 /* rnfemrc */;
3042 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3043 info.enable_mask = 1ull<<6 /* rnfemrc */;
3045 info.group = CVMX_ERROR_GROUP_PCI;
3046 info.group_index = 1;
3047 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3048 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3049 info.parent.status_mask = 1ull<<10 /* exc */;
3050 info.func = __cvmx_error_display;
3051 info.user_info = (long)
3052 "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3053 " pedc_radm_nonfatal_err\n";
3054 fail |= cvmx_error_add(&info);
3056 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3057 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3058 info.status_mask = 1ull<<7 /* rfemrc */;
3059 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3060 info.enable_mask = 1ull<<7 /* rfemrc */;
3062 info.group = CVMX_ERROR_GROUP_PCI;
3063 info.group_index = 1;
3064 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3065 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3066 info.parent.status_mask = 1ull<<10 /* exc */;
3067 info.func = __cvmx_error_display;
3068 info.user_info = (long)
3069 "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3070 " pedc_radm_fatal_err\n"
3071 " Bit set when a message with ERR_FATAL is set.\n";
3072 fail |= cvmx_error_add(&info);
3074 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3075 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3076 info.status_mask = 1ull<<8 /* rpmerc */;
3077 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3078 info.enable_mask = 1ull<<8 /* rpmerc */;
3080 info.group = CVMX_ERROR_GROUP_PCI;
3081 info.group_index = 1;
3082 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3083 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3084 info.parent.status_mask = 1ull<<10 /* exc */;
3085 info.func = __cvmx_error_display;
3086 info.user_info = (long)
3087 "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
3088 " pedc_radm_pm_pme\n";
3089 fail |= cvmx_error_add(&info);
3091 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3092 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3093 info.status_mask = 1ull<<9 /* rptamrc */;
3094 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3095 info.enable_mask = 1ull<<9 /* rptamrc */;
3097 info.group = CVMX_ERROR_GROUP_PCI;
3098 info.group_index = 1;
3099 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3100 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3101 info.parent.status_mask = 1ull<<10 /* exc */;
3102 info.func = __cvmx_error_display;
3103 info.user_info = (long)
3104 "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3106 " pedc_radm_pm_to_ack\n";
3107 fail |= cvmx_error_add(&info);
3109 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3110 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3111 info.status_mask = 1ull<<10 /* rumep */;
3112 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3113 info.enable_mask = 1ull<<10 /* rumep */;
3115 info.group = CVMX_ERROR_GROUP_PCI;
3116 info.group_index = 1;
3117 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3118 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3119 info.parent.status_mask = 1ull<<10 /* exc */;
3120 info.func = __cvmx_error_display;
3121 info.user_info = (long)
3122 "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
3123 " pedc_radm_msg_unlock\n";
3124 fail |= cvmx_error_add(&info);
3126 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3127 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3128 info.status_mask = 1ull<<11 /* rvdm */;
3129 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3130 info.enable_mask = 1ull<<11 /* rvdm */;
3132 info.group = CVMX_ERROR_GROUP_PCI;
3133 info.group_index = 1;
3134 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3135 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3136 info.parent.status_mask = 1ull<<10 /* exc */;
3137 info.func = __cvmx_error_display;
3138 info.user_info = (long)
3139 "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
3140 " pedc_radm_vendor_msg\n";
3141 fail |= cvmx_error_add(&info);
3143 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3144 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3145 info.status_mask = 1ull<<12 /* acto */;
3146 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3147 info.enable_mask = 1ull<<12 /* acto */;
3149 info.group = CVMX_ERROR_GROUP_PCI;
3150 info.group_index = 1;
3151 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3152 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3153 info.parent.status_mask = 1ull<<10 /* exc */;
3154 info.func = __cvmx_error_display;
3155 info.user_info = (long)
3156 "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
3157 " pedc_radm_cpl_timeout\n";
3158 fail |= cvmx_error_add(&info);
3160 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3161 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3162 info.status_mask = 1ull<<13 /* rte */;
3163 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3164 info.enable_mask = 1ull<<13 /* rte */;
3166 info.group = CVMX_ERROR_GROUP_PCI;
3167 info.group_index = 1;
3168 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3169 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3170 info.parent.status_mask = 1ull<<10 /* exc */;
3171 info.func = __cvmx_error_display;
3172 info.user_info = (long)
3173 "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
3174 " xdlh_replay_timeout_err\n"
3175 " This bit is set when the REPLAY_TIMER expires in\n"
3176 " the PCIE core. The probability of this bit being\n"
3177 " set will increase with the traffic load.\n";
3178 fail |= cvmx_error_add(&info);
3180 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3181 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3182 info.status_mask = 1ull<<14 /* mre */;
3183 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3184 info.enable_mask = 1ull<<14 /* mre */;
3186 info.group = CVMX_ERROR_GROUP_PCI;
3187 info.group_index = 1;
3188 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3189 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3190 info.parent.status_mask = 1ull<<10 /* exc */;
3191 info.func = __cvmx_error_display;
3192 info.user_info = (long)
3193 "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
3194 " xdlh_replay_num_rlover_err\n";
3195 fail |= cvmx_error_add(&info);
3197 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3198 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3199 info.status_mask = 1ull<<15 /* rdwdle */;
3200 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3201 info.enable_mask = 1ull<<15 /* rdwdle */;
3203 info.group = CVMX_ERROR_GROUP_PCI;
3204 info.group_index = 1;
3205 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3206 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3207 info.parent.status_mask = 1ull<<10 /* exc */;
3208 info.func = __cvmx_error_display;
3209 info.user_info = (long)
3210 "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
3211 " rdlh_bad_dllp_err\n";
3212 fail |= cvmx_error_add(&info);
3214 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3215 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3216 info.status_mask = 1ull<<16 /* rtwdle */;
3217 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3218 info.enable_mask = 1ull<<16 /* rtwdle */;
3220 info.group = CVMX_ERROR_GROUP_PCI;
3221 info.group_index = 1;
3222 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3223 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3224 info.parent.status_mask = 1ull<<10 /* exc */;
3225 info.func = __cvmx_error_display;
3226 info.user_info = (long)
3227 "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
3228 " rdlh_bad_tlp_err\n";
3229 fail |= cvmx_error_add(&info);
3231 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3232 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3233 info.status_mask = 1ull<<17 /* dpeoosd */;
3234 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3235 info.enable_mask = 1ull<<17 /* dpeoosd */;
3237 info.group = CVMX_ERROR_GROUP_PCI;
3238 info.group_index = 1;
3239 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3240 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3241 info.parent.status_mask = 1ull<<10 /* exc */;
3242 info.func = __cvmx_error_display;
3243 info.user_info = (long)
3244 "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
3246 fail |= cvmx_error_add(&info);
3248 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3249 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3250 info.status_mask = 1ull<<18 /* fcpvwt */;
3251 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3252 info.enable_mask = 1ull<<18 /* fcpvwt */;
3254 info.group = CVMX_ERROR_GROUP_PCI;
3255 info.group_index = 1;
3256 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3257 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3258 info.parent.status_mask = 1ull<<10 /* exc */;
3259 info.func = __cvmx_error_display;
3260 info.user_info = (long)
3261 "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
3262 " rtlh_fc_prot_err\n";
3263 fail |= cvmx_error_add(&info);
3265 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3266 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3267 info.status_mask = 1ull<<19 /* rpe */;
3268 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3269 info.enable_mask = 1ull<<19 /* rpe */;
3271 info.group = CVMX_ERROR_GROUP_PCI;
3272 info.group_index = 1;
3273 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3274 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3275 info.parent.status_mask = 1ull<<10 /* exc */;
3276 info.func = __cvmx_error_display;
3277 info.user_info = (long)
3278 "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
3279 " (RxStatus = 3b100) or disparity error\n"
3280 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
3283 fail |= cvmx_error_add(&info);
3285 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3286 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3287 info.status_mask = 1ull<<20 /* fcuv */;
3288 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3289 info.enable_mask = 1ull<<20 /* fcuv */;
3291 info.group = CVMX_ERROR_GROUP_PCI;
3292 info.group_index = 1;
3293 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3294 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3295 info.parent.status_mask = 1ull<<10 /* exc */;
3296 info.func = __cvmx_error_display;
3297 info.user_info = (long)
3298 "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
3299 " int_xadm_fc_prot_err\n";
3300 fail |= cvmx_error_add(&info);
3302 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3303 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3304 info.status_mask = 1ull<<21 /* rqo */;
3305 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3306 info.enable_mask = 1ull<<21 /* rqo */;
3308 info.group = CVMX_ERROR_GROUP_PCI;
3309 info.group_index = 1;
3310 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3311 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3312 info.parent.status_mask = 1ull<<10 /* exc */;
3313 info.func = __cvmx_error_display;
3314 info.user_info = (long)
3315 "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
3316 " flow control advertisements are ignored\n"
3317 " radm_qoverflow\n";
3318 fail |= cvmx_error_add(&info);
3320 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3321 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3322 info.status_mask = 1ull<<22 /* rauc */;
3323 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3324 info.enable_mask = 1ull<<22 /* rauc */;
3326 info.group = CVMX_ERROR_GROUP_PCI;
3327 info.group_index = 1;
3328 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3329 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3330 info.parent.status_mask = 1ull<<10 /* exc */;
3331 info.func = __cvmx_error_display;
3332 info.user_info = (long)
3333 "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
3334 " radm_unexp_cpl_err\n";
3335 fail |= cvmx_error_add(&info);
3337 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3338 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3339 info.status_mask = 1ull<<23 /* racur */;
3340 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3341 info.enable_mask = 1ull<<23 /* racur */;
3343 info.group = CVMX_ERROR_GROUP_PCI;
3344 info.group_index = 1;
3345 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3346 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3347 info.parent.status_mask = 1ull<<10 /* exc */;
3348 info.func = __cvmx_error_display;
3349 info.user_info = (long)
3350 "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
3351 " radm_rcvd_cpl_ur\n";
3352 fail |= cvmx_error_add(&info);
3354 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3355 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3356 info.status_mask = 1ull<<24 /* racca */;
3357 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3358 info.enable_mask = 1ull<<24 /* racca */;
3360 info.group = CVMX_ERROR_GROUP_PCI;
3361 info.group_index = 1;
3362 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3363 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3364 info.parent.status_mask = 1ull<<10 /* exc */;
3365 info.func = __cvmx_error_display;
3366 info.user_info = (long)
3367 "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
3368 " radm_rcvd_cpl_ca\n";
3369 fail |= cvmx_error_add(&info);
3371 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3372 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3373 info.status_mask = 1ull<<25 /* caar */;
3374 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3375 info.enable_mask = 1ull<<25 /* caar */;
3377 info.group = CVMX_ERROR_GROUP_PCI;
3378 info.group_index = 1;
3379 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3380 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3381 info.parent.status_mask = 1ull<<10 /* exc */;
3382 info.func = __cvmx_error_display;
3383 info.user_info = (long)
3384 "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
3385 " radm_rcvd_ca_req\n"
3386 " This bit will never be set because Octeon does\n"
3387 " not generate Completer Aborts.\n";
3388 fail |= cvmx_error_add(&info);
3390 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3391 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3392 info.status_mask = 1ull<<26 /* rarwdns */;
3393 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3394 info.enable_mask = 1ull<<26 /* rarwdns */;
3396 info.group = CVMX_ERROR_GROUP_PCI;
3397 info.group_index = 1;
3398 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3399 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3400 info.parent.status_mask = 1ull<<10 /* exc */;
3401 info.func = __cvmx_error_display;
3402 info.user_info = (long)
3403 "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
3404 " radm_rcvd_ur_req\n";
3405 fail |= cvmx_error_add(&info);
3407 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3408 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3409 info.status_mask = 1ull<<27 /* ramtlp */;
3410 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3411 info.enable_mask = 1ull<<27 /* ramtlp */;
3413 info.group = CVMX_ERROR_GROUP_PCI;
3414 info.group_index = 1;
3415 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3416 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3417 info.parent.status_mask = 1ull<<10 /* exc */;
3418 info.func = __cvmx_error_display;
3419 info.user_info = (long)
3420 "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
3421 " radm_mlf_tlp_err\n";
3422 fail |= cvmx_error_add(&info);
3424 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3425 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3426 info.status_mask = 1ull<<28 /* racpp */;
3427 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3428 info.enable_mask = 1ull<<28 /* racpp */;
3430 info.group = CVMX_ERROR_GROUP_PCI;
3431 info.group_index = 1;
3432 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3433 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3434 info.parent.status_mask = 1ull<<10 /* exc */;
3435 info.func = __cvmx_error_display;
3436 info.user_info = (long)
3437 "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
3438 " radm_rcvd_cpl_poisoned\n";
3439 fail |= cvmx_error_add(&info);
3441 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3442 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3443 info.status_mask = 1ull<<29 /* rawwpp */;
3444 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3445 info.enable_mask = 1ull<<29 /* rawwpp */;
3447 info.group = CVMX_ERROR_GROUP_PCI;
3448 info.group_index = 1;
3449 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3450 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3451 info.parent.status_mask = 1ull<<10 /* exc */;
3452 info.func = __cvmx_error_display;
3453 info.user_info = (long)
3454 "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
3455 " radm_rcvd_wreq_poisoned\n";
3456 fail |= cvmx_error_add(&info);
3458 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3459 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3460 info.status_mask = 1ull<<30 /* ecrc_e */;
3461 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3462 info.enable_mask = 1ull<<30 /* ecrc_e */;
3464 info.group = CVMX_ERROR_GROUP_PCI;
3465 info.group_index = 1;
3466 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3467 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3468 info.parent.status_mask = 1ull<<10 /* exc */;
3469 info.func = __cvmx_error_display;
3470 info.user_info = (long)
3471 "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
3473 fail |= cvmx_error_add(&info);
3475 /* CVMX_FPA_INT_SUM */
3476 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3477 info.status_addr = CVMX_FPA_INT_SUM;
3478 info.status_mask = 1ull<<0 /* fed0_sbe */;
3479 info.enable_addr = CVMX_FPA_INT_ENB;
3480 info.enable_mask = 1ull<<0 /* fed0_sbe */;
3482 info.group = CVMX_ERROR_GROUP_INTERNAL;
3483 info.group_index = 0;
3484 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3485 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3486 info.parent.status_mask = 1ull<<5 /* fpa */;
3487 info.func = __cvmx_error_display;
3488 info.user_info = (long)
3489 "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
3490 fail |= cvmx_error_add(&info);
3492 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3493 info.status_addr = CVMX_FPA_INT_SUM;
3494 info.status_mask = 1ull<<1 /* fed0_dbe */;
3495 info.enable_addr = CVMX_FPA_INT_ENB;
3496 info.enable_mask = 1ull<<1 /* fed0_dbe */;
3498 info.group = CVMX_ERROR_GROUP_INTERNAL;
3499 info.group_index = 0;
3500 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3501 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3502 info.parent.status_mask = 1ull<<5 /* fpa */;
3503 info.func = __cvmx_error_display;
3504 info.user_info = (long)
3505 "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
3506 fail |= cvmx_error_add(&info);
3508 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3509 info.status_addr = CVMX_FPA_INT_SUM;
3510 info.status_mask = 1ull<<2 /* fed1_sbe */;
3511 info.enable_addr = CVMX_FPA_INT_ENB;
3512 info.enable_mask = 1ull<<2 /* fed1_sbe */;
3514 info.group = CVMX_ERROR_GROUP_INTERNAL;
3515 info.group_index = 0;
3516 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3517 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3518 info.parent.status_mask = 1ull<<5 /* fpa */;
3519 info.func = __cvmx_error_display;
3520 info.user_info = (long)
3521 "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
3522 fail |= cvmx_error_add(&info);
3524 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3525 info.status_addr = CVMX_FPA_INT_SUM;
3526 info.status_mask = 1ull<<3 /* fed1_dbe */;
3527 info.enable_addr = CVMX_FPA_INT_ENB;
3528 info.enable_mask = 1ull<<3 /* fed1_dbe */;
3530 info.group = CVMX_ERROR_GROUP_INTERNAL;
3531 info.group_index = 0;
3532 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3533 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3534 info.parent.status_mask = 1ull<<5 /* fpa */;
3535 info.func = __cvmx_error_display;
3536 info.user_info = (long)
3537 "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
3538 fail |= cvmx_error_add(&info);
3540 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3541 info.status_addr = CVMX_FPA_INT_SUM;
3542 info.status_mask = 1ull<<4 /* q0_und */;
3543 info.enable_addr = CVMX_FPA_INT_ENB;
3544 info.enable_mask = 1ull<<4 /* q0_und */;
3546 info.group = CVMX_ERROR_GROUP_INTERNAL;
3547 info.group_index = 0;
3548 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3549 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3550 info.parent.status_mask = 1ull<<5 /* fpa */;
3551 info.func = __cvmx_error_display;
3552 info.user_info = (long)
3553 "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
3555 fail |= cvmx_error_add(&info);
3557 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3558 info.status_addr = CVMX_FPA_INT_SUM;
3559 info.status_mask = 1ull<<5 /* q0_coff */;
3560 info.enable_addr = CVMX_FPA_INT_ENB;
3561 info.enable_mask = 1ull<<5 /* q0_coff */;
3563 info.group = CVMX_ERROR_GROUP_INTERNAL;
3564 info.group_index = 0;
3565 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3566 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3567 info.parent.status_mask = 1ull<<5 /* fpa */;
3568 info.func = __cvmx_error_display;
3569 info.user_info = (long)
3570 "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
3571 " the count available is greater than pointers\n"
3572 " present in the FPA.\n";
3573 fail |= cvmx_error_add(&info);
3575 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3576 info.status_addr = CVMX_FPA_INT_SUM;
3577 info.status_mask = 1ull<<6 /* q0_perr */;
3578 info.enable_addr = CVMX_FPA_INT_ENB;
3579 info.enable_mask = 1ull<<6 /* q0_perr */;
3581 info.group = CVMX_ERROR_GROUP_INTERNAL;
3582 info.group_index = 0;
3583 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3584 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3585 info.parent.status_mask = 1ull<<5 /* fpa */;
3586 info.func = __cvmx_error_display;
3587 info.user_info = (long)
3588 "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
3589 " the L2C does not have the FPA owner ship bit set.\n";
3590 fail |= cvmx_error_add(&info);
3592 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3593 info.status_addr = CVMX_FPA_INT_SUM;
3594 info.status_mask = 1ull<<7 /* q1_und */;
3595 info.enable_addr = CVMX_FPA_INT_ENB;
3596 info.enable_mask = 1ull<<7 /* q1_und */;
3598 info.group = CVMX_ERROR_GROUP_INTERNAL;
3599 info.group_index = 0;
3600 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3601 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3602 info.parent.status_mask = 1ull<<5 /* fpa */;
3603 info.func = __cvmx_error_display;
3604 info.user_info = (long)
3605 "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
3607 fail |= cvmx_error_add(&info);
3609 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3610 info.status_addr = CVMX_FPA_INT_SUM;
3611 info.status_mask = 1ull<<8 /* q1_coff */;
3612 info.enable_addr = CVMX_FPA_INT_ENB;
3613 info.enable_mask = 1ull<<8 /* q1_coff */;
3615 info.group = CVMX_ERROR_GROUP_INTERNAL;
3616 info.group_index = 0;
3617 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3618 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3619 info.parent.status_mask = 1ull<<5 /* fpa */;
3620 info.func = __cvmx_error_display;
3621 info.user_info = (long)
3622 "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
3623 " the count available is greater than pointers\n"
3624 " present in the FPA.\n";
3625 fail |= cvmx_error_add(&info);
3627 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3628 info.status_addr = CVMX_FPA_INT_SUM;
3629 info.status_mask = 1ull<<9 /* q1_perr */;
3630 info.enable_addr = CVMX_FPA_INT_ENB;
3631 info.enable_mask = 1ull<<9 /* q1_perr */;
3633 info.group = CVMX_ERROR_GROUP_INTERNAL;
3634 info.group_index = 0;
3635 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3636 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3637 info.parent.status_mask = 1ull<<5 /* fpa */;
3638 info.func = __cvmx_error_display;
3639 info.user_info = (long)
3640 "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
3641 " the L2C does not have the FPA owner ship bit set.\n";
3642 fail |= cvmx_error_add(&info);
3644 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3645 info.status_addr = CVMX_FPA_INT_SUM;
3646 info.status_mask = 1ull<<10 /* q2_und */;
3647 info.enable_addr = CVMX_FPA_INT_ENB;
3648 info.enable_mask = 1ull<<10 /* q2_und */;
3650 info.group = CVMX_ERROR_GROUP_INTERNAL;
3651 info.group_index = 0;
3652 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3653 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3654 info.parent.status_mask = 1ull<<5 /* fpa */;
3655 info.func = __cvmx_error_display;
3656 info.user_info = (long)
3657 "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
3659 fail |= cvmx_error_add(&info);
3661 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3662 info.status_addr = CVMX_FPA_INT_SUM;
3663 info.status_mask = 1ull<<11 /* q2_coff */;
3664 info.enable_addr = CVMX_FPA_INT_ENB;
3665 info.enable_mask = 1ull<<11 /* q2_coff */;
3667 info.group = CVMX_ERROR_GROUP_INTERNAL;
3668 info.group_index = 0;
3669 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3670 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3671 info.parent.status_mask = 1ull<<5 /* fpa */;
3672 info.func = __cvmx_error_display;
3673 info.user_info = (long)
3674 "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
3675 " the count available is greater than than pointers\n"
3676 " present in the FPA.\n";
3677 fail |= cvmx_error_add(&info);
3679 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3680 info.status_addr = CVMX_FPA_INT_SUM;
3681 info.status_mask = 1ull<<12 /* q2_perr */;
3682 info.enable_addr = CVMX_FPA_INT_ENB;
3683 info.enable_mask = 1ull<<12 /* q2_perr */;
3685 info.group = CVMX_ERROR_GROUP_INTERNAL;
3686 info.group_index = 0;
3687 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3688 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3689 info.parent.status_mask = 1ull<<5 /* fpa */;
3690 info.func = __cvmx_error_display;
3691 info.user_info = (long)
3692 "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
3693 " the L2C does not have the FPA owner ship bit set.\n";
3694 fail |= cvmx_error_add(&info);
3696 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3697 info.status_addr = CVMX_FPA_INT_SUM;
3698 info.status_mask = 1ull<<13 /* q3_und */;
3699 info.enable_addr = CVMX_FPA_INT_ENB;
3700 info.enable_mask = 1ull<<13 /* q3_und */;
3702 info.group = CVMX_ERROR_GROUP_INTERNAL;
3703 info.group_index = 0;
3704 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3705 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3706 info.parent.status_mask = 1ull<<5 /* fpa */;
3707 info.func = __cvmx_error_display;
3708 info.user_info = (long)
3709 "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
3711 fail |= cvmx_error_add(&info);
3713 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3714 info.status_addr = CVMX_FPA_INT_SUM;
3715 info.status_mask = 1ull<<14 /* q3_coff */;
3716 info.enable_addr = CVMX_FPA_INT_ENB;
3717 info.enable_mask = 1ull<<14 /* q3_coff */;
3719 info.group = CVMX_ERROR_GROUP_INTERNAL;
3720 info.group_index = 0;
3721 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3722 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3723 info.parent.status_mask = 1ull<<5 /* fpa */;
3724 info.func = __cvmx_error_display;
3725 info.user_info = (long)
3726 "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
3727 " the count available is greater than than pointers\n"
3728 " present in the FPA.\n";
3729 fail |= cvmx_error_add(&info);
3731 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3732 info.status_addr = CVMX_FPA_INT_SUM;
3733 info.status_mask = 1ull<<15 /* q3_perr */;
3734 info.enable_addr = CVMX_FPA_INT_ENB;
3735 info.enable_mask = 1ull<<15 /* q3_perr */;
3737 info.group = CVMX_ERROR_GROUP_INTERNAL;
3738 info.group_index = 0;
3739 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3740 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3741 info.parent.status_mask = 1ull<<5 /* fpa */;
3742 info.func = __cvmx_error_display;
3743 info.user_info = (long)
3744 "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
3745 " the L2C does not have the FPA owner ship bit set.\n";
3746 fail |= cvmx_error_add(&info);
3748 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3749 info.status_addr = CVMX_FPA_INT_SUM;
3750 info.status_mask = 1ull<<16 /* q4_und */;
3751 info.enable_addr = CVMX_FPA_INT_ENB;
3752 info.enable_mask = 1ull<<16 /* q4_und */;
3754 info.group = CVMX_ERROR_GROUP_INTERNAL;
3755 info.group_index = 0;
3756 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3757 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3758 info.parent.status_mask = 1ull<<5 /* fpa */;
3759 info.func = __cvmx_error_display;
3760 info.user_info = (long)
3761 "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
3763 fail |= cvmx_error_add(&info);
3765 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3766 info.status_addr = CVMX_FPA_INT_SUM;
3767 info.status_mask = 1ull<<17 /* q4_coff */;
3768 info.enable_addr = CVMX_FPA_INT_ENB;
3769 info.enable_mask = 1ull<<17 /* q4_coff */;
3771 info.group = CVMX_ERROR_GROUP_INTERNAL;
3772 info.group_index = 0;
3773 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3774 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3775 info.parent.status_mask = 1ull<<5 /* fpa */;
3776 info.func = __cvmx_error_display;
3777 info.user_info = (long)
3778 "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
3779 " the count available is greater than than pointers\n"
3780 " present in the FPA.\n";
3781 fail |= cvmx_error_add(&info);
3783 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3784 info.status_addr = CVMX_FPA_INT_SUM;
3785 info.status_mask = 1ull<<18 /* q4_perr */;
3786 info.enable_addr = CVMX_FPA_INT_ENB;
3787 info.enable_mask = 1ull<<18 /* q4_perr */;
3789 info.group = CVMX_ERROR_GROUP_INTERNAL;
3790 info.group_index = 0;
3791 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3792 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3793 info.parent.status_mask = 1ull<<5 /* fpa */;
3794 info.func = __cvmx_error_display;
3795 info.user_info = (long)
3796 "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
3797 " the L2C does not have the FPA owner ship bit set.\n";
3798 fail |= cvmx_error_add(&info);
3800 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3801 info.status_addr = CVMX_FPA_INT_SUM;
3802 info.status_mask = 1ull<<19 /* q5_und */;
3803 info.enable_addr = CVMX_FPA_INT_ENB;
3804 info.enable_mask = 1ull<<19 /* q5_und */;
3806 info.group = CVMX_ERROR_GROUP_INTERNAL;
3807 info.group_index = 0;
3808 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3809 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3810 info.parent.status_mask = 1ull<<5 /* fpa */;
3811 info.func = __cvmx_error_display;
3812 info.user_info = (long)
3813 "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
3815 fail |= cvmx_error_add(&info);
3817 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3818 info.status_addr = CVMX_FPA_INT_SUM;
3819 info.status_mask = 1ull<<20 /* q5_coff */;
3820 info.enable_addr = CVMX_FPA_INT_ENB;
3821 info.enable_mask = 1ull<<20 /* q5_coff */;
3823 info.group = CVMX_ERROR_GROUP_INTERNAL;
3824 info.group_index = 0;
3825 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3826 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3827 info.parent.status_mask = 1ull<<5 /* fpa */;
3828 info.func = __cvmx_error_display;
3829 info.user_info = (long)
3830 "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
3831 " the count available is greater than than pointers\n"
3832 " present in the FPA.\n";
3833 fail |= cvmx_error_add(&info);
3835 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3836 info.status_addr = CVMX_FPA_INT_SUM;
3837 info.status_mask = 1ull<<21 /* q5_perr */;
3838 info.enable_addr = CVMX_FPA_INT_ENB;
3839 info.enable_mask = 1ull<<21 /* q5_perr */;
3841 info.group = CVMX_ERROR_GROUP_INTERNAL;
3842 info.group_index = 0;
3843 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3844 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3845 info.parent.status_mask = 1ull<<5 /* fpa */;
3846 info.func = __cvmx_error_display;
3847 info.user_info = (long)
3848 "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
3849 " the L2C does not have the FPA owner ship bit set.\n";
3850 fail |= cvmx_error_add(&info);
3852 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3853 info.status_addr = CVMX_FPA_INT_SUM;
3854 info.status_mask = 1ull<<22 /* q6_und */;
3855 info.enable_addr = CVMX_FPA_INT_ENB;
3856 info.enable_mask = 1ull<<22 /* q6_und */;
3858 info.group = CVMX_ERROR_GROUP_INTERNAL;
3859 info.group_index = 0;
3860 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3861 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3862 info.parent.status_mask = 1ull<<5 /* fpa */;
3863 info.func = __cvmx_error_display;
3864 info.user_info = (long)
3865 "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
3867 fail |= cvmx_error_add(&info);
3869 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3870 info.status_addr = CVMX_FPA_INT_SUM;
3871 info.status_mask = 1ull<<23 /* q6_coff */;
3872 info.enable_addr = CVMX_FPA_INT_ENB;
3873 info.enable_mask = 1ull<<23 /* q6_coff */;
3875 info.group = CVMX_ERROR_GROUP_INTERNAL;
3876 info.group_index = 0;
3877 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3878 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3879 info.parent.status_mask = 1ull<<5 /* fpa */;
3880 info.func = __cvmx_error_display;
3881 info.user_info = (long)
3882 "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
3883 " the count available is greater than than pointers\n"
3884 " present in the FPA.\n";
3885 fail |= cvmx_error_add(&info);
3887 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3888 info.status_addr = CVMX_FPA_INT_SUM;
3889 info.status_mask = 1ull<<24 /* q6_perr */;
3890 info.enable_addr = CVMX_FPA_INT_ENB;
3891 info.enable_mask = 1ull<<24 /* q6_perr */;
3893 info.group = CVMX_ERROR_GROUP_INTERNAL;
3894 info.group_index = 0;
3895 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3896 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3897 info.parent.status_mask = 1ull<<5 /* fpa */;
3898 info.func = __cvmx_error_display;
3899 info.user_info = (long)
3900 "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
3901 " the L2C does not have the FPA owner ship bit set.\n";
3902 fail |= cvmx_error_add(&info);
3904 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3905 info.status_addr = CVMX_FPA_INT_SUM;
3906 info.status_mask = 1ull<<25 /* q7_und */;
3907 info.enable_addr = CVMX_FPA_INT_ENB;
3908 info.enable_mask = 1ull<<25 /* q7_und */;
3910 info.group = CVMX_ERROR_GROUP_INTERNAL;
3911 info.group_index = 0;
3912 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3913 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3914 info.parent.status_mask = 1ull<<5 /* fpa */;
3915 info.func = __cvmx_error_display;
3916 info.user_info = (long)
3917 "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
3919 fail |= cvmx_error_add(&info);
3921 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3922 info.status_addr = CVMX_FPA_INT_SUM;
3923 info.status_mask = 1ull<<26 /* q7_coff */;
3924 info.enable_addr = CVMX_FPA_INT_ENB;
3925 info.enable_mask = 1ull<<26 /* q7_coff */;
3927 info.group = CVMX_ERROR_GROUP_INTERNAL;
3928 info.group_index = 0;
3929 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3930 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3931 info.parent.status_mask = 1ull<<5 /* fpa */;
3932 info.func = __cvmx_error_display;
3933 info.user_info = (long)
3934 "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
3935 " the count available is greater than than pointers\n"
3936 " present in the FPA.\n";
3937 fail |= cvmx_error_add(&info);
3939 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3940 info.status_addr = CVMX_FPA_INT_SUM;
3941 info.status_mask = 1ull<<27 /* q7_perr */;
3942 info.enable_addr = CVMX_FPA_INT_ENB;
3943 info.enable_mask = 1ull<<27 /* q7_perr */;
3945 info.group = CVMX_ERROR_GROUP_INTERNAL;
3946 info.group_index = 0;
3947 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3948 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3949 info.parent.status_mask = 1ull<<5 /* fpa */;
3950 info.func = __cvmx_error_display;
3951 info.user_info = (long)
3952 "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
3953 " the L2C does not have the FPA owner ship bit set.\n";
3954 fail |= cvmx_error_add(&info);
3956 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3957 info.status_addr = CVMX_FPA_INT_SUM;
3958 info.status_mask = 1ull<<28 /* pool0th */;
3959 info.enable_addr = CVMX_FPA_INT_ENB;
3960 info.enable_mask = 1ull<<28 /* pool0th */;
3962 info.group = CVMX_ERROR_GROUP_INTERNAL;
3963 info.group_index = 0;
3964 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3965 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3966 info.parent.status_mask = 1ull<<5 /* fpa */;
3967 info.func = __cvmx_error_display;
3968 info.user_info = (long)
3969 "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
3970 " FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
3971 " allocated or de-allocated.\n";
3972 fail |= cvmx_error_add(&info);
3974 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3975 info.status_addr = CVMX_FPA_INT_SUM;
3976 info.status_mask = 1ull<<29 /* pool1th */;
3977 info.enable_addr = CVMX_FPA_INT_ENB;
3978 info.enable_mask = 1ull<<29 /* pool1th */;
3980 info.group = CVMX_ERROR_GROUP_INTERNAL;
3981 info.group_index = 0;
3982 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3983 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3984 info.parent.status_mask = 1ull<<5 /* fpa */;
3985 info.func = __cvmx_error_display;
3986 info.user_info = (long)
3987 "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
3988 " FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
3989 " allocated or de-allocated.\n";
3990 fail |= cvmx_error_add(&info);
3992 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3993 info.status_addr = CVMX_FPA_INT_SUM;
3994 info.status_mask = 1ull<<30 /* pool2th */;
3995 info.enable_addr = CVMX_FPA_INT_ENB;
3996 info.enable_mask = 1ull<<30 /* pool2th */;
3998 info.group = CVMX_ERROR_GROUP_INTERNAL;
3999 info.group_index = 0;
4000 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4001 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4002 info.parent.status_mask = 1ull<<5 /* fpa */;
4003 info.func = __cvmx_error_display;
4004 info.user_info = (long)
4005 "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
4006 " FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
4007 " allocated or de-allocated.\n";
4008 fail |= cvmx_error_add(&info);
4010 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4011 info.status_addr = CVMX_FPA_INT_SUM;
4012 info.status_mask = 1ull<<31 /* pool3th */;
4013 info.enable_addr = CVMX_FPA_INT_ENB;
4014 info.enable_mask = 1ull<<31 /* pool3th */;
4016 info.group = CVMX_ERROR_GROUP_INTERNAL;
4017 info.group_index = 0;
4018 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4019 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4020 info.parent.status_mask = 1ull<<5 /* fpa */;
4021 info.func = __cvmx_error_display;
4022 info.user_info = (long)
4023 "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
4024 " FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
4025 " allocated or de-allocated.\n";
4026 fail |= cvmx_error_add(&info);
4028 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4029 info.status_addr = CVMX_FPA_INT_SUM;
4030 info.status_mask = 1ull<<32 /* pool4th */;
4031 info.enable_addr = CVMX_FPA_INT_ENB;
4032 info.enable_mask = 1ull<<32 /* pool4th */;
4034 info.group = CVMX_ERROR_GROUP_INTERNAL;
4035 info.group_index = 0;
4036 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4037 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4038 info.parent.status_mask = 1ull<<5 /* fpa */;
4039 info.func = __cvmx_error_display;
4040 info.user_info = (long)
4041 "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
4042 " FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
4043 " allocated or de-allocated.\n";
4044 fail |= cvmx_error_add(&info);
4046 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4047 info.status_addr = CVMX_FPA_INT_SUM;
4048 info.status_mask = 1ull<<33 /* pool5th */;
4049 info.enable_addr = CVMX_FPA_INT_ENB;
4050 info.enable_mask = 1ull<<33 /* pool5th */;
4052 info.group = CVMX_ERROR_GROUP_INTERNAL;
4053 info.group_index = 0;
4054 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4055 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4056 info.parent.status_mask = 1ull<<5 /* fpa */;
4057 info.func = __cvmx_error_display;
4058 info.user_info = (long)
4059 "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
4060 " FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
4061 " allocated or de-allocated.\n";
4062 fail |= cvmx_error_add(&info);
4064 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4065 info.status_addr = CVMX_FPA_INT_SUM;
4066 info.status_mask = 1ull<<34 /* pool6th */;
4067 info.enable_addr = CVMX_FPA_INT_ENB;
4068 info.enable_mask = 1ull<<34 /* pool6th */;
4070 info.group = CVMX_ERROR_GROUP_INTERNAL;
4071 info.group_index = 0;
4072 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4073 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4074 info.parent.status_mask = 1ull<<5 /* fpa */;
4075 info.func = __cvmx_error_display;
4076 info.user_info = (long)
4077 "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
4078 " FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
4079 " allocated or de-allocated.\n";
4080 fail |= cvmx_error_add(&info);
4082 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4083 info.status_addr = CVMX_FPA_INT_SUM;
4084 info.status_mask = 1ull<<35 /* pool7th */;
4085 info.enable_addr = CVMX_FPA_INT_ENB;
4086 info.enable_mask = 1ull<<35 /* pool7th */;
4088 info.group = CVMX_ERROR_GROUP_INTERNAL;
4089 info.group_index = 0;
4090 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4091 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4092 info.parent.status_mask = 1ull<<5 /* fpa */;
4093 info.func = __cvmx_error_display;
4094 info.user_info = (long)
4095 "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
4096 " FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
4097 " allocated or de-allocated.\n";
4098 fail |= cvmx_error_add(&info);
4100 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4101 info.status_addr = CVMX_FPA_INT_SUM;
4102 info.status_mask = 1ull<<36 /* free0 */;
4103 info.enable_addr = CVMX_FPA_INT_ENB;
4104 info.enable_mask = 1ull<<36 /* free0 */;
4106 info.group = CVMX_ERROR_GROUP_INTERNAL;
4107 info.group_index = 0;
4108 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4109 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4110 info.parent.status_mask = 1ull<<5 /* fpa */;
4111 info.func = __cvmx_error_display;
4112 info.user_info = (long)
4113 "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
4114 fail |= cvmx_error_add(&info);
4116 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4117 info.status_addr = CVMX_FPA_INT_SUM;
4118 info.status_mask = 1ull<<37 /* free1 */;
4119 info.enable_addr = CVMX_FPA_INT_ENB;
4120 info.enable_mask = 1ull<<37 /* free1 */;
4122 info.group = CVMX_ERROR_GROUP_INTERNAL;
4123 info.group_index = 0;
4124 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4125 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4126 info.parent.status_mask = 1ull<<5 /* fpa */;
4127 info.func = __cvmx_error_display;
4128 info.user_info = (long)
4129 "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
4130 fail |= cvmx_error_add(&info);
4132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4133 info.status_addr = CVMX_FPA_INT_SUM;
4134 info.status_mask = 1ull<<38 /* free2 */;
4135 info.enable_addr = CVMX_FPA_INT_ENB;
4136 info.enable_mask = 1ull<<38 /* free2 */;
4138 info.group = CVMX_ERROR_GROUP_INTERNAL;
4139 info.group_index = 0;
4140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4141 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4142 info.parent.status_mask = 1ull<<5 /* fpa */;
4143 info.func = __cvmx_error_display;
4144 info.user_info = (long)
4145 "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
4146 fail |= cvmx_error_add(&info);
4148 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4149 info.status_addr = CVMX_FPA_INT_SUM;
4150 info.status_mask = 1ull<<39 /* free3 */;
4151 info.enable_addr = CVMX_FPA_INT_ENB;
4152 info.enable_mask = 1ull<<39 /* free3 */;
4154 info.group = CVMX_ERROR_GROUP_INTERNAL;
4155 info.group_index = 0;
4156 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4157 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4158 info.parent.status_mask = 1ull<<5 /* fpa */;
4159 info.func = __cvmx_error_display;
4160 info.user_info = (long)
4161 "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
4162 fail |= cvmx_error_add(&info);
4164 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4165 info.status_addr = CVMX_FPA_INT_SUM;
4166 info.status_mask = 1ull<<40 /* free4 */;
4167 info.enable_addr = CVMX_FPA_INT_ENB;
4168 info.enable_mask = 1ull<<40 /* free4 */;
4170 info.group = CVMX_ERROR_GROUP_INTERNAL;
4171 info.group_index = 0;
4172 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4173 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4174 info.parent.status_mask = 1ull<<5 /* fpa */;
4175 info.func = __cvmx_error_display;
4176 info.user_info = (long)
4177 "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
4178 fail |= cvmx_error_add(&info);
4180 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4181 info.status_addr = CVMX_FPA_INT_SUM;
4182 info.status_mask = 1ull<<41 /* free5 */;
4183 info.enable_addr = CVMX_FPA_INT_ENB;
4184 info.enable_mask = 1ull<<41 /* free5 */;
4186 info.group = CVMX_ERROR_GROUP_INTERNAL;
4187 info.group_index = 0;
4188 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4189 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4190 info.parent.status_mask = 1ull<<5 /* fpa */;
4191 info.func = __cvmx_error_display;
4192 info.user_info = (long)
4193 "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
4194 fail |= cvmx_error_add(&info);
4196 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4197 info.status_addr = CVMX_FPA_INT_SUM;
4198 info.status_mask = 1ull<<42 /* free6 */;
4199 info.enable_addr = CVMX_FPA_INT_ENB;
4200 info.enable_mask = 1ull<<42 /* free6 */;
4202 info.group = CVMX_ERROR_GROUP_INTERNAL;
4203 info.group_index = 0;
4204 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4205 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4206 info.parent.status_mask = 1ull<<5 /* fpa */;
4207 info.func = __cvmx_error_display;
4208 info.user_info = (long)
4209 "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
4210 fail |= cvmx_error_add(&info);
4212 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4213 info.status_addr = CVMX_FPA_INT_SUM;
4214 info.status_mask = 1ull<<43 /* free7 */;
4215 info.enable_addr = CVMX_FPA_INT_ENB;
4216 info.enable_mask = 1ull<<43 /* free7 */;
4218 info.group = CVMX_ERROR_GROUP_INTERNAL;
4219 info.group_index = 0;
4220 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4221 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4222 info.parent.status_mask = 1ull<<5 /* fpa */;
4223 info.func = __cvmx_error_display;
4224 info.user_info = (long)
4225 "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
4226 fail |= cvmx_error_add(&info);
4228 /* CVMX_UCTLX_INT_REG(0) */
4229 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4230 info.status_addr = CVMX_UCTLX_INT_REG(0);
4231 info.status_mask = 1ull<<0 /* pp_psh_f */;
4232 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4233 info.enable_mask = 1ull<<0 /* pp_psh_f */;
4235 info.group = CVMX_ERROR_GROUP_USB;
4236 info.group_index = 0;
4237 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4238 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4239 info.parent.status_mask = 1ull<<13 /* usb */;
4240 info.func = __cvmx_error_display;
4241 info.user_info = (long)
4242 "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
4243 fail |= cvmx_error_add(&info);
4245 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4246 info.status_addr = CVMX_UCTLX_INT_REG(0);
4247 info.status_mask = 1ull<<1 /* er_psh_f */;
4248 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4249 info.enable_mask = 1ull<<1 /* er_psh_f */;
4251 info.group = CVMX_ERROR_GROUP_USB;
4252 info.group_index = 0;
4253 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4254 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4255 info.parent.status_mask = 1ull<<13 /* usb */;
4256 info.func = __cvmx_error_display;
4257 info.user_info = (long)
4258 "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
4259 fail |= cvmx_error_add(&info);
4261 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4262 info.status_addr = CVMX_UCTLX_INT_REG(0);
4263 info.status_mask = 1ull<<2 /* or_psh_f */;
4264 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4265 info.enable_mask = 1ull<<2 /* or_psh_f */;
4267 info.group = CVMX_ERROR_GROUP_USB;
4268 info.group_index = 0;
4269 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4270 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4271 info.parent.status_mask = 1ull<<13 /* usb */;
4272 info.func = __cvmx_error_display;
4273 info.user_info = (long)
4274 "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
4275 fail |= cvmx_error_add(&info);
4277 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4278 info.status_addr = CVMX_UCTLX_INT_REG(0);
4279 info.status_mask = 1ull<<3 /* cf_psh_f */;
4280 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4281 info.enable_mask = 1ull<<3 /* cf_psh_f */;
4283 info.group = CVMX_ERROR_GROUP_USB;
4284 info.group_index = 0;
4285 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4286 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4287 info.parent.status_mask = 1ull<<13 /* usb */;
4288 info.func = __cvmx_error_display;
4289 info.user_info = (long)
4290 "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
4291 fail |= cvmx_error_add(&info);
4293 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4294 info.status_addr = CVMX_UCTLX_INT_REG(0);
4295 info.status_mask = 1ull<<4 /* wb_psh_f */;
4296 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4297 info.enable_mask = 1ull<<4 /* wb_psh_f */;
4299 info.group = CVMX_ERROR_GROUP_USB;
4300 info.group_index = 0;
4301 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4302 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4303 info.parent.status_mask = 1ull<<13 /* usb */;
4304 info.func = __cvmx_error_display;
4305 info.user_info = (long)
4306 "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
4307 fail |= cvmx_error_add(&info);
4309 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4310 info.status_addr = CVMX_UCTLX_INT_REG(0);
4311 info.status_mask = 1ull<<5 /* wb_pop_e */;
4312 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4313 info.enable_mask = 1ull<<5 /* wb_pop_e */;
4315 info.group = CVMX_ERROR_GROUP_USB;
4316 info.group_index = 0;
4317 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4318 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4319 info.parent.status_mask = 1ull<<13 /* usb */;
4320 info.func = __cvmx_error_display;
4321 info.user_info = (long)
4322 "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
4323 fail |= cvmx_error_add(&info);
4325 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4326 info.status_addr = CVMX_UCTLX_INT_REG(0);
4327 info.status_mask = 1ull<<6 /* oc_ovf_e */;
4328 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4329 info.enable_mask = 1ull<<6 /* oc_ovf_e */;
4331 info.group = CVMX_ERROR_GROUP_USB;
4332 info.group_index = 0;
4333 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4334 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4335 info.parent.status_mask = 1ull<<13 /* usb */;
4336 info.func = __cvmx_error_display;
4337 info.user_info = (long)
4338 "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
4339 " When the error happenes, the whole NCB system needs\n"
4341 fail |= cvmx_error_add(&info);
4343 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4344 info.status_addr = CVMX_UCTLX_INT_REG(0);
4345 info.status_mask = 1ull<<7 /* ec_ovf_e */;
4346 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
4347 info.enable_mask = 1ull<<7 /* ec_ovf_e */;
4349 info.group = CVMX_ERROR_GROUP_USB;
4350 info.group_index = 0;
4351 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4352 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4353 info.parent.status_mask = 1ull<<13 /* usb */;
4354 info.func = __cvmx_error_display;
4355 info.user_info = (long)
4356 "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
4357 " When the error happenes, the whole NCB system needs\n"
4359 fail |= cvmx_error_add(&info);
4361 /* CVMX_MIO_BOOT_ERR */
4362 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4363 info.status_addr = CVMX_MIO_BOOT_ERR;
4364 info.status_mask = 1ull<<0 /* adr_err */;
4365 info.enable_addr = CVMX_MIO_BOOT_INT;
4366 info.enable_mask = 1ull<<0 /* adr_int */;
4368 info.group = CVMX_ERROR_GROUP_INTERNAL;
4369 info.group_index = 0;
4370 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4371 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4372 info.parent.status_mask = 1ull<<0 /* mio */;
4373 info.func = __cvmx_error_display;
4374 info.user_info = (long)
4375 "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
4376 fail |= cvmx_error_add(&info);
4378 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4379 info.status_addr = CVMX_MIO_BOOT_ERR;
4380 info.status_mask = 1ull<<1 /* wait_err */;
4381 info.enable_addr = CVMX_MIO_BOOT_INT;
4382 info.enable_mask = 1ull<<1 /* wait_int */;
4384 info.group = CVMX_ERROR_GROUP_INTERNAL;
4385 info.group_index = 0;
4386 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4387 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4388 info.parent.status_mask = 1ull<<0 /* mio */;
4389 info.func = __cvmx_error_display;
4390 info.user_info = (long)
4391 "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
4392 fail |= cvmx_error_add(&info);
4394 /* CVMX_MIO_RST_INT */
4395 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4396 info.status_addr = CVMX_MIO_RST_INT;
4397 info.status_mask = 1ull<<0 /* rst_link0 */;
4398 info.enable_addr = CVMX_MIO_RST_INT_EN;
4399 info.enable_mask = 1ull<<0 /* rst_link0 */;
4401 info.group = CVMX_ERROR_GROUP_INTERNAL;
4402 info.group_index = 0;
4403 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4404 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4405 info.parent.status_mask = 1ull<<0 /* mio */;
4406 info.func = __cvmx_error_display;
4407 info.user_info = (long)
4408 "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
4409 " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
4410 " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
4411 fail |= cvmx_error_add(&info);
4413 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4414 info.status_addr = CVMX_MIO_RST_INT;
4415 info.status_mask = 1ull<<1 /* rst_link1 */;
4416 info.enable_addr = CVMX_MIO_RST_INT_EN;
4417 info.enable_mask = 1ull<<1 /* rst_link1 */;
4419 info.group = CVMX_ERROR_GROUP_INTERNAL;
4420 info.group_index = 0;
4421 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4422 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4423 info.parent.status_mask = 1ull<<0 /* mio */;
4424 info.func = __cvmx_error_display;
4425 info.user_info = (long)
4426 "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
4427 " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
4428 " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
4429 fail |= cvmx_error_add(&info);
4431 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4432 info.status_addr = CVMX_MIO_RST_INT;
4433 info.status_mask = 1ull<<8 /* perst0 */;
4434 info.enable_addr = CVMX_MIO_RST_INT_EN;
4435 info.enable_mask = 1ull<<8 /* perst0 */;
4437 info.group = CVMX_ERROR_GROUP_INTERNAL;
4438 info.group_index = 0;
4439 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4440 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4441 info.parent.status_mask = 1ull<<0 /* mio */;
4442 info.func = __cvmx_error_display;
4443 info.user_info = (long)
4444 "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
4445 " and MIO_RST_CTL0[RST_CHIP]=0\n";
4446 fail |= cvmx_error_add(&info);
4448 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4449 info.status_addr = CVMX_MIO_RST_INT;
4450 info.status_mask = 1ull<<9 /* perst1 */;
4451 info.enable_addr = CVMX_MIO_RST_INT_EN;
4452 info.enable_mask = 1ull<<9 /* perst1 */;
4454 info.group = CVMX_ERROR_GROUP_INTERNAL;
4455 info.group_index = 0;
4456 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4457 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4458 info.parent.status_mask = 1ull<<0 /* mio */;
4459 info.func = __cvmx_error_display;
4460 info.user_info = (long)
4461 "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
4462 " and MIO_RST_CTL1[RST_CHIP]=0\n";
4463 fail |= cvmx_error_add(&info);
4465 /* CVMX_DFM_FNT_STAT */
4466 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4467 info.status_addr = CVMX_DFM_FNT_STAT;
4468 info.status_mask = 1ull<<0 /* sbe_err */;
4469 info.enable_addr = CVMX_DFM_FNT_IENA;
4470 info.enable_mask = 1ull<<0 /* sbe_intena */;
4472 info.group = CVMX_ERROR_GROUP_DFM;
4473 info.group_index = 0;
4474 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4475 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4476 info.parent.status_mask = 1ull<<40 /* dfm */;
4477 info.func = __cvmx_error_display;
4478 info.user_info = (long)
4479 "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
4481 " Write of 1 will clear the corresponding error bit\n";
4482 fail |= cvmx_error_add(&info);
4484 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4485 info.status_addr = CVMX_DFM_FNT_STAT;
4486 info.status_mask = 1ull<<1 /* dbe_err */;
4487 info.enable_addr = CVMX_DFM_FNT_IENA;
4488 info.enable_mask = 1ull<<1 /* dbe_intena */;
4490 info.group = CVMX_ERROR_GROUP_DFM;
4491 info.group_index = 0;
4492 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4493 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4494 info.parent.status_mask = 1ull<<40 /* dfm */;
4495 info.func = __cvmx_error_display;
4496 info.user_info = (long)
4497 "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
4499 " Write of 1 will clear the corresponding error bit\n";
4500 fail |= cvmx_error_add(&info);
4502 /* CVMX_TIM_REG_ERROR */
4503 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4504 info.status_addr = CVMX_TIM_REG_ERROR;
4505 info.status_mask = 0xffffull<<0 /* mask */;
4506 info.enable_addr = CVMX_TIM_REG_INT_MASK;
4507 info.enable_mask = 0xffffull<<0 /* mask */;
4509 info.group = CVMX_ERROR_GROUP_INTERNAL;
4510 info.group_index = 0;
4511 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4512 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4513 info.parent.status_mask = 1ull<<11 /* tim */;
4514 info.func = __cvmx_error_display;
4515 info.user_info = (long)
4516 "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
4517 fail |= cvmx_error_add(&info);
4519 /* CVMX_LMCX_INT(0) */
4520 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4521 info.status_addr = CVMX_LMCX_INT(0);
4522 info.status_mask = 0xfull<<1 /* sec_err */;
4523 info.enable_addr = CVMX_LMCX_INT_EN(0);
4524 info.enable_mask = 1ull<<1 /* intr_sec_ena */;
4525 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
4526 info.group = CVMX_ERROR_GROUP_LMC;
4527 info.group_index = 0;
4528 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4529 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4530 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4531 info.func = __cvmx_error_display;
4532 info.user_info = (long)
4533 "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
4534 " [0] corresponds to DQ[63:0]_c0_p0\n"
4535 " [1] corresponds to DQ[63:0]_c0_p1\n"
4536 " [2] corresponds to DQ[63:0]_c1_p0\n"
4537 " [3] corresponds to DQ[63:0]_c1_p1\n"
4538 " where _cC_pP denotes cycle C and phase P\n"
4539 " Write of 1 will clear the corresponding error bit\n";
4540 fail |= cvmx_error_add(&info);
4542 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4543 info.status_addr = CVMX_LMCX_INT(0);
4544 info.status_mask = 1ull<<0 /* nxm_wr_err */;
4545 info.enable_addr = CVMX_LMCX_INT_EN(0);
4546 info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
4548 info.group = CVMX_ERROR_GROUP_LMC;
4549 info.group_index = 0;
4550 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4551 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4552 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4553 info.func = __cvmx_error_display;
4554 info.user_info = (long)
4555 "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
4556 " Write of 1 will clear the corresponding error bit\n";
4557 fail |= cvmx_error_add(&info);
4559 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4560 info.status_addr = CVMX_LMCX_INT(0);
4561 info.status_mask = 0xfull<<5 /* ded_err */;
4562 info.enable_addr = CVMX_LMCX_INT_EN(0);
4563 info.enable_mask = 1ull<<2 /* intr_ded_ena */;
4565 info.group = CVMX_ERROR_GROUP_LMC;
4566 info.group_index = 0;
4567 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4568 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4569 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4570 info.func = __cvmx_error_display;
4571 info.user_info = (long)
4572 "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
4573 " [0] corresponds to DQ[63:0]_c0_p0\n"
4574 " [1] corresponds to DQ[63:0]_c0_p1\n"
4575 " [2] corresponds to DQ[63:0]_c1_p0\n"
4576 " [3] corresponds to DQ[63:0]_c1_p1\n"
4577 " where _cC_pP denotes cycle C and phase P\n"
4578 " Write of 1 will clear the corresponding error bit\n";
4579 fail |= cvmx_error_add(&info);
4581 /* CVMX_KEY_INT_SUM */
4582 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4583 info.status_addr = CVMX_KEY_INT_SUM;
4584 info.status_mask = 1ull<<0 /* ked0_sbe */;
4585 info.enable_addr = CVMX_KEY_INT_ENB;
4586 info.enable_mask = 1ull<<0 /* ked0_sbe */;
4588 info.group = CVMX_ERROR_GROUP_INTERNAL;
4589 info.group_index = 0;
4590 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4591 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4592 info.parent.status_mask = 1ull<<4 /* key */;
4593 info.func = __cvmx_error_display;
4594 info.user_info = (long)
4595 "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
4597 fail |= cvmx_error_add(&info);
4599 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4600 info.status_addr = CVMX_KEY_INT_SUM;
4601 info.status_mask = 1ull<<1 /* ked0_dbe */;
4602 info.enable_addr = CVMX_KEY_INT_ENB;
4603 info.enable_mask = 1ull<<1 /* ked0_dbe */;
4605 info.group = CVMX_ERROR_GROUP_INTERNAL;
4606 info.group_index = 0;
4607 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4608 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4609 info.parent.status_mask = 1ull<<4 /* key */;
4610 info.func = __cvmx_error_display;
4611 info.user_info = (long)
4612 "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
4614 fail |= cvmx_error_add(&info);
4616 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4617 info.status_addr = CVMX_KEY_INT_SUM;
4618 info.status_mask = 1ull<<2 /* ked1_sbe */;
4619 info.enable_addr = CVMX_KEY_INT_ENB;
4620 info.enable_mask = 1ull<<2 /* ked1_sbe */;
4622 info.group = CVMX_ERROR_GROUP_INTERNAL;
4623 info.group_index = 0;
4624 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4625 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4626 info.parent.status_mask = 1ull<<4 /* key */;
4627 info.func = __cvmx_error_display;
4628 info.user_info = (long)
4629 "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
4631 fail |= cvmx_error_add(&info);
4633 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4634 info.status_addr = CVMX_KEY_INT_SUM;
4635 info.status_mask = 1ull<<3 /* ked1_dbe */;
4636 info.enable_addr = CVMX_KEY_INT_ENB;
4637 info.enable_mask = 1ull<<3 /* ked1_dbe */;
4639 info.group = CVMX_ERROR_GROUP_INTERNAL;
4640 info.group_index = 0;
4641 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4642 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4643 info.parent.status_mask = 1ull<<4 /* key */;
4644 info.func = __cvmx_error_display;
4645 info.user_info = (long)
4646 "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
4648 fail |= cvmx_error_add(&info);
4650 /* CVMX_GMXX_BAD_REG(0) */
4651 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4652 info.status_addr = CVMX_GMXX_BAD_REG(0);
4653 info.status_mask = 0xfull<<2 /* out_ovr */;
4654 info.enable_addr = 0;
4655 info.enable_mask = 0;
4657 info.group = CVMX_ERROR_GROUP_ETHERNET;
4658 info.group_index = 0;
4659 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4660 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4661 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4662 info.func = __cvmx_error_display;
4663 info.user_info = (long)
4664 "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
4665 fail |= cvmx_error_add(&info);
4667 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4668 info.status_addr = CVMX_GMXX_BAD_REG(0);
4669 info.status_mask = 0xfull<<22 /* loststat */;
4670 info.enable_addr = 0;
4671 info.enable_mask = 0;
4673 info.group = CVMX_ERROR_GROUP_ETHERNET;
4674 info.group_index = 0;
4675 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4676 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4677 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4678 info.func = __cvmx_error_display;
4679 info.user_info = (long)
4680 "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
4681 " In SGMII, one bit per port\n"
4682 " In XAUI, only port0 is used\n"
4683 " TX Stats are corrupted\n";
4684 fail |= cvmx_error_add(&info);
4686 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4687 info.status_addr = CVMX_GMXX_BAD_REG(0);
4688 info.status_mask = 1ull<<26 /* statovr */;
4689 info.enable_addr = 0;
4690 info.enable_mask = 0;
4692 info.group = CVMX_ERROR_GROUP_ETHERNET;
4693 info.group_index = 0;
4694 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4695 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4696 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4697 info.func = __cvmx_error_display;
4698 info.user_info = (long)
4699 "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
4700 " The common FIFO to SGMII and XAUI had an overflow\n"
4701 " TX Stats are corrupted\n";
4702 fail |= cvmx_error_add(&info);
4704 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4705 info.status_addr = CVMX_GMXX_BAD_REG(0);
4706 info.status_mask = 0xfull<<27 /* inb_nxa */;
4707 info.enable_addr = 0;
4708 info.enable_mask = 0;
4710 info.group = CVMX_ERROR_GROUP_ETHERNET;
4711 info.group_index = 0;
4712 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4713 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4714 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4715 info.func = __cvmx_error_display;
4716 info.user_info = (long)
4717 "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
4718 fail |= cvmx_error_add(&info);
4720 /* CVMX_GMXX_RXX_INT_REG(0,0) */
4721 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4722 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4723 info.status_mask = 1ull<<1 /* carext */;
4724 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4725 info.enable_mask = 1ull<<1 /* carext */;
4727 info.group = CVMX_ERROR_GROUP_ETHERNET;
4728 info.group_index = 0;
4729 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4730 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4731 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4732 info.func = __cvmx_error_display;
4733 info.user_info = (long)
4734 "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
4735 " (SGMII/1000Base-X only)\n";
4736 fail |= cvmx_error_add(&info);
4738 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4739 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4740 info.status_mask = 1ull<<8 /* skperr */;
4741 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4742 info.enable_mask = 1ull<<8 /* skperr */;
4744 info.group = CVMX_ERROR_GROUP_ETHERNET;
4745 info.group_index = 0;
4746 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4747 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4748 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4749 info.func = __cvmx_error_display;
4750 info.user_info = (long)
4751 "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
4752 fail |= cvmx_error_add(&info);
4754 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4755 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4756 info.status_mask = 1ull<<10 /* ovrerr */;
4757 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4758 info.enable_mask = 1ull<<10 /* ovrerr */;
4760 info.group = CVMX_ERROR_GROUP_ETHERNET;
4761 info.group_index = 0;
4762 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4763 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4764 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4765 info.func = __cvmx_error_display;
4766 info.user_info = (long)
4767 "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
4768 " This interrupt should never assert\n"
4769 " (SGMII/1000Base-X only)\n";
4770 fail |= cvmx_error_add(&info);
4772 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4773 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4774 info.status_mask = 1ull<<20 /* loc_fault */;
4775 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4776 info.enable_mask = 1ull<<20 /* loc_fault */;
4778 info.group = CVMX_ERROR_GROUP_ETHERNET;
4779 info.group_index = 0;
4780 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4781 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4782 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4783 info.func = __cvmx_error_display;
4784 info.user_info = (long)
4785 "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
4786 " (XAUI Mode only)\n";
4787 fail |= cvmx_error_add(&info);
4789 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4790 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4791 info.status_mask = 1ull<<21 /* rem_fault */;
4792 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4793 info.enable_mask = 1ull<<21 /* rem_fault */;
4795 info.group = CVMX_ERROR_GROUP_ETHERNET;
4796 info.group_index = 0;
4797 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4798 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4799 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4800 info.func = __cvmx_error_display;
4801 info.user_info = (long)
4802 "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
4803 " (XAUI Mode only)\n";
4804 fail |= cvmx_error_add(&info);
4806 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4807 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4808 info.status_mask = 1ull<<22 /* bad_seq */;
4809 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4810 info.enable_mask = 1ull<<22 /* bad_seq */;
4812 info.group = CVMX_ERROR_GROUP_ETHERNET;
4813 info.group_index = 0;
4814 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4815 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4816 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4817 info.func = __cvmx_error_display;
4818 info.user_info = (long)
4819 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
4820 " (XAUI Mode only)\n";
4821 fail |= cvmx_error_add(&info);
4823 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4824 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4825 info.status_mask = 1ull<<23 /* bad_term */;
4826 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4827 info.enable_mask = 1ull<<23 /* bad_term */;
4829 info.group = CVMX_ERROR_GROUP_ETHERNET;
4830 info.group_index = 0;
4831 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4832 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4833 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4834 info.func = __cvmx_error_display;
4835 info.user_info = (long)
4836 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
4837 " than /T/. The error propagation control\n"
4838 " character /E/ will be included as part of the\n"
4839 " frame and does not cause a frame termination.\n"
4840 " (XAUI Mode only)\n";
4841 fail |= cvmx_error_add(&info);
4843 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4844 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4845 info.status_mask = 1ull<<24 /* unsop */;
4846 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4847 info.enable_mask = 1ull<<24 /* unsop */;
4849 info.group = CVMX_ERROR_GROUP_ETHERNET;
4850 info.group_index = 0;
4851 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4852 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4853 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4854 info.func = __cvmx_error_display;
4855 info.user_info = (long)
4856 "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
4857 " (XAUI Mode only)\n";
4858 fail |= cvmx_error_add(&info);
4860 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4861 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4862 info.status_mask = 1ull<<25 /* uneop */;
4863 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4864 info.enable_mask = 1ull<<25 /* uneop */;
4866 info.group = CVMX_ERROR_GROUP_ETHERNET;
4867 info.group_index = 0;
4868 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4869 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4870 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4871 info.func = __cvmx_error_display;
4872 info.user_info = (long)
4873 "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
4874 " (XAUI Mode only)\n";
4875 fail |= cvmx_error_add(&info);
4877 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4878 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4879 info.status_mask = 1ull<<26 /* undat */;
4880 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4881 info.enable_mask = 1ull<<26 /* undat */;
4883 info.group = CVMX_ERROR_GROUP_ETHERNET;
4884 info.group_index = 0;
4885 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4886 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4887 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4888 info.func = __cvmx_error_display;
4889 info.user_info = (long)
4890 "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
4891 " (XAUI Mode only)\n";
4892 fail |= cvmx_error_add(&info);
4894 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4895 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4896 info.status_mask = 1ull<<27 /* hg2fld */;
4897 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4898 info.enable_mask = 1ull<<27 /* hg2fld */;
4900 info.group = CVMX_ERROR_GROUP_ETHERNET;
4901 info.group_index = 0;
4902 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4903 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4904 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4905 info.func = __cvmx_error_display;
4906 info.user_info = (long)
4907 "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
4908 " 1) MSG_TYPE field not 6'b00_0000\n"
4909 " i.e. it is not a FLOW CONTROL message, which\n"
4910 " is the only defined type for HiGig2\n"
4911 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
4912 " which is the only defined type for HiGig2\n"
4913 " 3) FC_OBJECT field is neither 4'b0000 for\n"
4914 " Physical Link nor 4'b0010 for Logical Link.\n"
4915 " Those are the only two defined types in HiGig2\n";
4916 fail |= cvmx_error_add(&info);
4918 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4919 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4920 info.status_mask = 1ull<<28 /* hg2cc */;
4921 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4922 info.enable_mask = 1ull<<28 /* hg2cc */;
4924 info.group = CVMX_ERROR_GROUP_ETHERNET;
4925 info.group_index = 0;
4926 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4927 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4928 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4929 info.func = __cvmx_error_display;
4930 info.user_info = (long)
4931 "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
4932 " Set when either CRC8 error detected or when\n"
4933 " a Control Character is found in the message\n"
4934 " bytes after the K.SOM\n"
4935 " NOTE: HG2CC has higher priority than HG2FLD\n"
4936 " i.e. a HiGig2 message that results in HG2CC\n"
4937 " getting set, will never set HG2FLD.\n";
4938 fail |= cvmx_error_add(&info);
4940 /* CVMX_GMXX_RXX_INT_REG(1,0) */
4941 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4942 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4943 info.status_mask = 1ull<<1 /* carext */;
4944 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4945 info.enable_mask = 1ull<<1 /* carext */;
4947 info.group = CVMX_ERROR_GROUP_ETHERNET;
4948 info.group_index = 1;
4949 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4950 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4951 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4952 info.func = __cvmx_error_display;
4953 info.user_info = (long)
4954 "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
4955 " (SGMII/1000Base-X only)\n";
4956 fail |= cvmx_error_add(&info);
4958 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4959 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4960 info.status_mask = 1ull<<8 /* skperr */;
4961 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4962 info.enable_mask = 1ull<<8 /* skperr */;
4964 info.group = CVMX_ERROR_GROUP_ETHERNET;
4965 info.group_index = 1;
4966 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4967 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4968 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4969 info.func = __cvmx_error_display;
4970 info.user_info = (long)
4971 "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
4972 fail |= cvmx_error_add(&info);
4974 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4975 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4976 info.status_mask = 1ull<<10 /* ovrerr */;
4977 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4978 info.enable_mask = 1ull<<10 /* ovrerr */;
4980 info.group = CVMX_ERROR_GROUP_ETHERNET;
4981 info.group_index = 1;
4982 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4983 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4984 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4985 info.func = __cvmx_error_display;
4986 info.user_info = (long)
4987 "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
4988 " This interrupt should never assert\n"
4989 " (SGMII/1000Base-X only)\n";
4990 fail |= cvmx_error_add(&info);
4992 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4993 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4994 info.status_mask = 1ull<<20 /* loc_fault */;
4995 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4996 info.enable_mask = 1ull<<20 /* loc_fault */;
4998 info.group = CVMX_ERROR_GROUP_ETHERNET;
4999 info.group_index = 1;
5000 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5001 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5002 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5003 info.func = __cvmx_error_display;
5004 info.user_info = (long)
5005 "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5006 " (XAUI Mode only)\n";
5007 fail |= cvmx_error_add(&info);
5009 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5010 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5011 info.status_mask = 1ull<<21 /* rem_fault */;
5012 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5013 info.enable_mask = 1ull<<21 /* rem_fault */;
5015 info.group = CVMX_ERROR_GROUP_ETHERNET;
5016 info.group_index = 1;
5017 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5018 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5019 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5020 info.func = __cvmx_error_display;
5021 info.user_info = (long)
5022 "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5023 " (XAUI Mode only)\n";
5024 fail |= cvmx_error_add(&info);
5026 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5027 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5028 info.status_mask = 1ull<<22 /* bad_seq */;
5029 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5030 info.enable_mask = 1ull<<22 /* bad_seq */;
5032 info.group = CVMX_ERROR_GROUP_ETHERNET;
5033 info.group_index = 1;
5034 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5035 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5036 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5037 info.func = __cvmx_error_display;
5038 info.user_info = (long)
5039 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
5040 " (XAUI Mode only)\n";
5041 fail |= cvmx_error_add(&info);
5043 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5044 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5045 info.status_mask = 1ull<<23 /* bad_term */;
5046 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5047 info.enable_mask = 1ull<<23 /* bad_term */;
5049 info.group = CVMX_ERROR_GROUP_ETHERNET;
5050 info.group_index = 1;
5051 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5052 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5053 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5054 info.func = __cvmx_error_display;
5055 info.user_info = (long)
5056 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
5057 " than /T/. The error propagation control\n"
5058 " character /E/ will be included as part of the\n"
5059 " frame and does not cause a frame termination.\n"
5060 " (XAUI Mode only)\n";
5061 fail |= cvmx_error_add(&info);
5063 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5064 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5065 info.status_mask = 1ull<<24 /* unsop */;
5066 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5067 info.enable_mask = 1ull<<24 /* unsop */;
5069 info.group = CVMX_ERROR_GROUP_ETHERNET;
5070 info.group_index = 1;
5071 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5072 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5073 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5074 info.func = __cvmx_error_display;
5075 info.user_info = (long)
5076 "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
5077 " (XAUI Mode only)\n";
5078 fail |= cvmx_error_add(&info);
5080 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5081 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5082 info.status_mask = 1ull<<25 /* uneop */;
5083 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5084 info.enable_mask = 1ull<<25 /* uneop */;
5086 info.group = CVMX_ERROR_GROUP_ETHERNET;
5087 info.group_index = 1;
5088 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5089 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5090 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5091 info.func = __cvmx_error_display;
5092 info.user_info = (long)
5093 "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
5094 " (XAUI Mode only)\n";
5095 fail |= cvmx_error_add(&info);
5097 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5098 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5099 info.status_mask = 1ull<<26 /* undat */;
5100 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5101 info.enable_mask = 1ull<<26 /* undat */;
5103 info.group = CVMX_ERROR_GROUP_ETHERNET;
5104 info.group_index = 1;
5105 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5106 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5107 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5108 info.func = __cvmx_error_display;
5109 info.user_info = (long)
5110 "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
5111 " (XAUI Mode only)\n";
5112 fail |= cvmx_error_add(&info);
5114 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5115 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5116 info.status_mask = 1ull<<27 /* hg2fld */;
5117 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5118 info.enable_mask = 1ull<<27 /* hg2fld */;
5120 info.group = CVMX_ERROR_GROUP_ETHERNET;
5121 info.group_index = 1;
5122 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5123 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5124 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5125 info.func = __cvmx_error_display;
5126 info.user_info = (long)
5127 "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
5128 " 1) MSG_TYPE field not 6'b00_0000\n"
5129 " i.e. it is not a FLOW CONTROL message, which\n"
5130 " is the only defined type for HiGig2\n"
5131 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5132 " which is the only defined type for HiGig2\n"
5133 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5134 " Physical Link nor 4'b0010 for Logical Link.\n"
5135 " Those are the only two defined types in HiGig2\n";
5136 fail |= cvmx_error_add(&info);
5138 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5139 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
5140 info.status_mask = 1ull<<28 /* hg2cc */;
5141 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
5142 info.enable_mask = 1ull<<28 /* hg2cc */;
5144 info.group = CVMX_ERROR_GROUP_ETHERNET;
5145 info.group_index = 1;
5146 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5147 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5148 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5149 info.func = __cvmx_error_display;
5150 info.user_info = (long)
5151 "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5152 " Set when either CRC8 error detected or when\n"
5153 " a Control Character is found in the message\n"
5154 " bytes after the K.SOM\n"
5155 " NOTE: HG2CC has higher priority than HG2FLD\n"
5156 " i.e. a HiGig2 message that results in HG2CC\n"
5157 " getting set, will never set HG2FLD.\n";
5158 fail |= cvmx_error_add(&info);
5160 /* CVMX_GMXX_RXX_INT_REG(2,0) */
5161 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5162 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5163 info.status_mask = 1ull<<1 /* carext */;
5164 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5165 info.enable_mask = 1ull<<1 /* carext */;
5167 info.group = CVMX_ERROR_GROUP_ETHERNET;
5168 info.group_index = 2;
5169 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5170 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5171 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5172 info.func = __cvmx_error_display;
5173 info.user_info = (long)
5174 "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
5175 " (SGMII/1000Base-X only)\n";
5176 fail |= cvmx_error_add(&info);
5178 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5179 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5180 info.status_mask = 1ull<<8 /* skperr */;
5181 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5182 info.enable_mask = 1ull<<8 /* skperr */;
5184 info.group = CVMX_ERROR_GROUP_ETHERNET;
5185 info.group_index = 2;
5186 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5187 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5188 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5189 info.func = __cvmx_error_display;
5190 info.user_info = (long)
5191 "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
5192 fail |= cvmx_error_add(&info);
5194 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5195 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5196 info.status_mask = 1ull<<10 /* ovrerr */;
5197 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5198 info.enable_mask = 1ull<<10 /* ovrerr */;
5200 info.group = CVMX_ERROR_GROUP_ETHERNET;
5201 info.group_index = 2;
5202 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5203 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5204 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5205 info.func = __cvmx_error_display;
5206 info.user_info = (long)
5207 "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
5208 " This interrupt should never assert\n"
5209 " (SGMII/1000Base-X only)\n";
5210 fail |= cvmx_error_add(&info);
5212 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5213 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5214 info.status_mask = 1ull<<20 /* loc_fault */;
5215 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5216 info.enable_mask = 1ull<<20 /* loc_fault */;
5218 info.group = CVMX_ERROR_GROUP_ETHERNET;
5219 info.group_index = 2;
5220 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5221 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5222 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5223 info.func = __cvmx_error_display;
5224 info.user_info = (long)
5225 "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5226 " (XAUI Mode only)\n";
5227 fail |= cvmx_error_add(&info);
5229 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5230 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5231 info.status_mask = 1ull<<21 /* rem_fault */;
5232 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5233 info.enable_mask = 1ull<<21 /* rem_fault */;
5235 info.group = CVMX_ERROR_GROUP_ETHERNET;
5236 info.group_index = 2;
5237 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5238 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5239 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5240 info.func = __cvmx_error_display;
5241 info.user_info = (long)
5242 "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5243 " (XAUI Mode only)\n";
5244 fail |= cvmx_error_add(&info);
5246 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5247 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5248 info.status_mask = 1ull<<22 /* bad_seq */;
5249 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5250 info.enable_mask = 1ull<<22 /* bad_seq */;
5252 info.group = CVMX_ERROR_GROUP_ETHERNET;
5253 info.group_index = 2;
5254 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5255 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5256 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5257 info.func = __cvmx_error_display;
5258 info.user_info = (long)
5259 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
5260 " (XAUI Mode only)\n";
5261 fail |= cvmx_error_add(&info);
5263 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5264 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5265 info.status_mask = 1ull<<23 /* bad_term */;
5266 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5267 info.enable_mask = 1ull<<23 /* bad_term */;
5269 info.group = CVMX_ERROR_GROUP_ETHERNET;
5270 info.group_index = 2;
5271 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5272 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5273 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5274 info.func = __cvmx_error_display;
5275 info.user_info = (long)
5276 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
5277 " than /T/. The error propagation control\n"
5278 " character /E/ will be included as part of the\n"
5279 " frame and does not cause a frame termination.\n"
5280 " (XAUI Mode only)\n";
5281 fail |= cvmx_error_add(&info);
5283 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5284 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5285 info.status_mask = 1ull<<24 /* unsop */;
5286 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5287 info.enable_mask = 1ull<<24 /* unsop */;
5289 info.group = CVMX_ERROR_GROUP_ETHERNET;
5290 info.group_index = 2;
5291 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5292 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5293 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5294 info.func = __cvmx_error_display;
5295 info.user_info = (long)
5296 "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
5297 " (XAUI Mode only)\n";
5298 fail |= cvmx_error_add(&info);
5300 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5301 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5302 info.status_mask = 1ull<<25 /* uneop */;
5303 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5304 info.enable_mask = 1ull<<25 /* uneop */;
5306 info.group = CVMX_ERROR_GROUP_ETHERNET;
5307 info.group_index = 2;
5308 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5309 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5310 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5311 info.func = __cvmx_error_display;
5312 info.user_info = (long)
5313 "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
5314 " (XAUI Mode only)\n";
5315 fail |= cvmx_error_add(&info);
5317 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5318 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5319 info.status_mask = 1ull<<26 /* undat */;
5320 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5321 info.enable_mask = 1ull<<26 /* undat */;
5323 info.group = CVMX_ERROR_GROUP_ETHERNET;
5324 info.group_index = 2;
5325 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5326 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5327 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5328 info.func = __cvmx_error_display;
5329 info.user_info = (long)
5330 "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
5331 " (XAUI Mode only)\n";
5332 fail |= cvmx_error_add(&info);
5334 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5335 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5336 info.status_mask = 1ull<<27 /* hg2fld */;
5337 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5338 info.enable_mask = 1ull<<27 /* hg2fld */;
5340 info.group = CVMX_ERROR_GROUP_ETHERNET;
5341 info.group_index = 2;
5342 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5343 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5344 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5345 info.func = __cvmx_error_display;
5346 info.user_info = (long)
5347 "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
5348 " 1) MSG_TYPE field not 6'b00_0000\n"
5349 " i.e. it is not a FLOW CONTROL message, which\n"
5350 " is the only defined type for HiGig2\n"
5351 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5352 " which is the only defined type for HiGig2\n"
5353 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5354 " Physical Link nor 4'b0010 for Logical Link.\n"
5355 " Those are the only two defined types in HiGig2\n";
5356 fail |= cvmx_error_add(&info);
5358 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5359 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5360 info.status_mask = 1ull<<28 /* hg2cc */;
5361 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5362 info.enable_mask = 1ull<<28 /* hg2cc */;
5364 info.group = CVMX_ERROR_GROUP_ETHERNET;
5365 info.group_index = 2;
5366 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5367 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5368 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5369 info.func = __cvmx_error_display;
5370 info.user_info = (long)
5371 "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5372 " Set when either CRC8 error detected or when\n"
5373 " a Control Character is found in the message\n"
5374 " bytes after the K.SOM\n"
5375 " NOTE: HG2CC has higher priority than HG2FLD\n"
5376 " i.e. a HiGig2 message that results in HG2CC\n"
5377 " getting set, will never set HG2FLD.\n";
5378 fail |= cvmx_error_add(&info);
5380 /* CVMX_GMXX_RXX_INT_REG(3,0) */
5381 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5382 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5383 info.status_mask = 1ull<<1 /* carext */;
5384 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5385 info.enable_mask = 1ull<<1 /* carext */;
5387 info.group = CVMX_ERROR_GROUP_ETHERNET;
5388 info.group_index = 3;
5389 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5390 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5391 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5392 info.func = __cvmx_error_display;
5393 info.user_info = (long)
5394 "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
5395 " (SGMII/1000Base-X only)\n";
5396 fail |= cvmx_error_add(&info);
5398 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5399 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5400 info.status_mask = 1ull<<8 /* skperr */;
5401 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5402 info.enable_mask = 1ull<<8 /* skperr */;
5404 info.group = CVMX_ERROR_GROUP_ETHERNET;
5405 info.group_index = 3;
5406 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5407 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5408 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5409 info.func = __cvmx_error_display;
5410 info.user_info = (long)
5411 "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
5412 fail |= cvmx_error_add(&info);
5414 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5415 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5416 info.status_mask = 1ull<<10 /* ovrerr */;
5417 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5418 info.enable_mask = 1ull<<10 /* ovrerr */;
5420 info.group = CVMX_ERROR_GROUP_ETHERNET;
5421 info.group_index = 3;
5422 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5423 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5424 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5425 info.func = __cvmx_error_display;
5426 info.user_info = (long)
5427 "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
5428 " This interrupt should never assert\n"
5429 " (SGMII/1000Base-X only)\n";
5430 fail |= cvmx_error_add(&info);
5432 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5433 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5434 info.status_mask = 1ull<<20 /* loc_fault */;
5435 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5436 info.enable_mask = 1ull<<20 /* loc_fault */;
5438 info.group = CVMX_ERROR_GROUP_ETHERNET;
5439 info.group_index = 3;
5440 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5441 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5442 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5443 info.func = __cvmx_error_display;
5444 info.user_info = (long)
5445 "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5446 " (XAUI Mode only)\n";
5447 fail |= cvmx_error_add(&info);
5449 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5450 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5451 info.status_mask = 1ull<<21 /* rem_fault */;
5452 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5453 info.enable_mask = 1ull<<21 /* rem_fault */;
5455 info.group = CVMX_ERROR_GROUP_ETHERNET;
5456 info.group_index = 3;
5457 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5458 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5459 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5460 info.func = __cvmx_error_display;
5461 info.user_info = (long)
5462 "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5463 " (XAUI Mode only)\n";
5464 fail |= cvmx_error_add(&info);
5466 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5467 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5468 info.status_mask = 1ull<<22 /* bad_seq */;
5469 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5470 info.enable_mask = 1ull<<22 /* bad_seq */;
5472 info.group = CVMX_ERROR_GROUP_ETHERNET;
5473 info.group_index = 3;
5474 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5475 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5476 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5477 info.func = __cvmx_error_display;
5478 info.user_info = (long)
5479 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
5480 " (XAUI Mode only)\n";
5481 fail |= cvmx_error_add(&info);
5483 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5484 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5485 info.status_mask = 1ull<<23 /* bad_term */;
5486 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5487 info.enable_mask = 1ull<<23 /* bad_term */;
5489 info.group = CVMX_ERROR_GROUP_ETHERNET;
5490 info.group_index = 3;
5491 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5492 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5493 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5494 info.func = __cvmx_error_display;
5495 info.user_info = (long)
5496 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
5497 " than /T/. The error propagation control\n"
5498 " character /E/ will be included as part of the\n"
5499 " frame and does not cause a frame termination.\n"
5500 " (XAUI Mode only)\n";
5501 fail |= cvmx_error_add(&info);
5503 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5504 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5505 info.status_mask = 1ull<<24 /* unsop */;
5506 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5507 info.enable_mask = 1ull<<24 /* unsop */;
5509 info.group = CVMX_ERROR_GROUP_ETHERNET;
5510 info.group_index = 3;
5511 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5512 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5513 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5514 info.func = __cvmx_error_display;
5515 info.user_info = (long)
5516 "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
5517 " (XAUI Mode only)\n";
5518 fail |= cvmx_error_add(&info);
5520 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5521 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5522 info.status_mask = 1ull<<25 /* uneop */;
5523 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5524 info.enable_mask = 1ull<<25 /* uneop */;
5526 info.group = CVMX_ERROR_GROUP_ETHERNET;
5527 info.group_index = 3;
5528 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5529 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5530 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5531 info.func = __cvmx_error_display;
5532 info.user_info = (long)
5533 "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
5534 " (XAUI Mode only)\n";
5535 fail |= cvmx_error_add(&info);
5537 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5538 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5539 info.status_mask = 1ull<<26 /* undat */;
5540 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5541 info.enable_mask = 1ull<<26 /* undat */;
5543 info.group = CVMX_ERROR_GROUP_ETHERNET;
5544 info.group_index = 3;
5545 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5546 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5547 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5548 info.func = __cvmx_error_display;
5549 info.user_info = (long)
5550 "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
5551 " (XAUI Mode only)\n";
5552 fail |= cvmx_error_add(&info);
5554 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5555 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5556 info.status_mask = 1ull<<27 /* hg2fld */;
5557 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5558 info.enable_mask = 1ull<<27 /* hg2fld */;
5560 info.group = CVMX_ERROR_GROUP_ETHERNET;
5561 info.group_index = 3;
5562 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5563 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5564 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5565 info.func = __cvmx_error_display;
5566 info.user_info = (long)
5567 "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
5568 " 1) MSG_TYPE field not 6'b00_0000\n"
5569 " i.e. it is not a FLOW CONTROL message, which\n"
5570 " is the only defined type for HiGig2\n"
5571 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5572 " which is the only defined type for HiGig2\n"
5573 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5574 " Physical Link nor 4'b0010 for Logical Link.\n"
5575 " Those are the only two defined types in HiGig2\n";
5576 fail |= cvmx_error_add(&info);
5578 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5579 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5580 info.status_mask = 1ull<<28 /* hg2cc */;
5581 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5582 info.enable_mask = 1ull<<28 /* hg2cc */;
5584 info.group = CVMX_ERROR_GROUP_ETHERNET;
5585 info.group_index = 3;
5586 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5587 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5588 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5589 info.func = __cvmx_error_display;
5590 info.user_info = (long)
5591 "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5592 " Set when either CRC8 error detected or when\n"
5593 " a Control Character is found in the message\n"
5594 " bytes after the K.SOM\n"
5595 " NOTE: HG2CC has higher priority than HG2FLD\n"
5596 " i.e. a HiGig2 message that results in HG2CC\n"
5597 " getting set, will never set HG2FLD.\n";
5598 fail |= cvmx_error_add(&info);
5600 /* CVMX_GMXX_TX_INT_REG(0) */
5601 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5602 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5603 info.status_mask = 1ull<<0 /* pko_nxa */;
5604 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5605 info.enable_mask = 1ull<<0 /* pko_nxa */;
5607 info.group = CVMX_ERROR_GROUP_ETHERNET;
5608 info.group_index = 0;
5609 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5610 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5611 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5612 info.func = __cvmx_error_display;
5613 info.user_info = (long)
5614 "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
5615 fail |= cvmx_error_add(&info);
5617 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5618 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5619 info.status_mask = 0xfull<<2 /* undflw */;
5620 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5621 info.enable_mask = 0xfull<<2 /* undflw */;
5623 info.group = CVMX_ERROR_GROUP_ETHERNET;
5624 info.group_index = 0;
5625 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5626 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5627 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5628 info.func = __cvmx_error_display;
5629 info.user_info = (long)
5630 "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
5631 fail |= cvmx_error_add(&info);
5633 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5634 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5635 info.status_mask = 0xfull<<20 /* ptp_lost */;
5636 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5637 info.enable_mask = 0xfull<<20 /* ptp_lost */;
5639 info.group = CVMX_ERROR_GROUP_ETHERNET;
5640 info.group_index = 0;
5641 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5642 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5643 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5644 info.func = __cvmx_error_display;
5645 info.user_info = (long)
5646 "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
5647 " sent due to XSCOL\n";
5648 fail |= cvmx_error_add(&info);
5650 /* CVMX_IOB_INT_SUM */
5651 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5652 info.status_addr = CVMX_IOB_INT_SUM;
5653 info.status_mask = 1ull<<0 /* np_sop */;
5654 info.enable_addr = CVMX_IOB_INT_ENB;
5655 info.enable_mask = 1ull<<0 /* np_sop */;
5657 info.group = CVMX_ERROR_GROUP_INTERNAL;
5658 info.group_index = 0;
5659 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5660 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5661 info.parent.status_mask = 1ull<<30 /* iob */;
5662 info.func = __cvmx_error_display;
5663 info.user_info = (long)
5664 "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
5665 " port for a non-passthrough packet.\n"
5666 " The first detected error associated with bits [5:0]\n"
5667 " of this register will only be set here. A new bit\n"
5668 " can be set when the previous reported bit is cleared.\n";
5669 fail |= cvmx_error_add(&info);
5671 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5672 info.status_addr = CVMX_IOB_INT_SUM;
5673 info.status_mask = 1ull<<1 /* np_eop */;
5674 info.enable_addr = CVMX_IOB_INT_ENB;
5675 info.enable_mask = 1ull<<1 /* np_eop */;
5677 info.group = CVMX_ERROR_GROUP_INTERNAL;
5678 info.group_index = 0;
5679 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5680 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5681 info.parent.status_mask = 1ull<<30 /* iob */;
5682 info.func = __cvmx_error_display;
5683 info.user_info = (long)
5684 "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
5685 " port for a non-passthrough packet.\n"
5686 " The first detected error associated with bits [5:0]\n"
5687 " of this register will only be set here. A new bit\n"
5688 " can be set when the previous reported bit is cleared.\n";
5689 fail |= cvmx_error_add(&info);
5691 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5692 info.status_addr = CVMX_IOB_INT_SUM;
5693 info.status_mask = 1ull<<2 /* p_sop */;
5694 info.enable_addr = CVMX_IOB_INT_ENB;
5695 info.enable_mask = 1ull<<2 /* p_sop */;
5697 info.group = CVMX_ERROR_GROUP_INTERNAL;
5698 info.group_index = 0;
5699 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5700 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5701 info.parent.status_mask = 1ull<<30 /* iob */;
5702 info.func = __cvmx_error_display;
5703 info.user_info = (long)
5704 "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
5705 " port for a passthrough packet.\n"
5706 " The first detected error associated with bits [5:0]\n"
5707 " of this register will only be set here. A new bit\n"
5708 " can be set when the previous reported bit is cleared.\n";
5709 fail |= cvmx_error_add(&info);
5711 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5712 info.status_addr = CVMX_IOB_INT_SUM;
5713 info.status_mask = 1ull<<3 /* p_eop */;
5714 info.enable_addr = CVMX_IOB_INT_ENB;
5715 info.enable_mask = 1ull<<3 /* p_eop */;
5717 info.group = CVMX_ERROR_GROUP_INTERNAL;
5718 info.group_index = 0;
5719 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5720 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5721 info.parent.status_mask = 1ull<<30 /* iob */;
5722 info.func = __cvmx_error_display;
5723 info.user_info = (long)
5724 "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
5725 " port for a passthrough packet.\n"
5726 " The first detected error associated with bits [5:0]\n"
5727 " of this register will only be set here. A new bit\n"
5728 " can be set when the previous reported bit is cleared.\n";
5729 fail |= cvmx_error_add(&info);
5731 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5732 info.status_addr = CVMX_IOB_INT_SUM;
5733 info.status_mask = 1ull<<4 /* np_dat */;
5734 info.enable_addr = CVMX_IOB_INT_ENB;
5735 info.enable_mask = 1ull<<4 /* np_dat */;
5737 info.group = CVMX_ERROR_GROUP_INTERNAL;
5738 info.group_index = 0;
5739 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5740 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5741 info.parent.status_mask = 1ull<<30 /* iob */;
5742 info.func = __cvmx_error_display;
5743 info.user_info = (long)
5744 "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
5745 " port for a non-passthrough packet.\n"
5746 " The first detected error associated with bits [5:0]\n"
5747 " of this register will only be set here. A new bit\n"
5748 " can be set when the previous reported bit is cleared.\n";
5749 fail |= cvmx_error_add(&info);
5751 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5752 info.status_addr = CVMX_IOB_INT_SUM;
5753 info.status_mask = 1ull<<5 /* p_dat */;
5754 info.enable_addr = CVMX_IOB_INT_ENB;
5755 info.enable_mask = 1ull<<5 /* p_dat */;
5757 info.group = CVMX_ERROR_GROUP_INTERNAL;
5758 info.group_index = 0;
5759 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5760 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5761 info.parent.status_mask = 1ull<<30 /* iob */;
5762 info.func = __cvmx_error_display;
5763 info.user_info = (long)
5764 "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
5765 " port for a passthrough packet.\n"
5766 " The first detected error associated with bits [5:0]\n"
5767 " of this register will only be set here. A new bit\n"
5768 " can be set when the previous reported bit is cleared.\n";
5769 fail |= cvmx_error_add(&info);
5771 /* CVMX_AGL_GMX_BAD_REG */
5772 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5773 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5774 info.status_mask = 1ull<<32 /* ovrflw */;
5775 info.enable_addr = 0;
5776 info.enable_mask = 0;
5778 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5779 info.group_index = 0;
5780 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5781 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5782 info.parent.status_mask = 1ull<<28 /* agl */;
5783 info.func = __cvmx_error_display;
5784 info.user_info = (long)
5785 "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
5786 fail |= cvmx_error_add(&info);
5788 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5789 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5790 info.status_mask = 1ull<<33 /* txpop */;
5791 info.enable_addr = 0;
5792 info.enable_mask = 0;
5794 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5795 info.group_index = 0;
5796 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5797 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5798 info.parent.status_mask = 1ull<<28 /* agl */;
5799 info.func = __cvmx_error_display;
5800 info.user_info = (long)
5801 "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
5802 fail |= cvmx_error_add(&info);
5804 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5805 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5806 info.status_mask = 1ull<<34 /* txpsh */;
5807 info.enable_addr = 0;
5808 info.enable_mask = 0;
5810 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5811 info.group_index = 0;
5812 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5813 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5814 info.parent.status_mask = 1ull<<28 /* agl */;
5815 info.func = __cvmx_error_display;
5816 info.user_info = (long)
5817 "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
5818 fail |= cvmx_error_add(&info);
5820 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5821 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5822 info.status_mask = 1ull<<35 /* ovrflw1 */;
5823 info.enable_addr = 0;
5824 info.enable_mask = 0;
5826 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5827 info.group_index = 0;
5828 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5829 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5830 info.parent.status_mask = 1ull<<28 /* agl */;
5831 info.func = __cvmx_error_display;
5832 info.user_info = (long)
5833 "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
5834 fail |= cvmx_error_add(&info);
5836 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5837 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5838 info.status_mask = 1ull<<36 /* txpop1 */;
5839 info.enable_addr = 0;
5840 info.enable_mask = 0;
5842 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5843 info.group_index = 0;
5844 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5845 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5846 info.parent.status_mask = 1ull<<28 /* agl */;
5847 info.func = __cvmx_error_display;
5848 info.user_info = (long)
5849 "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
5850 fail |= cvmx_error_add(&info);
5852 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5853 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5854 info.status_mask = 1ull<<37 /* txpsh1 */;
5855 info.enable_addr = 0;
5856 info.enable_mask = 0;
5858 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5859 info.group_index = 0;
5860 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5861 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5862 info.parent.status_mask = 1ull<<28 /* agl */;
5863 info.func = __cvmx_error_display;
5864 info.user_info = (long)
5865 "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
5866 fail |= cvmx_error_add(&info);
5868 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5869 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5870 info.status_mask = 0x3ull<<2 /* out_ovr */;
5871 info.enable_addr = 0;
5872 info.enable_mask = 0;
5874 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5875 info.group_index = 0;
5876 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5877 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5878 info.parent.status_mask = 1ull<<28 /* agl */;
5879 info.func = __cvmx_error_display;
5880 info.user_info = (long)
5881 "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
5882 fail |= cvmx_error_add(&info);
5884 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5885 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5886 info.status_mask = 0x3ull<<22 /* loststat */;
5887 info.enable_addr = 0;
5888 info.enable_mask = 0;
5890 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5891 info.group_index = 0;
5892 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5893 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5894 info.parent.status_mask = 1ull<<28 /* agl */;
5895 info.func = __cvmx_error_display;
5896 info.user_info = (long)
5897 "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
5898 " In MII/RGMII, one bit per port\n"
5899 " TX Stats are corrupted\n";
5900 fail |= cvmx_error_add(&info);
5902 /* CVMX_AGL_GMX_RXX_INT_REG(0) */
5903 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5904 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
5905 info.status_mask = 1ull<<8 /* skperr */;
5906 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
5907 info.enable_mask = 1ull<<8 /* skperr */;
5909 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5910 info.group_index = 0;
5911 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5912 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5913 info.parent.status_mask = 1ull<<28 /* agl */;
5914 info.func = __cvmx_error_display;
5915 info.user_info = (long)
5916 "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
5917 fail |= cvmx_error_add(&info);
5919 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5920 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
5921 info.status_mask = 1ull<<10 /* ovrerr */;
5922 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
5923 info.enable_mask = 1ull<<10 /* ovrerr */;
5925 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5926 info.group_index = 0;
5927 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5928 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5929 info.parent.status_mask = 1ull<<28 /* agl */;
5930 info.func = __cvmx_error_display;
5931 info.user_info = (long)
5932 "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
5933 " This interrupt should never assert\n";
5934 fail |= cvmx_error_add(&info);
5936 /* CVMX_AGL_GMX_RXX_INT_REG(1) */
5937 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5938 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
5939 info.status_mask = 1ull<<8 /* skperr */;
5940 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
5941 info.enable_mask = 1ull<<8 /* skperr */;
5943 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5944 info.group_index = 1;
5945 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5946 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5947 info.parent.status_mask = 1ull<<28 /* agl */;
5948 info.func = __cvmx_error_display;
5949 info.user_info = (long)
5950 "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
5951 fail |= cvmx_error_add(&info);
5953 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5954 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
5955 info.status_mask = 1ull<<10 /* ovrerr */;
5956 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
5957 info.enable_mask = 1ull<<10 /* ovrerr */;
5959 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5960 info.group_index = 1;
5961 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5962 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5963 info.parent.status_mask = 1ull<<28 /* agl */;
5964 info.func = __cvmx_error_display;
5965 info.user_info = (long)
5966 "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
5967 " This interrupt should never assert\n";
5968 fail |= cvmx_error_add(&info);
5970 /* CVMX_AGL_GMX_TX_INT_REG */
5971 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5972 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
5973 info.status_mask = 1ull<<0 /* pko_nxa */;
5974 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
5975 info.enable_mask = 1ull<<0 /* pko_nxa */;
5977 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5978 info.group_index = 0;
5979 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5980 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5981 info.parent.status_mask = 1ull<<28 /* agl */;
5982 info.func = __cvmx_error_display;
5983 info.user_info = (long)
5984 "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
5985 fail |= cvmx_error_add(&info);
5987 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5988 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
5989 info.status_mask = 0x3ull<<2 /* undflw */;
5990 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
5991 info.enable_mask = 0x3ull<<2 /* undflw */;
5993 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5994 info.group_index = 0;
5995 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5996 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5997 info.parent.status_mask = 1ull<<28 /* agl */;
5998 info.func = __cvmx_error_display;
5999 info.user_info = (long)
6000 "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
6001 fail |= cvmx_error_add(&info);
6003 /* CVMX_ZIP_ERROR */
6004 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6005 info.status_addr = CVMX_ZIP_ERROR;
6006 info.status_mask = 1ull<<0 /* doorbell */;
6007 info.enable_addr = CVMX_ZIP_INT_MASK;
6008 info.enable_mask = 1ull<<0 /* doorbell */;
6010 info.group = CVMX_ERROR_GROUP_INTERNAL;
6011 info.group_index = 0;
6012 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6013 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6014 info.parent.status_mask = 1ull<<7 /* zip */;
6015 info.func = __cvmx_error_display;
6016 info.user_info = (long)
6017 "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
6018 fail |= cvmx_error_add(&info);
6020 /* CVMX_DFA_ERROR */
6021 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6022 info.status_addr = CVMX_DFA_ERROR;
6023 info.status_mask = 1ull<<0 /* dblovf */;
6024 info.enable_addr = CVMX_DFA_INTMSK;
6025 info.enable_mask = 1ull<<0 /* dblina */;
6027 info.group = CVMX_ERROR_GROUP_INTERNAL;
6028 info.group_index = 0;
6029 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6030 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6031 info.parent.status_mask = 1ull<<6 /* dfa */;
6032 info.func = __cvmx_error_display;
6033 info.user_info = (long)
6034 "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
6035 " When set, the 20b accumulated doorbell register\n"
6036 " had overflowed (SW wrote too many doorbell requests).\n"
6037 " If the DBLINA had previously been enabled(set),\n"
6038 " an interrupt will be posted. Software can clear\n"
6039 " the interrupt by writing a 1 to this register bit.\n"
6040 " NOTE: Detection of a Doorbell Register overflow\n"
6041 " is a catastrophic error which may leave the DFA\n"
6042 " HW in an unrecoverable state.\n";
6043 fail |= cvmx_error_add(&info);
6045 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6046 info.status_addr = CVMX_DFA_ERROR;
6047 info.status_mask = 0x7ull<<1 /* dc0perr */;
6048 info.enable_addr = CVMX_DFA_INTMSK;
6049 info.enable_mask = 0x7ull<<1 /* dc0pena */;
6051 info.group = CVMX_ERROR_GROUP_INTERNAL;
6052 info.group_index = 0;
6053 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6054 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6055 info.parent.status_mask = 1ull<<6 /* dfa */;
6056 info.func = __cvmx_error_display;
6057 info.user_info = (long)
6058 "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
6059 " See also DFA_DTCFADR register which contains the\n"
6060 " failing addresses for the internal node cache RAMs.\n";
6061 fail |= cvmx_error_add(&info);
6063 /* CVMX_SRIOX_INT_REG(0) */
6064 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6065 info.status_addr = CVMX_SRIOX_INT_REG(0);
6066 info.status_mask = 1ull<<4 /* bar_err */;
6067 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6068 info.enable_mask = 1ull<<4 /* bar_err */;
6070 info.group = CVMX_ERROR_GROUP_SRIO;
6071 info.group_index = 0;
6072 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6073 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6074 info.parent.status_mask = 1ull<<32 /* srio0 */;
6075 info.func = __cvmx_error_display;
6076 info.user_info = (long)
6077 "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
6078 fail |= cvmx_error_add(&info);
6080 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6081 info.status_addr = CVMX_SRIOX_INT_REG(0);
6082 info.status_mask = 1ull<<5 /* deny_wr */;
6083 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6084 info.enable_mask = 1ull<<5 /* deny_wr */;
6086 info.group = CVMX_ERROR_GROUP_SRIO;
6087 info.group_index = 0;
6088 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6089 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6090 info.parent.status_mask = 1ull<<32 /* srio0 */;
6091 info.func = __cvmx_error_display;
6092 info.user_info = (long)
6093 "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
6094 fail |= cvmx_error_add(&info);
6096 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6097 info.status_addr = CVMX_SRIOX_INT_REG(0);
6098 info.status_mask = 1ull<<6 /* sli_err */;
6099 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6100 info.enable_mask = 1ull<<6 /* sli_err */;
6102 info.group = CVMX_ERROR_GROUP_SRIO;
6103 info.group_index = 0;
6104 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6105 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6106 info.parent.status_mask = 1ull<<32 /* srio0 */;
6107 info.func = __cvmx_error_display;
6108 info.user_info = (long)
6109 "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
6110 " See SRIO(0..1)_INT_INFO[1:0]\n";
6111 fail |= cvmx_error_add(&info);
6113 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6114 info.status_addr = CVMX_SRIOX_INT_REG(0);
6115 info.status_mask = 1ull<<9 /* mce_rx */;
6116 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6117 info.enable_mask = 1ull<<9 /* mce_rx */;
6119 info.group = CVMX_ERROR_GROUP_SRIO;
6120 info.group_index = 0;
6121 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6122 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6123 info.parent.status_mask = 1ull<<32 /* srio0 */;
6124 info.func = __cvmx_error_display;
6125 info.user_info = (long)
6126 "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
6127 fail |= cvmx_error_add(&info);
6129 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6130 info.status_addr = CVMX_SRIOX_INT_REG(0);
6131 info.status_mask = 1ull<<12 /* log_erb */;
6132 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6133 info.enable_mask = 1ull<<12 /* log_erb */;
6135 info.group = CVMX_ERROR_GROUP_SRIO;
6136 info.group_index = 0;
6137 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6138 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6139 info.parent.status_mask = 1ull<<32 /* srio0 */;
6140 info.func = __cvmx_error_display;
6141 info.user_info = (long)
6142 "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
6143 " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
6144 fail |= cvmx_error_add(&info);
6146 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6147 info.status_addr = CVMX_SRIOX_INT_REG(0);
6148 info.status_mask = 1ull<<13 /* phy_erb */;
6149 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6150 info.enable_mask = 1ull<<13 /* phy_erb */;
6152 info.group = CVMX_ERROR_GROUP_SRIO;
6153 info.group_index = 0;
6154 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6155 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6156 info.parent.status_mask = 1ull<<32 /* srio0 */;
6157 info.func = __cvmx_error_display;
6158 info.user_info = (long)
6159 "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
6160 " See SRIOMAINT*_ERB_ATTR_CAPT\n";
6161 fail |= cvmx_error_add(&info);
6163 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6164 info.status_addr = CVMX_SRIOX_INT_REG(0);
6165 info.status_mask = 1ull<<18 /* omsg_err */;
6166 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6167 info.enable_mask = 1ull<<18 /* omsg_err */;
6169 info.group = CVMX_ERROR_GROUP_SRIO;
6170 info.group_index = 0;
6171 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6172 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6173 info.parent.status_mask = 1ull<<32 /* srio0 */;
6174 info.func = __cvmx_error_display;
6175 info.user_info = (long)
6176 "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
6177 " See SRIO(0..1)_INT_INFO2\n";
6178 fail |= cvmx_error_add(&info);
6180 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6181 info.status_addr = CVMX_SRIOX_INT_REG(0);
6182 info.status_mask = 1ull<<19 /* pko_err */;
6183 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6184 info.enable_mask = 1ull<<19 /* pko_err */;
6186 info.group = CVMX_ERROR_GROUP_SRIO;
6187 info.group_index = 0;
6188 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6189 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6190 info.parent.status_mask = 1ull<<32 /* srio0 */;
6191 info.func = __cvmx_error_display;
6192 info.user_info = (long)
6193 "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
6194 fail |= cvmx_error_add(&info);
6196 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6197 info.status_addr = CVMX_SRIOX_INT_REG(0);
6198 info.status_mask = 1ull<<20 /* rtry_err */;
6199 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6200 info.enable_mask = 1ull<<20 /* rtry_err */;
6202 info.group = CVMX_ERROR_GROUP_SRIO;
6203 info.group_index = 0;
6204 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6205 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6206 info.parent.status_mask = 1ull<<32 /* srio0 */;
6207 info.func = __cvmx_error_display;
6208 info.user_info = (long)
6209 "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
6210 " See SRIO(0..1)_INT_INFO3\n"
6211 " When one or more of the segments in an outgoing\n"
6212 " message have a RTRY_ERR, SRIO will not set\n"
6213 " OMSG* after the message \"transfer\".\n";
6214 fail |= cvmx_error_add(&info);
6216 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6217 info.status_addr = CVMX_SRIOX_INT_REG(0);
6218 info.status_mask = 1ull<<21 /* f_error */;
6219 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6220 info.enable_mask = 1ull<<21 /* f_error */;
6222 info.group = CVMX_ERROR_GROUP_SRIO;
6223 info.group_index = 0;
6224 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6225 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6226 info.parent.status_mask = 1ull<<32 /* srio0 */;
6227 info.func = __cvmx_error_display;
6228 info.user_info = (long)
6229 "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
6230 fail |= cvmx_error_add(&info);
6232 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6233 info.status_addr = CVMX_SRIOX_INT_REG(0);
6234 info.status_mask = 1ull<<22 /* mac_buf */;
6235 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6236 info.enable_mask = 1ull<<22 /* mac_buf */;
6238 info.group = CVMX_ERROR_GROUP_SRIO;
6239 info.group_index = 0;
6240 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6241 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6242 info.parent.status_mask = 1ull<<32 /* srio0 */;
6243 info.func = __cvmx_error_display;
6244 info.user_info = (long)
6245 "ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
6246 " See SRIO(0..1)_MAC_BUFFERS\n";
6247 fail |= cvmx_error_add(&info);
6249 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6250 info.status_addr = CVMX_SRIOX_INT_REG(0);
6251 info.status_mask = 1ull<<23 /* degrad */;
6252 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6253 info.enable_mask = 1ull<<23 /* degrade */;
6255 info.group = CVMX_ERROR_GROUP_SRIO;
6256 info.group_index = 0;
6257 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6258 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6259 info.parent.status_mask = 1ull<<32 /* srio0 */;
6260 info.func = __cvmx_error_display;
6261 info.user_info = (long)
6262 "ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
6263 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6264 fail |= cvmx_error_add(&info);
6266 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6267 info.status_addr = CVMX_SRIOX_INT_REG(0);
6268 info.status_mask = 1ull<<24 /* fail */;
6269 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6270 info.enable_mask = 1ull<<24 /* fail */;
6272 info.group = CVMX_ERROR_GROUP_SRIO;
6273 info.group_index = 0;
6274 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6275 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6276 info.parent.status_mask = 1ull<<32 /* srio0 */;
6277 info.func = __cvmx_error_display;
6278 info.user_info = (long)
6279 "ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
6280 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6281 fail |= cvmx_error_add(&info);
6283 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6284 info.status_addr = CVMX_SRIOX_INT_REG(0);
6285 info.status_mask = 1ull<<25 /* ttl_tout */;
6286 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6287 info.enable_mask = 1ull<<25 /* ttl_tout */;
6289 info.group = CVMX_ERROR_GROUP_SRIO;
6290 info.group_index = 0;
6291 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6292 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6293 info.parent.status_mask = 1ull<<32 /* srio0 */;
6294 info.func = __cvmx_error_display;
6295 info.user_info = (long)
6296 "ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
6297 " See SRIOMAINT(0..1)_DROP_PACKET\n";
6298 fail |= cvmx_error_add(&info);
6300 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6301 info.status_addr = CVMX_SRIOX_INT_REG(0);
6302 info.status_mask = 1ull<<26 /* zero_pkt */;
6303 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
6304 info.enable_mask = 1ull<<26 /* zero_pkt */;
6306 info.group = CVMX_ERROR_GROUP_SRIO;
6307 info.group_index = 0;
6308 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6309 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6310 info.parent.status_mask = 1ull<<32 /* srio0 */;
6311 info.func = __cvmx_error_display;
6312 info.user_info = (long)
6313 "ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
6314 fail |= cvmx_error_add(&info);
6316 /* CVMX_SRIOX_INT_REG(1) */
6317 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6318 info.status_addr = CVMX_SRIOX_INT_REG(1);
6319 info.status_mask = 1ull<<4 /* bar_err */;
6320 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6321 info.enable_mask = 1ull<<4 /* bar_err */;
6323 info.group = CVMX_ERROR_GROUP_SRIO;
6324 info.group_index = 1;
6325 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6326 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6327 info.parent.status_mask = 1ull<<33 /* srio1 */;
6328 info.func = __cvmx_error_display;
6329 info.user_info = (long)
6330 "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
6331 fail |= cvmx_error_add(&info);
6333 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6334 info.status_addr = CVMX_SRIOX_INT_REG(1);
6335 info.status_mask = 1ull<<5 /* deny_wr */;
6336 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6337 info.enable_mask = 1ull<<5 /* deny_wr */;
6339 info.group = CVMX_ERROR_GROUP_SRIO;
6340 info.group_index = 1;
6341 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6342 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6343 info.parent.status_mask = 1ull<<33 /* srio1 */;
6344 info.func = __cvmx_error_display;
6345 info.user_info = (long)
6346 "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
6347 fail |= cvmx_error_add(&info);
6349 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6350 info.status_addr = CVMX_SRIOX_INT_REG(1);
6351 info.status_mask = 1ull<<6 /* sli_err */;
6352 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6353 info.enable_mask = 1ull<<6 /* sli_err */;
6355 info.group = CVMX_ERROR_GROUP_SRIO;
6356 info.group_index = 1;
6357 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6358 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6359 info.parent.status_mask = 1ull<<33 /* srio1 */;
6360 info.func = __cvmx_error_display;
6361 info.user_info = (long)
6362 "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
6363 " See SRIO(0..1)_INT_INFO[1:0]\n";
6364 fail |= cvmx_error_add(&info);
6366 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6367 info.status_addr = CVMX_SRIOX_INT_REG(1);
6368 info.status_mask = 1ull<<9 /* mce_rx */;
6369 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6370 info.enable_mask = 1ull<<9 /* mce_rx */;
6372 info.group = CVMX_ERROR_GROUP_SRIO;
6373 info.group_index = 1;
6374 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6375 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6376 info.parent.status_mask = 1ull<<33 /* srio1 */;
6377 info.func = __cvmx_error_display;
6378 info.user_info = (long)
6379 "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n";
6380 fail |= cvmx_error_add(&info);
6382 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6383 info.status_addr = CVMX_SRIOX_INT_REG(1);
6384 info.status_mask = 1ull<<12 /* log_erb */;
6385 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6386 info.enable_mask = 1ull<<12 /* log_erb */;
6388 info.group = CVMX_ERROR_GROUP_SRIO;
6389 info.group_index = 1;
6390 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6391 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6392 info.parent.status_mask = 1ull<<33 /* srio1 */;
6393 info.func = __cvmx_error_display;
6394 info.user_info = (long)
6395 "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
6396 " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
6397 fail |= cvmx_error_add(&info);
6399 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6400 info.status_addr = CVMX_SRIOX_INT_REG(1);
6401 info.status_mask = 1ull<<13 /* phy_erb */;
6402 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6403 info.enable_mask = 1ull<<13 /* phy_erb */;
6405 info.group = CVMX_ERROR_GROUP_SRIO;
6406 info.group_index = 1;
6407 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6408 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6409 info.parent.status_mask = 1ull<<33 /* srio1 */;
6410 info.func = __cvmx_error_display;
6411 info.user_info = (long)
6412 "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n"
6413 " See SRIOMAINT*_ERB_ATTR_CAPT\n";
6414 fail |= cvmx_error_add(&info);
6416 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6417 info.status_addr = CVMX_SRIOX_INT_REG(1);
6418 info.status_mask = 1ull<<18 /* omsg_err */;
6419 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6420 info.enable_mask = 1ull<<18 /* omsg_err */;
6422 info.group = CVMX_ERROR_GROUP_SRIO;
6423 info.group_index = 1;
6424 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6425 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6426 info.parent.status_mask = 1ull<<33 /* srio1 */;
6427 info.func = __cvmx_error_display;
6428 info.user_info = (long)
6429 "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
6430 " See SRIO(0..1)_INT_INFO2\n";
6431 fail |= cvmx_error_add(&info);
6433 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6434 info.status_addr = CVMX_SRIOX_INT_REG(1);
6435 info.status_mask = 1ull<<19 /* pko_err */;
6436 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6437 info.enable_mask = 1ull<<19 /* pko_err */;
6439 info.group = CVMX_ERROR_GROUP_SRIO;
6440 info.group_index = 1;
6441 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6442 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6443 info.parent.status_mask = 1ull<<33 /* srio1 */;
6444 info.func = __cvmx_error_display;
6445 info.user_info = (long)
6446 "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n";
6447 fail |= cvmx_error_add(&info);
6449 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6450 info.status_addr = CVMX_SRIOX_INT_REG(1);
6451 info.status_mask = 1ull<<20 /* rtry_err */;
6452 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6453 info.enable_mask = 1ull<<20 /* rtry_err */;
6455 info.group = CVMX_ERROR_GROUP_SRIO;
6456 info.group_index = 1;
6457 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6458 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6459 info.parent.status_mask = 1ull<<33 /* srio1 */;
6460 info.func = __cvmx_error_display;
6461 info.user_info = (long)
6462 "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
6463 " See SRIO(0..1)_INT_INFO3\n"
6464 " When one or more of the segments in an outgoing\n"
6465 " message have a RTRY_ERR, SRIO will not set\n"
6466 " OMSG* after the message \"transfer\".\n";
6467 fail |= cvmx_error_add(&info);
6469 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6470 info.status_addr = CVMX_SRIOX_INT_REG(1);
6471 info.status_mask = 1ull<<21 /* f_error */;
6472 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6473 info.enable_mask = 1ull<<21 /* f_error */;
6475 info.group = CVMX_ERROR_GROUP_SRIO;
6476 info.group_index = 1;
6477 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6478 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6479 info.parent.status_mask = 1ull<<33 /* srio1 */;
6480 info.func = __cvmx_error_display;
6481 info.user_info = (long)
6482 "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
6483 fail |= cvmx_error_add(&info);
6485 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6486 info.status_addr = CVMX_SRIOX_INT_REG(1);
6487 info.status_mask = 1ull<<22 /* mac_buf */;
6488 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6489 info.enable_mask = 1ull<<22 /* mac_buf */;
6491 info.group = CVMX_ERROR_GROUP_SRIO;
6492 info.group_index = 1;
6493 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6494 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6495 info.parent.status_mask = 1ull<<33 /* srio1 */;
6496 info.func = __cvmx_error_display;
6497 info.user_info = (long)
6498 "ERROR SRIOX_INT_REG(1)[MAC_BUF]: SRIO MAC Buffer CRC Error (Pass 2)\n"
6499 " See SRIO(0..1)_MAC_BUFFERS\n";
6500 fail |= cvmx_error_add(&info);
6502 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6503 info.status_addr = CVMX_SRIOX_INT_REG(1);
6504 info.status_mask = 1ull<<23 /* degrad */;
6505 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6506 info.enable_mask = 1ull<<23 /* degrade */;
6508 info.group = CVMX_ERROR_GROUP_SRIO;
6509 info.group_index = 1;
6510 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6511 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6512 info.parent.status_mask = 1ull<<33 /* srio1 */;
6513 info.func = __cvmx_error_display;
6514 info.user_info = (long)
6515 "ERROR SRIOX_INT_REG(1)[DEGRAD]: ERB Error Rate reached Degrade Count (Pass 2)\n"
6516 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6517 fail |= cvmx_error_add(&info);
6519 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6520 info.status_addr = CVMX_SRIOX_INT_REG(1);
6521 info.status_mask = 1ull<<24 /* fail */;
6522 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6523 info.enable_mask = 1ull<<24 /* fail */;
6525 info.group = CVMX_ERROR_GROUP_SRIO;
6526 info.group_index = 1;
6527 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6528 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6529 info.parent.status_mask = 1ull<<33 /* srio1 */;
6530 info.func = __cvmx_error_display;
6531 info.user_info = (long)
6532 "ERROR SRIOX_INT_REG(1)[FAIL]: ERB Error Rate reached Fail Count (Pass 2)\n"
6533 " See SRIOMAINT(0..1)_ERB_ERR_RATE\n";
6534 fail |= cvmx_error_add(&info);
6536 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6537 info.status_addr = CVMX_SRIOX_INT_REG(1);
6538 info.status_mask = 1ull<<25 /* ttl_tout */;
6539 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6540 info.enable_mask = 1ull<<25 /* ttl_tout */;
6542 info.group = CVMX_ERROR_GROUP_SRIO;
6543 info.group_index = 1;
6544 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6545 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6546 info.parent.status_mask = 1ull<<33 /* srio1 */;
6547 info.func = __cvmx_error_display;
6548 info.user_info = (long)
6549 "ERROR SRIOX_INT_REG(1)[TTL_TOUT]: Outgoing Packet Time to Live Timeout (Pass 2)\n"
6550 " See SRIOMAINT(0..1)_DROP_PACKET\n";
6551 fail |= cvmx_error_add(&info);
6553 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6554 info.status_addr = CVMX_SRIOX_INT_REG(1);
6555 info.status_mask = 1ull<<26 /* zero_pkt */;
6556 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6557 info.enable_mask = 1ull<<26 /* zero_pkt */;
6559 info.group = CVMX_ERROR_GROUP_SRIO;
6560 info.group_index = 1;
6561 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6562 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6563 info.parent.status_mask = 1ull<<33 /* srio1 */;
6564 info.func = __cvmx_error_display;
6565 info.user_info = (long)
6566 "ERROR SRIOX_INT_REG(1)[ZERO_PKT]: Received Incoming SRIO Zero byte packet (Pass 2)\n";
6567 fail |= cvmx_error_add(&info);
6569 /* CVMX_PEXP_SLI_INT_SUM */
6570 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6571 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6572 info.status_mask = 1ull<<0 /* rml_to */;
6573 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6574 info.enable_mask = 1ull<<0 /* rml_to */;
6576 info.group = CVMX_ERROR_GROUP_INTERNAL;
6577 info.group_index = 0;
6578 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6579 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6580 info.parent.status_mask = 1ull<<3 /* sli */;
6581 info.func = __cvmx_error_display;
6582 info.user_info = (long)
6583 "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
6584 " within 0xffff core clocks.\n";
6585 fail |= cvmx_error_add(&info);
6587 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6588 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6589 info.status_mask = 1ull<<1 /* reserved_1_1 */;
6590 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6591 info.enable_mask = 1ull<<1 /* reserved_1_1 */;
6593 info.group = CVMX_ERROR_GROUP_INTERNAL;
6594 info.group_index = 0;
6595 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6596 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6597 info.parent.status_mask = 1ull<<3 /* sli */;
6598 info.func = __cvmx_error_display;
6599 info.user_info = (long)
6600 "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
6602 fail |= cvmx_error_add(&info);
6604 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6605 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6606 info.status_mask = 1ull<<2 /* bar0_to */;
6607 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6608 info.enable_mask = 1ull<<2 /* bar0_to */;
6610 info.group = CVMX_ERROR_GROUP_INTERNAL;
6611 info.group_index = 0;
6612 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6613 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6614 info.parent.status_mask = 1ull<<3 /* sli */;
6615 info.func = __cvmx_error_display;
6616 info.user_info = (long)
6617 "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
6618 " read-data/commit in 0xffff core clocks.\n";
6619 fail |= cvmx_error_add(&info);
6621 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6622 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6623 info.status_mask = 1ull<<3 /* iob2big */;
6624 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6625 info.enable_mask = 1ull<<3 /* iob2big */;
6627 info.group = CVMX_ERROR_GROUP_INTERNAL;
6628 info.group_index = 0;
6629 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6630 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6631 info.parent.status_mask = 1ull<<3 /* sli */;
6632 info.func = __cvmx_error_display;
6633 info.user_info = (long)
6634 "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
6635 fail |= cvmx_error_add(&info);
6637 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6638 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6639 info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
6640 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6641 info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
6643 info.group = CVMX_ERROR_GROUP_INTERNAL;
6644 info.group_index = 0;
6645 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6646 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6647 info.parent.status_mask = 1ull<<3 /* sli */;
6648 info.func = __cvmx_error_display;
6649 info.user_info = (long)
6650 "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
6652 fail |= cvmx_error_add(&info);
6654 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6655 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6656 info.status_mask = 1ull<<8 /* m0_up_b0 */;
6657 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6658 info.enable_mask = 1ull<<8 /* m0_up_b0 */;
6660 info.group = CVMX_ERROR_GROUP_INTERNAL;
6661 info.group_index = 0;
6662 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6663 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6664 info.parent.status_mask = 1ull<<3 /* sli */;
6665 info.func = __cvmx_error_display;
6666 info.user_info = (long)
6667 "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
6668 " This occurs when the BAR 0 address space is\n"
6670 fail |= cvmx_error_add(&info);
6672 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6673 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6674 info.status_mask = 1ull<<9 /* m0_up_wi */;
6675 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6676 info.enable_mask = 1ull<<9 /* m0_up_wi */;
6678 info.group = CVMX_ERROR_GROUP_INTERNAL;
6679 info.group_index = 0;
6680 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6681 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6682 info.parent.status_mask = 1ull<<3 /* sli */;
6683 info.func = __cvmx_error_display;
6684 info.user_info = (long)
6685 "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
6686 " from MAC 0. This occurs when the window registers\n"
6687 " are disabeld and a window register access occurs.\n";
6688 fail |= cvmx_error_add(&info);
6690 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6691 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6692 info.status_mask = 1ull<<10 /* m0_un_b0 */;
6693 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6694 info.enable_mask = 1ull<<10 /* m0_un_b0 */;
6696 info.group = CVMX_ERROR_GROUP_INTERNAL;
6697 info.group_index = 0;
6698 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6699 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6700 info.parent.status_mask = 1ull<<3 /* sli */;
6701 info.func = __cvmx_error_display;
6702 info.user_info = (long)
6703 "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
6704 " This occurs when the BAR 0 address space is\n"
6706 fail |= cvmx_error_add(&info);
6708 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6709 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6710 info.status_mask = 1ull<<11 /* m0_un_wi */;
6711 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6712 info.enable_mask = 1ull<<11 /* m0_un_wi */;
6714 info.group = CVMX_ERROR_GROUP_INTERNAL;
6715 info.group_index = 0;
6716 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6717 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6718 info.parent.status_mask = 1ull<<3 /* sli */;
6719 info.func = __cvmx_error_display;
6720 info.user_info = (long)
6721 "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
6722 " from MAC 0. This occurs when the window registers\n"
6723 " are disabeld and a window register access occurs.\n";
6724 fail |= cvmx_error_add(&info);
6726 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6727 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6728 info.status_mask = 1ull<<12 /* m1_up_b0 */;
6729 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6730 info.enable_mask = 1ull<<12 /* m1_up_b0 */;
6732 info.group = CVMX_ERROR_GROUP_INTERNAL;
6733 info.group_index = 0;
6734 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6735 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6736 info.parent.status_mask = 1ull<<3 /* sli */;
6737 info.func = __cvmx_error_display;
6738 info.user_info = (long)
6739 "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
6740 " This occurs when the BAR 0 address space is\n"
6742 fail |= cvmx_error_add(&info);
6744 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6745 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6746 info.status_mask = 1ull<<13 /* m1_up_wi */;
6747 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6748 info.enable_mask = 1ull<<13 /* m1_up_wi */;
6750 info.group = CVMX_ERROR_GROUP_INTERNAL;
6751 info.group_index = 0;
6752 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6753 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6754 info.parent.status_mask = 1ull<<3 /* sli */;
6755 info.func = __cvmx_error_display;
6756 info.user_info = (long)
6757 "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
6758 " from MAC 1. This occurs when the window registers\n"
6759 " are disabeld and a window register access occurs.\n";
6760 fail |= cvmx_error_add(&info);
6762 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6763 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6764 info.status_mask = 1ull<<14 /* m1_un_b0 */;
6765 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6766 info.enable_mask = 1ull<<14 /* m1_un_b0 */;
6768 info.group = CVMX_ERROR_GROUP_INTERNAL;
6769 info.group_index = 0;
6770 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6771 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6772 info.parent.status_mask = 1ull<<3 /* sli */;
6773 info.func = __cvmx_error_display;
6774 info.user_info = (long)
6775 "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
6776 " This occurs when the BAR 0 address space is\n"
6778 fail |= cvmx_error_add(&info);
6780 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6781 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6782 info.status_mask = 1ull<<15 /* m1_un_wi */;
6783 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6784 info.enable_mask = 1ull<<15 /* m1_un_wi */;
6786 info.group = CVMX_ERROR_GROUP_INTERNAL;
6787 info.group_index = 0;
6788 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6789 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6790 info.parent.status_mask = 1ull<<3 /* sli */;
6791 info.func = __cvmx_error_display;
6792 info.user_info = (long)
6793 "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
6794 " from MAC 1. This occurs when the window registers\n"
6795 " are disabeld and a window register access occurs.\n";
6796 fail |= cvmx_error_add(&info);
6798 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6799 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6800 info.status_mask = 1ull<<48 /* pidbof */;
6801 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6802 info.enable_mask = 1ull<<48 /* pidbof */;
6804 info.group = CVMX_ERROR_GROUP_INTERNAL;
6805 info.group_index = 0;
6806 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6807 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6808 info.parent.status_mask = 1ull<<3 /* sli */;
6809 info.func = __cvmx_error_display;
6810 info.user_info = (long)
6811 "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
6812 " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
6813 fail |= cvmx_error_add(&info);
6815 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6816 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6817 info.status_mask = 1ull<<49 /* psldbof */;
6818 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6819 info.enable_mask = 1ull<<49 /* psldbof */;
6821 info.group = CVMX_ERROR_GROUP_INTERNAL;
6822 info.group_index = 0;
6823 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6824 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6825 info.parent.status_mask = 1ull<<3 /* sli */;
6826 info.func = __cvmx_error_display;
6827 info.user_info = (long)
6828 "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
6829 " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
6830 fail |= cvmx_error_add(&info);
6832 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6833 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6834 info.status_mask = 1ull<<50 /* pout_err */;
6835 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6836 info.enable_mask = 1ull<<50 /* pout_err */;
6838 info.group = CVMX_ERROR_GROUP_INTERNAL;
6839 info.group_index = 0;
6840 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6841 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6842 info.parent.status_mask = 1ull<<3 /* sli */;
6843 info.func = __cvmx_error_display;
6844 info.user_info = (long)
6845 "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
6847 fail |= cvmx_error_add(&info);
6849 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6850 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6851 info.status_mask = 1ull<<51 /* pin_bp */;
6852 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6853 info.enable_mask = 1ull<<51 /* pin_bp */;
6855 info.group = CVMX_ERROR_GROUP_INTERNAL;
6856 info.group_index = 0;
6857 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6858 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6859 info.parent.status_mask = 1ull<<3 /* sli */;
6860 info.func = __cvmx_error_display;
6861 info.user_info = (long)
6862 "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
6863 " See SLI_PKT_IN_BP\n";
6864 fail |= cvmx_error_add(&info);
6866 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6867 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6868 info.status_mask = 1ull<<52 /* pgl_err */;
6869 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6870 info.enable_mask = 1ull<<52 /* pgl_err */;
6872 info.group = CVMX_ERROR_GROUP_INTERNAL;
6873 info.group_index = 0;
6874 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6875 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6876 info.parent.status_mask = 1ull<<3 /* sli */;
6877 info.func = __cvmx_error_display;
6878 info.user_info = (long)
6879 "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
6880 " read this bit is set.\n";
6881 fail |= cvmx_error_add(&info);
6883 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6884 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6885 info.status_mask = 1ull<<53 /* pdi_err */;
6886 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6887 info.enable_mask = 1ull<<53 /* pdi_err */;
6889 info.group = CVMX_ERROR_GROUP_INTERNAL;
6890 info.group_index = 0;
6891 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6892 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6893 info.parent.status_mask = 1ull<<3 /* sli */;
6894 info.func = __cvmx_error_display;
6895 info.user_info = (long)
6896 "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
6897 " this bit is set.\n";
6898 fail |= cvmx_error_add(&info);
6900 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6901 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6902 info.status_mask = 1ull<<54 /* pop_err */;
6903 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6904 info.enable_mask = 1ull<<54 /* pop_err */;
6906 info.group = CVMX_ERROR_GROUP_INTERNAL;
6907 info.group_index = 0;
6908 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6909 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6910 info.parent.status_mask = 1ull<<3 /* sli */;
6911 info.func = __cvmx_error_display;
6912 info.user_info = (long)
6913 "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
6914 " pointer pair this bit is set.\n";
6915 fail |= cvmx_error_add(&info);
6917 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6918 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6919 info.status_mask = 1ull<<55 /* pins_err */;
6920 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6921 info.enable_mask = 1ull<<55 /* pins_err */;
6923 info.group = CVMX_ERROR_GROUP_INTERNAL;
6924 info.group_index = 0;
6925 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6926 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6927 info.parent.status_mask = 1ull<<3 /* sli */;
6928 info.func = __cvmx_error_display;
6929 info.user_info = (long)
6930 "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
6931 " this bit is set.\n";
6932 fail |= cvmx_error_add(&info);
6934 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6935 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6936 info.status_mask = 1ull<<56 /* sprt0_err */;
6937 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6938 info.enable_mask = 1ull<<56 /* sprt0_err */;
6940 info.group = CVMX_ERROR_GROUP_INTERNAL;
6941 info.group_index = 0;
6942 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6943 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6944 info.parent.status_mask = 1ull<<3 /* sli */;
6945 info.func = __cvmx_error_display;
6946 info.user_info = (long)
6947 "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
6948 " this bit is set.\n";
6949 fail |= cvmx_error_add(&info);
6951 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6952 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6953 info.status_mask = 1ull<<57 /* sprt1_err */;
6954 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6955 info.enable_mask = 1ull<<57 /* sprt1_err */;
6957 info.group = CVMX_ERROR_GROUP_INTERNAL;
6958 info.group_index = 0;
6959 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6960 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6961 info.parent.status_mask = 1ull<<3 /* sli */;
6962 info.func = __cvmx_error_display;
6963 info.user_info = (long)
6964 "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
6965 " this bit is set.\n";
6966 fail |= cvmx_error_add(&info);
6968 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6969 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6970 info.status_mask = 1ull<<60 /* ill_pad */;
6971 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6972 info.enable_mask = 1ull<<60 /* ill_pad */;
6974 info.group = CVMX_ERROR_GROUP_INTERNAL;
6975 info.group_index = 0;
6976 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6977 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6978 info.parent.status_mask = 1ull<<3 /* sli */;
6979 info.func = __cvmx_error_display;
6980 info.user_info = (long)
6981 "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
6982 " range of the Packet-CSR, but for an unused\n"
6984 fail |= cvmx_error_add(&info);
6986 /* CVMX_DPI_INT_REG */
6987 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6988 info.status_addr = CVMX_DPI_INT_REG;
6989 info.status_mask = 1ull<<0 /* nderr */;
6990 info.enable_addr = CVMX_DPI_INT_EN;
6991 info.enable_mask = 1ull<<0 /* nderr */;
6993 info.group = CVMX_ERROR_GROUP_INTERNAL;
6994 info.group_index = 0;
6995 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6996 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6997 info.parent.status_mask = 1ull<<41 /* dpi */;
6998 info.func = __cvmx_error_display;
6999 info.user_info = (long)
7000 "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
7001 " DPI received a NCB transaction on the outbound\n"
7002 " bus to the DPI deviceID, but the command was not\n"
7004 fail |= cvmx_error_add(&info);
7006 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7007 info.status_addr = CVMX_DPI_INT_REG;
7008 info.status_mask = 1ull<<1 /* nfovr */;
7009 info.enable_addr = CVMX_DPI_INT_EN;
7010 info.enable_mask = 1ull<<1 /* nfovr */;
7012 info.group = CVMX_ERROR_GROUP_INTERNAL;
7013 info.group_index = 0;
7014 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7015 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7016 info.parent.status_mask = 1ull<<41 /* dpi */;
7017 info.func = __cvmx_error_display;
7018 info.user_info = (long)
7019 "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
7020 " DPI can store upto 16 CSR request. The FIFO will\n"
7021 " overflow if that number is exceeded.\n";
7022 fail |= cvmx_error_add(&info);
7024 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7025 info.status_addr = CVMX_DPI_INT_REG;
7026 info.status_mask = 0xffull<<8 /* dmadbo */;
7027 info.enable_addr = CVMX_DPI_INT_EN;
7028 info.enable_mask = 0xffull<<8 /* dmadbo */;
7030 info.group = CVMX_ERROR_GROUP_INTERNAL;
7031 info.group_index = 0;
7032 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7033 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7034 info.parent.status_mask = 1ull<<41 /* dpi */;
7035 info.func = __cvmx_error_display;
7036 info.user_info = (long)
7037 "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
7038 " DPI has a 32-bit counter for each request's queue\n"
7039 " outstanding doorbell counts. Interrupt will fire\n"
7040 " if the count overflows.\n";
7041 fail |= cvmx_error_add(&info);
7043 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7044 info.status_addr = CVMX_DPI_INT_REG;
7045 info.status_mask = 1ull<<16 /* req_badadr */;
7046 info.enable_addr = CVMX_DPI_INT_EN;
7047 info.enable_mask = 1ull<<16 /* req_badadr */;
7049 info.group = CVMX_ERROR_GROUP_INTERNAL;
7050 info.group_index = 0;
7051 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7052 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7053 info.parent.status_mask = 1ull<<41 /* dpi */;
7054 info.func = __cvmx_error_display;
7055 info.user_info = (long)
7056 "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
7057 " Interrupt will fire if DPI forms an instruction\n"
7058 " fetch to the NULL pointer.\n";
7059 fail |= cvmx_error_add(&info);
7061 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7062 info.status_addr = CVMX_DPI_INT_REG;
7063 info.status_mask = 1ull<<17 /* req_badlen */;
7064 info.enable_addr = CVMX_DPI_INT_EN;
7065 info.enable_mask = 1ull<<17 /* req_badlen */;
7067 info.group = CVMX_ERROR_GROUP_INTERNAL;
7068 info.group_index = 0;
7069 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7070 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7071 info.parent.status_mask = 1ull<<41 /* dpi */;
7072 info.func = __cvmx_error_display;
7073 info.user_info = (long)
7074 "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
7075 " Interrupt will fire if DPI forms an instruction\n"
7076 " fetch with length of zero.\n";
7077 fail |= cvmx_error_add(&info);
7079 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7080 info.status_addr = CVMX_DPI_INT_REG;
7081 info.status_mask = 1ull<<18 /* req_ovrflw */;
7082 info.enable_addr = CVMX_DPI_INT_EN;
7083 info.enable_mask = 1ull<<18 /* req_ovrflw */;
7085 info.group = CVMX_ERROR_GROUP_INTERNAL;
7086 info.group_index = 0;
7087 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7088 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7089 info.parent.status_mask = 1ull<<41 /* dpi */;
7090 info.func = __cvmx_error_display;
7091 info.user_info = (long)
7092 "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
7093 " DPI tracks outstanding instructions fetches.\n"
7094 " Interrupt will fire when FIFO overflows.\n";
7095 fail |= cvmx_error_add(&info);
7097 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7098 info.status_addr = CVMX_DPI_INT_REG;
7099 info.status_mask = 1ull<<19 /* req_undflw */;
7100 info.enable_addr = CVMX_DPI_INT_EN;
7101 info.enable_mask = 1ull<<19 /* req_undflw */;
7103 info.group = CVMX_ERROR_GROUP_INTERNAL;
7104 info.group_index = 0;
7105 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7106 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7107 info.parent.status_mask = 1ull<<41 /* dpi */;
7108 info.func = __cvmx_error_display;
7109 info.user_info = (long)
7110 "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
7111 " DPI tracks outstanding instructions fetches.\n"
7112 " Interrupt will fire when FIFO underflows.\n";
7113 fail |= cvmx_error_add(&info);
7115 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7116 info.status_addr = CVMX_DPI_INT_REG;
7117 info.status_mask = 1ull<<20 /* req_anull */;
7118 info.enable_addr = CVMX_DPI_INT_EN;
7119 info.enable_mask = 1ull<<20 /* req_anull */;
7121 info.group = CVMX_ERROR_GROUP_INTERNAL;
7122 info.group_index = 0;
7123 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7124 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7125 info.parent.status_mask = 1ull<<41 /* dpi */;
7126 info.func = __cvmx_error_display;
7127 info.user_info = (long)
7128 "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
7129 " Fetched instruction word was 0.\n";
7130 fail |= cvmx_error_add(&info);
7132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7133 info.status_addr = CVMX_DPI_INT_REG;
7134 info.status_mask = 1ull<<21 /* req_inull */;
7135 info.enable_addr = CVMX_DPI_INT_EN;
7136 info.enable_mask = 1ull<<21 /* req_inull */;
7138 info.group = CVMX_ERROR_GROUP_INTERNAL;
7139 info.group_index = 0;
7140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7141 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7142 info.parent.status_mask = 1ull<<41 /* dpi */;
7143 info.func = __cvmx_error_display;
7144 info.user_info = (long)
7145 "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
7146 " Next pointer was NULL.\n";
7147 fail |= cvmx_error_add(&info);
7149 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7150 info.status_addr = CVMX_DPI_INT_REG;
7151 info.status_mask = 1ull<<22 /* req_badfil */;
7152 info.enable_addr = CVMX_DPI_INT_EN;
7153 info.enable_mask = 1ull<<22 /* req_badfil */;
7155 info.group = CVMX_ERROR_GROUP_INTERNAL;
7156 info.group_index = 0;
7157 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7158 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7159 info.parent.status_mask = 1ull<<41 /* dpi */;
7160 info.func = __cvmx_error_display;
7161 info.user_info = (long)
7162 "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
7163 " Instruction fill when none outstanding.\n";
7164 fail |= cvmx_error_add(&info);
7166 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7167 info.status_addr = CVMX_DPI_INT_REG;
7168 info.status_mask = 1ull<<24 /* sprt0_rst */;
7169 info.enable_addr = CVMX_DPI_INT_EN;
7170 info.enable_mask = 1ull<<24 /* sprt0_rst */;
7172 info.group = CVMX_ERROR_GROUP_INTERNAL;
7173 info.group_index = 0;
7174 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7175 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7176 info.parent.status_mask = 1ull<<41 /* dpi */;
7177 info.func = __cvmx_error_display;
7178 info.user_info = (long)
7179 "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
7180 " destination port was in reset.\n"
7181 " this bit is set.\n";
7182 fail |= cvmx_error_add(&info);
7184 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7185 info.status_addr = CVMX_DPI_INT_REG;
7186 info.status_mask = 1ull<<25 /* sprt1_rst */;
7187 info.enable_addr = CVMX_DPI_INT_EN;
7188 info.enable_mask = 1ull<<25 /* sprt1_rst */;
7190 info.group = CVMX_ERROR_GROUP_INTERNAL;
7191 info.group_index = 0;
7192 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7193 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7194 info.parent.status_mask = 1ull<<41 /* dpi */;
7195 info.func = __cvmx_error_display;
7196 info.user_info = (long)
7197 "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
7198 " destination port was in reset.\n"
7199 " this bit is set.\n";
7200 fail |= cvmx_error_add(&info);
7202 /* CVMX_DPI_PKT_ERR_RSP */
7203 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7204 info.status_addr = CVMX_DPI_PKT_ERR_RSP;
7205 info.status_mask = 1ull<<0 /* pkterr */;
7206 info.enable_addr = 0;
7207 info.enable_mask = 0;
7209 info.group = CVMX_ERROR_GROUP_INTERNAL;
7210 info.group_index = 0;
7211 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7212 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7213 info.parent.status_mask = 1ull<<41 /* dpi */;
7214 info.func = __cvmx_error_display;
7215 info.user_info = (long)
7216 "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
7217 " the I/O subsystem.\n";
7218 fail |= cvmx_error_add(&info);
7220 /* CVMX_DPI_REQ_ERR_RSP */
7221 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7222 info.status_addr = CVMX_DPI_REQ_ERR_RSP;
7223 info.status_mask = 0xffull<<0 /* qerr */;
7224 info.enable_addr = 0;
7225 info.enable_mask = 0;
7227 info.group = CVMX_ERROR_GROUP_INTERNAL;
7228 info.group_index = 0;
7229 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7230 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7231 info.parent.status_mask = 1ull<<41 /* dpi */;
7232 info.func = __cvmx_error_display;
7233 info.user_info = (long)
7234 "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
7235 " ErrorResponse from the I/O subsystem.\n"
7236 " SW must clear the bit before the the cooresponding\n"
7237 " instruction queue will continue processing\n"
7238 " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
7239 fail |= cvmx_error_add(&info);
7241 /* CVMX_DPI_REQ_ERR_RST */
7242 info.reg_type = CVMX_ERROR_REGISTER_IO64;
7243 info.status_addr = CVMX_DPI_REQ_ERR_RST;
7244 info.status_mask = 0xffull<<0 /* qerr */;
7245 info.enable_addr = 0;
7246 info.enable_mask = 0;
7248 info.group = CVMX_ERROR_GROUP_INTERNAL;
7249 info.group_index = 0;
7250 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
7251 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7252 info.parent.status_mask = 1ull<<41 /* dpi */;
7253 info.func = __cvmx_error_display;
7254 info.user_info = (long)
7255 "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
7256 " instruction because the source or destination\n"
7258 " SW must clear the bit before the the cooresponding\n"
7259 " instruction queue will continue processing\n"
7260 " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
7261 fail |= cvmx_error_add(&info);