sys/contrib/octeon-sdk/cvmx-error-init-cn66xx.c

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  39
  40
  41 /**
  42  * @file
  43  *
  44  * Automatically generated error messages for cn66xx.
  45  *
  46  * This file is auto generated. Do not edit.
  47  *
  48  * <hr>$Revision$<hr>
  49  *
  50  * <hr><h2>Error tree for CN66XX</h2>
  51  * @dot
  52  * digraph cn66xx
  53  * {
  54  *     rankdir=LR;
  55  *     node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
  56  *     edge [fontsize=7, font=helvitica];
  57  *     cvmx_root [label="ROOT|<root>root"];
  58  *     cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
  59  *     cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
  60  *     cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
  61  *     cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
  62  *     cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
  63  *     cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
  64  *     cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
  65  *     cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
  66  *     cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
  67  *     cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
  68  *     cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs1>asxpcs1|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<gmx1>gmx1|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<usb>usb|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<sli>sli|<dpi>dpi"];
  69  *     cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<bigwr>bigwr|<bigrd>bigrd|<tad0>tad0"];
  70  *     cvmx_l2c_tad0_int [label="L2C_TADX_INT(0)|<l2dsbe>l2dsbe|<l2ddbe>l2ddbe|<tagsbe>tagsbe|<tagdbe>tagdbe|<vbfsbe>vbfsbe|<vbfdbe>vbfdbe|<noway>noway|<rddislmc>rddislmc|<wrdislmc>wrdislmc"];
  71  *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_tad0_int [label="tad0"];
  72  *     cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
  73  *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
  74  *     cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
  75  *     cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
  76  *     cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
  77  *     cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
  78  *     cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
  79  *     cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
  80  *     cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
  81  *     cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
  82  *     cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
  83  *     cvmx_pcs1_int0_reg [label="PCSX_INTX_REG(0,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  84  *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int0_reg [label="asxpcs1"];
  85  *     cvmx_pcs1_int1_reg [label="PCSX_INTX_REG(1,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  86  *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int1_reg [label="asxpcs1"];
  87  *     cvmx_pcs1_int2_reg [label="PCSX_INTX_REG(2,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  88  *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int2_reg [label="asxpcs1"];
  89  *     cvmx_pcs1_int3_reg [label="PCSX_INTX_REG(3,1)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  90  *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcs1_int3_reg [label="asxpcs1"];
  91  *     cvmx_pcsx1_int_reg [label="PCSXX_INT_REG(1)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
  92  *     cvmx_ciu_block_int:asxpcs1:e -> cvmx_pcsx1_int_reg [label="asxpcs1"];
  93  *     cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  94  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
  95  *     cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  96  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
  97  *     cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
  98  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
  99  *     cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
 100  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
 101  *     cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<bitlckls>bitlckls|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
 102  *     cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
 103  *     cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
 104  *     cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
 105  *     cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
 106  *     cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
 107  *     cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
 108  *     cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
 109  *     cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
 110  *     cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
 111  *     cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
 112  *     cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
 113  *     cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
 114  *     cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
 115  *     cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr|<pool0th>pool0th|<pool1th>pool1th|<pool2th>pool2th|<pool3th>pool3th|<pool4th>pool4th|<pool5th>pool5th|<pool6th>pool6th|<pool7th>pool7th|<free0>free0|<free1>free1|<free2>free2|<free3>free3|<free4>free4|<free5>free5|<free6>free6|<free7>free7|<paddr_e>paddr_e"];
 116  *     cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
 117  *     cvmx_gmx1_bad_reg [label="GMXX_BAD_REG(1)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
 118  *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_bad_reg [label="gmx1"];
 119  *     cvmx_gmx1_rx0_int_reg [label="GMXX_RXX_INT_REG(0,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 120  *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx0_int_reg [label="gmx1"];
 121  *     cvmx_gmx1_rx1_int_reg [label="GMXX_RXX_INT_REG(1,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 122  *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx1_int_reg [label="gmx1"];
 123  *     cvmx_gmx1_rx2_int_reg [label="GMXX_RXX_INT_REG(2,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 124  *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx2_int_reg [label="gmx1"];
 125  *     cvmx_gmx1_rx3_int_reg [label="GMXX_RXX_INT_REG(3,1)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 126  *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_rx3_int_reg [label="gmx1"];
 127  *     cvmx_gmx1_tx_int_reg [label="GMXX_TX_INT_REG(1)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
 128  *     cvmx_ciu_block_int:gmx1:e -> cvmx_gmx1_tx_int_reg [label="gmx1"];
 129  *     cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
 130  *     cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
 131  *     cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<rst_link2>rst_link2|<rst_link3>rst_link3|<perst0>perst0|<perst1>perst1"];
 132  *     cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
 133  *     cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
 134  *     cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
 135  *     cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
 136  *     cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
 137  *     cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
 138  *     cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
 139  *     cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
 140  *     cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
 141  *     cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
 142  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
 143  *     cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 144  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
 145  *     cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 146  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
 147  *     cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 148  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
 149  *     cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
 150  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
 151  *     cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
 152  *     cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
 153  *     cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
 154  *     cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
 155  *     cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
 156  *     cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
 157  *     cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
 158  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
 159  *     cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
 160  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
 161  *     cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
 162  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
 163  *     cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
 164  *     cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
 165  *     cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
 166  *     cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
 167  *     cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
 168  *     cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
 169  *     cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error|<mac_buf>mac_buf|<degrad>degrad|<fail>fail|<ttl_tout>ttl_tout|<zero_pkt>zero_pkt"];
 170  *     cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
 171  *     cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<m2_up_b0>m2_up_b0|<m2_up_wi>m2_up_wi|<m2_un_b0>m2_un_b0|<m2_un_wi>m2_un_wi|<m3_up_b0>m3_up_b0|<m3_up_wi>m3_up_wi|<m3_un_b0>m3_un_b0|<m3_un_wi>m3_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<sprt2_err>sprt2_err|<sprt3_err>sprt3_err|<ill_pad>ill_pad"];
 172  *     cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
 173  *     cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst|<sprt2_rst>sprt2_rst|<sprt3_rst>sprt3_rst"];
 174  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
 175  *     cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
 176  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
 177  *     cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
 178  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
 179  *     cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
 180  *     cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
 181  *     cvmx_pcs1_int0_reg -> cvmx_pcs1_int1_reg [style=invis];
 182  *     cvmx_pcs1_int1_reg -> cvmx_pcs1_int2_reg [style=invis];
 183  *     cvmx_pcs1_int2_reg -> cvmx_pcs1_int3_reg [style=invis];
 184  *     cvmx_pcs1_int3_reg -> cvmx_pcsx1_int_reg [style=invis];
 185  *     cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
 186  *     cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
 187  *     cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
 188  *     cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
 189  *     cvmx_gmx1_bad_reg -> cvmx_gmx1_rx0_int_reg [style=invis];
 190  *     cvmx_gmx1_rx0_int_reg -> cvmx_gmx1_rx1_int_reg [style=invis];
 191  *     cvmx_gmx1_rx1_int_reg -> cvmx_gmx1_rx2_int_reg [style=invis];
 192  *     cvmx_gmx1_rx2_int_reg -> cvmx_gmx1_rx3_int_reg [style=invis];
 193  *     cvmx_gmx1_rx3_int_reg -> cvmx_gmx1_tx_int_reg [style=invis];
 194  *     cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
 195  *     cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
 196  *     cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
 197  *     cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
 198  *     cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
 199  *     cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
 200  *     cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
 201  *     cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
 202  *     cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
 203  *     cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
 204  *     cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
 205  *     cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
 206  *     cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
 207  * }
 208  * @enddot
 209  */
 210 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
 211 #include <asm/octeon/cvmx.h>
 212 #include <asm/octeon/cvmx-error.h>
 213 #include <asm/octeon/cvmx-error-custom.h>
 214 #include <asm/octeon/cvmx-csr-typedefs.h>
 215 #else
 216 #include "cvmx.h"
 217 #include "cvmx-error.h"
 218 #include "cvmx-error-custom.h"
 219 #endif
 220
 221 int cvmx_error_initialize_cn66xx(void);
 222
 223 int cvmx_error_initialize_cn66xx(void)
 224 {
 225     cvmx_error_info_t info;
 226     int fail = 0;
 227
 228     /* CVMX_CIU_INTX_SUM0(0) */
 229     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 230     info.status_addr        = CVMX_CIU_INTX_SUM0(0);
 231     info.status_mask        = 0;
 232     info.enable_addr        = 0;
 233     info.enable_mask        = 0;
 234     info.flags              = 0;
 235     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 236     info.group_index        = 0;
 237     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 238     info.parent.status_addr = 0;
 239     info.parent.status_mask = 0;
 240     info.func               = __cvmx_error_decode;
 241     info.user_info          = 0;
 242     fail |= cvmx_error_add(&info);
 243
 244     /* CVMX_MIXX_ISR(0) */
 245     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 246     info.status_addr        = CVMX_MIXX_ISR(0);
 247     info.status_mask        = 1ull<<0 /* odblovf */;
 248     info.enable_addr        = CVMX_MIXX_INTENA(0);
 249     info.enable_mask        = 1ull<<0 /* ovfena */;
 250     info.flags              = 0;
 251     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 252     info.group_index        = 0;
 253     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 254     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 255     info.parent.status_mask = 1ull<<62 /* mii */;
 256     info.func               = __cvmx_error_display;
 257     info.user_info          = (long)
 258         "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
 259         "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
 260         "    with a value greater than the remaining #of\n"
 261         "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
 262         "    the following occurs:\n"
 263         "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
 264         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 265         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 266         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 267         "    and the local interrupt mask bit(OVFENA) is set, than an\n"
 268         "    interrupt is reported for this event.\n"
 269         "    SW should keep track of the #I-Ring Entries in use\n"
 270         "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
 271         "    future ODBELL writes don't exceed the size of the\n"
 272         "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
 273         "    SW must reclaim O-Ring Entries by writing to the\n"
 274         "    MIX_ORCNT[ORCNT]. .\n"
 275         "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
 276         "    If it occurs, it's an indication that SW has\n"
 277         "    overwritten the O-Ring buffer, and the only recourse\n"
 278         "    is a HW reset.\n";
 279     fail |= cvmx_error_add(&info);
 280
 281     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 282     info.status_addr        = CVMX_MIXX_ISR(0);
 283     info.status_mask        = 1ull<<1 /* idblovf */;
 284     info.enable_addr        = CVMX_MIXX_INTENA(0);
 285     info.enable_mask        = 1ull<<1 /* ivfena */;
 286     info.flags              = 0;
 287     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 288     info.group_index        = 0;
 289     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 290     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 291     info.parent.status_mask = 1ull<<62 /* mii */;
 292     info.func               = __cvmx_error_display;
 293     info.user_info          = (long)
 294         "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
 295         "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
 296         "    with a value greater than the remaining #of\n"
 297         "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
 298         "    the following occurs:\n"
 299         "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
 300         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 301         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 302         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 303         "    and the local interrupt mask bit(IVFENA) is set, than an\n"
 304         "    interrupt is reported for this event.\n"
 305         "    SW should keep track of the #I-Ring Entries in use\n"
 306         "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
 307         "    future IDBELL writes don't exceed the size of the\n"
 308         "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
 309         "    SW must reclaim I-Ring Entries by keeping track of the\n"
 310         "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
 311         "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
 312         "    total #packets(not IRing Entries) and SW must further\n"
 313         "    keep track of the # of I-Ring Entries associated with\n"
 314         "    each packet as they are processed.\n"
 315         "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
 316         "    If it occurs, it's an indication that SW has\n"
 317         "    overwritten the I-Ring buffer, and the only recourse\n"
 318         "    is a HW reset.\n";
 319     fail |= cvmx_error_add(&info);
 320
 321     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 322     info.status_addr        = CVMX_MIXX_ISR(0);
 323     info.status_mask        = 1ull<<4 /* data_drp */;
 324     info.enable_addr        = CVMX_MIXX_INTENA(0);
 325     info.enable_mask        = 1ull<<4 /* data_drpena */;
 326     info.flags              = 0;
 327     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 328     info.group_index        = 0;
 329     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 330     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 331     info.parent.status_mask = 1ull<<62 /* mii */;
 332     info.func               = __cvmx_error_display;
 333     info.user_info          = (long)
 334         "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
 335         "    If this does occur, the DATA_DRP is set and the\n"
 336         "    CIU_INTx_SUM0,4[MII] bits are set.\n"
 337         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 338         "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
 339         "    interrupt is reported for this event.\n";
 340     fail |= cvmx_error_add(&info);
 341
 342     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 343     info.status_addr        = CVMX_MIXX_ISR(0);
 344     info.status_mask        = 1ull<<5 /* irun */;
 345     info.enable_addr        = CVMX_MIXX_INTENA(0);
 346     info.enable_mask        = 1ull<<5 /* irunena */;
 347     info.flags              = 0;
 348     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 349     info.group_index        = 0;
 350     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 351     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 352     info.parent.status_mask = 1ull<<62 /* mii */;
 353     info.func               = __cvmx_error_display;
 354     info.user_info          = (long)
 355         "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
 356         "    If SW writes a larger value than what is currently\n"
 357         "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
 358         "    underflow condition.\n"
 359         "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
 360         "    NOTE: If an IRUN underflow condition is detected,\n"
 361         "    the integrity of the MIX/AGL HW state has\n"
 362         "    been compromised. To recover, SW must issue a\n"
 363         "    software reset sequence (see: MIX_CTL[RESET]\n";
 364     fail |= cvmx_error_add(&info);
 365
 366     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 367     info.status_addr        = CVMX_MIXX_ISR(0);
 368     info.status_mask        = 1ull<<6 /* orun */;
 369     info.enable_addr        = CVMX_MIXX_INTENA(0);
 370     info.enable_mask        = 1ull<<6 /* orunena */;
 371     info.flags              = 0;
 372     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 373     info.group_index        = 0;
 374     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 375     info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
 376     info.parent.status_mask = 1ull<<62 /* mii */;
 377     info.func               = __cvmx_error_display;
 378     info.user_info          = (long)
 379         "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
 380         "    If SW writes a larger value than what is currently\n"
 381         "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
 382         "    underflow condition.\n"
 383         "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
 384         "    NOTE: If an ORUN underflow condition is detected,\n"
 385         "    the integrity of the MIX/AGL HW state has\n"
 386         "    been compromised. To recover, SW must issue a\n"
 387         "    software reset sequence (see: MIX_CTL[RESET]\n";
 388     fail |= cvmx_error_add(&info);
 389
 390     /* CVMX_CIU_INT_SUM1 */
 391     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 392     info.status_addr        = CVMX_CIU_INT_SUM1;
 393     info.status_mask        = 0;
 394     info.enable_addr        = 0;
 395     info.enable_mask        = 0;
 396     info.flags              = 0;
 397     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 398     info.group_index        = 0;
 399     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 400     info.parent.status_addr = 0;
 401     info.parent.status_mask = 0;
 402     info.func               = __cvmx_error_decode;
 403     info.user_info          = 0;
 404     fail |= cvmx_error_add(&info);
 405
 406     /* CVMX_MIXX_ISR(1) */
 407     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 408     info.status_addr        = CVMX_MIXX_ISR(1);
 409     info.status_mask        = 1ull<<0 /* odblovf */;
 410     info.enable_addr        = CVMX_MIXX_INTENA(1);
 411     info.enable_mask        = 1ull<<0 /* ovfena */;
 412     info.flags              = 0;
 413     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 414     info.group_index        = 1;
 415     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 416     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 417     info.parent.status_mask = 1ull<<18 /* mii1 */;
 418     info.func               = __cvmx_error_display;
 419     info.user_info          = (long)
 420         "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
 421         "    If SW attempts to write to the MIX_ORING2[ODBELL]\n"
 422         "    with a value greater than the remaining #of\n"
 423         "    O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
 424         "    the following occurs:\n"
 425         "    1) The  MIX_ORING2[ODBELL] write is IGNORED\n"
 426         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 427         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 428         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 429         "    and the local interrupt mask bit(OVFENA) is set, than an\n"
 430         "    interrupt is reported for this event.\n"
 431         "    SW should keep track of the #I-Ring Entries in use\n"
 432         "    (ie: cumulative # of ODBELL writes),  and ensure that\n"
 433         "    future ODBELL writes don't exceed the size of the\n"
 434         "    O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
 435         "    SW must reclaim O-Ring Entries by writing to the\n"
 436         "    MIX_ORCNT[ORCNT]. .\n"
 437         "    NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
 438         "    If it occurs, it's an indication that SW has\n"
 439         "    overwritten the O-Ring buffer, and the only recourse\n"
 440         "    is a HW reset.\n";
 441     fail |= cvmx_error_add(&info);
 442
 443     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 444     info.status_addr        = CVMX_MIXX_ISR(1);
 445     info.status_mask        = 1ull<<1 /* idblovf */;
 446     info.enable_addr        = CVMX_MIXX_INTENA(1);
 447     info.enable_mask        = 1ull<<1 /* ivfena */;
 448     info.flags              = 0;
 449     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 450     info.group_index        = 1;
 451     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 452     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 453     info.parent.status_mask = 1ull<<18 /* mii1 */;
 454     info.func               = __cvmx_error_display;
 455     info.user_info          = (long)
 456         "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
 457         "    If SW attempts to write to the MIX_IRING2[IDBELL]\n"
 458         "    with a value greater than the remaining #of\n"
 459         "    I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
 460         "    the following occurs:\n"
 461         "    1) The  MIX_IRING2[IDBELL] write is IGNORED\n"
 462         "    2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
 463         "       bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
 464         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 465         "    and the local interrupt mask bit(IVFENA) is set, than an\n"
 466         "    interrupt is reported for this event.\n"
 467         "    SW should keep track of the #I-Ring Entries in use\n"
 468         "    (ie: cumulative # of IDBELL writes),  and ensure that\n"
 469         "    future IDBELL writes don't exceed the size of the\n"
 470         "    I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
 471         "    SW must reclaim I-Ring Entries by keeping track of the\n"
 472         "    #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
 473         "    NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
 474         "    total #packets(not IRing Entries) and SW must further\n"
 475         "    keep track of the # of I-Ring Entries associated with\n"
 476         "    each packet as they are processed.\n"
 477         "    NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
 478         "    If it occurs, it's an indication that SW has\n"
 479         "    overwritten the I-Ring buffer, and the only recourse\n"
 480         "    is a HW reset.\n";
 481     fail |= cvmx_error_add(&info);
 482
 483     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 484     info.status_addr        = CVMX_MIXX_ISR(1);
 485     info.status_mask        = 1ull<<4 /* data_drp */;
 486     info.enable_addr        = CVMX_MIXX_INTENA(1);
 487     info.enable_mask        = 1ull<<4 /* data_drpena */;
 488     info.flags              = 0;
 489     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 490     info.group_index        = 1;
 491     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 492     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 493     info.parent.status_mask = 1ull<<18 /* mii1 */;
 494     info.func               = __cvmx_error_display;
 495     info.user_info          = (long)
 496         "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
 497         "    If this does occur, the DATA_DRP is set and the\n"
 498         "    CIU_INTx_SUM0,4[MII] bits are set.\n"
 499         "    If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
 500         "    and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
 501         "    interrupt is reported for this event.\n";
 502     fail |= cvmx_error_add(&info);
 503
 504     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 505     info.status_addr        = CVMX_MIXX_ISR(1);
 506     info.status_mask        = 1ull<<5 /* irun */;
 507     info.enable_addr        = CVMX_MIXX_INTENA(1);
 508     info.enable_mask        = 1ull<<5 /* irunena */;
 509     info.flags              = 0;
 510     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 511     info.group_index        = 1;
 512     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 513     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 514     info.parent.status_mask = 1ull<<18 /* mii1 */;
 515     info.func               = __cvmx_error_display;
 516     info.user_info          = (long)
 517         "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
 518         "    If SW writes a larger value than what is currently\n"
 519         "    in the MIX_IRCNT[IRCNT], then HW will report the\n"
 520         "    underflow condition.\n"
 521         "    NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
 522         "    NOTE: If an IRUN underflow condition is detected,\n"
 523         "    the integrity of the MIX/AGL HW state has\n"
 524         "    been compromised. To recover, SW must issue a\n"
 525         "    software reset sequence (see: MIX_CTL[RESET]\n";
 526     fail |= cvmx_error_add(&info);
 527
 528     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 529     info.status_addr        = CVMX_MIXX_ISR(1);
 530     info.status_mask        = 1ull<<6 /* orun */;
 531     info.enable_addr        = CVMX_MIXX_INTENA(1);
 532     info.enable_mask        = 1ull<<6 /* orunena */;
 533     info.flags              = 0;
 534     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
 535     info.group_index        = 1;
 536     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 537     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 538     info.parent.status_mask = 1ull<<18 /* mii1 */;
 539     info.func               = __cvmx_error_display;
 540     info.user_info          = (long)
 541         "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
 542         "    If SW writes a larger value than what is currently\n"
 543         "    in the MIX_ORCNT[ORCNT], then HW will report the\n"
 544         "    underflow condition.\n"
 545         "    NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
 546         "    NOTE: If an ORUN underflow condition is detected,\n"
 547         "    the integrity of the MIX/AGL HW state has\n"
 548         "    been compromised. To recover, SW must issue a\n"
 549         "    software reset sequence (see: MIX_CTL[RESET]\n";
 550     fail |= cvmx_error_add(&info);
 551
 552     /* CVMX_NDF_INT */
 553     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 554     info.status_addr        = CVMX_NDF_INT;
 555     info.status_mask        = 1ull<<2 /* wdog */;
 556     info.enable_addr        = CVMX_NDF_INT_EN;
 557     info.enable_mask        = 1ull<<2 /* wdog */;
 558     info.flags              = 0;
 559     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 560     info.group_index        = 0;
 561     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 562     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 563     info.parent.status_mask = 1ull<<19 /* nand */;
 564     info.func               = __cvmx_error_display;
 565     info.user_info          = (long)
 566         "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
 567     fail |= cvmx_error_add(&info);
 568
 569     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 570     info.status_addr        = CVMX_NDF_INT;
 571     info.status_mask        = 1ull<<3 /* sm_bad */;
 572     info.enable_addr        = CVMX_NDF_INT_EN;
 573     info.enable_mask        = 1ull<<3 /* sm_bad */;
 574     info.flags              = 0;
 575     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 576     info.group_index        = 0;
 577     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 578     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 579     info.parent.status_mask = 1ull<<19 /* nand */;
 580     info.func               = __cvmx_error_display;
 581     info.user_info          = (long)
 582         "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
 583     fail |= cvmx_error_add(&info);
 584
 585     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 586     info.status_addr        = CVMX_NDF_INT;
 587     info.status_mask        = 1ull<<4 /* ecc_1bit */;
 588     info.enable_addr        = CVMX_NDF_INT_EN;
 589     info.enable_mask        = 1ull<<4 /* ecc_1bit */;
 590     info.flags              = 0;
 591     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 592     info.group_index        = 0;
 593     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 594     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 595     info.parent.status_mask = 1ull<<19 /* nand */;
 596     info.func               = __cvmx_error_display;
 597     info.user_info          = (long)
 598         "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
 599     fail |= cvmx_error_add(&info);
 600
 601     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 602     info.status_addr        = CVMX_NDF_INT;
 603     info.status_mask        = 1ull<<5 /* ecc_mult */;
 604     info.enable_addr        = CVMX_NDF_INT_EN;
 605     info.enable_mask        = 1ull<<5 /* ecc_mult */;
 606     info.flags              = 0;
 607     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 608     info.group_index        = 0;
 609     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 610     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 611     info.parent.status_mask = 1ull<<19 /* nand */;
 612     info.func               = __cvmx_error_display;
 613     info.user_info          = (long)
 614         "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
 615     fail |= cvmx_error_add(&info);
 616
 617     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 618     info.status_addr        = CVMX_NDF_INT;
 619     info.status_mask        = 1ull<<6 /* ovrf */;
 620     info.enable_addr        = CVMX_NDF_INT_EN;
 621     info.enable_mask        = 1ull<<6 /* ovrf */;
 622     info.flags              = 0;
 623     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 624     info.group_index        = 0;
 625     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 626     info.parent.status_addr = CVMX_CIU_INT_SUM1;
 627     info.parent.status_mask = 1ull<<19 /* nand */;
 628     info.func               = __cvmx_error_display;
 629     info.user_info          = (long)
 630         "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
 631         "    fatal error.\n";
 632     fail |= cvmx_error_add(&info);
 633
 634     /* CVMX_CIU_BLOCK_INT */
 635     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 636     info.status_addr        = CVMX_CIU_BLOCK_INT;
 637     info.status_mask        = 0;
 638     info.enable_addr        = 0;
 639     info.enable_mask        = 0;
 640     info.flags              = 0;
 641     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 642     info.group_index        = 0;
 643     info.parent.reg_type    = __CVMX_ERROR_REGISTER_NONE;
 644     info.parent.status_addr = 0;
 645     info.parent.status_mask = 0;
 646     info.func               = __cvmx_error_decode;
 647     info.user_info          = 0;
 648     fail |= cvmx_error_add(&info);
 649
 650     /* CVMX_L2C_INT_REG */
 651     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 652     info.status_addr        = CVMX_L2C_INT_REG;
 653     info.status_mask        = 1ull<<0 /* holerd */;
 654     info.enable_addr        = CVMX_L2C_INT_ENA;
 655     info.enable_mask        = 1ull<<0 /* holerd */;
 656     info.flags              = 0;
 657     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 658     info.group_index        = 0;
 659     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 660     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 661     info.parent.status_mask = 1ull<<16 /* l2c */;
 662     info.func               = __cvmx_error_display;
 663     info.user_info          = (long)
 664         "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
 665     fail |= cvmx_error_add(&info);
 666
 667     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 668     info.status_addr        = CVMX_L2C_INT_REG;
 669     info.status_mask        = 1ull<<1 /* holewr */;
 670     info.enable_addr        = CVMX_L2C_INT_ENA;
 671     info.enable_mask        = 1ull<<1 /* holewr */;
 672     info.flags              = 0;
 673     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 674     info.group_index        = 0;
 675     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 676     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 677     info.parent.status_mask = 1ull<<16 /* l2c */;
 678     info.func               = __cvmx_error_display;
 679     info.user_info          = (long)
 680         "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
 681     fail |= cvmx_error_add(&info);
 682
 683     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 684     info.status_addr        = CVMX_L2C_INT_REG;
 685     info.status_mask        = 1ull<<2 /* vrtwr */;
 686     info.enable_addr        = CVMX_L2C_INT_ENA;
 687     info.enable_mask        = 1ull<<2 /* vrtwr */;
 688     info.flags              = 0;
 689     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 690     info.group_index        = 0;
 691     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 692     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 693     info.parent.status_mask = 1ull<<16 /* l2c */;
 694     info.func               = __cvmx_error_display;
 695     info.user_info          = (long)
 696         "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
 697         "    Set when L2C_VRT_MEM blocked a store.\n";
 698     fail |= cvmx_error_add(&info);
 699
 700     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 701     info.status_addr        = CVMX_L2C_INT_REG;
 702     info.status_mask        = 1ull<<3 /* vrtidrng */;
 703     info.enable_addr        = CVMX_L2C_INT_ENA;
 704     info.enable_mask        = 1ull<<3 /* vrtidrng */;
 705     info.flags              = 0;
 706     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 707     info.group_index        = 0;
 708     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 709     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 710     info.parent.status_mask = 1ull<<16 /* l2c */;
 711     info.func               = __cvmx_error_display;
 712     info.user_info          = (long)
 713         "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
 714         "    Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
 715         "    store.\n";
 716     fail |= cvmx_error_add(&info);
 717
 718     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 719     info.status_addr        = CVMX_L2C_INT_REG;
 720     info.status_mask        = 1ull<<4 /* vrtadrng */;
 721     info.enable_addr        = CVMX_L2C_INT_ENA;
 722     info.enable_mask        = 1ull<<4 /* vrtadrng */;
 723     info.flags              = 0;
 724     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 725     info.group_index        = 0;
 726     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 727     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 728     info.parent.status_mask = 1ull<<16 /* l2c */;
 729     info.func               = __cvmx_error_display;
 730     info.user_info          = (long)
 731         "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
 732         "    Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
 733         "    store.\n"
 734         "    L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
 735     fail |= cvmx_error_add(&info);
 736
 737     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 738     info.status_addr        = CVMX_L2C_INT_REG;
 739     info.status_mask        = 1ull<<5 /* vrtpe */;
 740     info.enable_addr        = CVMX_L2C_INT_ENA;
 741     info.enable_mask        = 1ull<<5 /* vrtpe */;
 742     info.flags              = 0;
 743     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 744     info.group_index        = 0;
 745     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 746     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 747     info.parent.status_mask = 1ull<<16 /* l2c */;
 748     info.func               = __cvmx_error_display;
 749     info.user_info          = (long)
 750         "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
 751         "    Whenever an L2C_VRT_MEM read finds a parity error,\n"
 752         "    that L2C_VRT_MEM cannot cause stores to be blocked.\n"
 753         "    Software should correct the error.\n";
 754     fail |= cvmx_error_add(&info);
 755
 756     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 757     info.status_addr        = CVMX_L2C_INT_REG;
 758     info.status_mask        = 1ull<<6 /* bigwr */;
 759     info.enable_addr        = CVMX_L2C_INT_ENA;
 760     info.enable_mask        = 1ull<<6 /* bigwr */;
 761     info.flags              = 0;
 762     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 763     info.group_index        = 0;
 764     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 765     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 766     info.parent.status_mask = 1ull<<16 /* l2c */;
 767     info.func               = __cvmx_error_display;
 768     info.user_info          = (long)
 769         "ERROR L2C_INT_REG[BIGWR]: Write reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
 770     fail |= cvmx_error_add(&info);
 771
 772     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 773     info.status_addr        = CVMX_L2C_INT_REG;
 774     info.status_mask        = 1ull<<7 /* bigrd */;
 775     info.enable_addr        = CVMX_L2C_INT_ENA;
 776     info.enable_mask        = 1ull<<7 /* bigrd */;
 777     info.flags              = 0;
 778     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 779     info.group_index        = 0;
 780     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 781     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 782     info.parent.status_mask = 1ull<<16 /* l2c */;
 783     info.func               = __cvmx_error_display;
 784     info.user_info          = (long)
 785         "ERROR L2C_INT_REG[BIGRD]: Read reference past L2C_BIG_CTL[MAXDRAM] occurred\n";
 786     fail |= cvmx_error_add(&info);
 787
 788     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 789     info.status_addr        = CVMX_L2C_INT_REG;
 790     info.status_mask        = 0;
 791     info.enable_addr        = 0;
 792     info.enable_mask        = 0;
 793     info.flags              = 0;
 794     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 795     info.group_index        = 0;
 796     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 797     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
 798     info.parent.status_mask = 1ull<<16 /* l2c */;
 799     info.func               = __cvmx_error_decode;
 800     info.user_info          = 0;
 801     fail |= cvmx_error_add(&info);
 802
 803     /* CVMX_L2C_TADX_INT(0) */
 804     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 805     info.status_addr        = CVMX_L2C_TADX_INT(0);
 806     info.status_mask        = 1ull<<0 /* l2dsbe */;
 807     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 808     info.enable_mask        = 1ull<<0 /* l2dsbe */;
 809     info.flags              = 0;
 810     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 811     info.group_index        = 0;
 812     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 813     info.parent.status_addr = CVMX_L2C_INT_REG;
 814     info.parent.status_mask = 1ull<<16 /* tad0 */;
 815     info.func               = __cvmx_error_display;
 816     info.user_info          = (long)
 817         "ERROR L2C_TADX_INT(0)[L2DSBE]: L2D Single-Bit Error\n"
 818         "    Shadow copy of L2C_ERR_TDTX[SBE]\n"
 819         "    Writes of 1 also clear L2C_ERR_TDTX[SBE]\n";
 820     fail |= cvmx_error_add(&info);
 821
 822     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 823     info.status_addr        = CVMX_L2C_TADX_INT(0);
 824     info.status_mask        = 1ull<<1 /* l2ddbe */;
 825     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 826     info.enable_mask        = 1ull<<1 /* l2ddbe */;
 827     info.flags              = 0;
 828     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 829     info.group_index        = 0;
 830     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 831     info.parent.status_addr = CVMX_L2C_INT_REG;
 832     info.parent.status_mask = 1ull<<16 /* tad0 */;
 833     info.func               = __cvmx_error_display;
 834     info.user_info          = (long)
 835         "ERROR L2C_TADX_INT(0)[L2DDBE]: L2D Double-Bit Error\n"
 836         "    Shadow copy of L2C_ERR_TDTX[DBE]\n"
 837         "    Writes of 1 also clear L2C_ERR_TDTX[DBE]\n";
 838     fail |= cvmx_error_add(&info);
 839
 840     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 841     info.status_addr        = CVMX_L2C_TADX_INT(0);
 842     info.status_mask        = 1ull<<2 /* tagsbe */;
 843     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 844     info.enable_mask        = 1ull<<2 /* tagsbe */;
 845     info.flags              = 0;
 846     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 847     info.group_index        = 0;
 848     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 849     info.parent.status_addr = CVMX_L2C_INT_REG;
 850     info.parent.status_mask = 1ull<<16 /* tad0 */;
 851     info.func               = __cvmx_error_display;
 852     info.user_info          = (long)
 853         "ERROR L2C_TADX_INT(0)[TAGSBE]: TAG Single-Bit Error\n"
 854         "    Shadow copy of L2C_ERR_TTGX[SBE]\n"
 855         "    Writes of 1 also clear L2C_ERR_TTGX[SBE]\n";
 856     fail |= cvmx_error_add(&info);
 857
 858     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 859     info.status_addr        = CVMX_L2C_TADX_INT(0);
 860     info.status_mask        = 1ull<<3 /* tagdbe */;
 861     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 862     info.enable_mask        = 1ull<<3 /* tagdbe */;
 863     info.flags              = 0;
 864     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 865     info.group_index        = 0;
 866     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 867     info.parent.status_addr = CVMX_L2C_INT_REG;
 868     info.parent.status_mask = 1ull<<16 /* tad0 */;
 869     info.func               = __cvmx_error_display;
 870     info.user_info          = (long)
 871         "ERROR L2C_TADX_INT(0)[TAGDBE]: TAG Double-Bit Error\n"
 872         "    Shadow copy of L2C_ERR_TTGX[DBE]\n"
 873         "    Writes of 1 also clear L2C_ERR_TTGX[DBE]\n";
 874     fail |= cvmx_error_add(&info);
 875
 876     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 877     info.status_addr        = CVMX_L2C_TADX_INT(0);
 878     info.status_mask        = 1ull<<4 /* vbfsbe */;
 879     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 880     info.enable_mask        = 1ull<<4 /* vbfsbe */;
 881     info.flags              = 0;
 882     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 883     info.group_index        = 0;
 884     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 885     info.parent.status_addr = CVMX_L2C_INT_REG;
 886     info.parent.status_mask = 1ull<<16 /* tad0 */;
 887     info.func               = __cvmx_error_display;
 888     info.user_info          = (long)
 889         "ERROR L2C_TADX_INT(0)[VBFSBE]: VBF Single-Bit Error\n"
 890         "    Shadow copy of L2C_ERR_TDTX[VSBE]\n"
 891         "    Writes of 1 also clear L2C_ERR_TDTX[VSBE]\n";
 892     fail |= cvmx_error_add(&info);
 893
 894     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 895     info.status_addr        = CVMX_L2C_TADX_INT(0);
 896     info.status_mask        = 1ull<<5 /* vbfdbe */;
 897     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 898     info.enable_mask        = 1ull<<5 /* vbfdbe */;
 899     info.flags              = 0;
 900     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 901     info.group_index        = 0;
 902     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 903     info.parent.status_addr = CVMX_L2C_INT_REG;
 904     info.parent.status_mask = 1ull<<16 /* tad0 */;
 905     info.func               = __cvmx_error_display;
 906     info.user_info          = (long)
 907         "ERROR L2C_TADX_INT(0)[VBFDBE]: VBF Double-Bit Error\n"
 908         "    Shadow copy of L2C_ERR_TDTX[VDBE]\n"
 909         "    Writes of 1 also clear L2C_ERR_TDTX[VDBE]\n";
 910     fail |= cvmx_error_add(&info);
 911
 912     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 913     info.status_addr        = CVMX_L2C_TADX_INT(0);
 914     info.status_mask        = 1ull<<6 /* noway */;
 915     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 916     info.enable_mask        = 1ull<<6 /* noway */;
 917     info.flags              = 0;
 918     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 919     info.group_index        = 0;
 920     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 921     info.parent.status_addr = CVMX_L2C_INT_REG;
 922     info.parent.status_mask = 1ull<<16 /* tad0 */;
 923     info.func               = __cvmx_error_display;
 924     info.user_info          = (long)
 925         "ERROR L2C_TADX_INT(0)[NOWAY]: No way available interrupt\n"
 926         "    Shadow copy of L2C_ERR_TTGX[NOWAY]\n"
 927         "    Writes of 1 also clear L2C_ERR_TTGX[NOWAY]\n";
 928     fail |= cvmx_error_add(&info);
 929
 930     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 931     info.status_addr        = CVMX_L2C_TADX_INT(0);
 932     info.status_mask        = 1ull<<7 /* rddislmc */;
 933     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 934     info.enable_mask        = 1ull<<7 /* rddislmc */;
 935     info.flags              = 0;
 936     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 937     info.group_index        = 0;
 938     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 939     info.parent.status_addr = CVMX_L2C_INT_REG;
 940     info.parent.status_mask = 1ull<<16 /* tad0 */;
 941     info.func               = __cvmx_error_display;
 942     info.user_info          = (long)
 943         "ERROR L2C_TADX_INT(0)[RDDISLMC]: Illegal Read  to Disabled LMC Error\n"
 944         "    A DRAM read  arrived before the LMC(s) were enabled\n";
 945     fail |= cvmx_error_add(&info);
 946
 947     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 948     info.status_addr        = CVMX_L2C_TADX_INT(0);
 949     info.status_mask        = 1ull<<8 /* wrdislmc */;
 950     info.enable_addr        = CVMX_L2C_TADX_IEN(0);
 951     info.enable_mask        = 1ull<<8 /* wrdislmc */;
 952     info.flags              = 0;
 953     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 954     info.group_index        = 0;
 955     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 956     info.parent.status_addr = CVMX_L2C_INT_REG;
 957     info.parent.status_mask = 1ull<<16 /* tad0 */;
 958     info.func               = __cvmx_error_display;
 959     info.user_info          = (long)
 960         "ERROR L2C_TADX_INT(0)[WRDISLMC]: Illegal Write to Disabled LMC Error\n"
 961         "    A DRAM write arrived before the LMC(s) were enabled\n";
 962     fail |= cvmx_error_add(&info);
 963
 964     /* CVMX_L2C_ERR_TDTX(0) */
 965     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 966     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
 967     info.status_mask        = 1ull<<60 /* vsbe */;
 968     info.enable_addr        = 0;
 969     info.enable_mask        = 0;
 970     info.flags              = 0;
 971     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 972     info.group_index        = 0;
 973     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 974     info.parent.status_addr = CVMX_L2C_INT_REG;
 975     info.parent.status_mask = 1ull<<16 /* tad0 */;
 976     info.func               = __cvmx_error_display;
 977     info.user_info          = (long)
 978         "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
 979     fail |= cvmx_error_add(&info);
 980
 981     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 982     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
 983     info.status_mask        = 1ull<<61 /* vdbe */;
 984     info.enable_addr        = 0;
 985     info.enable_mask        = 0;
 986     info.flags              = 0;
 987     info.group              = CVMX_ERROR_GROUP_INTERNAL;
 988     info.group_index        = 0;
 989     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
 990     info.parent.status_addr = CVMX_L2C_INT_REG;
 991     info.parent.status_mask = 1ull<<16 /* tad0 */;
 992     info.func               = __cvmx_error_display;
 993     info.user_info          = (long)
 994         "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
 995     fail |= cvmx_error_add(&info);
 996
 997     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
 998     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
 999     info.status_mask        = 1ull<<62 /* sbe */;
1000     info.enable_addr        = 0;
1001     info.enable_mask        = 0;
1002     info.flags              = 0;
1003     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1004     info.group_index        = 0;
1005     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1006     info.parent.status_addr = CVMX_L2C_INT_REG;
1007     info.parent.status_mask = 1ull<<16 /* tad0 */;
1008     info.func               = __cvmx_error_display;
1009     info.user_info          = (long)
1010         "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
1011     fail |= cvmx_error_add(&info);
1012
1013     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1014     info.status_addr        = CVMX_L2C_ERR_TDTX(0);
1015     info.status_mask        = 1ull<<63 /* dbe */;
1016     info.enable_addr        = 0;
1017     info.enable_mask        = 0;
1018     info.flags              = 0;
1019     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1020     info.group_index        = 0;
1021     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1022     info.parent.status_addr = CVMX_L2C_INT_REG;
1023     info.parent.status_mask = 1ull<<16 /* tad0 */;
1024     info.func               = __cvmx_error_display;
1025     info.user_info          = (long)
1026         "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
1027     fail |= cvmx_error_add(&info);
1028
1029     /* CVMX_L2C_ERR_TTGX(0) */
1030     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1031     info.status_addr        = CVMX_L2C_ERR_TTGX(0);
1032     info.status_mask        = 1ull<<61 /* noway */;
1033     info.enable_addr        = 0;
1034     info.enable_mask        = 0;
1035     info.flags              = 0;
1036     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1037     info.group_index        = 0;
1038     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1039     info.parent.status_addr = CVMX_L2C_INT_REG;
1040     info.parent.status_mask = 1ull<<16 /* tad0 */;
1041     info.func               = __cvmx_error_display;
1042     info.user_info          = (long)
1043         "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
1044         "    L2C sets NOWAY during its processing of a\n"
1045         "    transaction whenever it needed/wanted to allocate\n"
1046         "    a WAY in the L2 cache, but was unable to. NOWAY==1\n"
1047         "    is (generally) not an indication that L2C failed to\n"
1048         "    complete transactions. Rather, it is a hint of\n"
1049         "    possible performance degradation. (For example, L2C\n"
1050         "    must read-modify-write DRAM for every transaction\n"
1051         "    that updates some, but not all, of the bytes in a\n"
1052         "    cache block, misses in the L2 cache, and cannot\n"
1053         "    allocate a WAY.) There is one \"failure\" case where\n"
1054         "    L2C will set NOWAY: when it cannot leave a block\n"
1055         "    locked in the L2 cache as part of a LCKL2\n"
1056         "    transaction.\n";
1057     fail |= cvmx_error_add(&info);
1058
1059     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1060     info.status_addr        = CVMX_L2C_ERR_TTGX(0);
1061     info.status_mask        = 1ull<<62 /* sbe */;
1062     info.enable_addr        = 0;
1063     info.enable_mask        = 0;
1064     info.flags              = 0;
1065     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1066     info.group_index        = 0;
1067     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1068     info.parent.status_addr = CVMX_L2C_INT_REG;
1069     info.parent.status_mask = 1ull<<16 /* tad0 */;
1070     info.func               = __cvmx_error_display;
1071     info.user_info          = (long)
1072         "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
1073     fail |= cvmx_error_add(&info);
1074
1075     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1076     info.status_addr        = CVMX_L2C_ERR_TTGX(0);
1077     info.status_mask        = 1ull<<63 /* dbe */;
1078     info.enable_addr        = 0;
1079     info.enable_mask        = 0;
1080     info.flags              = 0;
1081     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1082     info.group_index        = 0;
1083     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1084     info.parent.status_addr = CVMX_L2C_INT_REG;
1085     info.parent.status_mask = 1ull<<16 /* tad0 */;
1086     info.func               = __cvmx_error_display;
1087     info.user_info          = (long)
1088         "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
1089     fail |= cvmx_error_add(&info);
1090
1091     /* CVMX_IPD_INT_SUM */
1092     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1093     info.status_addr        = CVMX_IPD_INT_SUM;
1094     info.status_mask        = 1ull<<0 /* prc_par0 */;
1095     info.enable_addr        = CVMX_IPD_INT_ENB;
1096     info.enable_mask        = 1ull<<0 /* prc_par0 */;
1097     info.flags              = 0;
1098     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1099     info.group_index        = 0;
1100     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1101     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1102     info.parent.status_mask = 1ull<<9 /* ipd */;
1103     info.func               = __cvmx_error_display;
1104     info.user_info          = (long)
1105         "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
1106         "    [31:0] of the PBM memory.\n";
1107     fail |= cvmx_error_add(&info);
1108
1109     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1110     info.status_addr        = CVMX_IPD_INT_SUM;
1111     info.status_mask        = 1ull<<1 /* prc_par1 */;
1112     info.enable_addr        = CVMX_IPD_INT_ENB;
1113     info.enable_mask        = 1ull<<1 /* prc_par1 */;
1114     info.flags              = 0;
1115     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1116     info.group_index        = 0;
1117     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1118     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1119     info.parent.status_mask = 1ull<<9 /* ipd */;
1120     info.func               = __cvmx_error_display;
1121     info.user_info          = (long)
1122         "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
1123         "    [63:32] of the PBM memory.\n";
1124     fail |= cvmx_error_add(&info);
1125
1126     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1127     info.status_addr        = CVMX_IPD_INT_SUM;
1128     info.status_mask        = 1ull<<2 /* prc_par2 */;
1129     info.enable_addr        = CVMX_IPD_INT_ENB;
1130     info.enable_mask        = 1ull<<2 /* prc_par2 */;
1131     info.flags              = 0;
1132     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1133     info.group_index        = 0;
1134     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1135     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1136     info.parent.status_mask = 1ull<<9 /* ipd */;
1137     info.func               = __cvmx_error_display;
1138     info.user_info          = (long)
1139         "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
1140         "    [95:64] of the PBM memory.\n";
1141     fail |= cvmx_error_add(&info);
1142
1143     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1144     info.status_addr        = CVMX_IPD_INT_SUM;
1145     info.status_mask        = 1ull<<3 /* prc_par3 */;
1146     info.enable_addr        = CVMX_IPD_INT_ENB;
1147     info.enable_mask        = 1ull<<3 /* prc_par3 */;
1148     info.flags              = 0;
1149     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1150     info.group_index        = 0;
1151     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1152     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1153     info.parent.status_mask = 1ull<<9 /* ipd */;
1154     info.func               = __cvmx_error_display;
1155     info.user_info          = (long)
1156         "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
1157         "    [127:96] of the PBM memory.\n";
1158     fail |= cvmx_error_add(&info);
1159
1160     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1161     info.status_addr        = CVMX_IPD_INT_SUM;
1162     info.status_mask        = 1ull<<4 /* bp_sub */;
1163     info.enable_addr        = CVMX_IPD_INT_ENB;
1164     info.enable_mask        = 1ull<<4 /* bp_sub */;
1165     info.flags              = 0;
1166     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1167     info.group_index        = 0;
1168     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1169     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1170     info.parent.status_mask = 1ull<<9 /* ipd */;
1171     info.func               = __cvmx_error_display;
1172     info.user_info          = (long)
1173         "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
1174         "    supplied illegal value.\n";
1175     fail |= cvmx_error_add(&info);
1176
1177     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1178     info.status_addr        = CVMX_IPD_INT_SUM;
1179     info.status_mask        = 1ull<<5 /* dc_ovr */;
1180     info.enable_addr        = CVMX_IPD_INT_ENB;
1181     info.enable_mask        = 1ull<<5 /* dc_ovr */;
1182     info.flags              = 0;
1183     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1184     info.group_index        = 0;
1185     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1186     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1187     info.parent.status_mask = 1ull<<9 /* ipd */;
1188     info.func               = __cvmx_error_display;
1189     info.user_info          = (long)
1190         "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
1191     fail |= cvmx_error_add(&info);
1192
1193     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1194     info.status_addr        = CVMX_IPD_INT_SUM;
1195     info.status_mask        = 1ull<<6 /* cc_ovr */;
1196     info.enable_addr        = CVMX_IPD_INT_ENB;
1197     info.enable_mask        = 1ull<<6 /* cc_ovr */;
1198     info.flags              = 0;
1199     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1200     info.group_index        = 0;
1201     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1202     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1203     info.parent.status_mask = 1ull<<9 /* ipd */;
1204     info.func               = __cvmx_error_display;
1205     info.user_info          = (long)
1206         "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
1207     fail |= cvmx_error_add(&info);
1208
1209     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1210     info.status_addr        = CVMX_IPD_INT_SUM;
1211     info.status_mask        = 1ull<<7 /* c_coll */;
1212     info.enable_addr        = CVMX_IPD_INT_ENB;
1213     info.enable_mask        = 1ull<<7 /* c_coll */;
1214     info.flags              = 0;
1215     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1216     info.group_index        = 0;
1217     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1218     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1219     info.parent.status_mask = 1ull<<9 /* ipd */;
1220     info.func               = __cvmx_error_display;
1221     info.user_info          = (long)
1222         "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
1223         "    collides.\n";
1224     fail |= cvmx_error_add(&info);
1225
1226     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1227     info.status_addr        = CVMX_IPD_INT_SUM;
1228     info.status_mask        = 1ull<<8 /* d_coll */;
1229     info.enable_addr        = CVMX_IPD_INT_ENB;
1230     info.enable_mask        = 1ull<<8 /* d_coll */;
1231     info.flags              = 0;
1232     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1233     info.group_index        = 0;
1234     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1235     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1236     info.parent.status_mask = 1ull<<9 /* ipd */;
1237     info.func               = __cvmx_error_display;
1238     info.user_info          = (long)
1239         "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
1240         "    collides.\n";
1241     fail |= cvmx_error_add(&info);
1242
1243     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1244     info.status_addr        = CVMX_IPD_INT_SUM;
1245     info.status_mask        = 1ull<<9 /* bc_ovr */;
1246     info.enable_addr        = CVMX_IPD_INT_ENB;
1247     info.enable_mask        = 1ull<<9 /* bc_ovr */;
1248     info.flags              = 0;
1249     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1250     info.group_index        = 0;
1251     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1252     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1253     info.parent.status_mask = 1ull<<9 /* ipd */;
1254     info.func               = __cvmx_error_display;
1255     info.user_info          = (long)
1256         "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
1257     fail |= cvmx_error_add(&info);
1258
1259     /* CVMX_POW_ECC_ERR */
1260     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1261     info.status_addr        = CVMX_POW_ECC_ERR;
1262     info.status_mask        = 1ull<<0 /* sbe */;
1263     info.enable_addr        = CVMX_POW_ECC_ERR;
1264     info.enable_mask        = 1ull<<2 /* sbe_ie */;
1265     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
1266     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1267     info.group_index        = 0;
1268     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1269     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1270     info.parent.status_mask = 1ull<<12 /* pow */;
1271     info.func               = __cvmx_error_handle_pow_ecc_err_sbe;
1272     info.user_info          = (long)
1273         "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
1274     fail |= cvmx_error_add(&info);
1275
1276     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1277     info.status_addr        = CVMX_POW_ECC_ERR;
1278     info.status_mask        = 1ull<<1 /* dbe */;
1279     info.enable_addr        = CVMX_POW_ECC_ERR;
1280     info.enable_mask        = 1ull<<3 /* dbe_ie */;
1281     info.flags              = 0;
1282     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1283     info.group_index        = 0;
1284     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1285     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1286     info.parent.status_mask = 1ull<<12 /* pow */;
1287     info.func               = __cvmx_error_handle_pow_ecc_err_dbe;
1288     info.user_info          = (long)
1289         "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
1290     fail |= cvmx_error_add(&info);
1291
1292     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1293     info.status_addr        = CVMX_POW_ECC_ERR;
1294     info.status_mask        = 1ull<<12 /* rpe */;
1295     info.enable_addr        = CVMX_POW_ECC_ERR;
1296     info.enable_mask        = 1ull<<13 /* rpe_ie */;
1297     info.flags              = 0;
1298     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1299     info.group_index        = 0;
1300     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1301     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1302     info.parent.status_mask = 1ull<<12 /* pow */;
1303     info.func               = __cvmx_error_handle_pow_ecc_err_rpe;
1304     info.user_info          = (long)
1305         "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
1306     fail |= cvmx_error_add(&info);
1307
1308     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1309     info.status_addr        = CVMX_POW_ECC_ERR;
1310     info.status_mask        = 0x1fffull<<16 /* iop */;
1311     info.enable_addr        = CVMX_POW_ECC_ERR;
1312     info.enable_mask        = 0x1fffull<<32 /* iop_ie */;
1313     info.flags              = 0;
1314     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1315     info.group_index        = 0;
1316     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1317     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1318     info.parent.status_mask = 1ull<<12 /* pow */;
1319     info.func               = __cvmx_error_handle_pow_ecc_err_iop;
1320     info.user_info          = (long)
1321         "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
1322     fail |= cvmx_error_add(&info);
1323
1324     /* CVMX_RAD_REG_ERROR */
1325     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1326     info.status_addr        = CVMX_RAD_REG_ERROR;
1327     info.status_mask        = 1ull<<0 /* doorbell */;
1328     info.enable_addr        = CVMX_RAD_REG_INT_MASK;
1329     info.enable_mask        = 1ull<<0 /* doorbell */;
1330     info.flags              = 0;
1331     info.group              = CVMX_ERROR_GROUP_INTERNAL;
1332     info.group_index        = 0;
1333     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1334     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1335     info.parent.status_mask = 1ull<<14 /* rad */;
1336     info.func               = __cvmx_error_display;
1337     info.user_info          = (long)
1338         "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
1339     fail |= cvmx_error_add(&info);
1340
1341     /* CVMX_PCSX_INTX_REG(0,1) */
1342     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1343     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1344     info.status_mask        = 1ull<<2 /* an_err */;
1345     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1346     info.enable_mask        = 1ull<<2 /* an_err_en */;
1347     info.flags              = 0;
1348     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1349     info.group_index        = 16;
1350     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1351     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1352     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1353     info.func               = __cvmx_error_display;
1354     info.user_info          = (long)
1355         "ERROR PCSX_INTX_REG(0,1)[AN_ERR]: AN Error, AN resolution function failed\n";
1356     fail |= cvmx_error_add(&info);
1357
1358     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1359     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1360     info.status_mask        = 1ull<<3 /* txfifu */;
1361     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1362     info.enable_mask        = 1ull<<3 /* txfifu_en */;
1363     info.flags              = 0;
1364     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1365     info.group_index        = 16;
1366     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1367     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1368     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1369     info.func               = __cvmx_error_display;
1370     info.user_info          = (long)
1371         "ERROR PCSX_INTX_REG(0,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1372         "    condition\n";
1373     fail |= cvmx_error_add(&info);
1374
1375     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1376     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1377     info.status_mask        = 1ull<<4 /* txfifo */;
1378     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1379     info.enable_mask        = 1ull<<4 /* txfifo_en */;
1380     info.flags              = 0;
1381     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1382     info.group_index        = 16;
1383     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1384     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1385     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1386     info.func               = __cvmx_error_display;
1387     info.user_info          = (long)
1388         "ERROR PCSX_INTX_REG(0,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1389         "    condition\n";
1390     fail |= cvmx_error_add(&info);
1391
1392     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1393     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1394     info.status_mask        = 1ull<<5 /* txbad */;
1395     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1396     info.enable_mask        = 1ull<<5 /* txbad_en */;
1397     info.flags              = 0;
1398     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1399     info.group_index        = 16;
1400     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1401     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1402     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1403     info.func               = __cvmx_error_display;
1404     info.user_info          = (long)
1405         "ERROR PCSX_INTX_REG(0,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1406         "    state. Should never be set during normal operation\n";
1407     fail |= cvmx_error_add(&info);
1408
1409     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1410     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1411     info.status_mask        = 1ull<<7 /* rxbad */;
1412     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1413     info.enable_mask        = 1ull<<7 /* rxbad_en */;
1414     info.flags              = 0;
1415     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1416     info.group_index        = 16;
1417     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1418     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1419     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1420     info.func               = __cvmx_error_display;
1421     info.user_info          = (long)
1422         "ERROR PCSX_INTX_REG(0,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
1423         "    state. Should never be set during normal operation\n";
1424     fail |= cvmx_error_add(&info);
1425
1426     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1427     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1428     info.status_mask        = 1ull<<8 /* rxlock */;
1429     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1430     info.enable_mask        = 1ull<<8 /* rxlock_en */;
1431     info.flags              = 0;
1432     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1433     info.group_index        = 16;
1434     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1435     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1436     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1437     info.func               = __cvmx_error_display;
1438     info.user_info          = (long)
1439         "ERROR PCSX_INTX_REG(0,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1440         "    failure occurs\n"
1441         "    Cannot fire in loopback1 mode\n";
1442     fail |= cvmx_error_add(&info);
1443
1444     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1445     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1446     info.status_mask        = 1ull<<9 /* an_bad */;
1447     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1448     info.enable_mask        = 1ull<<9 /* an_bad_en */;
1449     info.flags              = 0;
1450     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1451     info.group_index        = 16;
1452     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1453     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1454     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1455     info.func               = __cvmx_error_display;
1456     info.user_info          = (long)
1457         "ERROR PCSX_INTX_REG(0,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1458         "    state. Should never be set during normal operation\n";
1459     fail |= cvmx_error_add(&info);
1460
1461     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1462     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1463     info.status_mask        = 1ull<<10 /* sync_bad */;
1464     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1465     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
1466     info.flags              = 0;
1467     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1468     info.group_index        = 16;
1469     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1470     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1471     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1472     info.func               = __cvmx_error_display;
1473     info.user_info          = (long)
1474         "ERROR PCSX_INTX_REG(0,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1475         "    state. Should never be set during normal operation\n";
1476     fail |= cvmx_error_add(&info);
1477
1478     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1479     info.status_addr        = CVMX_PCSX_INTX_REG(0,1);
1480     info.status_mask        = 1ull<<12 /* dbg_sync */;
1481     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,1);
1482     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
1483     info.flags              = 0;
1484     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1485     info.group_index        = 16;
1486     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1487     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1488     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1489     info.func               = __cvmx_error_display;
1490     info.user_info          = (long)
1491         "ERROR PCSX_INTX_REG(0,1)[DBG_SYNC]: Code Group sync failure debug help\n";
1492     fail |= cvmx_error_add(&info);
1493
1494     /* CVMX_PCSX_INTX_REG(1,1) */
1495     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1496     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1497     info.status_mask        = 1ull<<2 /* an_err */;
1498     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1499     info.enable_mask        = 1ull<<2 /* an_err_en */;
1500     info.flags              = 0;
1501     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1502     info.group_index        = 17;
1503     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1504     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1505     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1506     info.func               = __cvmx_error_display;
1507     info.user_info          = (long)
1508         "ERROR PCSX_INTX_REG(1,1)[AN_ERR]: AN Error, AN resolution function failed\n";
1509     fail |= cvmx_error_add(&info);
1510
1511     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1512     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1513     info.status_mask        = 1ull<<3 /* txfifu */;
1514     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1515     info.enable_mask        = 1ull<<3 /* txfifu_en */;
1516     info.flags              = 0;
1517     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1518     info.group_index        = 17;
1519     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1520     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1521     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1522     info.func               = __cvmx_error_display;
1523     info.user_info          = (long)
1524         "ERROR PCSX_INTX_REG(1,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1525         "    condition\n";
1526     fail |= cvmx_error_add(&info);
1527
1528     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1529     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1530     info.status_mask        = 1ull<<4 /* txfifo */;
1531     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1532     info.enable_mask        = 1ull<<4 /* txfifo_en */;
1533     info.flags              = 0;
1534     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1535     info.group_index        = 17;
1536     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1537     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1538     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1539     info.func               = __cvmx_error_display;
1540     info.user_info          = (long)
1541         "ERROR PCSX_INTX_REG(1,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1542         "    condition\n";
1543     fail |= cvmx_error_add(&info);
1544
1545     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1546     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1547     info.status_mask        = 1ull<<5 /* txbad */;
1548     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1549     info.enable_mask        = 1ull<<5 /* txbad_en */;
1550     info.flags              = 0;
1551     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1552     info.group_index        = 17;
1553     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1554     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1555     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1556     info.func               = __cvmx_error_display;
1557     info.user_info          = (long)
1558         "ERROR PCSX_INTX_REG(1,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1559         "    state. Should never be set during normal operation\n";
1560     fail |= cvmx_error_add(&info);
1561
1562     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1563     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1564     info.status_mask        = 1ull<<7 /* rxbad */;
1565     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1566     info.enable_mask        = 1ull<<7 /* rxbad_en */;
1567     info.flags              = 0;
1568     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1569     info.group_index        = 17;
1570     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1571     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1572     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1573     info.func               = __cvmx_error_display;
1574     info.user_info          = (long)
1575         "ERROR PCSX_INTX_REG(1,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
1576         "    state. Should never be set during normal operation\n";
1577     fail |= cvmx_error_add(&info);
1578
1579     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1580     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1581     info.status_mask        = 1ull<<8 /* rxlock */;
1582     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1583     info.enable_mask        = 1ull<<8 /* rxlock_en */;
1584     info.flags              = 0;
1585     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1586     info.group_index        = 17;
1587     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1588     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1589     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1590     info.func               = __cvmx_error_display;
1591     info.user_info          = (long)
1592         "ERROR PCSX_INTX_REG(1,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1593         "    failure occurs\n"
1594         "    Cannot fire in loopback1 mode\n";
1595     fail |= cvmx_error_add(&info);
1596
1597     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1598     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1599     info.status_mask        = 1ull<<9 /* an_bad */;
1600     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1601     info.enable_mask        = 1ull<<9 /* an_bad_en */;
1602     info.flags              = 0;
1603     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1604     info.group_index        = 17;
1605     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1606     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1607     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1608     info.func               = __cvmx_error_display;
1609     info.user_info          = (long)
1610         "ERROR PCSX_INTX_REG(1,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1611         "    state. Should never be set during normal operation\n";
1612     fail |= cvmx_error_add(&info);
1613
1614     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1615     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1616     info.status_mask        = 1ull<<10 /* sync_bad */;
1617     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1618     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
1619     info.flags              = 0;
1620     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1621     info.group_index        = 17;
1622     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1623     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1624     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1625     info.func               = __cvmx_error_display;
1626     info.user_info          = (long)
1627         "ERROR PCSX_INTX_REG(1,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1628         "    state. Should never be set during normal operation\n";
1629     fail |= cvmx_error_add(&info);
1630
1631     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1632     info.status_addr        = CVMX_PCSX_INTX_REG(1,1);
1633     info.status_mask        = 1ull<<12 /* dbg_sync */;
1634     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,1);
1635     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
1636     info.flags              = 0;
1637     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1638     info.group_index        = 17;
1639     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1640     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1641     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1642     info.func               = __cvmx_error_display;
1643     info.user_info          = (long)
1644         "ERROR PCSX_INTX_REG(1,1)[DBG_SYNC]: Code Group sync failure debug help\n";
1645     fail |= cvmx_error_add(&info);
1646
1647     /* CVMX_PCSX_INTX_REG(2,1) */
1648     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1649     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1650     info.status_mask        = 1ull<<2 /* an_err */;
1651     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1652     info.enable_mask        = 1ull<<2 /* an_err_en */;
1653     info.flags              = 0;
1654     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1655     info.group_index        = 18;
1656     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1657     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1658     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1659     info.func               = __cvmx_error_display;
1660     info.user_info          = (long)
1661         "ERROR PCSX_INTX_REG(2,1)[AN_ERR]: AN Error, AN resolution function failed\n";
1662     fail |= cvmx_error_add(&info);
1663
1664     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1665     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1666     info.status_mask        = 1ull<<3 /* txfifu */;
1667     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1668     info.enable_mask        = 1ull<<3 /* txfifu_en */;
1669     info.flags              = 0;
1670     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1671     info.group_index        = 18;
1672     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1673     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1674     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1675     info.func               = __cvmx_error_display;
1676     info.user_info          = (long)
1677         "ERROR PCSX_INTX_REG(2,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1678         "    condition\n";
1679     fail |= cvmx_error_add(&info);
1680
1681     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1682     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1683     info.status_mask        = 1ull<<4 /* txfifo */;
1684     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1685     info.enable_mask        = 1ull<<4 /* txfifo_en */;
1686     info.flags              = 0;
1687     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1688     info.group_index        = 18;
1689     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1690     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1691     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1692     info.func               = __cvmx_error_display;
1693     info.user_info          = (long)
1694         "ERROR PCSX_INTX_REG(2,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1695         "    condition\n";
1696     fail |= cvmx_error_add(&info);
1697
1698     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1699     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1700     info.status_mask        = 1ull<<5 /* txbad */;
1701     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1702     info.enable_mask        = 1ull<<5 /* txbad_en */;
1703     info.flags              = 0;
1704     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1705     info.group_index        = 18;
1706     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1707     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1708     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1709     info.func               = __cvmx_error_display;
1710     info.user_info          = (long)
1711         "ERROR PCSX_INTX_REG(2,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1712         "    state. Should never be set during normal operation\n";
1713     fail |= cvmx_error_add(&info);
1714
1715     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1716     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1717     info.status_mask        = 1ull<<7 /* rxbad */;
1718     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1719     info.enable_mask        = 1ull<<7 /* rxbad_en */;
1720     info.flags              = 0;
1721     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1722     info.group_index        = 18;
1723     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1724     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1725     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1726     info.func               = __cvmx_error_display;
1727     info.user_info          = (long)
1728         "ERROR PCSX_INTX_REG(2,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
1729         "    state. Should never be set during normal operation\n";
1730     fail |= cvmx_error_add(&info);
1731
1732     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1733     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1734     info.status_mask        = 1ull<<8 /* rxlock */;
1735     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1736     info.enable_mask        = 1ull<<8 /* rxlock_en */;
1737     info.flags              = 0;
1738     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1739     info.group_index        = 18;
1740     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1741     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1742     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1743     info.func               = __cvmx_error_display;
1744     info.user_info          = (long)
1745         "ERROR PCSX_INTX_REG(2,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1746         "    failure occurs\n"
1747         "    Cannot fire in loopback1 mode\n";
1748     fail |= cvmx_error_add(&info);
1749
1750     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1751     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1752     info.status_mask        = 1ull<<9 /* an_bad */;
1753     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1754     info.enable_mask        = 1ull<<9 /* an_bad_en */;
1755     info.flags              = 0;
1756     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1757     info.group_index        = 18;
1758     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1759     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1760     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1761     info.func               = __cvmx_error_display;
1762     info.user_info          = (long)
1763         "ERROR PCSX_INTX_REG(2,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1764         "    state. Should never be set during normal operation\n";
1765     fail |= cvmx_error_add(&info);
1766
1767     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1768     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1769     info.status_mask        = 1ull<<10 /* sync_bad */;
1770     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1771     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
1772     info.flags              = 0;
1773     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1774     info.group_index        = 18;
1775     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1776     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1777     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1778     info.func               = __cvmx_error_display;
1779     info.user_info          = (long)
1780         "ERROR PCSX_INTX_REG(2,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1781         "    state. Should never be set during normal operation\n";
1782     fail |= cvmx_error_add(&info);
1783
1784     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1785     info.status_addr        = CVMX_PCSX_INTX_REG(2,1);
1786     info.status_mask        = 1ull<<12 /* dbg_sync */;
1787     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,1);
1788     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
1789     info.flags              = 0;
1790     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1791     info.group_index        = 18;
1792     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1793     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1794     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1795     info.func               = __cvmx_error_display;
1796     info.user_info          = (long)
1797         "ERROR PCSX_INTX_REG(2,1)[DBG_SYNC]: Code Group sync failure debug help\n";
1798     fail |= cvmx_error_add(&info);
1799
1800     /* CVMX_PCSX_INTX_REG(3,1) */
1801     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1802     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1803     info.status_mask        = 1ull<<2 /* an_err */;
1804     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1805     info.enable_mask        = 1ull<<2 /* an_err_en */;
1806     info.flags              = 0;
1807     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1808     info.group_index        = 19;
1809     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1810     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1811     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1812     info.func               = __cvmx_error_display;
1813     info.user_info          = (long)
1814         "ERROR PCSX_INTX_REG(3,1)[AN_ERR]: AN Error, AN resolution function failed\n";
1815     fail |= cvmx_error_add(&info);
1816
1817     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1818     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1819     info.status_mask        = 1ull<<3 /* txfifu */;
1820     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1821     info.enable_mask        = 1ull<<3 /* txfifu_en */;
1822     info.flags              = 0;
1823     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1824     info.group_index        = 19;
1825     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1826     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1827     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1828     info.func               = __cvmx_error_display;
1829     info.user_info          = (long)
1830         "ERROR PCSX_INTX_REG(3,1)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1831         "    condition\n";
1832     fail |= cvmx_error_add(&info);
1833
1834     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1835     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1836     info.status_mask        = 1ull<<4 /* txfifo */;
1837     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1838     info.enable_mask        = 1ull<<4 /* txfifo_en */;
1839     info.flags              = 0;
1840     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1841     info.group_index        = 19;
1842     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1843     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1844     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1845     info.func               = __cvmx_error_display;
1846     info.user_info          = (long)
1847         "ERROR PCSX_INTX_REG(3,1)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1848         "    condition\n";
1849     fail |= cvmx_error_add(&info);
1850
1851     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1852     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1853     info.status_mask        = 1ull<<5 /* txbad */;
1854     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1855     info.enable_mask        = 1ull<<5 /* txbad_en */;
1856     info.flags              = 0;
1857     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1858     info.group_index        = 19;
1859     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1860     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1861     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1862     info.func               = __cvmx_error_display;
1863     info.user_info          = (long)
1864         "ERROR PCSX_INTX_REG(3,1)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1865         "    state. Should never be set during normal operation\n";
1866     fail |= cvmx_error_add(&info);
1867
1868     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1869     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1870     info.status_mask        = 1ull<<7 /* rxbad */;
1871     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1872     info.enable_mask        = 1ull<<7 /* rxbad_en */;
1873     info.flags              = 0;
1874     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1875     info.group_index        = 19;
1876     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1877     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1878     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1879     info.func               = __cvmx_error_display;
1880     info.user_info          = (long)
1881         "ERROR PCSX_INTX_REG(3,1)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
1882         "    state. Should never be set during normal operation\n";
1883     fail |= cvmx_error_add(&info);
1884
1885     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1886     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1887     info.status_mask        = 1ull<<8 /* rxlock */;
1888     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1889     info.enable_mask        = 1ull<<8 /* rxlock_en */;
1890     info.flags              = 0;
1891     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1892     info.group_index        = 19;
1893     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1894     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1895     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1896     info.func               = __cvmx_error_display;
1897     info.user_info          = (long)
1898         "ERROR PCSX_INTX_REG(3,1)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1899         "    failure occurs\n"
1900         "    Cannot fire in loopback1 mode\n";
1901     fail |= cvmx_error_add(&info);
1902
1903     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1904     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1905     info.status_mask        = 1ull<<9 /* an_bad */;
1906     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1907     info.enable_mask        = 1ull<<9 /* an_bad_en */;
1908     info.flags              = 0;
1909     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1910     info.group_index        = 19;
1911     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1912     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1913     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1914     info.func               = __cvmx_error_display;
1915     info.user_info          = (long)
1916         "ERROR PCSX_INTX_REG(3,1)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1917         "    state. Should never be set during normal operation\n";
1918     fail |= cvmx_error_add(&info);
1919
1920     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1921     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1922     info.status_mask        = 1ull<<10 /* sync_bad */;
1923     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1924     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
1925     info.flags              = 0;
1926     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1927     info.group_index        = 19;
1928     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1929     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1930     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1931     info.func               = __cvmx_error_display;
1932     info.user_info          = (long)
1933         "ERROR PCSX_INTX_REG(3,1)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1934         "    state. Should never be set during normal operation\n";
1935     fail |= cvmx_error_add(&info);
1936
1937     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1938     info.status_addr        = CVMX_PCSX_INTX_REG(3,1);
1939     info.status_mask        = 1ull<<12 /* dbg_sync */;
1940     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,1);
1941     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
1942     info.flags              = 0;
1943     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1944     info.group_index        = 19;
1945     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1946     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1947     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1948     info.func               = __cvmx_error_display;
1949     info.user_info          = (long)
1950         "ERROR PCSX_INTX_REG(3,1)[DBG_SYNC]: Code Group sync failure debug help\n";
1951     fail |= cvmx_error_add(&info);
1952
1953     /* CVMX_PCSXX_INT_REG(1) */
1954     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1955     info.status_addr        = CVMX_PCSXX_INT_REG(1);
1956     info.status_mask        = 1ull<<0 /* txflt */;
1957     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
1958     info.enable_mask        = 1ull<<0 /* txflt_en */;
1959     info.flags              = 0;
1960     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1961     info.group_index        = 16;
1962     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1963     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1964     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1965     info.func               = __cvmx_error_display;
1966     info.user_info          = (long)
1967         "ERROR PCSXX_INT_REG(1)[TXFLT]: None defined at this time, always 0x0\n";
1968     fail |= cvmx_error_add(&info);
1969
1970     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1971     info.status_addr        = CVMX_PCSXX_INT_REG(1);
1972     info.status_mask        = 1ull<<1 /* rxbad */;
1973     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
1974     info.enable_mask        = 1ull<<1 /* rxbad_en */;
1975     info.flags              = 0;
1976     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1977     info.group_index        = 16;
1978     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1979     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1980     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1981     info.func               = __cvmx_error_display;
1982     info.user_info          = (long)
1983         "ERROR PCSXX_INT_REG(1)[RXBAD]: Set when RX state machine in bad state\n";
1984     fail |= cvmx_error_add(&info);
1985
1986     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
1987     info.status_addr        = CVMX_PCSXX_INT_REG(1);
1988     info.status_mask        = 1ull<<2 /* rxsynbad */;
1989     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
1990     info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
1991     info.flags              = 0;
1992     info.group              = CVMX_ERROR_GROUP_ETHERNET;
1993     info.group_index        = 16;
1994     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
1995     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1996     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
1997     info.func               = __cvmx_error_display;
1998     info.user_info          = (long)
1999         "ERROR PCSXX_INT_REG(1)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
2000         "    in one of the 4 xaui lanes\n";
2001     fail |= cvmx_error_add(&info);
2002
2003     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2004     info.status_addr        = CVMX_PCSXX_INT_REG(1);
2005     info.status_mask        = 1ull<<3 /* bitlckls */;
2006     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
2007     info.enable_mask        = 1ull<<3 /* bitlckls_en */;
2008     info.flags              = 0;
2009     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2010     info.group_index        = 16;
2011     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2012     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2013     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
2014     info.func               = __cvmx_error_display;
2015     info.user_info          = (long)
2016         "ERROR PCSXX_INT_REG(1)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
2017     fail |= cvmx_error_add(&info);
2018
2019     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2020     info.status_addr        = CVMX_PCSXX_INT_REG(1);
2021     info.status_mask        = 1ull<<4 /* synlos */;
2022     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
2023     info.enable_mask        = 1ull<<4 /* synlos_en */;
2024     info.flags              = 0;
2025     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2026     info.group_index        = 16;
2027     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2028     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2029     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
2030     info.func               = __cvmx_error_display;
2031     info.user_info          = (long)
2032         "ERROR PCSXX_INT_REG(1)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
2033     fail |= cvmx_error_add(&info);
2034
2035     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2036     info.status_addr        = CVMX_PCSXX_INT_REG(1);
2037     info.status_mask        = 1ull<<5 /* algnlos */;
2038     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
2039     info.enable_mask        = 1ull<<5 /* algnlos_en */;
2040     info.flags              = 0;
2041     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2042     info.group_index        = 16;
2043     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2044     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2045     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
2046     info.func               = __cvmx_error_display;
2047     info.user_info          = (long)
2048         "ERROR PCSXX_INT_REG(1)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
2049     fail |= cvmx_error_add(&info);
2050
2051     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2052     info.status_addr        = CVMX_PCSXX_INT_REG(1);
2053     info.status_mask        = 1ull<<6 /* dbg_sync */;
2054     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(1);
2055     info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
2056     info.flags              = 0;
2057     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2058     info.group_index        = 16;
2059     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2060     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2061     info.parent.status_mask = 1ull<<23 /* asxpcs1 */;
2062     info.func               = __cvmx_error_display;
2063     info.user_info          = (long)
2064         "ERROR PCSXX_INT_REG(1)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
2065     fail |= cvmx_error_add(&info);
2066
2067     /* CVMX_PCSX_INTX_REG(0,0) */
2068     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2069     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2070     info.status_mask        = 1ull<<2 /* an_err */;
2071     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2072     info.enable_mask        = 1ull<<2 /* an_err_en */;
2073     info.flags              = 0;
2074     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2075     info.group_index        = 0;
2076     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2077     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2078     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2079     info.func               = __cvmx_error_display;
2080     info.user_info          = (long)
2081         "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
2082     fail |= cvmx_error_add(&info);
2083
2084     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2085     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2086     info.status_mask        = 1ull<<3 /* txfifu */;
2087     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2088     info.enable_mask        = 1ull<<3 /* txfifu_en */;
2089     info.flags              = 0;
2090     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2091     info.group_index        = 0;
2092     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2093     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2094     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2095     info.func               = __cvmx_error_display;
2096     info.user_info          = (long)
2097         "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
2098         "    condition\n";
2099     fail |= cvmx_error_add(&info);
2100
2101     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2102     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2103     info.status_mask        = 1ull<<4 /* txfifo */;
2104     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2105     info.enable_mask        = 1ull<<4 /* txfifo_en */;
2106     info.flags              = 0;
2107     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2108     info.group_index        = 0;
2109     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2110     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2111     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2112     info.func               = __cvmx_error_display;
2113     info.user_info          = (long)
2114         "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
2115         "    condition\n";
2116     fail |= cvmx_error_add(&info);
2117
2118     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2119     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2120     info.status_mask        = 1ull<<5 /* txbad */;
2121     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2122     info.enable_mask        = 1ull<<5 /* txbad_en */;
2123     info.flags              = 0;
2124     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2125     info.group_index        = 0;
2126     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2127     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2128     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2129     info.func               = __cvmx_error_display;
2130     info.user_info          = (long)
2131         "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
2132         "    state. Should never be set during normal operation\n";
2133     fail |= cvmx_error_add(&info);
2134
2135     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2136     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2137     info.status_mask        = 1ull<<7 /* rxbad */;
2138     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2139     info.enable_mask        = 1ull<<7 /* rxbad_en */;
2140     info.flags              = 0;
2141     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2142     info.group_index        = 0;
2143     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2144     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2145     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2146     info.func               = __cvmx_error_display;
2147     info.user_info          = (long)
2148         "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
2149         "    state. Should never be set during normal operation\n";
2150     fail |= cvmx_error_add(&info);
2151
2152     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2153     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2154     info.status_mask        = 1ull<<8 /* rxlock */;
2155     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2156     info.enable_mask        = 1ull<<8 /* rxlock_en */;
2157     info.flags              = 0;
2158     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2159     info.group_index        = 0;
2160     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2161     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2162     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2163     info.func               = __cvmx_error_display;
2164     info.user_info          = (long)
2165         "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
2166         "    failure occurs\n"
2167         "    Cannot fire in loopback1 mode\n";
2168     fail |= cvmx_error_add(&info);
2169
2170     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2171     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2172     info.status_mask        = 1ull<<9 /* an_bad */;
2173     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2174     info.enable_mask        = 1ull<<9 /* an_bad_en */;
2175     info.flags              = 0;
2176     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2177     info.group_index        = 0;
2178     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2179     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2180     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2181     info.func               = __cvmx_error_display;
2182     info.user_info          = (long)
2183         "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
2184         "    state. Should never be set during normal operation\n";
2185     fail |= cvmx_error_add(&info);
2186
2187     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2188     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2189     info.status_mask        = 1ull<<10 /* sync_bad */;
2190     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2191     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
2192     info.flags              = 0;
2193     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2194     info.group_index        = 0;
2195     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2196     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2197     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2198     info.func               = __cvmx_error_display;
2199     info.user_info          = (long)
2200         "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
2201         "    state. Should never be set during normal operation\n";
2202     fail |= cvmx_error_add(&info);
2203
2204     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2205     info.status_addr        = CVMX_PCSX_INTX_REG(0,0);
2206     info.status_mask        = 1ull<<12 /* dbg_sync */;
2207     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(0,0);
2208     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
2209     info.flags              = 0;
2210     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2211     info.group_index        = 0;
2212     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2213     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2214     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2215     info.func               = __cvmx_error_display;
2216     info.user_info          = (long)
2217         "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
2218     fail |= cvmx_error_add(&info);
2219
2220     /* CVMX_PCSX_INTX_REG(1,0) */
2221     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2222     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2223     info.status_mask        = 1ull<<2 /* an_err */;
2224     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2225     info.enable_mask        = 1ull<<2 /* an_err_en */;
2226     info.flags              = 0;
2227     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2228     info.group_index        = 1;
2229     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2230     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2231     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2232     info.func               = __cvmx_error_display;
2233     info.user_info          = (long)
2234         "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
2235     fail |= cvmx_error_add(&info);
2236
2237     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2238     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2239     info.status_mask        = 1ull<<3 /* txfifu */;
2240     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2241     info.enable_mask        = 1ull<<3 /* txfifu_en */;
2242     info.flags              = 0;
2243     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2244     info.group_index        = 1;
2245     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2246     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2247     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2248     info.func               = __cvmx_error_display;
2249     info.user_info          = (long)
2250         "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
2251         "    condition\n";
2252     fail |= cvmx_error_add(&info);
2253
2254     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2255     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2256     info.status_mask        = 1ull<<4 /* txfifo */;
2257     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2258     info.enable_mask        = 1ull<<4 /* txfifo_en */;
2259     info.flags              = 0;
2260     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2261     info.group_index        = 1;
2262     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2263     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2264     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2265     info.func               = __cvmx_error_display;
2266     info.user_info          = (long)
2267         "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
2268         "    condition\n";
2269     fail |= cvmx_error_add(&info);
2270
2271     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2272     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2273     info.status_mask        = 1ull<<5 /* txbad */;
2274     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2275     info.enable_mask        = 1ull<<5 /* txbad_en */;
2276     info.flags              = 0;
2277     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2278     info.group_index        = 1;
2279     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2280     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2281     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2282     info.func               = __cvmx_error_display;
2283     info.user_info          = (long)
2284         "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
2285         "    state. Should never be set during normal operation\n";
2286     fail |= cvmx_error_add(&info);
2287
2288     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2289     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2290     info.status_mask        = 1ull<<7 /* rxbad */;
2291     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2292     info.enable_mask        = 1ull<<7 /* rxbad_en */;
2293     info.flags              = 0;
2294     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2295     info.group_index        = 1;
2296     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2297     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2298     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2299     info.func               = __cvmx_error_display;
2300     info.user_info          = (long)
2301         "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
2302         "    state. Should never be set during normal operation\n";
2303     fail |= cvmx_error_add(&info);
2304
2305     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2306     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2307     info.status_mask        = 1ull<<8 /* rxlock */;
2308     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2309     info.enable_mask        = 1ull<<8 /* rxlock_en */;
2310     info.flags              = 0;
2311     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2312     info.group_index        = 1;
2313     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2314     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2315     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2316     info.func               = __cvmx_error_display;
2317     info.user_info          = (long)
2318         "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
2319         "    failure occurs\n"
2320         "    Cannot fire in loopback1 mode\n";
2321     fail |= cvmx_error_add(&info);
2322
2323     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2324     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2325     info.status_mask        = 1ull<<9 /* an_bad */;
2326     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2327     info.enable_mask        = 1ull<<9 /* an_bad_en */;
2328     info.flags              = 0;
2329     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2330     info.group_index        = 1;
2331     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2332     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2333     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2334     info.func               = __cvmx_error_display;
2335     info.user_info          = (long)
2336         "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
2337         "    state. Should never be set during normal operation\n";
2338     fail |= cvmx_error_add(&info);
2339
2340     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2341     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2342     info.status_mask        = 1ull<<10 /* sync_bad */;
2343     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2344     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
2345     info.flags              = 0;
2346     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2347     info.group_index        = 1;
2348     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2349     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2350     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2351     info.func               = __cvmx_error_display;
2352     info.user_info          = (long)
2353         "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
2354         "    state. Should never be set during normal operation\n";
2355     fail |= cvmx_error_add(&info);
2356
2357     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2358     info.status_addr        = CVMX_PCSX_INTX_REG(1,0);
2359     info.status_mask        = 1ull<<12 /* dbg_sync */;
2360     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(1,0);
2361     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
2362     info.flags              = 0;
2363     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2364     info.group_index        = 1;
2365     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2366     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2367     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2368     info.func               = __cvmx_error_display;
2369     info.user_info          = (long)
2370         "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
2371     fail |= cvmx_error_add(&info);
2372
2373     /* CVMX_PCSX_INTX_REG(2,0) */
2374     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2375     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2376     info.status_mask        = 1ull<<2 /* an_err */;
2377     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2378     info.enable_mask        = 1ull<<2 /* an_err_en */;
2379     info.flags              = 0;
2380     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2381     info.group_index        = 2;
2382     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2383     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2384     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2385     info.func               = __cvmx_error_display;
2386     info.user_info          = (long)
2387         "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
2388     fail |= cvmx_error_add(&info);
2389
2390     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2391     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2392     info.status_mask        = 1ull<<3 /* txfifu */;
2393     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2394     info.enable_mask        = 1ull<<3 /* txfifu_en */;
2395     info.flags              = 0;
2396     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2397     info.group_index        = 2;
2398     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2399     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2400     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2401     info.func               = __cvmx_error_display;
2402     info.user_info          = (long)
2403         "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
2404         "    condition\n";
2405     fail |= cvmx_error_add(&info);
2406
2407     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2408     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2409     info.status_mask        = 1ull<<4 /* txfifo */;
2410     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2411     info.enable_mask        = 1ull<<4 /* txfifo_en */;
2412     info.flags              = 0;
2413     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2414     info.group_index        = 2;
2415     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2416     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2417     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2418     info.func               = __cvmx_error_display;
2419     info.user_info          = (long)
2420         "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
2421         "    condition\n";
2422     fail |= cvmx_error_add(&info);
2423
2424     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2425     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2426     info.status_mask        = 1ull<<5 /* txbad */;
2427     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2428     info.enable_mask        = 1ull<<5 /* txbad_en */;
2429     info.flags              = 0;
2430     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2431     info.group_index        = 2;
2432     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2433     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2434     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2435     info.func               = __cvmx_error_display;
2436     info.user_info          = (long)
2437         "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
2438         "    state. Should never be set during normal operation\n";
2439     fail |= cvmx_error_add(&info);
2440
2441     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2442     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2443     info.status_mask        = 1ull<<7 /* rxbad */;
2444     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2445     info.enable_mask        = 1ull<<7 /* rxbad_en */;
2446     info.flags              = 0;
2447     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2448     info.group_index        = 2;
2449     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2450     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2451     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2452     info.func               = __cvmx_error_display;
2453     info.user_info          = (long)
2454         "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
2455         "    state. Should never be set during normal operation\n";
2456     fail |= cvmx_error_add(&info);
2457
2458     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2459     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2460     info.status_mask        = 1ull<<8 /* rxlock */;
2461     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2462     info.enable_mask        = 1ull<<8 /* rxlock_en */;
2463     info.flags              = 0;
2464     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2465     info.group_index        = 2;
2466     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2467     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2468     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2469     info.func               = __cvmx_error_display;
2470     info.user_info          = (long)
2471         "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
2472         "    failure occurs\n"
2473         "    Cannot fire in loopback1 mode\n";
2474     fail |= cvmx_error_add(&info);
2475
2476     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2477     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2478     info.status_mask        = 1ull<<9 /* an_bad */;
2479     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2480     info.enable_mask        = 1ull<<9 /* an_bad_en */;
2481     info.flags              = 0;
2482     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2483     info.group_index        = 2;
2484     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2485     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2486     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2487     info.func               = __cvmx_error_display;
2488     info.user_info          = (long)
2489         "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
2490         "    state. Should never be set during normal operation\n";
2491     fail |= cvmx_error_add(&info);
2492
2493     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2494     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2495     info.status_mask        = 1ull<<10 /* sync_bad */;
2496     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2497     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
2498     info.flags              = 0;
2499     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2500     info.group_index        = 2;
2501     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2502     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2503     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2504     info.func               = __cvmx_error_display;
2505     info.user_info          = (long)
2506         "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
2507         "    state. Should never be set during normal operation\n";
2508     fail |= cvmx_error_add(&info);
2509
2510     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2511     info.status_addr        = CVMX_PCSX_INTX_REG(2,0);
2512     info.status_mask        = 1ull<<12 /* dbg_sync */;
2513     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(2,0);
2514     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
2515     info.flags              = 0;
2516     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2517     info.group_index        = 2;
2518     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2519     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2520     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2521     info.func               = __cvmx_error_display;
2522     info.user_info          = (long)
2523         "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
2524     fail |= cvmx_error_add(&info);
2525
2526     /* CVMX_PCSX_INTX_REG(3,0) */
2527     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2528     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2529     info.status_mask        = 1ull<<2 /* an_err */;
2530     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2531     info.enable_mask        = 1ull<<2 /* an_err_en */;
2532     info.flags              = 0;
2533     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2534     info.group_index        = 3;
2535     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2536     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2537     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2538     info.func               = __cvmx_error_display;
2539     info.user_info          = (long)
2540         "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
2541     fail |= cvmx_error_add(&info);
2542
2543     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2544     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2545     info.status_mask        = 1ull<<3 /* txfifu */;
2546     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2547     info.enable_mask        = 1ull<<3 /* txfifu_en */;
2548     info.flags              = 0;
2549     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2550     info.group_index        = 3;
2551     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2552     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2553     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2554     info.func               = __cvmx_error_display;
2555     info.user_info          = (long)
2556         "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
2557         "    condition\n";
2558     fail |= cvmx_error_add(&info);
2559
2560     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2561     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2562     info.status_mask        = 1ull<<4 /* txfifo */;
2563     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2564     info.enable_mask        = 1ull<<4 /* txfifo_en */;
2565     info.flags              = 0;
2566     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2567     info.group_index        = 3;
2568     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2569     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2570     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2571     info.func               = __cvmx_error_display;
2572     info.user_info          = (long)
2573         "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
2574         "    condition\n";
2575     fail |= cvmx_error_add(&info);
2576
2577     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2578     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2579     info.status_mask        = 1ull<<5 /* txbad */;
2580     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2581     info.enable_mask        = 1ull<<5 /* txbad_en */;
2582     info.flags              = 0;
2583     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2584     info.group_index        = 3;
2585     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2586     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2587     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2588     info.func               = __cvmx_error_display;
2589     info.user_info          = (long)
2590         "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
2591         "    state. Should never be set during normal operation\n";
2592     fail |= cvmx_error_add(&info);
2593
2594     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2595     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2596     info.status_mask        = 1ull<<7 /* rxbad */;
2597     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2598     info.enable_mask        = 1ull<<7 /* rxbad_en */;
2599     info.flags              = 0;
2600     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2601     info.group_index        = 3;
2602     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2603     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2604     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2605     info.func               = __cvmx_error_display;
2606     info.user_info          = (long)
2607         "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a  bad\n"
2608         "    state. Should never be set during normal operation\n";
2609     fail |= cvmx_error_add(&info);
2610
2611     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2612     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2613     info.status_mask        = 1ull<<8 /* rxlock */;
2614     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2615     info.enable_mask        = 1ull<<8 /* rxlock_en */;
2616     info.flags              = 0;
2617     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2618     info.group_index        = 3;
2619     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2620     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2621     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2622     info.func               = __cvmx_error_display;
2623     info.user_info          = (long)
2624         "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
2625         "    failure occurs\n"
2626         "    Cannot fire in loopback1 mode\n";
2627     fail |= cvmx_error_add(&info);
2628
2629     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2630     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2631     info.status_mask        = 1ull<<9 /* an_bad */;
2632     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2633     info.enable_mask        = 1ull<<9 /* an_bad_en */;
2634     info.flags              = 0;
2635     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2636     info.group_index        = 3;
2637     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2638     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2639     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2640     info.func               = __cvmx_error_display;
2641     info.user_info          = (long)
2642         "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
2643         "    state. Should never be set during normal operation\n";
2644     fail |= cvmx_error_add(&info);
2645
2646     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2647     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2648     info.status_mask        = 1ull<<10 /* sync_bad */;
2649     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2650     info.enable_mask        = 1ull<<10 /* sync_bad_en */;
2651     info.flags              = 0;
2652     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2653     info.group_index        = 3;
2654     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2655     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2656     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2657     info.func               = __cvmx_error_display;
2658     info.user_info          = (long)
2659         "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
2660         "    state. Should never be set during normal operation\n";
2661     fail |= cvmx_error_add(&info);
2662
2663     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2664     info.status_addr        = CVMX_PCSX_INTX_REG(3,0);
2665     info.status_mask        = 1ull<<12 /* dbg_sync */;
2666     info.enable_addr        = CVMX_PCSX_INTX_EN_REG(3,0);
2667     info.enable_mask        = 1ull<<12 /* dbg_sync_en */;
2668     info.flags              = 0;
2669     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2670     info.group_index        = 3;
2671     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2672     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2673     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2674     info.func               = __cvmx_error_display;
2675     info.user_info          = (long)
2676         "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
2677     fail |= cvmx_error_add(&info);
2678
2679     /* CVMX_PCSXX_INT_REG(0) */
2680     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2681     info.status_addr        = CVMX_PCSXX_INT_REG(0);
2682     info.status_mask        = 1ull<<0 /* txflt */;
2683     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
2684     info.enable_mask        = 1ull<<0 /* txflt_en */;
2685     info.flags              = 0;
2686     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2687     info.group_index        = 0;
2688     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2689     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2690     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2691     info.func               = __cvmx_error_display;
2692     info.user_info          = (long)
2693         "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
2694     fail |= cvmx_error_add(&info);
2695
2696     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2697     info.status_addr        = CVMX_PCSXX_INT_REG(0);
2698     info.status_mask        = 1ull<<1 /* rxbad */;
2699     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
2700     info.enable_mask        = 1ull<<1 /* rxbad_en */;
2701     info.flags              = 0;
2702     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2703     info.group_index        = 0;
2704     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2705     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2706     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2707     info.func               = __cvmx_error_display;
2708     info.user_info          = (long)
2709         "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
2710     fail |= cvmx_error_add(&info);
2711
2712     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2713     info.status_addr        = CVMX_PCSXX_INT_REG(0);
2714     info.status_mask        = 1ull<<2 /* rxsynbad */;
2715     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
2716     info.enable_mask        = 1ull<<2 /* rxsynbad_en */;
2717     info.flags              = 0;
2718     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2719     info.group_index        = 0;
2720     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2721     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2722     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2723     info.func               = __cvmx_error_display;
2724     info.user_info          = (long)
2725         "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
2726         "    in one of the 4 xaui lanes\n";
2727     fail |= cvmx_error_add(&info);
2728
2729     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2730     info.status_addr        = CVMX_PCSXX_INT_REG(0);
2731     info.status_mask        = 1ull<<3 /* bitlckls */;
2732     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
2733     info.enable_mask        = 1ull<<3 /* bitlckls_en */;
2734     info.flags              = 0;
2735     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2736     info.group_index        = 0;
2737     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2738     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2739     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2740     info.func               = __cvmx_error_display;
2741     info.user_info          = (long)
2742         "ERROR PCSXX_INT_REG(0)[BITLCKLS]: Set when Bit lock lost on 1 or more xaui lanes\n";
2743     fail |= cvmx_error_add(&info);
2744
2745     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2746     info.status_addr        = CVMX_PCSXX_INT_REG(0);
2747     info.status_mask        = 1ull<<4 /* synlos */;
2748     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
2749     info.enable_mask        = 1ull<<4 /* synlos_en */;
2750     info.flags              = 0;
2751     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2752     info.group_index        = 0;
2753     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2754     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2755     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2756     info.func               = __cvmx_error_display;
2757     info.user_info          = (long)
2758         "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more  lanes\n";
2759     fail |= cvmx_error_add(&info);
2760
2761     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2762     info.status_addr        = CVMX_PCSXX_INT_REG(0);
2763     info.status_mask        = 1ull<<5 /* algnlos */;
2764     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
2765     info.enable_mask        = 1ull<<5 /* algnlos_en */;
2766     info.flags              = 0;
2767     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2768     info.group_index        = 0;
2769     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2770     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2771     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2772     info.func               = __cvmx_error_display;
2773     info.user_info          = (long)
2774         "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
2775     fail |= cvmx_error_add(&info);
2776
2777     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2778     info.status_addr        = CVMX_PCSXX_INT_REG(0);
2779     info.status_mask        = 1ull<<6 /* dbg_sync */;
2780     info.enable_addr        = CVMX_PCSXX_INT_EN_REG(0);
2781     info.enable_mask        = 1ull<<6 /* dbg_sync_en */;
2782     info.flags              = 0;
2783     info.group              = CVMX_ERROR_GROUP_ETHERNET;
2784     info.group_index        = 0;
2785     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2786     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2787     info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
2788     info.func               = __cvmx_error_display;
2789     info.user_info          = (long)
2790         "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
2791     fail |= cvmx_error_add(&info);
2792
2793     /* CVMX_PIP_INT_REG */
2794     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2795     info.status_addr        = CVMX_PIP_INT_REG;
2796     info.status_mask        = 1ull<<3 /* prtnxa */;
2797     info.enable_addr        = CVMX_PIP_INT_EN;
2798     info.enable_mask        = 1ull<<3 /* prtnxa */;
2799     info.flags              = 0;
2800     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2801     info.group_index        = 0;
2802     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2803     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2804     info.parent.status_mask = 1ull<<20 /* pip */;
2805     info.func               = __cvmx_error_display;
2806     info.user_info          = (long)
2807         "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
2808     fail |= cvmx_error_add(&info);
2809
2810     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2811     info.status_addr        = CVMX_PIP_INT_REG;
2812     info.status_mask        = 1ull<<4 /* badtag */;
2813     info.enable_addr        = CVMX_PIP_INT_EN;
2814     info.enable_mask        = 1ull<<4 /* badtag */;
2815     info.flags              = 0;
2816     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2817     info.group_index        = 0;
2818     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2819     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2820     info.parent.status_mask = 1ull<<20 /* pip */;
2821     info.func               = __cvmx_error_display;
2822     info.user_info          = (long)
2823         "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
2824     fail |= cvmx_error_add(&info);
2825
2826     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2827     info.status_addr        = CVMX_PIP_INT_REG;
2828     info.status_mask        = 1ull<<5 /* skprunt */;
2829     info.enable_addr        = CVMX_PIP_INT_EN;
2830     info.enable_mask        = 1ull<<5 /* skprunt */;
2831     info.flags              = 0;
2832     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2833     info.group_index        = 0;
2834     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2835     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2836     info.parent.status_mask = 1ull<<20 /* pip */;
2837     info.func               = __cvmx_error_display;
2838     info.user_info          = (long)
2839         "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
2840         "    This interrupt can occur with received PARTIAL\n"
2841         "    packets that are truncated to SKIP bytes or\n"
2842         "    smaller.\n";
2843     fail |= cvmx_error_add(&info);
2844
2845     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2846     info.status_addr        = CVMX_PIP_INT_REG;
2847     info.status_mask        = 1ull<<6 /* todoovr */;
2848     info.enable_addr        = CVMX_PIP_INT_EN;
2849     info.enable_mask        = 1ull<<6 /* todoovr */;
2850     info.flags              = 0;
2851     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2852     info.group_index        = 0;
2853     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2854     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2855     info.parent.status_mask = 1ull<<20 /* pip */;
2856     info.func               = __cvmx_error_display;
2857     info.user_info          = (long)
2858         "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
2859     fail |= cvmx_error_add(&info);
2860
2861     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2862     info.status_addr        = CVMX_PIP_INT_REG;
2863     info.status_mask        = 1ull<<7 /* feperr */;
2864     info.enable_addr        = CVMX_PIP_INT_EN;
2865     info.enable_mask        = 1ull<<7 /* feperr */;
2866     info.flags              = 0;
2867     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2868     info.group_index        = 0;
2869     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2870     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2871     info.parent.status_mask = 1ull<<20 /* pip */;
2872     info.func               = __cvmx_error_display;
2873     info.user_info          = (long)
2874         "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
2875     fail |= cvmx_error_add(&info);
2876
2877     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2878     info.status_addr        = CVMX_PIP_INT_REG;
2879     info.status_mask        = 1ull<<8 /* beperr */;
2880     info.enable_addr        = CVMX_PIP_INT_EN;
2881     info.enable_mask        = 1ull<<8 /* beperr */;
2882     info.flags              = 0;
2883     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2884     info.group_index        = 0;
2885     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2886     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2887     info.parent.status_mask = 1ull<<20 /* pip */;
2888     info.func               = __cvmx_error_display;
2889     info.user_info          = (long)
2890         "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
2891     fail |= cvmx_error_add(&info);
2892
2893     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2894     info.status_addr        = CVMX_PIP_INT_REG;
2895     info.status_mask        = 1ull<<12 /* punyerr */;
2896     info.enable_addr        = CVMX_PIP_INT_EN;
2897     info.enable_mask        = 1ull<<12 /* punyerr */;
2898     info.flags              = 0;
2899     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2900     info.group_index        = 0;
2901     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2902     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2903     info.parent.status_mask = 1ull<<20 /* pip */;
2904     info.func               = __cvmx_error_display;
2905     info.user_info          = (long)
2906         "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
2907         "    stripping in IPD is enable\n";
2908     fail |= cvmx_error_add(&info);
2909
2910     /* CVMX_PKO_REG_ERROR */
2911     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2912     info.status_addr        = CVMX_PKO_REG_ERROR;
2913     info.status_mask        = 1ull<<0 /* parity */;
2914     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2915     info.enable_mask        = 1ull<<0 /* parity */;
2916     info.flags              = 0;
2917     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2918     info.group_index        = 0;
2919     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2920     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2921     info.parent.status_mask = 1ull<<10 /* pko */;
2922     info.func               = __cvmx_error_display;
2923     info.user_info          = (long)
2924         "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
2925     fail |= cvmx_error_add(&info);
2926
2927     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2928     info.status_addr        = CVMX_PKO_REG_ERROR;
2929     info.status_mask        = 1ull<<1 /* doorbell */;
2930     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2931     info.enable_mask        = 1ull<<1 /* doorbell */;
2932     info.flags              = 0;
2933     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2934     info.group_index        = 0;
2935     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2936     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2937     info.parent.status_mask = 1ull<<10 /* pko */;
2938     info.func               = __cvmx_error_display;
2939     info.user_info          = (long)
2940         "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
2941     fail |= cvmx_error_add(&info);
2942
2943     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2944     info.status_addr        = CVMX_PKO_REG_ERROR;
2945     info.status_mask        = 1ull<<2 /* currzero */;
2946     info.enable_addr        = CVMX_PKO_REG_INT_MASK;
2947     info.enable_mask        = 1ull<<2 /* currzero */;
2948     info.flags              = 0;
2949     info.group              = CVMX_ERROR_GROUP_INTERNAL;
2950     info.group_index        = 0;
2951     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2952     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2953     info.parent.status_mask = 1ull<<10 /* pko */;
2954     info.func               = __cvmx_error_display;
2955     info.user_info          = (long)
2956         "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
2957     fail |= cvmx_error_add(&info);
2958
2959     /* CVMX_PEMX_INT_SUM(0) */
2960     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2961     info.status_addr        = CVMX_PEMX_INT_SUM(0);
2962     info.status_mask        = 1ull<<1 /* se */;
2963     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
2964     info.enable_mask        = 1ull<<1 /* se */;
2965     info.flags              = 0;
2966     info.group              = CVMX_ERROR_GROUP_PCI;
2967     info.group_index        = 0;
2968     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2969     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2970     info.parent.status_mask = 1ull<<25 /* pem0 */;
2971     info.func               = __cvmx_error_display;
2972     info.user_info          = (long)
2973         "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
2974         "    (cfg_sys_err_rc)\n";
2975     fail |= cvmx_error_add(&info);
2976
2977     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2978     info.status_addr        = CVMX_PEMX_INT_SUM(0);
2979     info.status_mask        = 1ull<<4 /* up_b1 */;
2980     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
2981     info.enable_mask        = 1ull<<4 /* up_b1 */;
2982     info.flags              = 0;
2983     info.group              = CVMX_ERROR_GROUP_PCI;
2984     info.group_index        = 0;
2985     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
2986     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2987     info.parent.status_mask = 1ull<<25 /* pem0 */;
2988     info.func               = __cvmx_error_display;
2989     info.user_info          = (long)
2990         "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
2991         "    is not set.\n";
2992     fail |= cvmx_error_add(&info);
2993
2994     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
2995     info.status_addr        = CVMX_PEMX_INT_SUM(0);
2996     info.status_mask        = 1ull<<5 /* up_b2 */;
2997     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
2998     info.enable_mask        = 1ull<<5 /* up_b2 */;
2999     info.flags              = 0;
3000     info.group              = CVMX_ERROR_GROUP_PCI;
3001     info.group_index        = 0;
3002     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3003     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3004     info.parent.status_mask = 1ull<<25 /* pem0 */;
3005     info.func               = __cvmx_error_display;
3006     info.user_info          = (long)
3007         "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
3008     fail |= cvmx_error_add(&info);
3009
3010     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3011     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3012     info.status_mask        = 1ull<<6 /* up_bx */;
3013     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
3014     info.enable_mask        = 1ull<<6 /* up_bx */;
3015     info.flags              = 0;
3016     info.group              = CVMX_ERROR_GROUP_PCI;
3017     info.group_index        = 0;
3018     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3019     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3020     info.parent.status_mask = 1ull<<25 /* pem0 */;
3021     info.func               = __cvmx_error_display;
3022     info.user_info          = (long)
3023         "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
3024     fail |= cvmx_error_add(&info);
3025
3026     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3027     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3028     info.status_mask        = 1ull<<7 /* un_b1 */;
3029     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
3030     info.enable_mask        = 1ull<<7 /* un_b1 */;
3031     info.flags              = 0;
3032     info.group              = CVMX_ERROR_GROUP_PCI;
3033     info.group_index        = 0;
3034     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3035     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3036     info.parent.status_mask = 1ull<<25 /* pem0 */;
3037     info.func               = __cvmx_error_display;
3038     info.user_info          = (long)
3039         "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
3040         "    is not set.\n";
3041     fail |= cvmx_error_add(&info);
3042
3043     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3044     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3045     info.status_mask        = 1ull<<8 /* un_b2 */;
3046     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
3047     info.enable_mask        = 1ull<<8 /* un_b2 */;
3048     info.flags              = 0;
3049     info.group              = CVMX_ERROR_GROUP_PCI;
3050     info.group_index        = 0;
3051     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3052     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3053     info.parent.status_mask = 1ull<<25 /* pem0 */;
3054     info.func               = __cvmx_error_display;
3055     info.user_info          = (long)
3056         "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
3057     fail |= cvmx_error_add(&info);
3058
3059     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3060     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3061     info.status_mask        = 1ull<<9 /* un_bx */;
3062     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
3063     info.enable_mask        = 1ull<<9 /* un_bx */;
3064     info.flags              = 0;
3065     info.group              = CVMX_ERROR_GROUP_PCI;
3066     info.group_index        = 0;
3067     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3068     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3069     info.parent.status_mask = 1ull<<25 /* pem0 */;
3070     info.func               = __cvmx_error_display;
3071     info.user_info          = (long)
3072         "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
3073     fail |= cvmx_error_add(&info);
3074
3075     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3076     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3077     info.status_mask        = 1ull<<11 /* rdlk */;
3078     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
3079     info.enable_mask        = 1ull<<11 /* rdlk */;
3080     info.flags              = 0;
3081     info.group              = CVMX_ERROR_GROUP_PCI;
3082     info.group_index        = 0;
3083     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3084     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3085     info.parent.status_mask = 1ull<<25 /* pem0 */;
3086     info.func               = __cvmx_error_display;
3087     info.user_info          = (long)
3088         "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
3089     fail |= cvmx_error_add(&info);
3090
3091     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3092     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3093     info.status_mask        = 1ull<<12 /* crs_er */;
3094     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
3095     info.enable_mask        = 1ull<<12 /* crs_er */;
3096     info.flags              = 0;
3097     info.group              = CVMX_ERROR_GROUP_PCI;
3098     info.group_index        = 0;
3099     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3100     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3101     info.parent.status_mask = 1ull<<25 /* pem0 */;
3102     info.func               = __cvmx_error_display;
3103     info.user_info          = (long)
3104         "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
3105     fail |= cvmx_error_add(&info);
3106
3107     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3108     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3109     info.status_mask        = 1ull<<13 /* crs_dr */;
3110     info.enable_addr        = CVMX_PEMX_INT_ENB(0);
3111     info.enable_mask        = 1ull<<13 /* crs_dr */;
3112     info.flags              = 0;
3113     info.group              = CVMX_ERROR_GROUP_PCI;
3114     info.group_index        = 0;
3115     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3116     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3117     info.parent.status_mask = 1ull<<25 /* pem0 */;
3118     info.func               = __cvmx_error_display;
3119     info.user_info          = (long)
3120         "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
3121     fail |= cvmx_error_add(&info);
3122
3123     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3124     info.status_addr        = CVMX_PEMX_INT_SUM(0);
3125     info.status_mask        = 0;
3126     info.enable_addr        = 0;
3127     info.enable_mask        = 0;
3128     info.flags              = 0;
3129     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3130     info.group_index        = 0;
3131     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3132     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3133     info.parent.status_mask = 1ull<<25 /* pem0 */;
3134     info.func               = __cvmx_error_decode;
3135     info.user_info          = 0;
3136     fail |= cvmx_error_add(&info);
3137
3138     /* CVMX_PEMX_DBG_INFO(0) */
3139     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3140     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3141     info.status_mask        = 1ull<<0 /* spoison */;
3142     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3143     info.enable_mask        = 1ull<<0 /* spoison */;
3144     info.flags              = 0;
3145     info.group              = CVMX_ERROR_GROUP_PCI;
3146     info.group_index        = 0;
3147     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3148     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3149     info.parent.status_mask = 1ull<<10 /* exc */;
3150     info.func               = __cvmx_error_display;
3151     info.user_info          = (long)
3152         "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
3153         "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
3154     fail |= cvmx_error_add(&info);
3155
3156     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3157     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3158     info.status_mask        = 1ull<<2 /* rtlplle */;
3159     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3160     info.enable_mask        = 1ull<<2 /* rtlplle */;
3161     info.flags              = 0;
3162     info.group              = CVMX_ERROR_GROUP_PCI;
3163     info.group_index        = 0;
3164     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3165     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3166     info.parent.status_mask = 1ull<<10 /* exc */;
3167     info.func               = __cvmx_error_display;
3168     info.user_info          = (long)
3169         "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
3170         "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
3171     fail |= cvmx_error_add(&info);
3172
3173     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3174     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3175     info.status_mask        = 1ull<<3 /* recrce */;
3176     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3177     info.enable_mask        = 1ull<<3 /* recrce */;
3178     info.flags              = 0;
3179     info.group              = CVMX_ERROR_GROUP_PCI;
3180     info.group_index        = 0;
3181     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3182     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3183     info.parent.status_mask = 1ull<<10 /* exc */;
3184     info.func               = __cvmx_error_display;
3185     info.user_info          = (long)
3186         "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
3187         "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3188     fail |= cvmx_error_add(&info);
3189
3190     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3191     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3192     info.status_mask        = 1ull<<4 /* rpoison */;
3193     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3194     info.enable_mask        = 1ull<<4 /* rpoison */;
3195     info.flags              = 0;
3196     info.group              = CVMX_ERROR_GROUP_PCI;
3197     info.group_index        = 0;
3198     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3199     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3200     info.parent.status_mask = 1ull<<10 /* exc */;
3201     info.func               = __cvmx_error_display;
3202     info.user_info          = (long)
3203         "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
3204         "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3205     fail |= cvmx_error_add(&info);
3206
3207     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3208     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3209     info.status_mask        = 1ull<<5 /* rcemrc */;
3210     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3211     info.enable_mask        = 1ull<<5 /* rcemrc */;
3212     info.flags              = 0;
3213     info.group              = CVMX_ERROR_GROUP_PCI;
3214     info.group_index        = 0;
3215     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3216     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3217     info.parent.status_mask = 1ull<<10 /* exc */;
3218     info.func               = __cvmx_error_display;
3219     info.user_info          = (long)
3220         "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
3221         "    pedc_radm_correctable_err\n";
3222     fail |= cvmx_error_add(&info);
3223
3224     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3225     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3226     info.status_mask        = 1ull<<6 /* rnfemrc */;
3227     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3228     info.enable_mask        = 1ull<<6 /* rnfemrc */;
3229     info.flags              = 0;
3230     info.group              = CVMX_ERROR_GROUP_PCI;
3231     info.group_index        = 0;
3232     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3233     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3234     info.parent.status_mask = 1ull<<10 /* exc */;
3235     info.func               = __cvmx_error_display;
3236     info.user_info          = (long)
3237         "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3238         "    pedc_radm_nonfatal_err\n";
3239     fail |= cvmx_error_add(&info);
3240
3241     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3242     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3243     info.status_mask        = 1ull<<7 /* rfemrc */;
3244     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3245     info.enable_mask        = 1ull<<7 /* rfemrc */;
3246     info.flags              = 0;
3247     info.group              = CVMX_ERROR_GROUP_PCI;
3248     info.group_index        = 0;
3249     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3250     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3251     info.parent.status_mask = 1ull<<10 /* exc */;
3252     info.func               = __cvmx_error_display;
3253     info.user_info          = (long)
3254         "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3255         "    pedc_radm_fatal_err\n"
3256         "    Bit set when a message with ERR_FATAL is set.\n";
3257     fail |= cvmx_error_add(&info);
3258
3259     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3260     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3261     info.status_mask        = 1ull<<8 /* rpmerc */;
3262     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3263     info.enable_mask        = 1ull<<8 /* rpmerc */;
3264     info.flags              = 0;
3265     info.group              = CVMX_ERROR_GROUP_PCI;
3266     info.group_index        = 0;
3267     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3268     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3269     info.parent.status_mask = 1ull<<10 /* exc */;
3270     info.func               = __cvmx_error_display;
3271     info.user_info          = (long)
3272         "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
3273         "    pedc_radm_pm_pme\n";
3274     fail |= cvmx_error_add(&info);
3275
3276     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3277     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3278     info.status_mask        = 1ull<<9 /* rptamrc */;
3279     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3280     info.enable_mask        = 1ull<<9 /* rptamrc */;
3281     info.flags              = 0;
3282     info.group              = CVMX_ERROR_GROUP_PCI;
3283     info.group_index        = 0;
3284     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3285     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3286     info.parent.status_mask = 1ull<<10 /* exc */;
3287     info.func               = __cvmx_error_display;
3288     info.user_info          = (long)
3289         "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3290         "    (RC Mode only)\n"
3291         "    pedc_radm_pm_to_ack\n";
3292     fail |= cvmx_error_add(&info);
3293
3294     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3295     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3296     info.status_mask        = 1ull<<10 /* rumep */;
3297     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3298     info.enable_mask        = 1ull<<10 /* rumep */;
3299     info.flags              = 0;
3300     info.group              = CVMX_ERROR_GROUP_PCI;
3301     info.group_index        = 0;
3302     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3303     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3304     info.parent.status_mask = 1ull<<10 /* exc */;
3305     info.func               = __cvmx_error_display;
3306     info.user_info          = (long)
3307         "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
3308         "    pedc_radm_msg_unlock\n";
3309     fail |= cvmx_error_add(&info);
3310
3311     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3312     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3313     info.status_mask        = 1ull<<11 /* rvdm */;
3314     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3315     info.enable_mask        = 1ull<<11 /* rvdm */;
3316     info.flags              = 0;
3317     info.group              = CVMX_ERROR_GROUP_PCI;
3318     info.group_index        = 0;
3319     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3320     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3321     info.parent.status_mask = 1ull<<10 /* exc */;
3322     info.func               = __cvmx_error_display;
3323     info.user_info          = (long)
3324         "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
3325         "    pedc_radm_vendor_msg\n";
3326     fail |= cvmx_error_add(&info);
3327
3328     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3329     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3330     info.status_mask        = 1ull<<12 /* acto */;
3331     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3332     info.enable_mask        = 1ull<<12 /* acto */;
3333     info.flags              = 0;
3334     info.group              = CVMX_ERROR_GROUP_PCI;
3335     info.group_index        = 0;
3336     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3337     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3338     info.parent.status_mask = 1ull<<10 /* exc */;
3339     info.func               = __cvmx_error_display;
3340     info.user_info          = (long)
3341         "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
3342         "    pedc_radm_cpl_timeout\n";
3343     fail |= cvmx_error_add(&info);
3344
3345     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3346     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3347     info.status_mask        = 1ull<<13 /* rte */;
3348     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3349     info.enable_mask        = 1ull<<13 /* rte */;
3350     info.flags              = 0;
3351     info.group              = CVMX_ERROR_GROUP_PCI;
3352     info.group_index        = 0;
3353     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3354     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3355     info.parent.status_mask = 1ull<<10 /* exc */;
3356     info.func               = __cvmx_error_display;
3357     info.user_info          = (long)
3358         "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
3359         "    xdlh_replay_timeout_err\n"
3360         "    This bit is set when the REPLAY_TIMER expires in\n"
3361         "    the PCIE core. The probability of this bit being\n"
3362         "    set will increase with the traffic load.\n";
3363     fail |= cvmx_error_add(&info);
3364
3365     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3366     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3367     info.status_mask        = 1ull<<14 /* mre */;
3368     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3369     info.enable_mask        = 1ull<<14 /* mre */;
3370     info.flags              = 0;
3371     info.group              = CVMX_ERROR_GROUP_PCI;
3372     info.group_index        = 0;
3373     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3374     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3375     info.parent.status_mask = 1ull<<10 /* exc */;
3376     info.func               = __cvmx_error_display;
3377     info.user_info          = (long)
3378         "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
3379         "    xdlh_replay_num_rlover_err\n";
3380     fail |= cvmx_error_add(&info);
3381
3382     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3383     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3384     info.status_mask        = 1ull<<15 /* rdwdle */;
3385     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3386     info.enable_mask        = 1ull<<15 /* rdwdle */;
3387     info.flags              = 0;
3388     info.group              = CVMX_ERROR_GROUP_PCI;
3389     info.group_index        = 0;
3390     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3391     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3392     info.parent.status_mask = 1ull<<10 /* exc */;
3393     info.func               = __cvmx_error_display;
3394     info.user_info          = (long)
3395         "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
3396         "    rdlh_bad_dllp_err\n";
3397     fail |= cvmx_error_add(&info);
3398
3399     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3400     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3401     info.status_mask        = 1ull<<16 /* rtwdle */;
3402     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3403     info.enable_mask        = 1ull<<16 /* rtwdle */;
3404     info.flags              = 0;
3405     info.group              = CVMX_ERROR_GROUP_PCI;
3406     info.group_index        = 0;
3407     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3408     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3409     info.parent.status_mask = 1ull<<10 /* exc */;
3410     info.func               = __cvmx_error_display;
3411     info.user_info          = (long)
3412         "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
3413         "    rdlh_bad_tlp_err\n";
3414     fail |= cvmx_error_add(&info);
3415
3416     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3417     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3418     info.status_mask        = 1ull<<17 /* dpeoosd */;
3419     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3420     info.enable_mask        = 1ull<<17 /* dpeoosd */;
3421     info.flags              = 0;
3422     info.group              = CVMX_ERROR_GROUP_PCI;
3423     info.group_index        = 0;
3424     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3425     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3426     info.parent.status_mask = 1ull<<10 /* exc */;
3427     info.func               = __cvmx_error_display;
3428     info.user_info          = (long)
3429         "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
3430         "    rdlh_prot_err\n";
3431     fail |= cvmx_error_add(&info);
3432
3433     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3434     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3435     info.status_mask        = 1ull<<18 /* fcpvwt */;
3436     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3437     info.enable_mask        = 1ull<<18 /* fcpvwt */;
3438     info.flags              = 0;
3439     info.group              = CVMX_ERROR_GROUP_PCI;
3440     info.group_index        = 0;
3441     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3442     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3443     info.parent.status_mask = 1ull<<10 /* exc */;
3444     info.func               = __cvmx_error_display;
3445     info.user_info          = (long)
3446         "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
3447         "    rtlh_fc_prot_err\n";
3448     fail |= cvmx_error_add(&info);
3449
3450     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3451     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3452     info.status_mask        = 1ull<<19 /* rpe */;
3453     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3454     info.enable_mask        = 1ull<<19 /* rpe */;
3455     info.flags              = 0;
3456     info.group              = CVMX_ERROR_GROUP_PCI;
3457     info.group_index        = 0;
3458     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3459     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3460     info.parent.status_mask = 1ull<<10 /* exc */;
3461     info.func               = __cvmx_error_display;
3462     info.user_info          = (long)
3463         "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
3464         "    (RxStatus = 3b100) or disparity error\n"
3465         "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
3466         "    be asserted.\n"
3467         "    rmlh_rcvd_err\n";
3468     fail |= cvmx_error_add(&info);
3469
3470     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3471     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3472     info.status_mask        = 1ull<<20 /* fcuv */;
3473     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3474     info.enable_mask        = 1ull<<20 /* fcuv */;
3475     info.flags              = 0;
3476     info.group              = CVMX_ERROR_GROUP_PCI;
3477     info.group_index        = 0;
3478     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3479     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3480     info.parent.status_mask = 1ull<<10 /* exc */;
3481     info.func               = __cvmx_error_display;
3482     info.user_info          = (long)
3483         "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
3484         "    int_xadm_fc_prot_err\n";
3485     fail |= cvmx_error_add(&info);
3486
3487     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3488     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3489     info.status_mask        = 1ull<<21 /* rqo */;
3490     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3491     info.enable_mask        = 1ull<<21 /* rqo */;
3492     info.flags              = 0;
3493     info.group              = CVMX_ERROR_GROUP_PCI;
3494     info.group_index        = 0;
3495     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3496     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3497     info.parent.status_mask = 1ull<<10 /* exc */;
3498     info.func               = __cvmx_error_display;
3499     info.user_info          = (long)
3500         "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
3501         "    flow control advertisements are ignored\n"
3502         "    radm_qoverflow\n";
3503     fail |= cvmx_error_add(&info);
3504
3505     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3506     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3507     info.status_mask        = 1ull<<22 /* rauc */;
3508     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3509     info.enable_mask        = 1ull<<22 /* rauc */;
3510     info.flags              = 0;
3511     info.group              = CVMX_ERROR_GROUP_PCI;
3512     info.group_index        = 0;
3513     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3514     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3515     info.parent.status_mask = 1ull<<10 /* exc */;
3516     info.func               = __cvmx_error_display;
3517     info.user_info          = (long)
3518         "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
3519         "    radm_unexp_cpl_err\n";
3520     fail |= cvmx_error_add(&info);
3521
3522     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3523     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3524     info.status_mask        = 1ull<<23 /* racur */;
3525     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3526     info.enable_mask        = 1ull<<23 /* racur */;
3527     info.flags              = 0;
3528     info.group              = CVMX_ERROR_GROUP_PCI;
3529     info.group_index        = 0;
3530     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3531     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3532     info.parent.status_mask = 1ull<<10 /* exc */;
3533     info.func               = __cvmx_error_display;
3534     info.user_info          = (long)
3535         "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
3536         "    radm_rcvd_cpl_ur\n";
3537     fail |= cvmx_error_add(&info);
3538
3539     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3540     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3541     info.status_mask        = 1ull<<24 /* racca */;
3542     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3543     info.enable_mask        = 1ull<<24 /* racca */;
3544     info.flags              = 0;
3545     info.group              = CVMX_ERROR_GROUP_PCI;
3546     info.group_index        = 0;
3547     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3548     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3549     info.parent.status_mask = 1ull<<10 /* exc */;
3550     info.func               = __cvmx_error_display;
3551     info.user_info          = (long)
3552         "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
3553         "    radm_rcvd_cpl_ca\n";
3554     fail |= cvmx_error_add(&info);
3555
3556     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3557     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3558     info.status_mask        = 1ull<<25 /* caar */;
3559     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3560     info.enable_mask        = 1ull<<25 /* caar */;
3561     info.flags              = 0;
3562     info.group              = CVMX_ERROR_GROUP_PCI;
3563     info.group_index        = 0;
3564     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3565     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3566     info.parent.status_mask = 1ull<<10 /* exc */;
3567     info.func               = __cvmx_error_display;
3568     info.user_info          = (long)
3569         "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
3570         "    radm_rcvd_ca_req\n"
3571         "    This bit will never be set because Octeon does\n"
3572         "    not generate Completer Aborts.\n";
3573     fail |= cvmx_error_add(&info);
3574
3575     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3576     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3577     info.status_mask        = 1ull<<26 /* rarwdns */;
3578     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3579     info.enable_mask        = 1ull<<26 /* rarwdns */;
3580     info.flags              = 0;
3581     info.group              = CVMX_ERROR_GROUP_PCI;
3582     info.group_index        = 0;
3583     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3584     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3585     info.parent.status_mask = 1ull<<10 /* exc */;
3586     info.func               = __cvmx_error_display;
3587     info.user_info          = (long)
3588         "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
3589         "    radm_rcvd_ur_req\n";
3590     fail |= cvmx_error_add(&info);
3591
3592     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3593     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3594     info.status_mask        = 1ull<<27 /* ramtlp */;
3595     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3596     info.enable_mask        = 1ull<<27 /* ramtlp */;
3597     info.flags              = 0;
3598     info.group              = CVMX_ERROR_GROUP_PCI;
3599     info.group_index        = 0;
3600     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3601     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3602     info.parent.status_mask = 1ull<<10 /* exc */;
3603     info.func               = __cvmx_error_display;
3604     info.user_info          = (long)
3605         "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
3606         "    radm_mlf_tlp_err\n";
3607     fail |= cvmx_error_add(&info);
3608
3609     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3610     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3611     info.status_mask        = 1ull<<28 /* racpp */;
3612     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3613     info.enable_mask        = 1ull<<28 /* racpp */;
3614     info.flags              = 0;
3615     info.group              = CVMX_ERROR_GROUP_PCI;
3616     info.group_index        = 0;
3617     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3618     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3619     info.parent.status_mask = 1ull<<10 /* exc */;
3620     info.func               = __cvmx_error_display;
3621     info.user_info          = (long)
3622         "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
3623         "    radm_rcvd_cpl_poisoned\n";
3624     fail |= cvmx_error_add(&info);
3625
3626     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3627     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3628     info.status_mask        = 1ull<<29 /* rawwpp */;
3629     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3630     info.enable_mask        = 1ull<<29 /* rawwpp */;
3631     info.flags              = 0;
3632     info.group              = CVMX_ERROR_GROUP_PCI;
3633     info.group_index        = 0;
3634     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3635     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3636     info.parent.status_mask = 1ull<<10 /* exc */;
3637     info.func               = __cvmx_error_display;
3638     info.user_info          = (long)
3639         "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
3640         "    radm_rcvd_wreq_poisoned\n";
3641     fail |= cvmx_error_add(&info);
3642
3643     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3644     info.status_addr        = CVMX_PEMX_DBG_INFO(0);
3645     info.status_mask        = 1ull<<30 /* ecrc_e */;
3646     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(0);
3647     info.enable_mask        = 1ull<<30 /* ecrc_e */;
3648     info.flags              = 0;
3649     info.group              = CVMX_ERROR_GROUP_PCI;
3650     info.group_index        = 0;
3651     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3652     info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
3653     info.parent.status_mask = 1ull<<10 /* exc */;
3654     info.func               = __cvmx_error_display;
3655     info.user_info          = (long)
3656         "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
3657         "    radm_ecrc_err\n";
3658     fail |= cvmx_error_add(&info);
3659
3660     /* CVMX_PEMX_INT_SUM(1) */
3661     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3662     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3663     info.status_mask        = 1ull<<1 /* se */;
3664     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3665     info.enable_mask        = 1ull<<1 /* se */;
3666     info.flags              = 0;
3667     info.group              = CVMX_ERROR_GROUP_PCI;
3668     info.group_index        = 1;
3669     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3670     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3671     info.parent.status_mask = 1ull<<26 /* pem1 */;
3672     info.func               = __cvmx_error_display;
3673     info.user_info          = (long)
3674         "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
3675         "    (cfg_sys_err_rc)\n";
3676     fail |= cvmx_error_add(&info);
3677
3678     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3679     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3680     info.status_mask        = 1ull<<4 /* up_b1 */;
3681     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3682     info.enable_mask        = 1ull<<4 /* up_b1 */;
3683     info.flags              = 0;
3684     info.group              = CVMX_ERROR_GROUP_PCI;
3685     info.group_index        = 1;
3686     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3687     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3688     info.parent.status_mask = 1ull<<26 /* pem1 */;
3689     info.func               = __cvmx_error_display;
3690     info.user_info          = (long)
3691         "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
3692         "    is not set.\n";
3693     fail |= cvmx_error_add(&info);
3694
3695     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3696     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3697     info.status_mask        = 1ull<<5 /* up_b2 */;
3698     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3699     info.enable_mask        = 1ull<<5 /* up_b2 */;
3700     info.flags              = 0;
3701     info.group              = CVMX_ERROR_GROUP_PCI;
3702     info.group_index        = 1;
3703     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3704     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3705     info.parent.status_mask = 1ull<<26 /* pem1 */;
3706     info.func               = __cvmx_error_display;
3707     info.user_info          = (long)
3708         "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
3709     fail |= cvmx_error_add(&info);
3710
3711     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3712     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3713     info.status_mask        = 1ull<<6 /* up_bx */;
3714     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3715     info.enable_mask        = 1ull<<6 /* up_bx */;
3716     info.flags              = 0;
3717     info.group              = CVMX_ERROR_GROUP_PCI;
3718     info.group_index        = 1;
3719     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3720     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3721     info.parent.status_mask = 1ull<<26 /* pem1 */;
3722     info.func               = __cvmx_error_display;
3723     info.user_info          = (long)
3724         "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
3725     fail |= cvmx_error_add(&info);
3726
3727     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3728     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3729     info.status_mask        = 1ull<<7 /* un_b1 */;
3730     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3731     info.enable_mask        = 1ull<<7 /* un_b1 */;
3732     info.flags              = 0;
3733     info.group              = CVMX_ERROR_GROUP_PCI;
3734     info.group_index        = 1;
3735     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3736     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3737     info.parent.status_mask = 1ull<<26 /* pem1 */;
3738     info.func               = __cvmx_error_display;
3739     info.user_info          = (long)
3740         "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
3741         "    is not set.\n";
3742     fail |= cvmx_error_add(&info);
3743
3744     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3745     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3746     info.status_mask        = 1ull<<8 /* un_b2 */;
3747     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3748     info.enable_mask        = 1ull<<8 /* un_b2 */;
3749     info.flags              = 0;
3750     info.group              = CVMX_ERROR_GROUP_PCI;
3751     info.group_index        = 1;
3752     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3753     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3754     info.parent.status_mask = 1ull<<26 /* pem1 */;
3755     info.func               = __cvmx_error_display;
3756     info.user_info          = (long)
3757         "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
3758     fail |= cvmx_error_add(&info);
3759
3760     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3761     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3762     info.status_mask        = 1ull<<9 /* un_bx */;
3763     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3764     info.enable_mask        = 1ull<<9 /* un_bx */;
3765     info.flags              = 0;
3766     info.group              = CVMX_ERROR_GROUP_PCI;
3767     info.group_index        = 1;
3768     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3769     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3770     info.parent.status_mask = 1ull<<26 /* pem1 */;
3771     info.func               = __cvmx_error_display;
3772     info.user_info          = (long)
3773         "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
3774     fail |= cvmx_error_add(&info);
3775
3776     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3777     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3778     info.status_mask        = 1ull<<11 /* rdlk */;
3779     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3780     info.enable_mask        = 1ull<<11 /* rdlk */;
3781     info.flags              = 0;
3782     info.group              = CVMX_ERROR_GROUP_PCI;
3783     info.group_index        = 1;
3784     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3785     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3786     info.parent.status_mask = 1ull<<26 /* pem1 */;
3787     info.func               = __cvmx_error_display;
3788     info.user_info          = (long)
3789         "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
3790     fail |= cvmx_error_add(&info);
3791
3792     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3793     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3794     info.status_mask        = 1ull<<12 /* crs_er */;
3795     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3796     info.enable_mask        = 1ull<<12 /* crs_er */;
3797     info.flags              = 0;
3798     info.group              = CVMX_ERROR_GROUP_PCI;
3799     info.group_index        = 1;
3800     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3801     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3802     info.parent.status_mask = 1ull<<26 /* pem1 */;
3803     info.func               = __cvmx_error_display;
3804     info.user_info          = (long)
3805         "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
3806     fail |= cvmx_error_add(&info);
3807
3808     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3809     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3810     info.status_mask        = 1ull<<13 /* crs_dr */;
3811     info.enable_addr        = CVMX_PEMX_INT_ENB(1);
3812     info.enable_mask        = 1ull<<13 /* crs_dr */;
3813     info.flags              = 0;
3814     info.group              = CVMX_ERROR_GROUP_PCI;
3815     info.group_index        = 1;
3816     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3817     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3818     info.parent.status_mask = 1ull<<26 /* pem1 */;
3819     info.func               = __cvmx_error_display;
3820     info.user_info          = (long)
3821         "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
3822     fail |= cvmx_error_add(&info);
3823
3824     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3825     info.status_addr        = CVMX_PEMX_INT_SUM(1);
3826     info.status_mask        = 0;
3827     info.enable_addr        = 0;
3828     info.enable_mask        = 0;
3829     info.flags              = 0;
3830     info.group              = CVMX_ERROR_GROUP_INTERNAL;
3831     info.group_index        = 0;
3832     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3833     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3834     info.parent.status_mask = 1ull<<26 /* pem1 */;
3835     info.func               = __cvmx_error_decode;
3836     info.user_info          = 0;
3837     fail |= cvmx_error_add(&info);
3838
3839     /* CVMX_PEMX_DBG_INFO(1) */
3840     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3841     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3842     info.status_mask        = 1ull<<0 /* spoison */;
3843     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3844     info.enable_mask        = 1ull<<0 /* spoison */;
3845     info.flags              = 0;
3846     info.group              = CVMX_ERROR_GROUP_PCI;
3847     info.group_index        = 1;
3848     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3849     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3850     info.parent.status_mask = 1ull<<10 /* exc */;
3851     info.func               = __cvmx_error_display;
3852     info.user_info          = (long)
3853         "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
3854         "    peai__client0_tlp_ep & peai__client0_tlp_hv\n";
3855     fail |= cvmx_error_add(&info);
3856
3857     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3858     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3859     info.status_mask        = 1ull<<2 /* rtlplle */;
3860     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3861     info.enable_mask        = 1ull<<2 /* rtlplle */;
3862     info.flags              = 0;
3863     info.group              = CVMX_ERROR_GROUP_PCI;
3864     info.group_index        = 1;
3865     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3866     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3867     info.parent.status_mask = 1ull<<10 /* exc */;
3868     info.func               = __cvmx_error_display;
3869     info.user_info          = (long)
3870         "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
3871         "    pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
3872     fail |= cvmx_error_add(&info);
3873
3874     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3875     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3876     info.status_mask        = 1ull<<3 /* recrce */;
3877     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3878     info.enable_mask        = 1ull<<3 /* recrce */;
3879     info.flags              = 0;
3880     info.group              = CVMX_ERROR_GROUP_PCI;
3881     info.group_index        = 1;
3882     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3883     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3884     info.parent.status_mask = 1ull<<10 /* exc */;
3885     info.func               = __cvmx_error_display;
3886     info.user_info          = (long)
3887         "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
3888         "    pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
3889     fail |= cvmx_error_add(&info);
3890
3891     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3892     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3893     info.status_mask        = 1ull<<4 /* rpoison */;
3894     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3895     info.enable_mask        = 1ull<<4 /* rpoison */;
3896     info.flags              = 0;
3897     info.group              = CVMX_ERROR_GROUP_PCI;
3898     info.group_index        = 1;
3899     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3900     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3901     info.parent.status_mask = 1ull<<10 /* exc */;
3902     info.func               = __cvmx_error_display;
3903     info.user_info          = (long)
3904         "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
3905         "    pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
3906     fail |= cvmx_error_add(&info);
3907
3908     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3909     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3910     info.status_mask        = 1ull<<5 /* rcemrc */;
3911     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3912     info.enable_mask        = 1ull<<5 /* rcemrc */;
3913     info.flags              = 0;
3914     info.group              = CVMX_ERROR_GROUP_PCI;
3915     info.group_index        = 1;
3916     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3917     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3918     info.parent.status_mask = 1ull<<10 /* exc */;
3919     info.func               = __cvmx_error_display;
3920     info.user_info          = (long)
3921         "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
3922         "    pedc_radm_correctable_err\n";
3923     fail |= cvmx_error_add(&info);
3924
3925     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3926     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3927     info.status_mask        = 1ull<<6 /* rnfemrc */;
3928     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3929     info.enable_mask        = 1ull<<6 /* rnfemrc */;
3930     info.flags              = 0;
3931     info.group              = CVMX_ERROR_GROUP_PCI;
3932     info.group_index        = 1;
3933     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3934     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3935     info.parent.status_mask = 1ull<<10 /* exc */;
3936     info.func               = __cvmx_error_display;
3937     info.user_info          = (long)
3938         "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
3939         "    pedc_radm_nonfatal_err\n";
3940     fail |= cvmx_error_add(&info);
3941
3942     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3943     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3944     info.status_mask        = 1ull<<7 /* rfemrc */;
3945     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3946     info.enable_mask        = 1ull<<7 /* rfemrc */;
3947     info.flags              = 0;
3948     info.group              = CVMX_ERROR_GROUP_PCI;
3949     info.group_index        = 1;
3950     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3951     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3952     info.parent.status_mask = 1ull<<10 /* exc */;
3953     info.func               = __cvmx_error_display;
3954     info.user_info          = (long)
3955         "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
3956         "    pedc_radm_fatal_err\n"
3957         "    Bit set when a message with ERR_FATAL is set.\n";
3958     fail |= cvmx_error_add(&info);
3959
3960     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3961     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3962     info.status_mask        = 1ull<<8 /* rpmerc */;
3963     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3964     info.enable_mask        = 1ull<<8 /* rpmerc */;
3965     info.flags              = 0;
3966     info.group              = CVMX_ERROR_GROUP_PCI;
3967     info.group_index        = 1;
3968     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3969     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3970     info.parent.status_mask = 1ull<<10 /* exc */;
3971     info.func               = __cvmx_error_display;
3972     info.user_info          = (long)
3973         "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
3974         "    pedc_radm_pm_pme\n";
3975     fail |= cvmx_error_add(&info);
3976
3977     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3978     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3979     info.status_mask        = 1ull<<9 /* rptamrc */;
3980     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3981     info.enable_mask        = 1ull<<9 /* rptamrc */;
3982     info.flags              = 0;
3983     info.group              = CVMX_ERROR_GROUP_PCI;
3984     info.group_index        = 1;
3985     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
3986     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3987     info.parent.status_mask = 1ull<<10 /* exc */;
3988     info.func               = __cvmx_error_display;
3989     info.user_info          = (long)
3990         "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3991         "    (RC Mode only)\n"
3992         "    pedc_radm_pm_to_ack\n";
3993     fail |= cvmx_error_add(&info);
3994
3995     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
3996     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
3997     info.status_mask        = 1ull<<10 /* rumep */;
3998     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
3999     info.enable_mask        = 1ull<<10 /* rumep */;
4000     info.flags              = 0;
4001     info.group              = CVMX_ERROR_GROUP_PCI;
4002     info.group_index        = 1;
4003     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4004     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4005     info.parent.status_mask = 1ull<<10 /* exc */;
4006     info.func               = __cvmx_error_display;
4007     info.user_info          = (long)
4008         "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
4009         "    pedc_radm_msg_unlock\n";
4010     fail |= cvmx_error_add(&info);
4011
4012     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4013     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4014     info.status_mask        = 1ull<<11 /* rvdm */;
4015     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4016     info.enable_mask        = 1ull<<11 /* rvdm */;
4017     info.flags              = 0;
4018     info.group              = CVMX_ERROR_GROUP_PCI;
4019     info.group_index        = 1;
4020     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4021     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4022     info.parent.status_mask = 1ull<<10 /* exc */;
4023     info.func               = __cvmx_error_display;
4024     info.user_info          = (long)
4025         "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
4026         "    pedc_radm_vendor_msg\n";
4027     fail |= cvmx_error_add(&info);
4028
4029     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4030     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4031     info.status_mask        = 1ull<<12 /* acto */;
4032     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4033     info.enable_mask        = 1ull<<12 /* acto */;
4034     info.flags              = 0;
4035     info.group              = CVMX_ERROR_GROUP_PCI;
4036     info.group_index        = 1;
4037     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4038     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4039     info.parent.status_mask = 1ull<<10 /* exc */;
4040     info.func               = __cvmx_error_display;
4041     info.user_info          = (long)
4042         "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
4043         "    pedc_radm_cpl_timeout\n";
4044     fail |= cvmx_error_add(&info);
4045
4046     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4047     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4048     info.status_mask        = 1ull<<13 /* rte */;
4049     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4050     info.enable_mask        = 1ull<<13 /* rte */;
4051     info.flags              = 0;
4052     info.group              = CVMX_ERROR_GROUP_PCI;
4053     info.group_index        = 1;
4054     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4055     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4056     info.parent.status_mask = 1ull<<10 /* exc */;
4057     info.func               = __cvmx_error_display;
4058     info.user_info          = (long)
4059         "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
4060         "    xdlh_replay_timeout_err\n"
4061         "    This bit is set when the REPLAY_TIMER expires in\n"
4062         "    the PCIE core. The probability of this bit being\n"
4063         "    set will increase with the traffic load.\n";
4064     fail |= cvmx_error_add(&info);
4065
4066     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4067     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4068     info.status_mask        = 1ull<<14 /* mre */;
4069     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4070     info.enable_mask        = 1ull<<14 /* mre */;
4071     info.flags              = 0;
4072     info.group              = CVMX_ERROR_GROUP_PCI;
4073     info.group_index        = 1;
4074     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4075     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4076     info.parent.status_mask = 1ull<<10 /* exc */;
4077     info.func               = __cvmx_error_display;
4078     info.user_info          = (long)
4079         "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
4080         "    xdlh_replay_num_rlover_err\n";
4081     fail |= cvmx_error_add(&info);
4082
4083     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4084     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4085     info.status_mask        = 1ull<<15 /* rdwdle */;
4086     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4087     info.enable_mask        = 1ull<<15 /* rdwdle */;
4088     info.flags              = 0;
4089     info.group              = CVMX_ERROR_GROUP_PCI;
4090     info.group_index        = 1;
4091     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4092     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4093     info.parent.status_mask = 1ull<<10 /* exc */;
4094     info.func               = __cvmx_error_display;
4095     info.user_info          = (long)
4096         "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
4097         "    rdlh_bad_dllp_err\n";
4098     fail |= cvmx_error_add(&info);
4099
4100     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4101     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4102     info.status_mask        = 1ull<<16 /* rtwdle */;
4103     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4104     info.enable_mask        = 1ull<<16 /* rtwdle */;
4105     info.flags              = 0;
4106     info.group              = CVMX_ERROR_GROUP_PCI;
4107     info.group_index        = 1;
4108     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4109     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4110     info.parent.status_mask = 1ull<<10 /* exc */;
4111     info.func               = __cvmx_error_display;
4112     info.user_info          = (long)
4113         "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
4114         "    rdlh_bad_tlp_err\n";
4115     fail |= cvmx_error_add(&info);
4116
4117     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4118     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4119     info.status_mask        = 1ull<<17 /* dpeoosd */;
4120     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4121     info.enable_mask        = 1ull<<17 /* dpeoosd */;
4122     info.flags              = 0;
4123     info.group              = CVMX_ERROR_GROUP_PCI;
4124     info.group_index        = 1;
4125     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4126     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4127     info.parent.status_mask = 1ull<<10 /* exc */;
4128     info.func               = __cvmx_error_display;
4129     info.user_info          = (long)
4130         "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
4131         "    rdlh_prot_err\n";
4132     fail |= cvmx_error_add(&info);
4133
4134     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4135     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4136     info.status_mask        = 1ull<<18 /* fcpvwt */;
4137     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4138     info.enable_mask        = 1ull<<18 /* fcpvwt */;
4139     info.flags              = 0;
4140     info.group              = CVMX_ERROR_GROUP_PCI;
4141     info.group_index        = 1;
4142     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4143     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4144     info.parent.status_mask = 1ull<<10 /* exc */;
4145     info.func               = __cvmx_error_display;
4146     info.user_info          = (long)
4147         "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
4148         "    rtlh_fc_prot_err\n";
4149     fail |= cvmx_error_add(&info);
4150
4151     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4152     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4153     info.status_mask        = 1ull<<19 /* rpe */;
4154     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4155     info.enable_mask        = 1ull<<19 /* rpe */;
4156     info.flags              = 0;
4157     info.group              = CVMX_ERROR_GROUP_PCI;
4158     info.group_index        = 1;
4159     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4160     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4161     info.parent.status_mask = 1ull<<10 /* exc */;
4162     info.func               = __cvmx_error_display;
4163     info.user_info          = (long)
4164         "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
4165         "    (RxStatus = 3b100) or disparity error\n"
4166         "    (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
4167         "    be asserted.\n"
4168         "    rmlh_rcvd_err\n";
4169     fail |= cvmx_error_add(&info);
4170
4171     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4172     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4173     info.status_mask        = 1ull<<20 /* fcuv */;
4174     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4175     info.enable_mask        = 1ull<<20 /* fcuv */;
4176     info.flags              = 0;
4177     info.group              = CVMX_ERROR_GROUP_PCI;
4178     info.group_index        = 1;
4179     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4180     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4181     info.parent.status_mask = 1ull<<10 /* exc */;
4182     info.func               = __cvmx_error_display;
4183     info.user_info          = (long)
4184         "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
4185         "    int_xadm_fc_prot_err\n";
4186     fail |= cvmx_error_add(&info);
4187
4188     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4189     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4190     info.status_mask        = 1ull<<21 /* rqo */;
4191     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4192     info.enable_mask        = 1ull<<21 /* rqo */;
4193     info.flags              = 0;
4194     info.group              = CVMX_ERROR_GROUP_PCI;
4195     info.group_index        = 1;
4196     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4197     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4198     info.parent.status_mask = 1ull<<10 /* exc */;
4199     info.func               = __cvmx_error_display;
4200     info.user_info          = (long)
4201         "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
4202         "    flow control advertisements are ignored\n"
4203         "    radm_qoverflow\n";
4204     fail |= cvmx_error_add(&info);
4205
4206     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4207     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4208     info.status_mask        = 1ull<<22 /* rauc */;
4209     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4210     info.enable_mask        = 1ull<<22 /* rauc */;
4211     info.flags              = 0;
4212     info.group              = CVMX_ERROR_GROUP_PCI;
4213     info.group_index        = 1;
4214     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4215     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4216     info.parent.status_mask = 1ull<<10 /* exc */;
4217     info.func               = __cvmx_error_display;
4218     info.user_info          = (long)
4219         "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
4220         "    radm_unexp_cpl_err\n";
4221     fail |= cvmx_error_add(&info);
4222
4223     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4224     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4225     info.status_mask        = 1ull<<23 /* racur */;
4226     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4227     info.enable_mask        = 1ull<<23 /* racur */;
4228     info.flags              = 0;
4229     info.group              = CVMX_ERROR_GROUP_PCI;
4230     info.group_index        = 1;
4231     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4232     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4233     info.parent.status_mask = 1ull<<10 /* exc */;
4234     info.func               = __cvmx_error_display;
4235     info.user_info          = (long)
4236         "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
4237         "    radm_rcvd_cpl_ur\n";
4238     fail |= cvmx_error_add(&info);
4239
4240     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4241     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4242     info.status_mask        = 1ull<<24 /* racca */;
4243     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4244     info.enable_mask        = 1ull<<24 /* racca */;
4245     info.flags              = 0;
4246     info.group              = CVMX_ERROR_GROUP_PCI;
4247     info.group_index        = 1;
4248     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4249     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4250     info.parent.status_mask = 1ull<<10 /* exc */;
4251     info.func               = __cvmx_error_display;
4252     info.user_info          = (long)
4253         "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
4254         "    radm_rcvd_cpl_ca\n";
4255     fail |= cvmx_error_add(&info);
4256
4257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4258     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4259     info.status_mask        = 1ull<<25 /* caar */;
4260     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4261     info.enable_mask        = 1ull<<25 /* caar */;
4262     info.flags              = 0;
4263     info.group              = CVMX_ERROR_GROUP_PCI;
4264     info.group_index        = 1;
4265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4266     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4267     info.parent.status_mask = 1ull<<10 /* exc */;
4268     info.func               = __cvmx_error_display;
4269     info.user_info          = (long)
4270         "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
4271         "    radm_rcvd_ca_req\n"
4272         "    This bit will never be set because Octeon does\n"
4273         "    not generate Completer Aborts.\n";
4274     fail |= cvmx_error_add(&info);
4275
4276     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4277     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4278     info.status_mask        = 1ull<<26 /* rarwdns */;
4279     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4280     info.enable_mask        = 1ull<<26 /* rarwdns */;
4281     info.flags              = 0;
4282     info.group              = CVMX_ERROR_GROUP_PCI;
4283     info.group_index        = 1;
4284     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4285     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4286     info.parent.status_mask = 1ull<<10 /* exc */;
4287     info.func               = __cvmx_error_display;
4288     info.user_info          = (long)
4289         "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
4290         "    radm_rcvd_ur_req\n";
4291     fail |= cvmx_error_add(&info);
4292
4293     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4294     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4295     info.status_mask        = 1ull<<27 /* ramtlp */;
4296     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4297     info.enable_mask        = 1ull<<27 /* ramtlp */;
4298     info.flags              = 0;
4299     info.group              = CVMX_ERROR_GROUP_PCI;
4300     info.group_index        = 1;
4301     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4302     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4303     info.parent.status_mask = 1ull<<10 /* exc */;
4304     info.func               = __cvmx_error_display;
4305     info.user_info          = (long)
4306         "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
4307         "    radm_mlf_tlp_err\n";
4308     fail |= cvmx_error_add(&info);
4309
4310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4311     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4312     info.status_mask        = 1ull<<28 /* racpp */;
4313     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4314     info.enable_mask        = 1ull<<28 /* racpp */;
4315     info.flags              = 0;
4316     info.group              = CVMX_ERROR_GROUP_PCI;
4317     info.group_index        = 1;
4318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4319     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4320     info.parent.status_mask = 1ull<<10 /* exc */;
4321     info.func               = __cvmx_error_display;
4322     info.user_info          = (long)
4323         "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
4324         "    radm_rcvd_cpl_poisoned\n";
4325     fail |= cvmx_error_add(&info);
4326
4327     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4328     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4329     info.status_mask        = 1ull<<29 /* rawwpp */;
4330     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4331     info.enable_mask        = 1ull<<29 /* rawwpp */;
4332     info.flags              = 0;
4333     info.group              = CVMX_ERROR_GROUP_PCI;
4334     info.group_index        = 1;
4335     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4336     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4337     info.parent.status_mask = 1ull<<10 /* exc */;
4338     info.func               = __cvmx_error_display;
4339     info.user_info          = (long)
4340         "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
4341         "    radm_rcvd_wreq_poisoned\n";
4342     fail |= cvmx_error_add(&info);
4343
4344     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4345     info.status_addr        = CVMX_PEMX_DBG_INFO(1);
4346     info.status_mask        = 1ull<<30 /* ecrc_e */;
4347     info.enable_addr        = CVMX_PEMX_DBG_INFO_EN(1);
4348     info.enable_mask        = 1ull<<30 /* ecrc_e */;
4349     info.flags              = 0;
4350     info.group              = CVMX_ERROR_GROUP_PCI;
4351     info.group_index        = 1;
4352     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4353     info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
4354     info.parent.status_mask = 1ull<<10 /* exc */;
4355     info.func               = __cvmx_error_display;
4356     info.user_info          = (long)
4357         "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
4358         "    radm_ecrc_err\n";
4359     fail |= cvmx_error_add(&info);
4360
4361     /* CVMX_FPA_INT_SUM */
4362     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4363     info.status_addr        = CVMX_FPA_INT_SUM;
4364     info.status_mask        = 1ull<<0 /* fed0_sbe */;
4365     info.enable_addr        = CVMX_FPA_INT_ENB;
4366     info.enable_mask        = 1ull<<0 /* fed0_sbe */;
4367     info.flags              = 0;
4368     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4369     info.group_index        = 0;
4370     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4371     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4372     info.parent.status_mask = 1ull<<5 /* fpa */;
4373     info.func               = __cvmx_error_display;
4374     info.user_info          = (long)
4375         "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
4376     fail |= cvmx_error_add(&info);
4377
4378     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4379     info.status_addr        = CVMX_FPA_INT_SUM;
4380     info.status_mask        = 1ull<<1 /* fed0_dbe */;
4381     info.enable_addr        = CVMX_FPA_INT_ENB;
4382     info.enable_mask        = 1ull<<1 /* fed0_dbe */;
4383     info.flags              = 0;
4384     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4385     info.group_index        = 0;
4386     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4387     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4388     info.parent.status_mask = 1ull<<5 /* fpa */;
4389     info.func               = __cvmx_error_display;
4390     info.user_info          = (long)
4391         "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
4392     fail |= cvmx_error_add(&info);
4393
4394     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4395     info.status_addr        = CVMX_FPA_INT_SUM;
4396     info.status_mask        = 1ull<<2 /* fed1_sbe */;
4397     info.enable_addr        = CVMX_FPA_INT_ENB;
4398     info.enable_mask        = 1ull<<2 /* fed1_sbe */;
4399     info.flags              = 0;
4400     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4401     info.group_index        = 0;
4402     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4403     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4404     info.parent.status_mask = 1ull<<5 /* fpa */;
4405     info.func               = __cvmx_error_display;
4406     info.user_info          = (long)
4407         "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
4408     fail |= cvmx_error_add(&info);
4409
4410     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4411     info.status_addr        = CVMX_FPA_INT_SUM;
4412     info.status_mask        = 1ull<<3 /* fed1_dbe */;
4413     info.enable_addr        = CVMX_FPA_INT_ENB;
4414     info.enable_mask        = 1ull<<3 /* fed1_dbe */;
4415     info.flags              = 0;
4416     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4417     info.group_index        = 0;
4418     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4419     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4420     info.parent.status_mask = 1ull<<5 /* fpa */;
4421     info.func               = __cvmx_error_display;
4422     info.user_info          = (long)
4423         "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
4424     fail |= cvmx_error_add(&info);
4425
4426     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4427     info.status_addr        = CVMX_FPA_INT_SUM;
4428     info.status_mask        = 1ull<<4 /* q0_und */;
4429     info.enable_addr        = CVMX_FPA_INT_ENB;
4430     info.enable_mask        = 1ull<<4 /* q0_und */;
4431     info.flags              = 0;
4432     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4433     info.group_index        = 0;
4434     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4435     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4436     info.parent.status_mask = 1ull<<5 /* fpa */;
4437     info.func               = __cvmx_error_display;
4438     info.user_info          = (long)
4439         "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
4440         "    negative.\n";
4441     fail |= cvmx_error_add(&info);
4442
4443     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4444     info.status_addr        = CVMX_FPA_INT_SUM;
4445     info.status_mask        = 1ull<<5 /* q0_coff */;
4446     info.enable_addr        = CVMX_FPA_INT_ENB;
4447     info.enable_mask        = 1ull<<5 /* q0_coff */;
4448     info.flags              = 0;
4449     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4450     info.group_index        = 0;
4451     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4452     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4453     info.parent.status_mask = 1ull<<5 /* fpa */;
4454     info.func               = __cvmx_error_display;
4455     info.user_info          = (long)
4456         "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
4457         "    the count available is greater than pointers\n"
4458         "    present in the FPA.\n";
4459     fail |= cvmx_error_add(&info);
4460
4461     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4462     info.status_addr        = CVMX_FPA_INT_SUM;
4463     info.status_mask        = 1ull<<6 /* q0_perr */;
4464     info.enable_addr        = CVMX_FPA_INT_ENB;
4465     info.enable_mask        = 1ull<<6 /* q0_perr */;
4466     info.flags              = 0;
4467     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4468     info.group_index        = 0;
4469     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4470     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4471     info.parent.status_mask = 1ull<<5 /* fpa */;
4472     info.func               = __cvmx_error_display;
4473     info.user_info          = (long)
4474         "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
4475         "    the L2C does not have the FPA owner ship bit set.\n";
4476     fail |= cvmx_error_add(&info);
4477
4478     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4479     info.status_addr        = CVMX_FPA_INT_SUM;
4480     info.status_mask        = 1ull<<7 /* q1_und */;
4481     info.enable_addr        = CVMX_FPA_INT_ENB;
4482     info.enable_mask        = 1ull<<7 /* q1_und */;
4483     info.flags              = 0;
4484     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4485     info.group_index        = 0;
4486     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4487     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4488     info.parent.status_mask = 1ull<<5 /* fpa */;
4489     info.func               = __cvmx_error_display;
4490     info.user_info          = (long)
4491         "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
4492         "    negative.\n";
4493     fail |= cvmx_error_add(&info);
4494
4495     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4496     info.status_addr        = CVMX_FPA_INT_SUM;
4497     info.status_mask        = 1ull<<8 /* q1_coff */;
4498     info.enable_addr        = CVMX_FPA_INT_ENB;
4499     info.enable_mask        = 1ull<<8 /* q1_coff */;
4500     info.flags              = 0;
4501     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4502     info.group_index        = 0;
4503     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4504     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4505     info.parent.status_mask = 1ull<<5 /* fpa */;
4506     info.func               = __cvmx_error_display;
4507     info.user_info          = (long)
4508         "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
4509         "    the count available is greater than pointers\n"
4510         "    present in the FPA.\n";
4511     fail |= cvmx_error_add(&info);
4512
4513     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4514     info.status_addr        = CVMX_FPA_INT_SUM;
4515     info.status_mask        = 1ull<<9 /* q1_perr */;
4516     info.enable_addr        = CVMX_FPA_INT_ENB;
4517     info.enable_mask        = 1ull<<9 /* q1_perr */;
4518     info.flags              = 0;
4519     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4520     info.group_index        = 0;
4521     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4522     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4523     info.parent.status_mask = 1ull<<5 /* fpa */;
4524     info.func               = __cvmx_error_display;
4525     info.user_info          = (long)
4526         "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
4527         "    the L2C does not have the FPA owner ship bit set.\n";
4528     fail |= cvmx_error_add(&info);
4529
4530     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4531     info.status_addr        = CVMX_FPA_INT_SUM;
4532     info.status_mask        = 1ull<<10 /* q2_und */;
4533     info.enable_addr        = CVMX_FPA_INT_ENB;
4534     info.enable_mask        = 1ull<<10 /* q2_und */;
4535     info.flags              = 0;
4536     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4537     info.group_index        = 0;
4538     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4539     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4540     info.parent.status_mask = 1ull<<5 /* fpa */;
4541     info.func               = __cvmx_error_display;
4542     info.user_info          = (long)
4543         "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
4544         "    negative.\n";
4545     fail |= cvmx_error_add(&info);
4546
4547     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4548     info.status_addr        = CVMX_FPA_INT_SUM;
4549     info.status_mask        = 1ull<<11 /* q2_coff */;
4550     info.enable_addr        = CVMX_FPA_INT_ENB;
4551     info.enable_mask        = 1ull<<11 /* q2_coff */;
4552     info.flags              = 0;
4553     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4554     info.group_index        = 0;
4555     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4556     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4557     info.parent.status_mask = 1ull<<5 /* fpa */;
4558     info.func               = __cvmx_error_display;
4559     info.user_info          = (long)
4560         "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
4561         "    the count available is greater than than pointers\n"
4562         "    present in the FPA.\n";
4563     fail |= cvmx_error_add(&info);
4564
4565     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4566     info.status_addr        = CVMX_FPA_INT_SUM;
4567     info.status_mask        = 1ull<<12 /* q2_perr */;
4568     info.enable_addr        = CVMX_FPA_INT_ENB;
4569     info.enable_mask        = 1ull<<12 /* q2_perr */;
4570     info.flags              = 0;
4571     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4572     info.group_index        = 0;
4573     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4574     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4575     info.parent.status_mask = 1ull<<5 /* fpa */;
4576     info.func               = __cvmx_error_display;
4577     info.user_info          = (long)
4578         "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
4579         "    the L2C does not have the FPA owner ship bit set.\n";
4580     fail |= cvmx_error_add(&info);
4581
4582     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4583     info.status_addr        = CVMX_FPA_INT_SUM;
4584     info.status_mask        = 1ull<<13 /* q3_und */;
4585     info.enable_addr        = CVMX_FPA_INT_ENB;
4586     info.enable_mask        = 1ull<<13 /* q3_und */;
4587     info.flags              = 0;
4588     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4589     info.group_index        = 0;
4590     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4591     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4592     info.parent.status_mask = 1ull<<5 /* fpa */;
4593     info.func               = __cvmx_error_display;
4594     info.user_info          = (long)
4595         "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
4596         "    negative.\n";
4597     fail |= cvmx_error_add(&info);
4598
4599     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4600     info.status_addr        = CVMX_FPA_INT_SUM;
4601     info.status_mask        = 1ull<<14 /* q3_coff */;
4602     info.enable_addr        = CVMX_FPA_INT_ENB;
4603     info.enable_mask        = 1ull<<14 /* q3_coff */;
4604     info.flags              = 0;
4605     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4606     info.group_index        = 0;
4607     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4608     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4609     info.parent.status_mask = 1ull<<5 /* fpa */;
4610     info.func               = __cvmx_error_display;
4611     info.user_info          = (long)
4612         "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
4613         "    the count available is greater than than pointers\n"
4614         "    present in the FPA.\n";
4615     fail |= cvmx_error_add(&info);
4616
4617     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4618     info.status_addr        = CVMX_FPA_INT_SUM;
4619     info.status_mask        = 1ull<<15 /* q3_perr */;
4620     info.enable_addr        = CVMX_FPA_INT_ENB;
4621     info.enable_mask        = 1ull<<15 /* q3_perr */;
4622     info.flags              = 0;
4623     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4624     info.group_index        = 0;
4625     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4626     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4627     info.parent.status_mask = 1ull<<5 /* fpa */;
4628     info.func               = __cvmx_error_display;
4629     info.user_info          = (long)
4630         "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
4631         "    the L2C does not have the FPA owner ship bit set.\n";
4632     fail |= cvmx_error_add(&info);
4633
4634     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4635     info.status_addr        = CVMX_FPA_INT_SUM;
4636     info.status_mask        = 1ull<<16 /* q4_und */;
4637     info.enable_addr        = CVMX_FPA_INT_ENB;
4638     info.enable_mask        = 1ull<<16 /* q4_und */;
4639     info.flags              = 0;
4640     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4641     info.group_index        = 0;
4642     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4643     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4644     info.parent.status_mask = 1ull<<5 /* fpa */;
4645     info.func               = __cvmx_error_display;
4646     info.user_info          = (long)
4647         "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
4648         "    negative.\n";
4649     fail |= cvmx_error_add(&info);
4650
4651     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4652     info.status_addr        = CVMX_FPA_INT_SUM;
4653     info.status_mask        = 1ull<<17 /* q4_coff */;
4654     info.enable_addr        = CVMX_FPA_INT_ENB;
4655     info.enable_mask        = 1ull<<17 /* q4_coff */;
4656     info.flags              = 0;
4657     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4658     info.group_index        = 0;
4659     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4660     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4661     info.parent.status_mask = 1ull<<5 /* fpa */;
4662     info.func               = __cvmx_error_display;
4663     info.user_info          = (long)
4664         "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
4665         "    the count available is greater than than pointers\n"
4666         "    present in the FPA.\n";
4667     fail |= cvmx_error_add(&info);
4668
4669     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4670     info.status_addr        = CVMX_FPA_INT_SUM;
4671     info.status_mask        = 1ull<<18 /* q4_perr */;
4672     info.enable_addr        = CVMX_FPA_INT_ENB;
4673     info.enable_mask        = 1ull<<18 /* q4_perr */;
4674     info.flags              = 0;
4675     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4676     info.group_index        = 0;
4677     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4678     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4679     info.parent.status_mask = 1ull<<5 /* fpa */;
4680     info.func               = __cvmx_error_display;
4681     info.user_info          = (long)
4682         "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
4683         "    the L2C does not have the FPA owner ship bit set.\n";
4684     fail |= cvmx_error_add(&info);
4685
4686     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4687     info.status_addr        = CVMX_FPA_INT_SUM;
4688     info.status_mask        = 1ull<<19 /* q5_und */;
4689     info.enable_addr        = CVMX_FPA_INT_ENB;
4690     info.enable_mask        = 1ull<<19 /* q5_und */;
4691     info.flags              = 0;
4692     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4693     info.group_index        = 0;
4694     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4695     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4696     info.parent.status_mask = 1ull<<5 /* fpa */;
4697     info.func               = __cvmx_error_display;
4698     info.user_info          = (long)
4699         "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
4700         "    negative.\n";
4701     fail |= cvmx_error_add(&info);
4702
4703     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4704     info.status_addr        = CVMX_FPA_INT_SUM;
4705     info.status_mask        = 1ull<<20 /* q5_coff */;
4706     info.enable_addr        = CVMX_FPA_INT_ENB;
4707     info.enable_mask        = 1ull<<20 /* q5_coff */;
4708     info.flags              = 0;
4709     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4710     info.group_index        = 0;
4711     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4712     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4713     info.parent.status_mask = 1ull<<5 /* fpa */;
4714     info.func               = __cvmx_error_display;
4715     info.user_info          = (long)
4716         "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
4717         "    the count available is greater than than pointers\n"
4718         "    present in the FPA.\n";
4719     fail |= cvmx_error_add(&info);
4720
4721     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4722     info.status_addr        = CVMX_FPA_INT_SUM;
4723     info.status_mask        = 1ull<<21 /* q5_perr */;
4724     info.enable_addr        = CVMX_FPA_INT_ENB;
4725     info.enable_mask        = 1ull<<21 /* q5_perr */;
4726     info.flags              = 0;
4727     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4728     info.group_index        = 0;
4729     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4730     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4731     info.parent.status_mask = 1ull<<5 /* fpa */;
4732     info.func               = __cvmx_error_display;
4733     info.user_info          = (long)
4734         "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
4735         "    the L2C does not have the FPA owner ship bit set.\n";
4736     fail |= cvmx_error_add(&info);
4737
4738     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4739     info.status_addr        = CVMX_FPA_INT_SUM;
4740     info.status_mask        = 1ull<<22 /* q6_und */;
4741     info.enable_addr        = CVMX_FPA_INT_ENB;
4742     info.enable_mask        = 1ull<<22 /* q6_und */;
4743     info.flags              = 0;
4744     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4745     info.group_index        = 0;
4746     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4747     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4748     info.parent.status_mask = 1ull<<5 /* fpa */;
4749     info.func               = __cvmx_error_display;
4750     info.user_info          = (long)
4751         "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
4752         "    negative.\n";
4753     fail |= cvmx_error_add(&info);
4754
4755     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4756     info.status_addr        = CVMX_FPA_INT_SUM;
4757     info.status_mask        = 1ull<<23 /* q6_coff */;
4758     info.enable_addr        = CVMX_FPA_INT_ENB;
4759     info.enable_mask        = 1ull<<23 /* q6_coff */;
4760     info.flags              = 0;
4761     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4762     info.group_index        = 0;
4763     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4764     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4765     info.parent.status_mask = 1ull<<5 /* fpa */;
4766     info.func               = __cvmx_error_display;
4767     info.user_info          = (long)
4768         "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
4769         "    the count available is greater than than pointers\n"
4770         "    present in the FPA.\n";
4771     fail |= cvmx_error_add(&info);
4772
4773     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4774     info.status_addr        = CVMX_FPA_INT_SUM;
4775     info.status_mask        = 1ull<<24 /* q6_perr */;
4776     info.enable_addr        = CVMX_FPA_INT_ENB;
4777     info.enable_mask        = 1ull<<24 /* q6_perr */;
4778     info.flags              = 0;
4779     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4780     info.group_index        = 0;
4781     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4782     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4783     info.parent.status_mask = 1ull<<5 /* fpa */;
4784     info.func               = __cvmx_error_display;
4785     info.user_info          = (long)
4786         "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
4787         "    the L2C does not have the FPA owner ship bit set.\n";
4788     fail |= cvmx_error_add(&info);
4789
4790     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4791     info.status_addr        = CVMX_FPA_INT_SUM;
4792     info.status_mask        = 1ull<<25 /* q7_und */;
4793     info.enable_addr        = CVMX_FPA_INT_ENB;
4794     info.enable_mask        = 1ull<<25 /* q7_und */;
4795     info.flags              = 0;
4796     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4797     info.group_index        = 0;
4798     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4799     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4800     info.parent.status_mask = 1ull<<5 /* fpa */;
4801     info.func               = __cvmx_error_display;
4802     info.user_info          = (long)
4803         "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
4804         "    negative.\n";
4805     fail |= cvmx_error_add(&info);
4806
4807     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4808     info.status_addr        = CVMX_FPA_INT_SUM;
4809     info.status_mask        = 1ull<<26 /* q7_coff */;
4810     info.enable_addr        = CVMX_FPA_INT_ENB;
4811     info.enable_mask        = 1ull<<26 /* q7_coff */;
4812     info.flags              = 0;
4813     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4814     info.group_index        = 0;
4815     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4816     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4817     info.parent.status_mask = 1ull<<5 /* fpa */;
4818     info.func               = __cvmx_error_display;
4819     info.user_info          = (long)
4820         "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
4821         "    the count available is greater than than pointers\n"
4822         "    present in the FPA.\n";
4823     fail |= cvmx_error_add(&info);
4824
4825     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4826     info.status_addr        = CVMX_FPA_INT_SUM;
4827     info.status_mask        = 1ull<<27 /* q7_perr */;
4828     info.enable_addr        = CVMX_FPA_INT_ENB;
4829     info.enable_mask        = 1ull<<27 /* q7_perr */;
4830     info.flags              = 0;
4831     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4832     info.group_index        = 0;
4833     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4834     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4835     info.parent.status_mask = 1ull<<5 /* fpa */;
4836     info.func               = __cvmx_error_display;
4837     info.user_info          = (long)
4838         "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
4839         "    the L2C does not have the FPA owner ship bit set.\n";
4840     fail |= cvmx_error_add(&info);
4841
4842     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4843     info.status_addr        = CVMX_FPA_INT_SUM;
4844     info.status_mask        = 1ull<<28 /* pool0th */;
4845     info.enable_addr        = CVMX_FPA_INT_ENB;
4846     info.enable_mask        = 1ull<<28 /* pool0th */;
4847     info.flags              = 0;
4848     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4849     info.group_index        = 0;
4850     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4851     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4852     info.parent.status_mask = 1ull<<5 /* fpa */;
4853     info.func               = __cvmx_error_display;
4854     info.user_info          = (long)
4855         "ERROR FPA_INT_SUM[POOL0TH]: Set when FPA_QUE0_AVAILABLE is equal to\n"
4856         "    FPA_POOL`_THRESHOLD[THRESH] and a pointer is\n"
4857         "    allocated or de-allocated.\n";
4858     fail |= cvmx_error_add(&info);
4859
4860     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4861     info.status_addr        = CVMX_FPA_INT_SUM;
4862     info.status_mask        = 1ull<<29 /* pool1th */;
4863     info.enable_addr        = CVMX_FPA_INT_ENB;
4864     info.enable_mask        = 1ull<<29 /* pool1th */;
4865     info.flags              = 0;
4866     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4867     info.group_index        = 0;
4868     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4869     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4870     info.parent.status_mask = 1ull<<5 /* fpa */;
4871     info.func               = __cvmx_error_display;
4872     info.user_info          = (long)
4873         "ERROR FPA_INT_SUM[POOL1TH]: Set when FPA_QUE1_AVAILABLE is equal to\n"
4874         "    FPA_POOL1_THRESHOLD[THRESH] and a pointer is\n"
4875         "    allocated or de-allocated.\n";
4876     fail |= cvmx_error_add(&info);
4877
4878     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4879     info.status_addr        = CVMX_FPA_INT_SUM;
4880     info.status_mask        = 1ull<<30 /* pool2th */;
4881     info.enable_addr        = CVMX_FPA_INT_ENB;
4882     info.enable_mask        = 1ull<<30 /* pool2th */;
4883     info.flags              = 0;
4884     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4885     info.group_index        = 0;
4886     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4887     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4888     info.parent.status_mask = 1ull<<5 /* fpa */;
4889     info.func               = __cvmx_error_display;
4890     info.user_info          = (long)
4891         "ERROR FPA_INT_SUM[POOL2TH]: Set when FPA_QUE2_AVAILABLE is equal to\n"
4892         "    FPA_POOL2_THRESHOLD[THRESH] and a pointer is\n"
4893         "    allocated or de-allocated.\n";
4894     fail |= cvmx_error_add(&info);
4895
4896     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4897     info.status_addr        = CVMX_FPA_INT_SUM;
4898     info.status_mask        = 1ull<<31 /* pool3th */;
4899     info.enable_addr        = CVMX_FPA_INT_ENB;
4900     info.enable_mask        = 1ull<<31 /* pool3th */;
4901     info.flags              = 0;
4902     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4903     info.group_index        = 0;
4904     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4905     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4906     info.parent.status_mask = 1ull<<5 /* fpa */;
4907     info.func               = __cvmx_error_display;
4908     info.user_info          = (long)
4909         "ERROR FPA_INT_SUM[POOL3TH]: Set when FPA_QUE3_AVAILABLE is equal to\n"
4910         "    FPA_POOL3_THRESHOLD[THRESH] and a pointer is\n"
4911         "    allocated or de-allocated.\n";
4912     fail |= cvmx_error_add(&info);
4913
4914     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4915     info.status_addr        = CVMX_FPA_INT_SUM;
4916     info.status_mask        = 1ull<<32 /* pool4th */;
4917     info.enable_addr        = CVMX_FPA_INT_ENB;
4918     info.enable_mask        = 1ull<<32 /* pool4th */;
4919     info.flags              = 0;
4920     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4921     info.group_index        = 0;
4922     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4923     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4924     info.parent.status_mask = 1ull<<5 /* fpa */;
4925     info.func               = __cvmx_error_display;
4926     info.user_info          = (long)
4927         "ERROR FPA_INT_SUM[POOL4TH]: Set when FPA_QUE4_AVAILABLE is equal to\n"
4928         "    FPA_POOL4_THRESHOLD[THRESH] and a pointer is\n"
4929         "    allocated or de-allocated.\n";
4930     fail |= cvmx_error_add(&info);
4931
4932     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4933     info.status_addr        = CVMX_FPA_INT_SUM;
4934     info.status_mask        = 1ull<<33 /* pool5th */;
4935     info.enable_addr        = CVMX_FPA_INT_ENB;
4936     info.enable_mask        = 1ull<<33 /* pool5th */;
4937     info.flags              = 0;
4938     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4939     info.group_index        = 0;
4940     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4941     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4942     info.parent.status_mask = 1ull<<5 /* fpa */;
4943     info.func               = __cvmx_error_display;
4944     info.user_info          = (long)
4945         "ERROR FPA_INT_SUM[POOL5TH]: Set when FPA_QUE5_AVAILABLE is equal to\n"
4946         "    FPA_POOL5_THRESHOLD[THRESH] and a pointer is\n"
4947         "    allocated or de-allocated.\n";
4948     fail |= cvmx_error_add(&info);
4949
4950     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4951     info.status_addr        = CVMX_FPA_INT_SUM;
4952     info.status_mask        = 1ull<<34 /* pool6th */;
4953     info.enable_addr        = CVMX_FPA_INT_ENB;
4954     info.enable_mask        = 1ull<<34 /* pool6th */;
4955     info.flags              = 0;
4956     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4957     info.group_index        = 0;
4958     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4959     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4960     info.parent.status_mask = 1ull<<5 /* fpa */;
4961     info.func               = __cvmx_error_display;
4962     info.user_info          = (long)
4963         "ERROR FPA_INT_SUM[POOL6TH]: Set when FPA_QUE6_AVAILABLE is equal to\n"
4964         "    FPA_POOL6_THRESHOLD[THRESH] and a pointer is\n"
4965         "    allocated or de-allocated.\n";
4966     fail |= cvmx_error_add(&info);
4967
4968     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4969     info.status_addr        = CVMX_FPA_INT_SUM;
4970     info.status_mask        = 1ull<<35 /* pool7th */;
4971     info.enable_addr        = CVMX_FPA_INT_ENB;
4972     info.enable_mask        = 1ull<<35 /* pool7th */;
4973     info.flags              = 0;
4974     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4975     info.group_index        = 0;
4976     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4977     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4978     info.parent.status_mask = 1ull<<5 /* fpa */;
4979     info.func               = __cvmx_error_display;
4980     info.user_info          = (long)
4981         "ERROR FPA_INT_SUM[POOL7TH]: Set when FPA_QUE7_AVAILABLE is equal to\n"
4982         "    FPA_POOL7_THRESHOLD[THRESH] and a pointer is\n"
4983         "    allocated or de-allocated.\n";
4984     fail |= cvmx_error_add(&info);
4985
4986     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
4987     info.status_addr        = CVMX_FPA_INT_SUM;
4988     info.status_mask        = 1ull<<36 /* free0 */;
4989     info.enable_addr        = CVMX_FPA_INT_ENB;
4990     info.enable_mask        = 1ull<<36 /* free0 */;
4991     info.flags              = 0;
4992     info.group              = CVMX_ERROR_GROUP_INTERNAL;
4993     info.group_index        = 0;
4994     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
4995     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4996     info.parent.status_mask = 1ull<<5 /* fpa */;
4997     info.func               = __cvmx_error_display;
4998     info.user_info          = (long)
4999         "ERROR FPA_INT_SUM[FREE0]: When a pointer for POOL0 is freed bit is set.\n";
5000     fail |= cvmx_error_add(&info);
5001
5002     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5003     info.status_addr        = CVMX_FPA_INT_SUM;
5004     info.status_mask        = 1ull<<37 /* free1 */;
5005     info.enable_addr        = CVMX_FPA_INT_ENB;
5006     info.enable_mask        = 1ull<<37 /* free1 */;
5007     info.flags              = 0;
5008     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5009     info.group_index        = 0;
5010     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5011     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5012     info.parent.status_mask = 1ull<<5 /* fpa */;
5013     info.func               = __cvmx_error_display;
5014     info.user_info          = (long)
5015         "ERROR FPA_INT_SUM[FREE1]: When a pointer for POOL1 is freed bit is set.\n";
5016     fail |= cvmx_error_add(&info);
5017
5018     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5019     info.status_addr        = CVMX_FPA_INT_SUM;
5020     info.status_mask        = 1ull<<38 /* free2 */;
5021     info.enable_addr        = CVMX_FPA_INT_ENB;
5022     info.enable_mask        = 1ull<<38 /* free2 */;
5023     info.flags              = 0;
5024     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5025     info.group_index        = 0;
5026     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5027     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5028     info.parent.status_mask = 1ull<<5 /* fpa */;
5029     info.func               = __cvmx_error_display;
5030     info.user_info          = (long)
5031         "ERROR FPA_INT_SUM[FREE2]: When a pointer for POOL2 is freed bit is set.\n";
5032     fail |= cvmx_error_add(&info);
5033
5034     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5035     info.status_addr        = CVMX_FPA_INT_SUM;
5036     info.status_mask        = 1ull<<39 /* free3 */;
5037     info.enable_addr        = CVMX_FPA_INT_ENB;
5038     info.enable_mask        = 1ull<<39 /* free3 */;
5039     info.flags              = 0;
5040     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5041     info.group_index        = 0;
5042     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5043     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5044     info.parent.status_mask = 1ull<<5 /* fpa */;
5045     info.func               = __cvmx_error_display;
5046     info.user_info          = (long)
5047         "ERROR FPA_INT_SUM[FREE3]: When a pointer for POOL3 is freed bit is set.\n";
5048     fail |= cvmx_error_add(&info);
5049
5050     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5051     info.status_addr        = CVMX_FPA_INT_SUM;
5052     info.status_mask        = 1ull<<40 /* free4 */;
5053     info.enable_addr        = CVMX_FPA_INT_ENB;
5054     info.enable_mask        = 1ull<<40 /* free4 */;
5055     info.flags              = 0;
5056     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5057     info.group_index        = 0;
5058     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5059     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5060     info.parent.status_mask = 1ull<<5 /* fpa */;
5061     info.func               = __cvmx_error_display;
5062     info.user_info          = (long)
5063         "ERROR FPA_INT_SUM[FREE4]: When a pointer for POOL4 is freed bit is set.\n";
5064     fail |= cvmx_error_add(&info);
5065
5066     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5067     info.status_addr        = CVMX_FPA_INT_SUM;
5068     info.status_mask        = 1ull<<41 /* free5 */;
5069     info.enable_addr        = CVMX_FPA_INT_ENB;
5070     info.enable_mask        = 1ull<<41 /* free5 */;
5071     info.flags              = 0;
5072     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5073     info.group_index        = 0;
5074     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5075     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5076     info.parent.status_mask = 1ull<<5 /* fpa */;
5077     info.func               = __cvmx_error_display;
5078     info.user_info          = (long)
5079         "ERROR FPA_INT_SUM[FREE5]: When a pointer for POOL5 is freed bit is set.\n";
5080     fail |= cvmx_error_add(&info);
5081
5082     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5083     info.status_addr        = CVMX_FPA_INT_SUM;
5084     info.status_mask        = 1ull<<42 /* free6 */;
5085     info.enable_addr        = CVMX_FPA_INT_ENB;
5086     info.enable_mask        = 1ull<<42 /* free6 */;
5087     info.flags              = 0;
5088     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5089     info.group_index        = 0;
5090     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5091     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5092     info.parent.status_mask = 1ull<<5 /* fpa */;
5093     info.func               = __cvmx_error_display;
5094     info.user_info          = (long)
5095         "ERROR FPA_INT_SUM[FREE6]: When a pointer for POOL6 is freed bit is set.\n";
5096     fail |= cvmx_error_add(&info);
5097
5098     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5099     info.status_addr        = CVMX_FPA_INT_SUM;
5100     info.status_mask        = 1ull<<43 /* free7 */;
5101     info.enable_addr        = CVMX_FPA_INT_ENB;
5102     info.enable_mask        = 1ull<<43 /* free7 */;
5103     info.flags              = 0;
5104     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5105     info.group_index        = 0;
5106     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5107     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5108     info.parent.status_mask = 1ull<<5 /* fpa */;
5109     info.func               = __cvmx_error_display;
5110     info.user_info          = (long)
5111         "ERROR FPA_INT_SUM[FREE7]: When a pointer for POOL7 is freed bit is set.\n";
5112     fail |= cvmx_error_add(&info);
5113
5114     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5115     info.status_addr        = CVMX_FPA_INT_SUM;
5116     info.status_mask        = 1ull<<49 /* paddr_e */;
5117     info.enable_addr        = CVMX_FPA_INT_ENB;
5118     info.enable_mask        = 1ull<<49 /* paddr_e */;
5119     info.flags              = 0;
5120     info.group              = CVMX_ERROR_GROUP_INTERNAL;
5121     info.group_index        = 0;
5122     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5123     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5124     info.parent.status_mask = 1ull<<5 /* fpa */;
5125     info.func               = __cvmx_error_display;
5126     info.user_info          = (long)
5127         "ERROR FPA_INT_SUM[PADDR_E]: Set when a pointer address does not fall in the\n"
5128         "    address range for a pool specified by\n"
5129         "    FPA_POOLX_START_ADDR and FPA_POOLX_END_ADDR.\n";
5130     fail |= cvmx_error_add(&info);
5131
5132     /* CVMX_GMXX_BAD_REG(1) */
5133     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5134     info.status_addr        = CVMX_GMXX_BAD_REG(1);
5135     info.status_mask        = 0xfull<<2 /* out_ovr */;
5136     info.enable_addr        = 0;
5137     info.enable_mask        = 0;
5138     info.flags              = 0;
5139     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5140     info.group_index        = 16;
5141     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5142     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5143     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5144     info.func               = __cvmx_error_display;
5145     info.user_info          = (long)
5146         "ERROR GMXX_BAD_REG(1)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
5147     fail |= cvmx_error_add(&info);
5148
5149     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5150     info.status_addr        = CVMX_GMXX_BAD_REG(1);
5151     info.status_mask        = 0xfull<<22 /* loststat */;
5152     info.enable_addr        = 0;
5153     info.enable_mask        = 0;
5154     info.flags              = 0;
5155     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5156     info.group_index        = 16;
5157     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5158     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5159     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5160     info.func               = __cvmx_error_display;
5161     info.user_info          = (long)
5162         "ERROR GMXX_BAD_REG(1)[LOSTSTAT]: TX Statistics data was over-written\n"
5163         "    In SGMII, one bit per port\n"
5164         "    In XAUI, only port0 is used\n"
5165         "    TX Stats are corrupted\n";
5166     fail |= cvmx_error_add(&info);
5167
5168     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5169     info.status_addr        = CVMX_GMXX_BAD_REG(1);
5170     info.status_mask        = 1ull<<26 /* statovr */;
5171     info.enable_addr        = 0;
5172     info.enable_mask        = 0;
5173     info.flags              = 0;
5174     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5175     info.group_index        = 16;
5176     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5177     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5178     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5179     info.func               = __cvmx_error_display;
5180     info.user_info          = (long)
5181         "ERROR GMXX_BAD_REG(1)[STATOVR]: TX Statistics overflow\n"
5182         "    The common FIFO to SGMII and XAUI had an overflow\n"
5183         "    TX Stats are corrupted\n";
5184     fail |= cvmx_error_add(&info);
5185
5186     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5187     info.status_addr        = CVMX_GMXX_BAD_REG(1);
5188     info.status_mask        = 0xfull<<27 /* inb_nxa */;
5189     info.enable_addr        = 0;
5190     info.enable_mask        = 0;
5191     info.flags              = 0;
5192     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5193     info.group_index        = 16;
5194     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5195     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5196     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5197     info.func               = __cvmx_error_display;
5198     info.user_info          = (long)
5199         "ERROR GMXX_BAD_REG(1)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
5200     fail |= cvmx_error_add(&info);
5201
5202     /* CVMX_GMXX_RXX_INT_REG(0,1) */
5203     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5204     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5205     info.status_mask        = 1ull<<1 /* carext */;
5206     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5207     info.enable_mask        = 1ull<<1 /* carext */;
5208     info.flags              = 0;
5209     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5210     info.group_index        = 16;
5211     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5212     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5213     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5214     info.func               = __cvmx_error_display;
5215     info.user_info          = (long)
5216         "ERROR GMXX_RXX_INT_REG(0,1)[CAREXT]: Carrier extend error\n"
5217         "    (SGMII/1000Base-X only)\n";
5218     fail |= cvmx_error_add(&info);
5219
5220     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5221     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5222     info.status_mask        = 1ull<<8 /* skperr */;
5223     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5224     info.enable_mask        = 1ull<<8 /* skperr */;
5225     info.flags              = 0;
5226     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5227     info.group_index        = 16;
5228     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5229     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5230     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5231     info.func               = __cvmx_error_display;
5232     info.user_info          = (long)
5233         "ERROR GMXX_RXX_INT_REG(0,1)[SKPERR]: Skipper error\n";
5234     fail |= cvmx_error_add(&info);
5235
5236     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5237     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5238     info.status_mask        = 1ull<<10 /* ovrerr */;
5239     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5240     info.enable_mask        = 1ull<<10 /* ovrerr */;
5241     info.flags              = 0;
5242     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5243     info.group_index        = 16;
5244     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5245     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5246     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5247     info.func               = __cvmx_error_display;
5248     info.user_info          = (long)
5249         "ERROR GMXX_RXX_INT_REG(0,1)[OVRERR]: Internal Data Aggregation Overflow\n"
5250         "    This interrupt should never assert\n"
5251         "    (SGMII/1000Base-X only)\n";
5252     fail |= cvmx_error_add(&info);
5253
5254     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5255     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5256     info.status_mask        = 1ull<<20 /* loc_fault */;
5257     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5258     info.enable_mask        = 1ull<<20 /* loc_fault */;
5259     info.flags              = 0;
5260     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5261     info.group_index        = 16;
5262     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5263     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5264     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5265     info.func               = __cvmx_error_display;
5266     info.user_info          = (long)
5267         "ERROR GMXX_RXX_INT_REG(0,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5268         "    (XAUI Mode only)\n";
5269     fail |= cvmx_error_add(&info);
5270
5271     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5272     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5273     info.status_mask        = 1ull<<21 /* rem_fault */;
5274     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5275     info.enable_mask        = 1ull<<21 /* rem_fault */;
5276     info.flags              = 0;
5277     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5278     info.group_index        = 16;
5279     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5280     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5281     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5282     info.func               = __cvmx_error_display;
5283     info.user_info          = (long)
5284         "ERROR GMXX_RXX_INT_REG(0,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5285         "    (XAUI Mode only)\n";
5286     fail |= cvmx_error_add(&info);
5287
5288     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5289     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5290     info.status_mask        = 1ull<<22 /* bad_seq */;
5291     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5292     info.enable_mask        = 1ull<<22 /* bad_seq */;
5293     info.flags              = 0;
5294     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5295     info.group_index        = 16;
5296     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5297     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5298     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5299     info.func               = __cvmx_error_display;
5300     info.user_info          = (long)
5301         "ERROR GMXX_RXX_INT_REG(0,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
5302         "    (XAUI Mode only)\n";
5303     fail |= cvmx_error_add(&info);
5304
5305     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5306     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5307     info.status_mask        = 1ull<<23 /* bad_term */;
5308     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5309     info.enable_mask        = 1ull<<23 /* bad_term */;
5310     info.flags              = 0;
5311     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5312     info.group_index        = 16;
5313     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5314     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5315     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5316     info.func               = __cvmx_error_display;
5317     info.user_info          = (long)
5318         "ERROR GMXX_RXX_INT_REG(0,1)[BAD_TERM]: Frame is terminated by control character other\n"
5319         "    than /T/.  The error propagation control\n"
5320         "    character /E/ will be included as part of the\n"
5321         "    frame and does not cause a frame termination.\n"
5322         "    (XAUI Mode only)\n";
5323     fail |= cvmx_error_add(&info);
5324
5325     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5326     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5327     info.status_mask        = 1ull<<24 /* unsop */;
5328     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5329     info.enable_mask        = 1ull<<24 /* unsop */;
5330     info.flags              = 0;
5331     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5332     info.group_index        = 16;
5333     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5334     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5335     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5336     info.func               = __cvmx_error_display;
5337     info.user_info          = (long)
5338         "ERROR GMXX_RXX_INT_REG(0,1)[UNSOP]: Unexpected SOP\n"
5339         "    (XAUI Mode only)\n";
5340     fail |= cvmx_error_add(&info);
5341
5342     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5343     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5344     info.status_mask        = 1ull<<25 /* uneop */;
5345     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5346     info.enable_mask        = 1ull<<25 /* uneop */;
5347     info.flags              = 0;
5348     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5349     info.group_index        = 16;
5350     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5351     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5352     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5353     info.func               = __cvmx_error_display;
5354     info.user_info          = (long)
5355         "ERROR GMXX_RXX_INT_REG(0,1)[UNEOP]: Unexpected EOP\n"
5356         "    (XAUI Mode only)\n";
5357     fail |= cvmx_error_add(&info);
5358
5359     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5360     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5361     info.status_mask        = 1ull<<26 /* undat */;
5362     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5363     info.enable_mask        = 1ull<<26 /* undat */;
5364     info.flags              = 0;
5365     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5366     info.group_index        = 16;
5367     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5368     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5369     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5370     info.func               = __cvmx_error_display;
5371     info.user_info          = (long)
5372         "ERROR GMXX_RXX_INT_REG(0,1)[UNDAT]: Unexpected Data\n"
5373         "    (XAUI Mode only)\n";
5374     fail |= cvmx_error_add(&info);
5375
5376     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5377     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5378     info.status_mask        = 1ull<<27 /* hg2fld */;
5379     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5380     info.enable_mask        = 1ull<<27 /* hg2fld */;
5381     info.flags              = 0;
5382     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5383     info.group_index        = 16;
5384     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5385     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5386     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5387     info.func               = __cvmx_error_display;
5388     info.user_info          = (long)
5389         "ERROR GMXX_RXX_INT_REG(0,1)[HG2FLD]: HiGig2 received message field error, as below\n"
5390         "    1) MSG_TYPE field not 6'b00_0000\n"
5391         "       i.e. it is not a FLOW CONTROL message, which\n"
5392         "       is the only defined type for HiGig2\n"
5393         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5394         "       which is the only defined type for HiGig2\n"
5395         "    3) FC_OBJECT field is neither 4'b0000 for\n"
5396         "       Physical Link nor 4'b0010 for Logical Link.\n"
5397         "       Those are the only two defined types in HiGig2\n";
5398     fail |= cvmx_error_add(&info);
5399
5400     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5401     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,1);
5402     info.status_mask        = 1ull<<28 /* hg2cc */;
5403     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,1);
5404     info.enable_mask        = 1ull<<28 /* hg2cc */;
5405     info.flags              = 0;
5406     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5407     info.group_index        = 16;
5408     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5409     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5410     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5411     info.func               = __cvmx_error_display;
5412     info.user_info          = (long)
5413         "ERROR GMXX_RXX_INT_REG(0,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
5414         "    Set when either CRC8 error detected or when\n"
5415         "    a Control Character is found in the message\n"
5416         "    bytes after the K.SOM\n"
5417         "    NOTE: HG2CC has higher priority than HG2FLD\n"
5418         "          i.e. a HiGig2 message that results in HG2CC\n"
5419         "          getting set, will never set HG2FLD.\n";
5420     fail |= cvmx_error_add(&info);
5421
5422     /* CVMX_GMXX_RXX_INT_REG(1,1) */
5423     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5424     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5425     info.status_mask        = 1ull<<1 /* carext */;
5426     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5427     info.enable_mask        = 1ull<<1 /* carext */;
5428     info.flags              = 0;
5429     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5430     info.group_index        = 17;
5431     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5432     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5433     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5434     info.func               = __cvmx_error_display;
5435     info.user_info          = (long)
5436         "ERROR GMXX_RXX_INT_REG(1,1)[CAREXT]: Carrier extend error\n"
5437         "    (SGMII/1000Base-X only)\n";
5438     fail |= cvmx_error_add(&info);
5439
5440     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5441     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5442     info.status_mask        = 1ull<<8 /* skperr */;
5443     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5444     info.enable_mask        = 1ull<<8 /* skperr */;
5445     info.flags              = 0;
5446     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5447     info.group_index        = 17;
5448     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5449     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5450     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5451     info.func               = __cvmx_error_display;
5452     info.user_info          = (long)
5453         "ERROR GMXX_RXX_INT_REG(1,1)[SKPERR]: Skipper error\n";
5454     fail |= cvmx_error_add(&info);
5455
5456     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5457     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5458     info.status_mask        = 1ull<<10 /* ovrerr */;
5459     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5460     info.enable_mask        = 1ull<<10 /* ovrerr */;
5461     info.flags              = 0;
5462     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5463     info.group_index        = 17;
5464     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5465     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5466     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5467     info.func               = __cvmx_error_display;
5468     info.user_info          = (long)
5469         "ERROR GMXX_RXX_INT_REG(1,1)[OVRERR]: Internal Data Aggregation Overflow\n"
5470         "    This interrupt should never assert\n"
5471         "    (SGMII/1000Base-X only)\n";
5472     fail |= cvmx_error_add(&info);
5473
5474     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5475     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5476     info.status_mask        = 1ull<<20 /* loc_fault */;
5477     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5478     info.enable_mask        = 1ull<<20 /* loc_fault */;
5479     info.flags              = 0;
5480     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5481     info.group_index        = 17;
5482     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5483     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5484     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5485     info.func               = __cvmx_error_display;
5486     info.user_info          = (long)
5487         "ERROR GMXX_RXX_INT_REG(1,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5488         "    (XAUI Mode only)\n";
5489     fail |= cvmx_error_add(&info);
5490
5491     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5492     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5493     info.status_mask        = 1ull<<21 /* rem_fault */;
5494     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5495     info.enable_mask        = 1ull<<21 /* rem_fault */;
5496     info.flags              = 0;
5497     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5498     info.group_index        = 17;
5499     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5500     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5501     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5502     info.func               = __cvmx_error_display;
5503     info.user_info          = (long)
5504         "ERROR GMXX_RXX_INT_REG(1,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5505         "    (XAUI Mode only)\n";
5506     fail |= cvmx_error_add(&info);
5507
5508     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5509     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5510     info.status_mask        = 1ull<<22 /* bad_seq */;
5511     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5512     info.enable_mask        = 1ull<<22 /* bad_seq */;
5513     info.flags              = 0;
5514     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5515     info.group_index        = 17;
5516     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5517     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5518     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5519     info.func               = __cvmx_error_display;
5520     info.user_info          = (long)
5521         "ERROR GMXX_RXX_INT_REG(1,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
5522         "    (XAUI Mode only)\n";
5523     fail |= cvmx_error_add(&info);
5524
5525     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5526     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5527     info.status_mask        = 1ull<<23 /* bad_term */;
5528     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5529     info.enable_mask        = 1ull<<23 /* bad_term */;
5530     info.flags              = 0;
5531     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5532     info.group_index        = 17;
5533     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5534     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5535     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5536     info.func               = __cvmx_error_display;
5537     info.user_info          = (long)
5538         "ERROR GMXX_RXX_INT_REG(1,1)[BAD_TERM]: Frame is terminated by control character other\n"
5539         "    than /T/.  The error propagation control\n"
5540         "    character /E/ will be included as part of the\n"
5541         "    frame and does not cause a frame termination.\n"
5542         "    (XAUI Mode only)\n";
5543     fail |= cvmx_error_add(&info);
5544
5545     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5546     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5547     info.status_mask        = 1ull<<24 /* unsop */;
5548     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5549     info.enable_mask        = 1ull<<24 /* unsop */;
5550     info.flags              = 0;
5551     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5552     info.group_index        = 17;
5553     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5554     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5555     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5556     info.func               = __cvmx_error_display;
5557     info.user_info          = (long)
5558         "ERROR GMXX_RXX_INT_REG(1,1)[UNSOP]: Unexpected SOP\n"
5559         "    (XAUI Mode only)\n";
5560     fail |= cvmx_error_add(&info);
5561
5562     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5563     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5564     info.status_mask        = 1ull<<25 /* uneop */;
5565     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5566     info.enable_mask        = 1ull<<25 /* uneop */;
5567     info.flags              = 0;
5568     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5569     info.group_index        = 17;
5570     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5571     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5572     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5573     info.func               = __cvmx_error_display;
5574     info.user_info          = (long)
5575         "ERROR GMXX_RXX_INT_REG(1,1)[UNEOP]: Unexpected EOP\n"
5576         "    (XAUI Mode only)\n";
5577     fail |= cvmx_error_add(&info);
5578
5579     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5580     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5581     info.status_mask        = 1ull<<26 /* undat */;
5582     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5583     info.enable_mask        = 1ull<<26 /* undat */;
5584     info.flags              = 0;
5585     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5586     info.group_index        = 17;
5587     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5588     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5589     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5590     info.func               = __cvmx_error_display;
5591     info.user_info          = (long)
5592         "ERROR GMXX_RXX_INT_REG(1,1)[UNDAT]: Unexpected Data\n"
5593         "    (XAUI Mode only)\n";
5594     fail |= cvmx_error_add(&info);
5595
5596     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5597     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5598     info.status_mask        = 1ull<<27 /* hg2fld */;
5599     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5600     info.enable_mask        = 1ull<<27 /* hg2fld */;
5601     info.flags              = 0;
5602     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5603     info.group_index        = 17;
5604     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5605     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5606     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5607     info.func               = __cvmx_error_display;
5608     info.user_info          = (long)
5609         "ERROR GMXX_RXX_INT_REG(1,1)[HG2FLD]: HiGig2 received message field error, as below\n"
5610         "    1) MSG_TYPE field not 6'b00_0000\n"
5611         "       i.e. it is not a FLOW CONTROL message, which\n"
5612         "       is the only defined type for HiGig2\n"
5613         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5614         "       which is the only defined type for HiGig2\n"
5615         "    3) FC_OBJECT field is neither 4'b0000 for\n"
5616         "       Physical Link nor 4'b0010 for Logical Link.\n"
5617         "       Those are the only two defined types in HiGig2\n";
5618     fail |= cvmx_error_add(&info);
5619
5620     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5621     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,1);
5622     info.status_mask        = 1ull<<28 /* hg2cc */;
5623     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,1);
5624     info.enable_mask        = 1ull<<28 /* hg2cc */;
5625     info.flags              = 0;
5626     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5627     info.group_index        = 17;
5628     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5629     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5630     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5631     info.func               = __cvmx_error_display;
5632     info.user_info          = (long)
5633         "ERROR GMXX_RXX_INT_REG(1,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
5634         "    Set when either CRC8 error detected or when\n"
5635         "    a Control Character is found in the message\n"
5636         "    bytes after the K.SOM\n"
5637         "    NOTE: HG2CC has higher priority than HG2FLD\n"
5638         "          i.e. a HiGig2 message that results in HG2CC\n"
5639         "          getting set, will never set HG2FLD.\n";
5640     fail |= cvmx_error_add(&info);
5641
5642     /* CVMX_GMXX_RXX_INT_REG(2,1) */
5643     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5644     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5645     info.status_mask        = 1ull<<1 /* carext */;
5646     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5647     info.enable_mask        = 1ull<<1 /* carext */;
5648     info.flags              = 0;
5649     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5650     info.group_index        = 18;
5651     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5652     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5653     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5654     info.func               = __cvmx_error_display;
5655     info.user_info          = (long)
5656         "ERROR GMXX_RXX_INT_REG(2,1)[CAREXT]: Carrier extend error\n"
5657         "    (SGMII/1000Base-X only)\n";
5658     fail |= cvmx_error_add(&info);
5659
5660     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5661     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5662     info.status_mask        = 1ull<<8 /* skperr */;
5663     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5664     info.enable_mask        = 1ull<<8 /* skperr */;
5665     info.flags              = 0;
5666     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5667     info.group_index        = 18;
5668     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5669     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5670     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5671     info.func               = __cvmx_error_display;
5672     info.user_info          = (long)
5673         "ERROR GMXX_RXX_INT_REG(2,1)[SKPERR]: Skipper error\n";
5674     fail |= cvmx_error_add(&info);
5675
5676     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5677     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5678     info.status_mask        = 1ull<<10 /* ovrerr */;
5679     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5680     info.enable_mask        = 1ull<<10 /* ovrerr */;
5681     info.flags              = 0;
5682     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5683     info.group_index        = 18;
5684     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5685     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5686     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5687     info.func               = __cvmx_error_display;
5688     info.user_info          = (long)
5689         "ERROR GMXX_RXX_INT_REG(2,1)[OVRERR]: Internal Data Aggregation Overflow\n"
5690         "    This interrupt should never assert\n"
5691         "    (SGMII/1000Base-X only)\n";
5692     fail |= cvmx_error_add(&info);
5693
5694     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5695     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5696     info.status_mask        = 1ull<<20 /* loc_fault */;
5697     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5698     info.enable_mask        = 1ull<<20 /* loc_fault */;
5699     info.flags              = 0;
5700     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5701     info.group_index        = 18;
5702     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5703     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5704     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5705     info.func               = __cvmx_error_display;
5706     info.user_info          = (long)
5707         "ERROR GMXX_RXX_INT_REG(2,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5708         "    (XAUI Mode only)\n";
5709     fail |= cvmx_error_add(&info);
5710
5711     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5712     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5713     info.status_mask        = 1ull<<21 /* rem_fault */;
5714     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5715     info.enable_mask        = 1ull<<21 /* rem_fault */;
5716     info.flags              = 0;
5717     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5718     info.group_index        = 18;
5719     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5720     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5721     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5722     info.func               = __cvmx_error_display;
5723     info.user_info          = (long)
5724         "ERROR GMXX_RXX_INT_REG(2,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5725         "    (XAUI Mode only)\n";
5726     fail |= cvmx_error_add(&info);
5727
5728     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5729     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5730     info.status_mask        = 1ull<<22 /* bad_seq */;
5731     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5732     info.enable_mask        = 1ull<<22 /* bad_seq */;
5733     info.flags              = 0;
5734     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5735     info.group_index        = 18;
5736     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5737     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5738     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5739     info.func               = __cvmx_error_display;
5740     info.user_info          = (long)
5741         "ERROR GMXX_RXX_INT_REG(2,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
5742         "    (XAUI Mode only)\n";
5743     fail |= cvmx_error_add(&info);
5744
5745     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5746     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5747     info.status_mask        = 1ull<<23 /* bad_term */;
5748     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5749     info.enable_mask        = 1ull<<23 /* bad_term */;
5750     info.flags              = 0;
5751     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5752     info.group_index        = 18;
5753     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5754     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5755     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5756     info.func               = __cvmx_error_display;
5757     info.user_info          = (long)
5758         "ERROR GMXX_RXX_INT_REG(2,1)[BAD_TERM]: Frame is terminated by control character other\n"
5759         "    than /T/.  The error propagation control\n"
5760         "    character /E/ will be included as part of the\n"
5761         "    frame and does not cause a frame termination.\n"
5762         "    (XAUI Mode only)\n";
5763     fail |= cvmx_error_add(&info);
5764
5765     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5766     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5767     info.status_mask        = 1ull<<24 /* unsop */;
5768     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5769     info.enable_mask        = 1ull<<24 /* unsop */;
5770     info.flags              = 0;
5771     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5772     info.group_index        = 18;
5773     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5774     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5775     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5776     info.func               = __cvmx_error_display;
5777     info.user_info          = (long)
5778         "ERROR GMXX_RXX_INT_REG(2,1)[UNSOP]: Unexpected SOP\n"
5779         "    (XAUI Mode only)\n";
5780     fail |= cvmx_error_add(&info);
5781
5782     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5783     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5784     info.status_mask        = 1ull<<25 /* uneop */;
5785     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5786     info.enable_mask        = 1ull<<25 /* uneop */;
5787     info.flags              = 0;
5788     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5789     info.group_index        = 18;
5790     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5791     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5792     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5793     info.func               = __cvmx_error_display;
5794     info.user_info          = (long)
5795         "ERROR GMXX_RXX_INT_REG(2,1)[UNEOP]: Unexpected EOP\n"
5796         "    (XAUI Mode only)\n";
5797     fail |= cvmx_error_add(&info);
5798
5799     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5800     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5801     info.status_mask        = 1ull<<26 /* undat */;
5802     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5803     info.enable_mask        = 1ull<<26 /* undat */;
5804     info.flags              = 0;
5805     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5806     info.group_index        = 18;
5807     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5808     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5809     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5810     info.func               = __cvmx_error_display;
5811     info.user_info          = (long)
5812         "ERROR GMXX_RXX_INT_REG(2,1)[UNDAT]: Unexpected Data\n"
5813         "    (XAUI Mode only)\n";
5814     fail |= cvmx_error_add(&info);
5815
5816     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5817     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5818     info.status_mask        = 1ull<<27 /* hg2fld */;
5819     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5820     info.enable_mask        = 1ull<<27 /* hg2fld */;
5821     info.flags              = 0;
5822     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5823     info.group_index        = 18;
5824     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5825     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5826     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5827     info.func               = __cvmx_error_display;
5828     info.user_info          = (long)
5829         "ERROR GMXX_RXX_INT_REG(2,1)[HG2FLD]: HiGig2 received message field error, as below\n"
5830         "    1) MSG_TYPE field not 6'b00_0000\n"
5831         "       i.e. it is not a FLOW CONTROL message, which\n"
5832         "       is the only defined type for HiGig2\n"
5833         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5834         "       which is the only defined type for HiGig2\n"
5835         "    3) FC_OBJECT field is neither 4'b0000 for\n"
5836         "       Physical Link nor 4'b0010 for Logical Link.\n"
5837         "       Those are the only two defined types in HiGig2\n";
5838     fail |= cvmx_error_add(&info);
5839
5840     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5841     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,1);
5842     info.status_mask        = 1ull<<28 /* hg2cc */;
5843     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,1);
5844     info.enable_mask        = 1ull<<28 /* hg2cc */;
5845     info.flags              = 0;
5846     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5847     info.group_index        = 18;
5848     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5849     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5850     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5851     info.func               = __cvmx_error_display;
5852     info.user_info          = (long)
5853         "ERROR GMXX_RXX_INT_REG(2,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
5854         "    Set when either CRC8 error detected or when\n"
5855         "    a Control Character is found in the message\n"
5856         "    bytes after the K.SOM\n"
5857         "    NOTE: HG2CC has higher priority than HG2FLD\n"
5858         "          i.e. a HiGig2 message that results in HG2CC\n"
5859         "          getting set, will never set HG2FLD.\n";
5860     fail |= cvmx_error_add(&info);
5861
5862     /* CVMX_GMXX_RXX_INT_REG(3,1) */
5863     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5864     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5865     info.status_mask        = 1ull<<1 /* carext */;
5866     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5867     info.enable_mask        = 1ull<<1 /* carext */;
5868     info.flags              = 0;
5869     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5870     info.group_index        = 19;
5871     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5872     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5873     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5874     info.func               = __cvmx_error_display;
5875     info.user_info          = (long)
5876         "ERROR GMXX_RXX_INT_REG(3,1)[CAREXT]: Carrier extend error\n"
5877         "    (SGMII/1000Base-X only)\n";
5878     fail |= cvmx_error_add(&info);
5879
5880     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5881     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5882     info.status_mask        = 1ull<<8 /* skperr */;
5883     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5884     info.enable_mask        = 1ull<<8 /* skperr */;
5885     info.flags              = 0;
5886     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5887     info.group_index        = 19;
5888     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5889     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5890     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5891     info.func               = __cvmx_error_display;
5892     info.user_info          = (long)
5893         "ERROR GMXX_RXX_INT_REG(3,1)[SKPERR]: Skipper error\n";
5894     fail |= cvmx_error_add(&info);
5895
5896     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5897     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5898     info.status_mask        = 1ull<<10 /* ovrerr */;
5899     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5900     info.enable_mask        = 1ull<<10 /* ovrerr */;
5901     info.flags              = 0;
5902     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5903     info.group_index        = 19;
5904     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5905     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5906     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5907     info.func               = __cvmx_error_display;
5908     info.user_info          = (long)
5909         "ERROR GMXX_RXX_INT_REG(3,1)[OVRERR]: Internal Data Aggregation Overflow\n"
5910         "    This interrupt should never assert\n"
5911         "    (SGMII/1000Base-X only)\n";
5912     fail |= cvmx_error_add(&info);
5913
5914     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5915     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5916     info.status_mask        = 1ull<<20 /* loc_fault */;
5917     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5918     info.enable_mask        = 1ull<<20 /* loc_fault */;
5919     info.flags              = 0;
5920     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5921     info.group_index        = 19;
5922     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5923     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5924     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5925     info.func               = __cvmx_error_display;
5926     info.user_info          = (long)
5927         "ERROR GMXX_RXX_INT_REG(3,1)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5928         "    (XAUI Mode only)\n";
5929     fail |= cvmx_error_add(&info);
5930
5931     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5932     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5933     info.status_mask        = 1ull<<21 /* rem_fault */;
5934     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5935     info.enable_mask        = 1ull<<21 /* rem_fault */;
5936     info.flags              = 0;
5937     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5938     info.group_index        = 19;
5939     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5940     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5941     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5942     info.func               = __cvmx_error_display;
5943     info.user_info          = (long)
5944         "ERROR GMXX_RXX_INT_REG(3,1)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5945         "    (XAUI Mode only)\n";
5946     fail |= cvmx_error_add(&info);
5947
5948     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5949     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5950     info.status_mask        = 1ull<<22 /* bad_seq */;
5951     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5952     info.enable_mask        = 1ull<<22 /* bad_seq */;
5953     info.flags              = 0;
5954     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5955     info.group_index        = 19;
5956     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5957     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5958     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5959     info.func               = __cvmx_error_display;
5960     info.user_info          = (long)
5961         "ERROR GMXX_RXX_INT_REG(3,1)[BAD_SEQ]: Reserved Sequence Deteted\n"
5962         "    (XAUI Mode only)\n";
5963     fail |= cvmx_error_add(&info);
5964
5965     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5966     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5967     info.status_mask        = 1ull<<23 /* bad_term */;
5968     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5969     info.enable_mask        = 1ull<<23 /* bad_term */;
5970     info.flags              = 0;
5971     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5972     info.group_index        = 19;
5973     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5974     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5975     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5976     info.func               = __cvmx_error_display;
5977     info.user_info          = (long)
5978         "ERROR GMXX_RXX_INT_REG(3,1)[BAD_TERM]: Frame is terminated by control character other\n"
5979         "    than /T/.  The error propagation control\n"
5980         "    character /E/ will be included as part of the\n"
5981         "    frame and does not cause a frame termination.\n"
5982         "    (XAUI Mode only)\n";
5983     fail |= cvmx_error_add(&info);
5984
5985     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
5986     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
5987     info.status_mask        = 1ull<<24 /* unsop */;
5988     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
5989     info.enable_mask        = 1ull<<24 /* unsop */;
5990     info.flags              = 0;
5991     info.group              = CVMX_ERROR_GROUP_ETHERNET;
5992     info.group_index        = 19;
5993     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
5994     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5995     info.parent.status_mask = 1ull<<2 /* gmx1 */;
5996     info.func               = __cvmx_error_display;
5997     info.user_info          = (long)
5998         "ERROR GMXX_RXX_INT_REG(3,1)[UNSOP]: Unexpected SOP\n"
5999         "    (XAUI Mode only)\n";
6000     fail |= cvmx_error_add(&info);
6001
6002     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6003     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
6004     info.status_mask        = 1ull<<25 /* uneop */;
6005     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
6006     info.enable_mask        = 1ull<<25 /* uneop */;
6007     info.flags              = 0;
6008     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6009     info.group_index        = 19;
6010     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6011     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6012     info.parent.status_mask = 1ull<<2 /* gmx1 */;
6013     info.func               = __cvmx_error_display;
6014     info.user_info          = (long)
6015         "ERROR GMXX_RXX_INT_REG(3,1)[UNEOP]: Unexpected EOP\n"
6016         "    (XAUI Mode only)\n";
6017     fail |= cvmx_error_add(&info);
6018
6019     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6020     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
6021     info.status_mask        = 1ull<<26 /* undat */;
6022     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
6023     info.enable_mask        = 1ull<<26 /* undat */;
6024     info.flags              = 0;
6025     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6026     info.group_index        = 19;
6027     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6028     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6029     info.parent.status_mask = 1ull<<2 /* gmx1 */;
6030     info.func               = __cvmx_error_display;
6031     info.user_info          = (long)
6032         "ERROR GMXX_RXX_INT_REG(3,1)[UNDAT]: Unexpected Data\n"
6033         "    (XAUI Mode only)\n";
6034     fail |= cvmx_error_add(&info);
6035
6036     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6037     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
6038     info.status_mask        = 1ull<<27 /* hg2fld */;
6039     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
6040     info.enable_mask        = 1ull<<27 /* hg2fld */;
6041     info.flags              = 0;
6042     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6043     info.group_index        = 19;
6044     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6045     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6046     info.parent.status_mask = 1ull<<2 /* gmx1 */;
6047     info.func               = __cvmx_error_display;
6048     info.user_info          = (long)
6049         "ERROR GMXX_RXX_INT_REG(3,1)[HG2FLD]: HiGig2 received message field error, as below\n"
6050         "    1) MSG_TYPE field not 6'b00_0000\n"
6051         "       i.e. it is not a FLOW CONTROL message, which\n"
6052         "       is the only defined type for HiGig2\n"
6053         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
6054         "       which is the only defined type for HiGig2\n"
6055         "    3) FC_OBJECT field is neither 4'b0000 for\n"
6056         "       Physical Link nor 4'b0010 for Logical Link.\n"
6057         "       Those are the only two defined types in HiGig2\n";
6058     fail |= cvmx_error_add(&info);
6059
6060     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6061     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,1);
6062     info.status_mask        = 1ull<<28 /* hg2cc */;
6063     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,1);
6064     info.enable_mask        = 1ull<<28 /* hg2cc */;
6065     info.flags              = 0;
6066     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6067     info.group_index        = 19;
6068     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6069     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6070     info.parent.status_mask = 1ull<<2 /* gmx1 */;
6071     info.func               = __cvmx_error_display;
6072     info.user_info          = (long)
6073         "ERROR GMXX_RXX_INT_REG(3,1)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
6074         "    Set when either CRC8 error detected or when\n"
6075         "    a Control Character is found in the message\n"
6076         "    bytes after the K.SOM\n"
6077         "    NOTE: HG2CC has higher priority than HG2FLD\n"
6078         "          i.e. a HiGig2 message that results in HG2CC\n"
6079         "          getting set, will never set HG2FLD.\n";
6080     fail |= cvmx_error_add(&info);
6081
6082     /* CVMX_GMXX_TX_INT_REG(1) */
6083     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6084     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
6085     info.status_mask        = 1ull<<0 /* pko_nxa */;
6086     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
6087     info.enable_mask        = 1ull<<0 /* pko_nxa */;
6088     info.flags              = 0;
6089     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6090     info.group_index        = 16;
6091     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6092     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6093     info.parent.status_mask = 1ull<<2 /* gmx1 */;
6094     info.func               = __cvmx_error_display;
6095     info.user_info          = (long)
6096         "ERROR GMXX_TX_INT_REG(1)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
6097     fail |= cvmx_error_add(&info);
6098
6099     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6100     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
6101     info.status_mask        = 0xfull<<2 /* undflw */;
6102     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
6103     info.enable_mask        = 0xfull<<2 /* undflw */;
6104     info.flags              = 0;
6105     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6106     info.group_index        = 16;
6107     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6108     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6109     info.parent.status_mask = 1ull<<2 /* gmx1 */;
6110     info.func               = __cvmx_error_display;
6111     info.user_info          = (long)
6112         "ERROR GMXX_TX_INT_REG(1)[UNDFLW]: TX Underflow\n";
6113     fail |= cvmx_error_add(&info);
6114
6115     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6116     info.status_addr        = CVMX_GMXX_TX_INT_REG(1);
6117     info.status_mask        = 0xfull<<20 /* ptp_lost */;
6118     info.enable_addr        = CVMX_GMXX_TX_INT_EN(1);
6119     info.enable_mask        = 0xfull<<20 /* ptp_lost */;
6120     info.flags              = 0;
6121     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6122     info.group_index        = 16;
6123     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6124     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6125     info.parent.status_mask = 1ull<<2 /* gmx1 */;
6126     info.func               = __cvmx_error_display;
6127     info.user_info          = (long)
6128         "ERROR GMXX_TX_INT_REG(1)[PTP_LOST]: A packet with a PTP request was not able to be\n"
6129         "    sent due to XSCOL\n";
6130     fail |= cvmx_error_add(&info);
6131
6132     /* CVMX_MIO_BOOT_ERR */
6133     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6134     info.status_addr        = CVMX_MIO_BOOT_ERR;
6135     info.status_mask        = 1ull<<0 /* adr_err */;
6136     info.enable_addr        = CVMX_MIO_BOOT_INT;
6137     info.enable_mask        = 1ull<<0 /* adr_int */;
6138     info.flags              = 0;
6139     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6140     info.group_index        = 0;
6141     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6142     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6143     info.parent.status_mask = 1ull<<0 /* mio */;
6144     info.func               = __cvmx_error_display;
6145     info.user_info          = (long)
6146         "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
6147     fail |= cvmx_error_add(&info);
6148
6149     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6150     info.status_addr        = CVMX_MIO_BOOT_ERR;
6151     info.status_mask        = 1ull<<1 /* wait_err */;
6152     info.enable_addr        = CVMX_MIO_BOOT_INT;
6153     info.enable_mask        = 1ull<<1 /* wait_int */;
6154     info.flags              = 0;
6155     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6156     info.group_index        = 0;
6157     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6158     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6159     info.parent.status_mask = 1ull<<0 /* mio */;
6160     info.func               = __cvmx_error_display;
6161     info.user_info          = (long)
6162         "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
6163     fail |= cvmx_error_add(&info);
6164
6165     /* CVMX_MIO_RST_INT */
6166     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6167     info.status_addr        = CVMX_MIO_RST_INT;
6168     info.status_mask        = 1ull<<0 /* rst_link0 */;
6169     info.enable_addr        = CVMX_MIO_RST_INT_EN;
6170     info.enable_mask        = 1ull<<0 /* rst_link0 */;
6171     info.flags              = 0;
6172     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6173     info.group_index        = 0;
6174     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6175     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6176     info.parent.status_mask = 1ull<<0 /* mio */;
6177     info.func               = __cvmx_error_display;
6178     info.user_info          = (long)
6179         "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
6180         "    MIO_RST_CNTL0[RST_LINK]=0.  Software must assert\n"
6181         "    then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
6182     fail |= cvmx_error_add(&info);
6183
6184     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6185     info.status_addr        = CVMX_MIO_RST_INT;
6186     info.status_mask        = 1ull<<1 /* rst_link1 */;
6187     info.enable_addr        = CVMX_MIO_RST_INT_EN;
6188     info.enable_mask        = 1ull<<1 /* rst_link1 */;
6189     info.flags              = 0;
6190     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6191     info.group_index        = 0;
6192     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6193     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6194     info.parent.status_mask = 1ull<<0 /* mio */;
6195     info.func               = __cvmx_error_display;
6196     info.user_info          = (long)
6197         "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
6198         "    MIO_RST_CNTL1[RST_LINK]=0.  Software must assert\n"
6199         "    then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
6200     fail |= cvmx_error_add(&info);
6201
6202     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6203     info.status_addr        = CVMX_MIO_RST_INT;
6204     info.status_mask        = 1ull<<2 /* rst_link2 */;
6205     info.enable_addr        = CVMX_MIO_RST_INT_EN;
6206     info.enable_mask        = 1ull<<2 /* rst_link2 */;
6207     info.flags              = 0;
6208     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6209     info.group_index        = 0;
6210     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6211     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6212     info.parent.status_mask = 1ull<<0 /* mio */;
6213     info.func               = __cvmx_error_display;
6214     info.user_info          = (long)
6215         "ERROR MIO_RST_INT[RST_LINK2]: A controller2 link-down/hot-reset occurred while\n"
6216         "    MIO_RST_CNTL2[RST_LINK]=0.  Software must assert\n"
6217         "    then de-assert CIU_SOFT_PRST2[SOFT_PRST]\n";
6218     fail |= cvmx_error_add(&info);
6219
6220     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6221     info.status_addr        = CVMX_MIO_RST_INT;
6222     info.status_mask        = 1ull<<3 /* rst_link3 */;
6223     info.enable_addr        = CVMX_MIO_RST_INT_EN;
6224     info.enable_mask        = 1ull<<3 /* rst_link3 */;
6225     info.flags              = 0;
6226     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6227     info.group_index        = 0;
6228     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6229     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6230     info.parent.status_mask = 1ull<<0 /* mio */;
6231     info.func               = __cvmx_error_display;
6232     info.user_info          = (long)
6233         "ERROR MIO_RST_INT[RST_LINK3]: A controller3 link-down/hot-reset occurred while\n"
6234         "    MIO_RST_CNTL3[RST_LINK]=0.  Software must assert\n"
6235         "    then de-assert CIU_SOFT_PRST3[SOFT_PRST]\n";
6236     fail |= cvmx_error_add(&info);
6237
6238     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6239     info.status_addr        = CVMX_MIO_RST_INT;
6240     info.status_mask        = 1ull<<8 /* perst0 */;
6241     info.enable_addr        = CVMX_MIO_RST_INT_EN;
6242     info.enable_mask        = 1ull<<8 /* perst0 */;
6243     info.flags              = 0;
6244     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6245     info.group_index        = 0;
6246     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6247     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6248     info.parent.status_mask = 1ull<<0 /* mio */;
6249     info.func               = __cvmx_error_display;
6250     info.user_info          = (long)
6251         "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CNTL0[RST_RCV]=1\n"
6252         "    and MIO_RST_CNTL0[RST_CHIP]=0\n";
6253     fail |= cvmx_error_add(&info);
6254
6255     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6256     info.status_addr        = CVMX_MIO_RST_INT;
6257     info.status_mask        = 1ull<<9 /* perst1 */;
6258     info.enable_addr        = CVMX_MIO_RST_INT_EN;
6259     info.enable_mask        = 1ull<<9 /* perst1 */;
6260     info.flags              = 0;
6261     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6262     info.group_index        = 0;
6263     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6264     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6265     info.parent.status_mask = 1ull<<0 /* mio */;
6266     info.func               = __cvmx_error_display;
6267     info.user_info          = (long)
6268         "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CNTL1[RST_RCV]=1\n"
6269         "    and MIO_RST_CNTL1[RST_CHIP]=0\n";
6270     fail |= cvmx_error_add(&info);
6271
6272     /* CVMX_DFM_FNT_STAT */
6273     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6274     info.status_addr        = CVMX_DFM_FNT_STAT;
6275     info.status_mask        = 1ull<<0 /* sbe_err */;
6276     info.enable_addr        = CVMX_DFM_FNT_IENA;
6277     info.enable_mask        = 1ull<<0 /* sbe_intena */;
6278     info.flags              = 0;
6279     info.group              = CVMX_ERROR_GROUP_DFM;
6280     info.group_index        = 0;
6281     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6282     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6283     info.parent.status_mask = 1ull<<40 /* dfm */;
6284     info.func               = __cvmx_error_display;
6285     info.user_info          = (long)
6286         "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
6287         "    Memory Read.\n"
6288         "    Write of 1 will clear the corresponding error bit\n";
6289     fail |= cvmx_error_add(&info);
6290
6291     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6292     info.status_addr        = CVMX_DFM_FNT_STAT;
6293     info.status_mask        = 1ull<<1 /* dbe_err */;
6294     info.enable_addr        = CVMX_DFM_FNT_IENA;
6295     info.enable_mask        = 1ull<<1 /* dbe_intena */;
6296     info.flags              = 0;
6297     info.group              = CVMX_ERROR_GROUP_DFM;
6298     info.group_index        = 0;
6299     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6300     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6301     info.parent.status_mask = 1ull<<40 /* dfm */;
6302     info.func               = __cvmx_error_display;
6303     info.user_info          = (long)
6304         "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
6305         "    Memory Read.\n"
6306         "    Write of 1 will clear the corresponding error bit\n";
6307     fail |= cvmx_error_add(&info);
6308
6309     /* CVMX_TIM_REG_ERROR */
6310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6311     info.status_addr        = CVMX_TIM_REG_ERROR;
6312     info.status_mask        = 0xffffull<<0 /* mask */;
6313     info.enable_addr        = CVMX_TIM_REG_INT_MASK;
6314     info.enable_mask        = 0xffffull<<0 /* mask */;
6315     info.flags              = 0;
6316     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6317     info.group_index        = 0;
6318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6319     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6320     info.parent.status_mask = 1ull<<11 /* tim */;
6321     info.func               = __cvmx_error_display;
6322     info.user_info          = (long)
6323         "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
6324     fail |= cvmx_error_add(&info);
6325
6326     /* CVMX_LMCX_INT(0) */
6327     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6328     info.status_addr        = CVMX_LMCX_INT(0);
6329     info.status_mask        = 0xfull<<1 /* sec_err */;
6330     info.enable_addr        = CVMX_LMCX_INT_EN(0);
6331     info.enable_mask        = 1ull<<1 /* intr_sec_ena */;
6332     info.flags              = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
6333     info.group              = CVMX_ERROR_GROUP_LMC;
6334     info.group_index        = 0;
6335     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6336     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6337     info.parent.status_mask = 1ull<<17 /* lmc0 */;
6338     info.func               = __cvmx_error_display;
6339     info.user_info          = (long)
6340         "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
6341         "    [0] corresponds to DQ[63:0]_c0_p0\n"
6342         "    [1] corresponds to DQ[63:0]_c0_p1\n"
6343         "    [2] corresponds to DQ[63:0]_c1_p0\n"
6344         "    [3] corresponds to DQ[63:0]_c1_p1\n"
6345         "    where _cC_pP denotes cycle C and phase P\n"
6346         "    Write of 1 will clear the corresponding error bit\n";
6347     fail |= cvmx_error_add(&info);
6348
6349     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6350     info.status_addr        = CVMX_LMCX_INT(0);
6351     info.status_mask        = 1ull<<0 /* nxm_wr_err */;
6352     info.enable_addr        = CVMX_LMCX_INT_EN(0);
6353     info.enable_mask        = 1ull<<0 /* intr_nxm_wr_ena */;
6354     info.flags              = 0;
6355     info.group              = CVMX_ERROR_GROUP_LMC;
6356     info.group_index        = 0;
6357     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6358     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6359     info.parent.status_mask = 1ull<<17 /* lmc0 */;
6360     info.func               = __cvmx_error_display;
6361     info.user_info          = (long)
6362         "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
6363         "    Write of 1 will clear the corresponding error bit\n";
6364     fail |= cvmx_error_add(&info);
6365
6366     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6367     info.status_addr        = CVMX_LMCX_INT(0);
6368     info.status_mask        = 0xfull<<5 /* ded_err */;
6369     info.enable_addr        = CVMX_LMCX_INT_EN(0);
6370     info.enable_mask        = 1ull<<2 /* intr_ded_ena */;
6371     info.flags              = 0;
6372     info.group              = CVMX_ERROR_GROUP_LMC;
6373     info.group_index        = 0;
6374     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6375     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6376     info.parent.status_mask = 1ull<<17 /* lmc0 */;
6377     info.func               = __cvmx_error_display;
6378     info.user_info          = (long)
6379         "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
6380         "    [0] corresponds to DQ[63:0]_c0_p0\n"
6381         "    [1] corresponds to DQ[63:0]_c0_p1\n"
6382         "    [2] corresponds to DQ[63:0]_c1_p0\n"
6383         "    [3] corresponds to DQ[63:0]_c1_p1\n"
6384         "    where _cC_pP denotes cycle C and phase P\n"
6385         "    Write of 1 will clear the corresponding error bit\n";
6386     fail |= cvmx_error_add(&info);
6387
6388     /* CVMX_KEY_INT_SUM */
6389     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6390     info.status_addr        = CVMX_KEY_INT_SUM;
6391     info.status_mask        = 1ull<<0 /* ked0_sbe */;
6392     info.enable_addr        = CVMX_KEY_INT_ENB;
6393     info.enable_mask        = 1ull<<0 /* ked0_sbe */;
6394     info.flags              = 0;
6395     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6396     info.group_index        = 0;
6397     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6398     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6399     info.parent.status_mask = 1ull<<4 /* key */;
6400     info.func               = __cvmx_error_display;
6401     info.user_info          = (long)
6402         "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
6403 ;
6404     fail |= cvmx_error_add(&info);
6405
6406     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6407     info.status_addr        = CVMX_KEY_INT_SUM;
6408     info.status_mask        = 1ull<<1 /* ked0_dbe */;
6409     info.enable_addr        = CVMX_KEY_INT_ENB;
6410     info.enable_mask        = 1ull<<1 /* ked0_dbe */;
6411     info.flags              = 0;
6412     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6413     info.group_index        = 0;
6414     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6415     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6416     info.parent.status_mask = 1ull<<4 /* key */;
6417     info.func               = __cvmx_error_display;
6418     info.user_info          = (long)
6419         "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
6420 ;
6421     fail |= cvmx_error_add(&info);
6422
6423     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6424     info.status_addr        = CVMX_KEY_INT_SUM;
6425     info.status_mask        = 1ull<<2 /* ked1_sbe */;
6426     info.enable_addr        = CVMX_KEY_INT_ENB;
6427     info.enable_mask        = 1ull<<2 /* ked1_sbe */;
6428     info.flags              = 0;
6429     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6430     info.group_index        = 0;
6431     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6432     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6433     info.parent.status_mask = 1ull<<4 /* key */;
6434     info.func               = __cvmx_error_display;
6435     info.user_info          = (long)
6436         "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
6437 ;
6438     fail |= cvmx_error_add(&info);
6439
6440     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6441     info.status_addr        = CVMX_KEY_INT_SUM;
6442     info.status_mask        = 1ull<<3 /* ked1_dbe */;
6443     info.enable_addr        = CVMX_KEY_INT_ENB;
6444     info.enable_mask        = 1ull<<3 /* ked1_dbe */;
6445     info.flags              = 0;
6446     info.group              = CVMX_ERROR_GROUP_INTERNAL;
6447     info.group_index        = 0;
6448     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6449     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6450     info.parent.status_mask = 1ull<<4 /* key */;
6451     info.func               = __cvmx_error_display;
6452     info.user_info          = (long)
6453         "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
6454 ;
6455     fail |= cvmx_error_add(&info);
6456
6457     /* CVMX_GMXX_BAD_REG(0) */
6458     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6459     info.status_addr        = CVMX_GMXX_BAD_REG(0);
6460     info.status_mask        = 0xfull<<2 /* out_ovr */;
6461     info.enable_addr        = 0;
6462     info.enable_mask        = 0;
6463     info.flags              = 0;
6464     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6465     info.group_index        = 0;
6466     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6467     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6468     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6469     info.func               = __cvmx_error_display;
6470     info.user_info          = (long)
6471         "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
6472     fail |= cvmx_error_add(&info);
6473
6474     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6475     info.status_addr        = CVMX_GMXX_BAD_REG(0);
6476     info.status_mask        = 0xfull<<22 /* loststat */;
6477     info.enable_addr        = 0;
6478     info.enable_mask        = 0;
6479     info.flags              = 0;
6480     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6481     info.group_index        = 0;
6482     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6483     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6484     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6485     info.func               = __cvmx_error_display;
6486     info.user_info          = (long)
6487         "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
6488         "    In SGMII, one bit per port\n"
6489         "    In XAUI, only port0 is used\n"
6490         "    TX Stats are corrupted\n";
6491     fail |= cvmx_error_add(&info);
6492
6493     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6494     info.status_addr        = CVMX_GMXX_BAD_REG(0);
6495     info.status_mask        = 1ull<<26 /* statovr */;
6496     info.enable_addr        = 0;
6497     info.enable_mask        = 0;
6498     info.flags              = 0;
6499     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6500     info.group_index        = 0;
6501     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6502     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6503     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6504     info.func               = __cvmx_error_display;
6505     info.user_info          = (long)
6506         "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
6507         "    The common FIFO to SGMII and XAUI had an overflow\n"
6508         "    TX Stats are corrupted\n";
6509     fail |= cvmx_error_add(&info);
6510
6511     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6512     info.status_addr        = CVMX_GMXX_BAD_REG(0);
6513     info.status_mask        = 0xfull<<27 /* inb_nxa */;
6514     info.enable_addr        = 0;
6515     info.enable_mask        = 0;
6516     info.flags              = 0;
6517     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6518     info.group_index        = 0;
6519     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6520     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6521     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6522     info.func               = __cvmx_error_display;
6523     info.user_info          = (long)
6524         "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
6525     fail |= cvmx_error_add(&info);
6526
6527     /* CVMX_GMXX_RXX_INT_REG(0,0) */
6528     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6529     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6530     info.status_mask        = 1ull<<1 /* carext */;
6531     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6532     info.enable_mask        = 1ull<<1 /* carext */;
6533     info.flags              = 0;
6534     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6535     info.group_index        = 0;
6536     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6537     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6538     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6539     info.func               = __cvmx_error_display;
6540     info.user_info          = (long)
6541         "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
6542         "    (SGMII/1000Base-X only)\n";
6543     fail |= cvmx_error_add(&info);
6544
6545     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6546     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6547     info.status_mask        = 1ull<<8 /* skperr */;
6548     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6549     info.enable_mask        = 1ull<<8 /* skperr */;
6550     info.flags              = 0;
6551     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6552     info.group_index        = 0;
6553     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6554     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6555     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6556     info.func               = __cvmx_error_display;
6557     info.user_info          = (long)
6558         "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
6559     fail |= cvmx_error_add(&info);
6560
6561     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6562     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6563     info.status_mask        = 1ull<<10 /* ovrerr */;
6564     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6565     info.enable_mask        = 1ull<<10 /* ovrerr */;
6566     info.flags              = 0;
6567     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6568     info.group_index        = 0;
6569     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6570     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6571     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6572     info.func               = __cvmx_error_display;
6573     info.user_info          = (long)
6574         "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
6575         "    This interrupt should never assert\n"
6576         "    (SGMII/1000Base-X only)\n";
6577     fail |= cvmx_error_add(&info);
6578
6579     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6580     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6581     info.status_mask        = 1ull<<20 /* loc_fault */;
6582     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6583     info.enable_mask        = 1ull<<20 /* loc_fault */;
6584     info.flags              = 0;
6585     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6586     info.group_index        = 0;
6587     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6588     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6589     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6590     info.func               = __cvmx_error_display;
6591     info.user_info          = (long)
6592         "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
6593         "    (XAUI Mode only)\n";
6594     fail |= cvmx_error_add(&info);
6595
6596     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6597     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6598     info.status_mask        = 1ull<<21 /* rem_fault */;
6599     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6600     info.enable_mask        = 1ull<<21 /* rem_fault */;
6601     info.flags              = 0;
6602     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6603     info.group_index        = 0;
6604     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6605     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6606     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6607     info.func               = __cvmx_error_display;
6608     info.user_info          = (long)
6609         "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
6610         "    (XAUI Mode only)\n";
6611     fail |= cvmx_error_add(&info);
6612
6613     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6614     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6615     info.status_mask        = 1ull<<22 /* bad_seq */;
6616     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6617     info.enable_mask        = 1ull<<22 /* bad_seq */;
6618     info.flags              = 0;
6619     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6620     info.group_index        = 0;
6621     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6622     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6623     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6624     info.func               = __cvmx_error_display;
6625     info.user_info          = (long)
6626         "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
6627         "    (XAUI Mode only)\n";
6628     fail |= cvmx_error_add(&info);
6629
6630     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6631     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6632     info.status_mask        = 1ull<<23 /* bad_term */;
6633     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6634     info.enable_mask        = 1ull<<23 /* bad_term */;
6635     info.flags              = 0;
6636     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6637     info.group_index        = 0;
6638     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6639     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6640     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6641     info.func               = __cvmx_error_display;
6642     info.user_info          = (long)
6643         "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
6644         "    than /T/.  The error propagation control\n"
6645         "    character /E/ will be included as part of the\n"
6646         "    frame and does not cause a frame termination.\n"
6647         "    (XAUI Mode only)\n";
6648     fail |= cvmx_error_add(&info);
6649
6650     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6651     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6652     info.status_mask        = 1ull<<24 /* unsop */;
6653     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6654     info.enable_mask        = 1ull<<24 /* unsop */;
6655     info.flags              = 0;
6656     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6657     info.group_index        = 0;
6658     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6659     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6660     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6661     info.func               = __cvmx_error_display;
6662     info.user_info          = (long)
6663         "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
6664         "    (XAUI Mode only)\n";
6665     fail |= cvmx_error_add(&info);
6666
6667     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6668     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6669     info.status_mask        = 1ull<<25 /* uneop */;
6670     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6671     info.enable_mask        = 1ull<<25 /* uneop */;
6672     info.flags              = 0;
6673     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6674     info.group_index        = 0;
6675     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6676     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6677     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6678     info.func               = __cvmx_error_display;
6679     info.user_info          = (long)
6680         "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
6681         "    (XAUI Mode only)\n";
6682     fail |= cvmx_error_add(&info);
6683
6684     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6685     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6686     info.status_mask        = 1ull<<26 /* undat */;
6687     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6688     info.enable_mask        = 1ull<<26 /* undat */;
6689     info.flags              = 0;
6690     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6691     info.group_index        = 0;
6692     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6693     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6694     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6695     info.func               = __cvmx_error_display;
6696     info.user_info          = (long)
6697         "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
6698         "    (XAUI Mode only)\n";
6699     fail |= cvmx_error_add(&info);
6700
6701     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6702     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6703     info.status_mask        = 1ull<<27 /* hg2fld */;
6704     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6705     info.enable_mask        = 1ull<<27 /* hg2fld */;
6706     info.flags              = 0;
6707     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6708     info.group_index        = 0;
6709     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6710     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6711     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6712     info.func               = __cvmx_error_display;
6713     info.user_info          = (long)
6714         "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
6715         "    1) MSG_TYPE field not 6'b00_0000\n"
6716         "       i.e. it is not a FLOW CONTROL message, which\n"
6717         "       is the only defined type for HiGig2\n"
6718         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
6719         "       which is the only defined type for HiGig2\n"
6720         "    3) FC_OBJECT field is neither 4'b0000 for\n"
6721         "       Physical Link nor 4'b0010 for Logical Link.\n"
6722         "       Those are the only two defined types in HiGig2\n";
6723     fail |= cvmx_error_add(&info);
6724
6725     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6726     info.status_addr        = CVMX_GMXX_RXX_INT_REG(0,0);
6727     info.status_mask        = 1ull<<28 /* hg2cc */;
6728     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(0,0);
6729     info.enable_mask        = 1ull<<28 /* hg2cc */;
6730     info.flags              = 0;
6731     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6732     info.group_index        = 0;
6733     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6734     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6735     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6736     info.func               = __cvmx_error_display;
6737     info.user_info          = (long)
6738         "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
6739         "    Set when either CRC8 error detected or when\n"
6740         "    a Control Character is found in the message\n"
6741         "    bytes after the K.SOM\n"
6742         "    NOTE: HG2CC has higher priority than HG2FLD\n"
6743         "          i.e. a HiGig2 message that results in HG2CC\n"
6744         "          getting set, will never set HG2FLD.\n";
6745     fail |= cvmx_error_add(&info);
6746
6747     /* CVMX_GMXX_RXX_INT_REG(1,0) */
6748     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6749     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6750     info.status_mask        = 1ull<<1 /* carext */;
6751     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6752     info.enable_mask        = 1ull<<1 /* carext */;
6753     info.flags              = 0;
6754     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6755     info.group_index        = 1;
6756     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6757     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6758     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6759     info.func               = __cvmx_error_display;
6760     info.user_info          = (long)
6761         "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
6762         "    (SGMII/1000Base-X only)\n";
6763     fail |= cvmx_error_add(&info);
6764
6765     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6766     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6767     info.status_mask        = 1ull<<8 /* skperr */;
6768     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6769     info.enable_mask        = 1ull<<8 /* skperr */;
6770     info.flags              = 0;
6771     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6772     info.group_index        = 1;
6773     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6774     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6775     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6776     info.func               = __cvmx_error_display;
6777     info.user_info          = (long)
6778         "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
6779     fail |= cvmx_error_add(&info);
6780
6781     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6782     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6783     info.status_mask        = 1ull<<10 /* ovrerr */;
6784     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6785     info.enable_mask        = 1ull<<10 /* ovrerr */;
6786     info.flags              = 0;
6787     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6788     info.group_index        = 1;
6789     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6790     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6791     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6792     info.func               = __cvmx_error_display;
6793     info.user_info          = (long)
6794         "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
6795         "    This interrupt should never assert\n"
6796         "    (SGMII/1000Base-X only)\n";
6797     fail |= cvmx_error_add(&info);
6798
6799     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6800     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6801     info.status_mask        = 1ull<<20 /* loc_fault */;
6802     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6803     info.enable_mask        = 1ull<<20 /* loc_fault */;
6804     info.flags              = 0;
6805     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6806     info.group_index        = 1;
6807     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6808     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6809     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6810     info.func               = __cvmx_error_display;
6811     info.user_info          = (long)
6812         "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
6813         "    (XAUI Mode only)\n";
6814     fail |= cvmx_error_add(&info);
6815
6816     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6817     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6818     info.status_mask        = 1ull<<21 /* rem_fault */;
6819     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6820     info.enable_mask        = 1ull<<21 /* rem_fault */;
6821     info.flags              = 0;
6822     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6823     info.group_index        = 1;
6824     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6825     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6826     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6827     info.func               = __cvmx_error_display;
6828     info.user_info          = (long)
6829         "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
6830         "    (XAUI Mode only)\n";
6831     fail |= cvmx_error_add(&info);
6832
6833     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6834     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6835     info.status_mask        = 1ull<<22 /* bad_seq */;
6836     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6837     info.enable_mask        = 1ull<<22 /* bad_seq */;
6838     info.flags              = 0;
6839     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6840     info.group_index        = 1;
6841     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6842     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6843     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6844     info.func               = __cvmx_error_display;
6845     info.user_info          = (long)
6846         "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
6847         "    (XAUI Mode only)\n";
6848     fail |= cvmx_error_add(&info);
6849
6850     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6851     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6852     info.status_mask        = 1ull<<23 /* bad_term */;
6853     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6854     info.enable_mask        = 1ull<<23 /* bad_term */;
6855     info.flags              = 0;
6856     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6857     info.group_index        = 1;
6858     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6859     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6860     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6861     info.func               = __cvmx_error_display;
6862     info.user_info          = (long)
6863         "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
6864         "    than /T/.  The error propagation control\n"
6865         "    character /E/ will be included as part of the\n"
6866         "    frame and does not cause a frame termination.\n"
6867         "    (XAUI Mode only)\n";
6868     fail |= cvmx_error_add(&info);
6869
6870     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6871     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6872     info.status_mask        = 1ull<<24 /* unsop */;
6873     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6874     info.enable_mask        = 1ull<<24 /* unsop */;
6875     info.flags              = 0;
6876     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6877     info.group_index        = 1;
6878     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6879     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6880     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6881     info.func               = __cvmx_error_display;
6882     info.user_info          = (long)
6883         "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
6884         "    (XAUI Mode only)\n";
6885     fail |= cvmx_error_add(&info);
6886
6887     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6888     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6889     info.status_mask        = 1ull<<25 /* uneop */;
6890     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6891     info.enable_mask        = 1ull<<25 /* uneop */;
6892     info.flags              = 0;
6893     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6894     info.group_index        = 1;
6895     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6896     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6897     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6898     info.func               = __cvmx_error_display;
6899     info.user_info          = (long)
6900         "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
6901         "    (XAUI Mode only)\n";
6902     fail |= cvmx_error_add(&info);
6903
6904     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6905     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6906     info.status_mask        = 1ull<<26 /* undat */;
6907     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6908     info.enable_mask        = 1ull<<26 /* undat */;
6909     info.flags              = 0;
6910     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6911     info.group_index        = 1;
6912     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6913     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6914     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6915     info.func               = __cvmx_error_display;
6916     info.user_info          = (long)
6917         "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
6918         "    (XAUI Mode only)\n";
6919     fail |= cvmx_error_add(&info);
6920
6921     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6922     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6923     info.status_mask        = 1ull<<27 /* hg2fld */;
6924     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6925     info.enable_mask        = 1ull<<27 /* hg2fld */;
6926     info.flags              = 0;
6927     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6928     info.group_index        = 1;
6929     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6930     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6931     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6932     info.func               = __cvmx_error_display;
6933     info.user_info          = (long)
6934         "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
6935         "    1) MSG_TYPE field not 6'b00_0000\n"
6936         "       i.e. it is not a FLOW CONTROL message, which\n"
6937         "       is the only defined type for HiGig2\n"
6938         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
6939         "       which is the only defined type for HiGig2\n"
6940         "    3) FC_OBJECT field is neither 4'b0000 for\n"
6941         "       Physical Link nor 4'b0010 for Logical Link.\n"
6942         "       Those are the only two defined types in HiGig2\n";
6943     fail |= cvmx_error_add(&info);
6944
6945     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6946     info.status_addr        = CVMX_GMXX_RXX_INT_REG(1,0);
6947     info.status_mask        = 1ull<<28 /* hg2cc */;
6948     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(1,0);
6949     info.enable_mask        = 1ull<<28 /* hg2cc */;
6950     info.flags              = 0;
6951     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6952     info.group_index        = 1;
6953     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6954     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6955     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6956     info.func               = __cvmx_error_display;
6957     info.user_info          = (long)
6958         "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
6959         "    Set when either CRC8 error detected or when\n"
6960         "    a Control Character is found in the message\n"
6961         "    bytes after the K.SOM\n"
6962         "    NOTE: HG2CC has higher priority than HG2FLD\n"
6963         "          i.e. a HiGig2 message that results in HG2CC\n"
6964         "          getting set, will never set HG2FLD.\n";
6965     fail |= cvmx_error_add(&info);
6966
6967     /* CVMX_GMXX_RXX_INT_REG(2,0) */
6968     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6969     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
6970     info.status_mask        = 1ull<<1 /* carext */;
6971     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
6972     info.enable_mask        = 1ull<<1 /* carext */;
6973     info.flags              = 0;
6974     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6975     info.group_index        = 2;
6976     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6977     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6978     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6979     info.func               = __cvmx_error_display;
6980     info.user_info          = (long)
6981         "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
6982         "    (SGMII/1000Base-X only)\n";
6983     fail |= cvmx_error_add(&info);
6984
6985     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
6986     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
6987     info.status_mask        = 1ull<<8 /* skperr */;
6988     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
6989     info.enable_mask        = 1ull<<8 /* skperr */;
6990     info.flags              = 0;
6991     info.group              = CVMX_ERROR_GROUP_ETHERNET;
6992     info.group_index        = 2;
6993     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
6994     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6995     info.parent.status_mask = 1ull<<1 /* gmx0 */;
6996     info.func               = __cvmx_error_display;
6997     info.user_info          = (long)
6998         "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
6999     fail |= cvmx_error_add(&info);
7000
7001     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7002     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7003     info.status_mask        = 1ull<<10 /* ovrerr */;
7004     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7005     info.enable_mask        = 1ull<<10 /* ovrerr */;
7006     info.flags              = 0;
7007     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7008     info.group_index        = 2;
7009     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7010     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7011     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7012     info.func               = __cvmx_error_display;
7013     info.user_info          = (long)
7014         "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
7015         "    This interrupt should never assert\n"
7016         "    (SGMII/1000Base-X only)\n";
7017     fail |= cvmx_error_add(&info);
7018
7019     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7020     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7021     info.status_mask        = 1ull<<20 /* loc_fault */;
7022     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7023     info.enable_mask        = 1ull<<20 /* loc_fault */;
7024     info.flags              = 0;
7025     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7026     info.group_index        = 2;
7027     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7028     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7029     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7030     info.func               = __cvmx_error_display;
7031     info.user_info          = (long)
7032         "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
7033         "    (XAUI Mode only)\n";
7034     fail |= cvmx_error_add(&info);
7035
7036     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7037     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7038     info.status_mask        = 1ull<<21 /* rem_fault */;
7039     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7040     info.enable_mask        = 1ull<<21 /* rem_fault */;
7041     info.flags              = 0;
7042     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7043     info.group_index        = 2;
7044     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7045     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7046     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7047     info.func               = __cvmx_error_display;
7048     info.user_info          = (long)
7049         "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
7050         "    (XAUI Mode only)\n";
7051     fail |= cvmx_error_add(&info);
7052
7053     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7054     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7055     info.status_mask        = 1ull<<22 /* bad_seq */;
7056     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7057     info.enable_mask        = 1ull<<22 /* bad_seq */;
7058     info.flags              = 0;
7059     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7060     info.group_index        = 2;
7061     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7062     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7063     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7064     info.func               = __cvmx_error_display;
7065     info.user_info          = (long)
7066         "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
7067         "    (XAUI Mode only)\n";
7068     fail |= cvmx_error_add(&info);
7069
7070     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7071     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7072     info.status_mask        = 1ull<<23 /* bad_term */;
7073     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7074     info.enable_mask        = 1ull<<23 /* bad_term */;
7075     info.flags              = 0;
7076     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7077     info.group_index        = 2;
7078     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7079     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7080     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7081     info.func               = __cvmx_error_display;
7082     info.user_info          = (long)
7083         "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
7084         "    than /T/.  The error propagation control\n"
7085         "    character /E/ will be included as part of the\n"
7086         "    frame and does not cause a frame termination.\n"
7087         "    (XAUI Mode only)\n";
7088     fail |= cvmx_error_add(&info);
7089
7090     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7091     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7092     info.status_mask        = 1ull<<24 /* unsop */;
7093     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7094     info.enable_mask        = 1ull<<24 /* unsop */;
7095     info.flags              = 0;
7096     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7097     info.group_index        = 2;
7098     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7099     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7100     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7101     info.func               = __cvmx_error_display;
7102     info.user_info          = (long)
7103         "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
7104         "    (XAUI Mode only)\n";
7105     fail |= cvmx_error_add(&info);
7106
7107     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7108     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7109     info.status_mask        = 1ull<<25 /* uneop */;
7110     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7111     info.enable_mask        = 1ull<<25 /* uneop */;
7112     info.flags              = 0;
7113     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7114     info.group_index        = 2;
7115     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7116     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7117     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7118     info.func               = __cvmx_error_display;
7119     info.user_info          = (long)
7120         "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
7121         "    (XAUI Mode only)\n";
7122     fail |= cvmx_error_add(&info);
7123
7124     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7125     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7126     info.status_mask        = 1ull<<26 /* undat */;
7127     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7128     info.enable_mask        = 1ull<<26 /* undat */;
7129     info.flags              = 0;
7130     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7131     info.group_index        = 2;
7132     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7133     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7134     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7135     info.func               = __cvmx_error_display;
7136     info.user_info          = (long)
7137         "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
7138         "    (XAUI Mode only)\n";
7139     fail |= cvmx_error_add(&info);
7140
7141     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7142     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7143     info.status_mask        = 1ull<<27 /* hg2fld */;
7144     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7145     info.enable_mask        = 1ull<<27 /* hg2fld */;
7146     info.flags              = 0;
7147     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7148     info.group_index        = 2;
7149     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7150     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7151     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7152     info.func               = __cvmx_error_display;
7153     info.user_info          = (long)
7154         "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
7155         "    1) MSG_TYPE field not 6'b00_0000\n"
7156         "       i.e. it is not a FLOW CONTROL message, which\n"
7157         "       is the only defined type for HiGig2\n"
7158         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
7159         "       which is the only defined type for HiGig2\n"
7160         "    3) FC_OBJECT field is neither 4'b0000 for\n"
7161         "       Physical Link nor 4'b0010 for Logical Link.\n"
7162         "       Those are the only two defined types in HiGig2\n";
7163     fail |= cvmx_error_add(&info);
7164
7165     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7166     info.status_addr        = CVMX_GMXX_RXX_INT_REG(2,0);
7167     info.status_mask        = 1ull<<28 /* hg2cc */;
7168     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(2,0);
7169     info.enable_mask        = 1ull<<28 /* hg2cc */;
7170     info.flags              = 0;
7171     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7172     info.group_index        = 2;
7173     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7174     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7175     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7176     info.func               = __cvmx_error_display;
7177     info.user_info          = (long)
7178         "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
7179         "    Set when either CRC8 error detected or when\n"
7180         "    a Control Character is found in the message\n"
7181         "    bytes after the K.SOM\n"
7182         "    NOTE: HG2CC has higher priority than HG2FLD\n"
7183         "          i.e. a HiGig2 message that results in HG2CC\n"
7184         "          getting set, will never set HG2FLD.\n";
7185     fail |= cvmx_error_add(&info);
7186
7187     /* CVMX_GMXX_RXX_INT_REG(3,0) */
7188     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7189     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7190     info.status_mask        = 1ull<<1 /* carext */;
7191     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7192     info.enable_mask        = 1ull<<1 /* carext */;
7193     info.flags              = 0;
7194     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7195     info.group_index        = 3;
7196     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7197     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7198     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7199     info.func               = __cvmx_error_display;
7200     info.user_info          = (long)
7201         "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
7202         "    (SGMII/1000Base-X only)\n";
7203     fail |= cvmx_error_add(&info);
7204
7205     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7206     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7207     info.status_mask        = 1ull<<8 /* skperr */;
7208     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7209     info.enable_mask        = 1ull<<8 /* skperr */;
7210     info.flags              = 0;
7211     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7212     info.group_index        = 3;
7213     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7214     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7215     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7216     info.func               = __cvmx_error_display;
7217     info.user_info          = (long)
7218         "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
7219     fail |= cvmx_error_add(&info);
7220
7221     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7222     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7223     info.status_mask        = 1ull<<10 /* ovrerr */;
7224     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7225     info.enable_mask        = 1ull<<10 /* ovrerr */;
7226     info.flags              = 0;
7227     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7228     info.group_index        = 3;
7229     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7230     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7231     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7232     info.func               = __cvmx_error_display;
7233     info.user_info          = (long)
7234         "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
7235         "    This interrupt should never assert\n"
7236         "    (SGMII/1000Base-X only)\n";
7237     fail |= cvmx_error_add(&info);
7238
7239     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7240     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7241     info.status_mask        = 1ull<<20 /* loc_fault */;
7242     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7243     info.enable_mask        = 1ull<<20 /* loc_fault */;
7244     info.flags              = 0;
7245     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7246     info.group_index        = 3;
7247     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7248     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7249     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7250     info.func               = __cvmx_error_display;
7251     info.user_info          = (long)
7252         "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
7253         "    (XAUI Mode only)\n";
7254     fail |= cvmx_error_add(&info);
7255
7256     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7257     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7258     info.status_mask        = 1ull<<21 /* rem_fault */;
7259     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7260     info.enable_mask        = 1ull<<21 /* rem_fault */;
7261     info.flags              = 0;
7262     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7263     info.group_index        = 3;
7264     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7265     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7266     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7267     info.func               = __cvmx_error_display;
7268     info.user_info          = (long)
7269         "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
7270         "    (XAUI Mode only)\n";
7271     fail |= cvmx_error_add(&info);
7272
7273     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7274     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7275     info.status_mask        = 1ull<<22 /* bad_seq */;
7276     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7277     info.enable_mask        = 1ull<<22 /* bad_seq */;
7278     info.flags              = 0;
7279     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7280     info.group_index        = 3;
7281     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7282     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7283     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7284     info.func               = __cvmx_error_display;
7285     info.user_info          = (long)
7286         "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
7287         "    (XAUI Mode only)\n";
7288     fail |= cvmx_error_add(&info);
7289
7290     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7291     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7292     info.status_mask        = 1ull<<23 /* bad_term */;
7293     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7294     info.enable_mask        = 1ull<<23 /* bad_term */;
7295     info.flags              = 0;
7296     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7297     info.group_index        = 3;
7298     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7299     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7300     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7301     info.func               = __cvmx_error_display;
7302     info.user_info          = (long)
7303         "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
7304         "    than /T/.  The error propagation control\n"
7305         "    character /E/ will be included as part of the\n"
7306         "    frame and does not cause a frame termination.\n"
7307         "    (XAUI Mode only)\n";
7308     fail |= cvmx_error_add(&info);
7309
7310     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7311     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7312     info.status_mask        = 1ull<<24 /* unsop */;
7313     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7314     info.enable_mask        = 1ull<<24 /* unsop */;
7315     info.flags              = 0;
7316     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7317     info.group_index        = 3;
7318     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7319     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7320     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7321     info.func               = __cvmx_error_display;
7322     info.user_info          = (long)
7323         "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
7324         "    (XAUI Mode only)\n";
7325     fail |= cvmx_error_add(&info);
7326
7327     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7328     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7329     info.status_mask        = 1ull<<25 /* uneop */;
7330     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7331     info.enable_mask        = 1ull<<25 /* uneop */;
7332     info.flags              = 0;
7333     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7334     info.group_index        = 3;
7335     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7336     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7337     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7338     info.func               = __cvmx_error_display;
7339     info.user_info          = (long)
7340         "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
7341         "    (XAUI Mode only)\n";
7342     fail |= cvmx_error_add(&info);
7343
7344     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7345     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7346     info.status_mask        = 1ull<<26 /* undat */;
7347     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7348     info.enable_mask        = 1ull<<26 /* undat */;
7349     info.flags              = 0;
7350     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7351     info.group_index        = 3;
7352     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7353     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7354     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7355     info.func               = __cvmx_error_display;
7356     info.user_info          = (long)
7357         "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
7358         "    (XAUI Mode only)\n";
7359     fail |= cvmx_error_add(&info);
7360
7361     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7362     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7363     info.status_mask        = 1ull<<27 /* hg2fld */;
7364     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7365     info.enable_mask        = 1ull<<27 /* hg2fld */;
7366     info.flags              = 0;
7367     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7368     info.group_index        = 3;
7369     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7370     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7371     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7372     info.func               = __cvmx_error_display;
7373     info.user_info          = (long)
7374         "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
7375         "    1) MSG_TYPE field not 6'b00_0000\n"
7376         "       i.e. it is not a FLOW CONTROL message, which\n"
7377         "       is the only defined type for HiGig2\n"
7378         "    2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
7379         "       which is the only defined type for HiGig2\n"
7380         "    3) FC_OBJECT field is neither 4'b0000 for\n"
7381         "       Physical Link nor 4'b0010 for Logical Link.\n"
7382         "       Those are the only two defined types in HiGig2\n";
7383     fail |= cvmx_error_add(&info);
7384
7385     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7386     info.status_addr        = CVMX_GMXX_RXX_INT_REG(3,0);
7387     info.status_mask        = 1ull<<28 /* hg2cc */;
7388     info.enable_addr        = CVMX_GMXX_RXX_INT_EN(3,0);
7389     info.enable_mask        = 1ull<<28 /* hg2cc */;
7390     info.flags              = 0;
7391     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7392     info.group_index        = 3;
7393     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7394     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7395     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7396     info.func               = __cvmx_error_display;
7397     info.user_info          = (long)
7398         "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char  error\n"
7399         "    Set when either CRC8 error detected or when\n"
7400         "    a Control Character is found in the message\n"
7401         "    bytes after the K.SOM\n"
7402         "    NOTE: HG2CC has higher priority than HG2FLD\n"
7403         "          i.e. a HiGig2 message that results in HG2CC\n"
7404         "          getting set, will never set HG2FLD.\n";
7405     fail |= cvmx_error_add(&info);
7406
7407     /* CVMX_GMXX_TX_INT_REG(0) */
7408     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7409     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
7410     info.status_mask        = 1ull<<0 /* pko_nxa */;
7411     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
7412     info.enable_mask        = 1ull<<0 /* pko_nxa */;
7413     info.flags              = 0;
7414     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7415     info.group_index        = 0;
7416     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7417     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7418     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7419     info.func               = __cvmx_error_display;
7420     info.user_info          = (long)
7421         "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
7422     fail |= cvmx_error_add(&info);
7423
7424     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7425     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
7426     info.status_mask        = 0xfull<<2 /* undflw */;
7427     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
7428     info.enable_mask        = 0xfull<<2 /* undflw */;
7429     info.flags              = 0;
7430     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7431     info.group_index        = 0;
7432     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7433     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7434     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7435     info.func               = __cvmx_error_display;
7436     info.user_info          = (long)
7437         "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
7438     fail |= cvmx_error_add(&info);
7439
7440     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7441     info.status_addr        = CVMX_GMXX_TX_INT_REG(0);
7442     info.status_mask        = 0xfull<<20 /* ptp_lost */;
7443     info.enable_addr        = CVMX_GMXX_TX_INT_EN(0);
7444     info.enable_mask        = 0xfull<<20 /* ptp_lost */;
7445     info.flags              = 0;
7446     info.group              = CVMX_ERROR_GROUP_ETHERNET;
7447     info.group_index        = 0;
7448     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7449     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7450     info.parent.status_mask = 1ull<<1 /* gmx0 */;
7451     info.func               = __cvmx_error_display;
7452     info.user_info          = (long)
7453         "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
7454         "    sent due to XSCOL\n";
7455     fail |= cvmx_error_add(&info);
7456
7457     /* CVMX_IOB_INT_SUM */
7458     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7459     info.status_addr        = CVMX_IOB_INT_SUM;
7460     info.status_mask        = 1ull<<0 /* np_sop */;
7461     info.enable_addr        = CVMX_IOB_INT_ENB;
7462     info.enable_mask        = 1ull<<0 /* np_sop */;
7463     info.flags              = 0;
7464     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7465     info.group_index        = 0;
7466     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7467     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7468     info.parent.status_mask = 1ull<<30 /* iob */;
7469     info.func               = __cvmx_error_display;
7470     info.user_info          = (long)
7471         "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
7472         "    port for a non-passthrough packet.\n"
7473         "    The first detected error associated with bits [5:0]\n"
7474         "    of this register will only be set here. A new bit\n"
7475         "    can be set when the previous reported bit is cleared.\n";
7476     fail |= cvmx_error_add(&info);
7477
7478     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7479     info.status_addr        = CVMX_IOB_INT_SUM;
7480     info.status_mask        = 1ull<<1 /* np_eop */;
7481     info.enable_addr        = CVMX_IOB_INT_ENB;
7482     info.enable_mask        = 1ull<<1 /* np_eop */;
7483     info.flags              = 0;
7484     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7485     info.group_index        = 0;
7486     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7487     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7488     info.parent.status_mask = 1ull<<30 /* iob */;
7489     info.func               = __cvmx_error_display;
7490     info.user_info          = (long)
7491         "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
7492         "    port for a non-passthrough packet.\n"
7493         "    The first detected error associated with bits [5:0]\n"
7494         "    of this register will only be set here. A new bit\n"
7495         "    can be set when the previous reported bit is cleared.\n";
7496     fail |= cvmx_error_add(&info);
7497
7498     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7499     info.status_addr        = CVMX_IOB_INT_SUM;
7500     info.status_mask        = 1ull<<2 /* p_sop */;
7501     info.enable_addr        = CVMX_IOB_INT_ENB;
7502     info.enable_mask        = 1ull<<2 /* p_sop */;
7503     info.flags              = 0;
7504     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7505     info.group_index        = 0;
7506     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7507     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7508     info.parent.status_mask = 1ull<<30 /* iob */;
7509     info.func               = __cvmx_error_display;
7510     info.user_info          = (long)
7511         "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
7512         "    port for a passthrough packet.\n"
7513         "    The first detected error associated with bits [5:0]\n"
7514         "    of this register will only be set here. A new bit\n"
7515         "    can be set when the previous reported bit is cleared.\n";
7516     fail |= cvmx_error_add(&info);
7517
7518     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7519     info.status_addr        = CVMX_IOB_INT_SUM;
7520     info.status_mask        = 1ull<<3 /* p_eop */;
7521     info.enable_addr        = CVMX_IOB_INT_ENB;
7522     info.enable_mask        = 1ull<<3 /* p_eop */;
7523     info.flags              = 0;
7524     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7525     info.group_index        = 0;
7526     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7527     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7528     info.parent.status_mask = 1ull<<30 /* iob */;
7529     info.func               = __cvmx_error_display;
7530     info.user_info          = (long)
7531         "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
7532         "    port for a passthrough packet.\n"
7533         "    The first detected error associated with bits [5:0]\n"
7534         "    of this register will only be set here. A new bit\n"
7535         "    can be set when the previous reported bit is cleared.\n";
7536     fail |= cvmx_error_add(&info);
7537
7538     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7539     info.status_addr        = CVMX_IOB_INT_SUM;
7540     info.status_mask        = 1ull<<4 /* np_dat */;
7541     info.enable_addr        = CVMX_IOB_INT_ENB;
7542     info.enable_mask        = 1ull<<4 /* np_dat */;
7543     info.flags              = 0;
7544     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7545     info.group_index        = 0;
7546     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7547     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7548     info.parent.status_mask = 1ull<<30 /* iob */;
7549     info.func               = __cvmx_error_display;
7550     info.user_info          = (long)
7551         "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
7552         "    port for a non-passthrough packet.\n"
7553         "    The first detected error associated with bits [5:0]\n"
7554         "    of this register will only be set here. A new bit\n"
7555         "    can be set when the previous reported bit is cleared.\n";
7556     fail |= cvmx_error_add(&info);
7557
7558     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7559     info.status_addr        = CVMX_IOB_INT_SUM;
7560     info.status_mask        = 1ull<<5 /* p_dat */;
7561     info.enable_addr        = CVMX_IOB_INT_ENB;
7562     info.enable_mask        = 1ull<<5 /* p_dat */;
7563     info.flags              = 0;
7564     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7565     info.group_index        = 0;
7566     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7567     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7568     info.parent.status_mask = 1ull<<30 /* iob */;
7569     info.func               = __cvmx_error_display;
7570     info.user_info          = (long)
7571         "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
7572         "    port for a passthrough packet.\n"
7573         "    The first detected error associated with bits [5:0]\n"
7574         "    of this register will only be set here. A new bit\n"
7575         "    can be set when the previous reported bit is cleared.\n";
7576     fail |= cvmx_error_add(&info);
7577
7578     /* CVMX_UCTLX_INT_REG(0) */
7579     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7580     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7581     info.status_mask        = 1ull<<0 /* pp_psh_f */;
7582     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7583     info.enable_mask        = 1ull<<0 /* pp_psh_f */;
7584     info.flags              = 0;
7585     info.group              = CVMX_ERROR_GROUP_USB;
7586     info.group_index        = 0;
7587     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7588     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7589     info.parent.status_mask = 1ull<<13 /* usb */;
7590     info.func               = __cvmx_error_display;
7591     info.user_info          = (long)
7592         "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO  Pushed When Full\n";
7593     fail |= cvmx_error_add(&info);
7594
7595     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7596     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7597     info.status_mask        = 1ull<<1 /* er_psh_f */;
7598     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7599     info.enable_mask        = 1ull<<1 /* er_psh_f */;
7600     info.flags              = 0;
7601     info.group              = CVMX_ERROR_GROUP_USB;
7602     info.group_index        = 0;
7603     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7604     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7605     info.parent.status_mask = 1ull<<13 /* usb */;
7606     info.func               = __cvmx_error_display;
7607     info.user_info          = (long)
7608         "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
7609     fail |= cvmx_error_add(&info);
7610
7611     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7612     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7613     info.status_mask        = 1ull<<2 /* or_psh_f */;
7614     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7615     info.enable_mask        = 1ull<<2 /* or_psh_f */;
7616     info.flags              = 0;
7617     info.group              = CVMX_ERROR_GROUP_USB;
7618     info.group_index        = 0;
7619     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7620     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7621     info.parent.status_mask = 1ull<<13 /* usb */;
7622     info.func               = __cvmx_error_display;
7623     info.user_info          = (long)
7624         "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
7625     fail |= cvmx_error_add(&info);
7626
7627     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7628     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7629     info.status_mask        = 1ull<<3 /* cf_psh_f */;
7630     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7631     info.enable_mask        = 1ull<<3 /* cf_psh_f */;
7632     info.flags              = 0;
7633     info.group              = CVMX_ERROR_GROUP_USB;
7634     info.group_index        = 0;
7635     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7636     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7637     info.parent.status_mask = 1ull<<13 /* usb */;
7638     info.func               = __cvmx_error_display;
7639     info.user_info          = (long)
7640         "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
7641     fail |= cvmx_error_add(&info);
7642
7643     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7644     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7645     info.status_mask        = 1ull<<4 /* wb_psh_f */;
7646     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7647     info.enable_mask        = 1ull<<4 /* wb_psh_f */;
7648     info.flags              = 0;
7649     info.group              = CVMX_ERROR_GROUP_USB;
7650     info.group_index        = 0;
7651     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7652     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7653     info.parent.status_mask = 1ull<<13 /* usb */;
7654     info.func               = __cvmx_error_display;
7655     info.user_info          = (long)
7656         "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
7657     fail |= cvmx_error_add(&info);
7658
7659     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7660     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7661     info.status_mask        = 1ull<<5 /* wb_pop_e */;
7662     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7663     info.enable_mask        = 1ull<<5 /* wb_pop_e */;
7664     info.flags              = 0;
7665     info.group              = CVMX_ERROR_GROUP_USB;
7666     info.group_index        = 0;
7667     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7668     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7669     info.parent.status_mask = 1ull<<13 /* usb */;
7670     info.func               = __cvmx_error_display;
7671     info.user_info          = (long)
7672         "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
7673     fail |= cvmx_error_add(&info);
7674
7675     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7676     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7677     info.status_mask        = 1ull<<6 /* oc_ovf_e */;
7678     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7679     info.enable_mask        = 1ull<<6 /* oc_ovf_e */;
7680     info.flags              = 0;
7681     info.group              = CVMX_ERROR_GROUP_USB;
7682     info.group_index        = 0;
7683     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7684     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7685     info.parent.status_mask = 1ull<<13 /* usb */;
7686     info.func               = __cvmx_error_display;
7687     info.user_info          = (long)
7688         "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
7689         "    When the error happenes, the whole NCB system needs\n"
7690         "    to be reset.\n";
7691     fail |= cvmx_error_add(&info);
7692
7693     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7694     info.status_addr        = CVMX_UCTLX_INT_REG(0);
7695     info.status_mask        = 1ull<<7 /* ec_ovf_e */;
7696     info.enable_addr        = CVMX_UCTLX_INT_ENA(0);
7697     info.enable_mask        = 1ull<<7 /* ec_ovf_e */;
7698     info.flags              = 0;
7699     info.group              = CVMX_ERROR_GROUP_USB;
7700     info.group_index        = 0;
7701     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7702     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7703     info.parent.status_mask = 1ull<<13 /* usb */;
7704     info.func               = __cvmx_error_display;
7705     info.user_info          = (long)
7706         "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
7707         "    When the error happenes, the whole NCB system needs\n"
7708         "    to be reset.\n";
7709     fail |= cvmx_error_add(&info);
7710
7711     /* CVMX_AGL_GMX_BAD_REG */
7712     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7713     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7714     info.status_mask        = 1ull<<32 /* ovrflw */;
7715     info.enable_addr        = 0;
7716     info.enable_mask        = 0;
7717     info.flags              = 0;
7718     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7719     info.group_index        = 0;
7720     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7721     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7722     info.parent.status_mask = 1ull<<28 /* agl */;
7723     info.func               = __cvmx_error_display;
7724     info.user_info          = (long)
7725         "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
7726     fail |= cvmx_error_add(&info);
7727
7728     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7729     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7730     info.status_mask        = 1ull<<33 /* txpop */;
7731     info.enable_addr        = 0;
7732     info.enable_mask        = 0;
7733     info.flags              = 0;
7734     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7735     info.group_index        = 0;
7736     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7737     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7738     info.parent.status_mask = 1ull<<28 /* agl */;
7739     info.func               = __cvmx_error_display;
7740     info.user_info          = (long)
7741         "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
7742     fail |= cvmx_error_add(&info);
7743
7744     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7745     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7746     info.status_mask        = 1ull<<34 /* txpsh */;
7747     info.enable_addr        = 0;
7748     info.enable_mask        = 0;
7749     info.flags              = 0;
7750     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7751     info.group_index        = 0;
7752     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7753     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7754     info.parent.status_mask = 1ull<<28 /* agl */;
7755     info.func               = __cvmx_error_display;
7756     info.user_info          = (long)
7757         "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
7758     fail |= cvmx_error_add(&info);
7759
7760     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7761     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7762     info.status_mask        = 1ull<<35 /* ovrflw1 */;
7763     info.enable_addr        = 0;
7764     info.enable_mask        = 0;
7765     info.flags              = 0;
7766     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7767     info.group_index        = 0;
7768     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7769     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7770     info.parent.status_mask = 1ull<<28 /* agl */;
7771     info.func               = __cvmx_error_display;
7772     info.user_info          = (long)
7773         "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
7774     fail |= cvmx_error_add(&info);
7775
7776     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7777     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7778     info.status_mask        = 1ull<<36 /* txpop1 */;
7779     info.enable_addr        = 0;
7780     info.enable_mask        = 0;
7781     info.flags              = 0;
7782     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7783     info.group_index        = 0;
7784     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7785     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7786     info.parent.status_mask = 1ull<<28 /* agl */;
7787     info.func               = __cvmx_error_display;
7788     info.user_info          = (long)
7789         "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
7790     fail |= cvmx_error_add(&info);
7791
7792     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7793     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7794     info.status_mask        = 1ull<<37 /* txpsh1 */;
7795     info.enable_addr        = 0;
7796     info.enable_mask        = 0;
7797     info.flags              = 0;
7798     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7799     info.group_index        = 0;
7800     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7801     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7802     info.parent.status_mask = 1ull<<28 /* agl */;
7803     info.func               = __cvmx_error_display;
7804     info.user_info          = (long)
7805         "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
7806     fail |= cvmx_error_add(&info);
7807
7808     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7809     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7810     info.status_mask        = 0x3ull<<2 /* out_ovr */;
7811     info.enable_addr        = 0;
7812     info.enable_mask        = 0;
7813     info.flags              = 0;
7814     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7815     info.group_index        = 0;
7816     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7817     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7818     info.parent.status_mask = 1ull<<28 /* agl */;
7819     info.func               = __cvmx_error_display;
7820     info.user_info          = (long)
7821         "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
7822     fail |= cvmx_error_add(&info);
7823
7824     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7825     info.status_addr        = CVMX_AGL_GMX_BAD_REG;
7826     info.status_mask        = 0x3ull<<22 /* loststat */;
7827     info.enable_addr        = 0;
7828     info.enable_mask        = 0;
7829     info.flags              = 0;
7830     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7831     info.group_index        = 0;
7832     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7833     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7834     info.parent.status_mask = 1ull<<28 /* agl */;
7835     info.func               = __cvmx_error_display;
7836     info.user_info          = (long)
7837         "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
7838         "    In MII/RGMII, one bit per port\n"
7839         "    TX Stats are corrupted\n";
7840     fail |= cvmx_error_add(&info);
7841
7842     /* CVMX_AGL_GMX_RXX_INT_REG(0) */
7843     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7844     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
7845     info.status_mask        = 1ull<<8 /* skperr */;
7846     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
7847     info.enable_mask        = 1ull<<8 /* skperr */;
7848     info.flags              = 0;
7849     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7850     info.group_index        = 0;
7851     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7852     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7853     info.parent.status_mask = 1ull<<28 /* agl */;
7854     info.func               = __cvmx_error_display;
7855     info.user_info          = (long)
7856         "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
7857     fail |= cvmx_error_add(&info);
7858
7859     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7860     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(0);
7861     info.status_mask        = 1ull<<10 /* ovrerr */;
7862     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(0);
7863     info.enable_mask        = 1ull<<10 /* ovrerr */;
7864     info.flags              = 0;
7865     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7866     info.group_index        = 0;
7867     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7868     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7869     info.parent.status_mask = 1ull<<28 /* agl */;
7870     info.func               = __cvmx_error_display;
7871     info.user_info          = (long)
7872         "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
7873         "    This interrupt should never assert\n";
7874     fail |= cvmx_error_add(&info);
7875
7876     /* CVMX_AGL_GMX_RXX_INT_REG(1) */
7877     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7878     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
7879     info.status_mask        = 1ull<<8 /* skperr */;
7880     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
7881     info.enable_mask        = 1ull<<8 /* skperr */;
7882     info.flags              = 0;
7883     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7884     info.group_index        = 1;
7885     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7886     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7887     info.parent.status_mask = 1ull<<28 /* agl */;
7888     info.func               = __cvmx_error_display;
7889     info.user_info          = (long)
7890         "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
7891     fail |= cvmx_error_add(&info);
7892
7893     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7894     info.status_addr        = CVMX_AGL_GMX_RXX_INT_REG(1);
7895     info.status_mask        = 1ull<<10 /* ovrerr */;
7896     info.enable_addr        = CVMX_AGL_GMX_RXX_INT_EN(1);
7897     info.enable_mask        = 1ull<<10 /* ovrerr */;
7898     info.flags              = 0;
7899     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7900     info.group_index        = 1;
7901     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7902     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7903     info.parent.status_mask = 1ull<<28 /* agl */;
7904     info.func               = __cvmx_error_display;
7905     info.user_info          = (long)
7906         "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
7907         "    This interrupt should never assert\n";
7908     fail |= cvmx_error_add(&info);
7909
7910     /* CVMX_AGL_GMX_TX_INT_REG */
7911     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7912     info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
7913     info.status_mask        = 1ull<<0 /* pko_nxa */;
7914     info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
7915     info.enable_mask        = 1ull<<0 /* pko_nxa */;
7916     info.flags              = 0;
7917     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7918     info.group_index        = 0;
7919     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7920     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7921     info.parent.status_mask = 1ull<<28 /* agl */;
7922     info.func               = __cvmx_error_display;
7923     info.user_info          = (long)
7924         "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
7925     fail |= cvmx_error_add(&info);
7926
7927     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7928     info.status_addr        = CVMX_AGL_GMX_TX_INT_REG;
7929     info.status_mask        = 0x3ull<<2 /* undflw */;
7930     info.enable_addr        = CVMX_AGL_GMX_TX_INT_EN;
7931     info.enable_mask        = 0x3ull<<2 /* undflw */;
7932     info.flags              = 0;
7933     info.group              = CVMX_ERROR_GROUP_MGMT_PORT;
7934     info.group_index        = 0;
7935     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7936     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7937     info.parent.status_mask = 1ull<<28 /* agl */;
7938     info.func               = __cvmx_error_display;
7939     info.user_info          = (long)
7940         "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
7941     fail |= cvmx_error_add(&info);
7942
7943     /* CVMX_ZIP_ERROR */
7944     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7945     info.status_addr        = CVMX_ZIP_ERROR;
7946     info.status_mask        = 1ull<<0 /* doorbell */;
7947     info.enable_addr        = CVMX_ZIP_INT_MASK;
7948     info.enable_mask        = 1ull<<0 /* doorbell */;
7949     info.flags              = 0;
7950     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7951     info.group_index        = 0;
7952     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7953     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7954     info.parent.status_mask = 1ull<<7 /* zip */;
7955     info.func               = __cvmx_error_display;
7956     info.user_info          = (long)
7957         "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
7958     fail |= cvmx_error_add(&info);
7959
7960     /* CVMX_DFA_ERROR */
7961     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7962     info.status_addr        = CVMX_DFA_ERROR;
7963     info.status_mask        = 1ull<<0 /* dblovf */;
7964     info.enable_addr        = CVMX_DFA_INTMSK;
7965     info.enable_mask        = 1ull<<0 /* dblina */;
7966     info.flags              = 0;
7967     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7968     info.group_index        = 0;
7969     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7970     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7971     info.parent.status_mask = 1ull<<6 /* dfa */;
7972     info.func               = __cvmx_error_display;
7973     info.user_info          = (long)
7974         "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
7975         "    When set, the 20b accumulated doorbell register\n"
7976         "    had overflowed (SW wrote too many doorbell requests).\n"
7977         "    If the DBLINA had previously been enabled(set),\n"
7978         "    an interrupt will be posted. Software can clear\n"
7979         "    the interrupt by writing a 1 to this register bit.\n"
7980         "    NOTE: Detection of a Doorbell Register overflow\n"
7981         "    is a catastrophic error which may leave the DFA\n"
7982         "    HW in an unrecoverable state.\n";
7983     fail |= cvmx_error_add(&info);
7984
7985     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
7986     info.status_addr        = CVMX_DFA_ERROR;
7987     info.status_mask        = 0x7ull<<1 /* dc0perr */;
7988     info.enable_addr        = CVMX_DFA_INTMSK;
7989     info.enable_mask        = 0x7ull<<1 /* dc0pena */;
7990     info.flags              = 0;
7991     info.group              = CVMX_ERROR_GROUP_INTERNAL;
7992     info.group_index        = 0;
7993     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
7994     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
7995     info.parent.status_mask = 1ull<<6 /* dfa */;
7996     info.func               = __cvmx_error_display;
7997     info.user_info          = (long)
7998         "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
7999         "    See also DFA_DTCFADR register which contains the\n"
8000         "    failing addresses for the internal node cache RAMs.\n";
8001     fail |= cvmx_error_add(&info);
8002
8003     /* CVMX_SRIOX_INT_REG(0) */
8004     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8005     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8006     info.status_mask        = 1ull<<4 /* bar_err */;
8007     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8008     info.enable_mask        = 1ull<<4 /* bar_err */;
8009     info.flags              = 0;
8010     info.group              = CVMX_ERROR_GROUP_SRIO;
8011     info.group_index        = 0;
8012     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8013     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8014     info.parent.status_mask = 1ull<<32 /* srio0 */;
8015     info.func               = __cvmx_error_display;
8016     info.user_info          = (long)
8017         "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
8018     fail |= cvmx_error_add(&info);
8019
8020     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8021     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8022     info.status_mask        = 1ull<<5 /* deny_wr */;
8023     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8024     info.enable_mask        = 1ull<<5 /* deny_wr */;
8025     info.flags              = 0;
8026     info.group              = CVMX_ERROR_GROUP_SRIO;
8027     info.group_index        = 0;
8028     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8029     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8030     info.parent.status_mask = 1ull<<32 /* srio0 */;
8031     info.func               = __cvmx_error_display;
8032     info.user_info          = (long)
8033         "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
8034     fail |= cvmx_error_add(&info);
8035
8036     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8037     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8038     info.status_mask        = 1ull<<6 /* sli_err */;
8039     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8040     info.enable_mask        = 1ull<<6 /* sli_err */;
8041     info.flags              = 0;
8042     info.group              = CVMX_ERROR_GROUP_SRIO;
8043     info.group_index        = 0;
8044     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8045     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8046     info.parent.status_mask = 1ull<<32 /* srio0 */;
8047     info.func               = __cvmx_error_display;
8048     info.user_info          = (long)
8049         "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
8050         "    See SRIO(0,2..3)_INT_INFO[1:0]\n";
8051     fail |= cvmx_error_add(&info);
8052
8053     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8054     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8055     info.status_mask        = 1ull<<9 /* mce_rx */;
8056     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8057     info.enable_mask        = 1ull<<9 /* mce_rx */;
8058     info.flags              = 0;
8059     info.group              = CVMX_ERROR_GROUP_SRIO;
8060     info.group_index        = 0;
8061     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8062     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8063     info.parent.status_mask = 1ull<<32 /* srio0 */;
8064     info.func               = __cvmx_error_display;
8065     info.user_info          = (long)
8066         "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
8067     fail |= cvmx_error_add(&info);
8068
8069     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8070     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8071     info.status_mask        = 1ull<<12 /* log_erb */;
8072     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8073     info.enable_mask        = 1ull<<12 /* log_erb */;
8074     info.flags              = 0;
8075     info.group              = CVMX_ERROR_GROUP_SRIO;
8076     info.group_index        = 0;
8077     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8078     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8079     info.parent.status_mask = 1ull<<32 /* srio0 */;
8080     info.func               = __cvmx_error_display;
8081     info.user_info          = (long)
8082         "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
8083         "    See SRIOMAINT(0,2..3)_ERB_LT_ERR_DET\n";
8084     fail |= cvmx_error_add(&info);
8085
8086     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8087     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8088     info.status_mask        = 1ull<<13 /* phy_erb */;
8089     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8090     info.enable_mask        = 1ull<<13 /* phy_erb */;
8091     info.flags              = 0;
8092     info.group              = CVMX_ERROR_GROUP_SRIO;
8093     info.group_index        = 0;
8094     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8095     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8096     info.parent.status_mask = 1ull<<32 /* srio0 */;
8097     info.func               = __cvmx_error_display;
8098     info.user_info          = (long)
8099         "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
8100         "    See SRIOMAINT*_ERB_ATTR_CAPT\n";
8101     fail |= cvmx_error_add(&info);
8102
8103     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8104     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8105     info.status_mask        = 1ull<<18 /* omsg_err */;
8106     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8107     info.enable_mask        = 1ull<<18 /* omsg_err */;
8108     info.flags              = 0;
8109     info.group              = CVMX_ERROR_GROUP_SRIO;
8110     info.group_index        = 0;
8111     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8112     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8113     info.parent.status_mask = 1ull<<32 /* srio0 */;
8114     info.func               = __cvmx_error_display;
8115     info.user_info          = (long)
8116         "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
8117         "    See SRIO(0,2..3)_INT_INFO2\n";
8118     fail |= cvmx_error_add(&info);
8119
8120     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8121     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8122     info.status_mask        = 1ull<<19 /* pko_err */;
8123     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8124     info.enable_mask        = 1ull<<19 /* pko_err */;
8125     info.flags              = 0;
8126     info.group              = CVMX_ERROR_GROUP_SRIO;
8127     info.group_index        = 0;
8128     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8129     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8130     info.parent.status_mask = 1ull<<32 /* srio0 */;
8131     info.func               = __cvmx_error_display;
8132     info.user_info          = (long)
8133         "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
8134     fail |= cvmx_error_add(&info);
8135
8136     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8137     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8138     info.status_mask        = 1ull<<20 /* rtry_err */;
8139     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8140     info.enable_mask        = 1ull<<20 /* rtry_err */;
8141     info.flags              = 0;
8142     info.group              = CVMX_ERROR_GROUP_SRIO;
8143     info.group_index        = 0;
8144     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8145     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8146     info.parent.status_mask = 1ull<<32 /* srio0 */;
8147     info.func               = __cvmx_error_display;
8148     info.user_info          = (long)
8149         "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
8150         "    See SRIO(0,2..3)_INT_INFO3\n"
8151         "    When one or more of the segments in an outgoing\n"
8152         "    message have a RTRY_ERR, SRIO will not set\n"
8153         "    OMSG* after the message \"transfer\".\n";
8154     fail |= cvmx_error_add(&info);
8155
8156     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8157     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8158     info.status_mask        = 1ull<<21 /* f_error */;
8159     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8160     info.enable_mask        = 1ull<<21 /* f_error */;
8161     info.flags              = 0;
8162     info.group              = CVMX_ERROR_GROUP_SRIO;
8163     info.group_index        = 0;
8164     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8165     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8166     info.parent.status_mask = 1ull<<32 /* srio0 */;
8167     info.func               = __cvmx_error_display;
8168     info.user_info          = (long)
8169         "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
8170     fail |= cvmx_error_add(&info);
8171
8172     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8173     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8174     info.status_mask        = 1ull<<22 /* mac_buf */;
8175     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8176     info.enable_mask        = 1ull<<22 /* mac_buf */;
8177     info.flags              = 0;
8178     info.group              = CVMX_ERROR_GROUP_SRIO;
8179     info.group_index        = 0;
8180     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8181     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8182     info.parent.status_mask = 1ull<<32 /* srio0 */;
8183     info.func               = __cvmx_error_display;
8184     info.user_info          = (long)
8185         "ERROR SRIOX_INT_REG(0)[MAC_BUF]: SRIO MAC Buffer CRC Error\n"
8186         "    See SRIO(0,2..3)_MAC_BUFFERS\n";
8187     fail |= cvmx_error_add(&info);
8188
8189     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8190     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8191     info.status_mask        = 1ull<<23 /* degrad */;
8192     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8193     info.enable_mask        = 1ull<<23 /* degrade */;
8194     info.flags              = 0;
8195     info.group              = CVMX_ERROR_GROUP_SRIO;
8196     info.group_index        = 0;
8197     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8198     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8199     info.parent.status_mask = 1ull<<32 /* srio0 */;
8200     info.func               = __cvmx_error_display;
8201     info.user_info          = (long)
8202         "ERROR SRIOX_INT_REG(0)[DEGRAD]: ERB Error Rate reached Degrade Count\n"
8203         "    See SRIOMAINT(0,2..3)_ERB_ERR_RATE\n";
8204     fail |= cvmx_error_add(&info);
8205
8206     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8207     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8208     info.status_mask        = 1ull<<24 /* fail */;
8209     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8210     info.enable_mask        = 1ull<<24 /* fail */;
8211     info.flags              = 0;
8212     info.group              = CVMX_ERROR_GROUP_SRIO;
8213     info.group_index        = 0;
8214     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8215     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8216     info.parent.status_mask = 1ull<<32 /* srio0 */;
8217     info.func               = __cvmx_error_display;
8218     info.user_info          = (long)
8219         "ERROR SRIOX_INT_REG(0)[FAIL]: ERB Error Rate reached Fail Count\n"
8220         "    See SRIOMAINT(0,2..3)_ERB_ERR_RATE\n";
8221     fail |= cvmx_error_add(&info);
8222
8223     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8224     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8225     info.status_mask        = 1ull<<25 /* ttl_tout */;
8226     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8227     info.enable_mask        = 1ull<<25 /* ttl_tout */;
8228     info.flags              = 0;
8229     info.group              = CVMX_ERROR_GROUP_SRIO;
8230     info.group_index        = 0;
8231     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8232     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8233     info.parent.status_mask = 1ull<<32 /* srio0 */;
8234     info.func               = __cvmx_error_display;
8235     info.user_info          = (long)
8236         "ERROR SRIOX_INT_REG(0)[TTL_TOUT]: Outgoing Packet Time to Live Timeout\n"
8237         "    See SRIOMAINT(0,2..3)_DROP_PACKET\n";
8238     fail |= cvmx_error_add(&info);
8239
8240     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8241     info.status_addr        = CVMX_SRIOX_INT_REG(0);
8242     info.status_mask        = 1ull<<26 /* zero_pkt */;
8243     info.enable_addr        = CVMX_SRIOX_INT_ENABLE(0);
8244     info.enable_mask        = 1ull<<26 /* zero_pkt */;
8245     info.flags              = 0;
8246     info.group              = CVMX_ERROR_GROUP_SRIO;
8247     info.group_index        = 0;
8248     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8249     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8250     info.parent.status_mask = 1ull<<32 /* srio0 */;
8251     info.func               = __cvmx_error_display;
8252     info.user_info          = (long)
8253         "ERROR SRIOX_INT_REG(0)[ZERO_PKT]: Received Incoming SRIO Zero byte packet\n";
8254     fail |= cvmx_error_add(&info);
8255
8256     /* CVMX_PEXP_SLI_INT_SUM */
8257     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8258     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8259     info.status_mask        = 1ull<<0 /* rml_to */;
8260     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8261     info.enable_mask        = 1ull<<0 /* rml_to */;
8262     info.flags              = 0;
8263     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8264     info.group_index        = 0;
8265     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8266     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8267     info.parent.status_mask = 1ull<<3 /* sli */;
8268     info.func               = __cvmx_error_display;
8269     info.user_info          = (long)
8270         "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
8271         "    within 0xffff core clocks.\n";
8272     fail |= cvmx_error_add(&info);
8273
8274     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8275     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8276     info.status_mask        = 1ull<<1 /* reserved_1_1 */;
8277     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8278     info.enable_mask        = 1ull<<1 /* reserved_1_1 */;
8279     info.flags              = 0;
8280     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8281     info.group_index        = 0;
8282     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8283     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8284     info.parent.status_mask = 1ull<<3 /* sli */;
8285     info.func               = __cvmx_error_display;
8286     info.user_info          = (long)
8287         "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
8288 ;
8289     fail |= cvmx_error_add(&info);
8290
8291     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8292     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8293     info.status_mask        = 1ull<<2 /* bar0_to */;
8294     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8295     info.enable_mask        = 1ull<<2 /* bar0_to */;
8296     info.flags              = 0;
8297     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8298     info.group_index        = 0;
8299     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8300     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8301     info.parent.status_mask = 1ull<<3 /* sli */;
8302     info.func               = __cvmx_error_display;
8303     info.user_info          = (long)
8304         "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
8305         "    read-data/commit in 0xffff core clocks.\n";
8306     fail |= cvmx_error_add(&info);
8307
8308     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8309     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8310     info.status_mask        = 1ull<<3 /* iob2big */;
8311     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8312     info.enable_mask        = 1ull<<3 /* iob2big */;
8313     info.flags              = 0;
8314     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8315     info.group_index        = 0;
8316     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8317     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8318     info.parent.status_mask = 1ull<<3 /* sli */;
8319     info.func               = __cvmx_error_display;
8320     info.user_info          = (long)
8321         "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
8322     fail |= cvmx_error_add(&info);
8323
8324     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8325     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8326     info.status_mask        = 0x3ull<<6 /* reserved_6_7 */;
8327     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8328     info.enable_mask        = 0x3ull<<6 /* reserved_6_7 */;
8329     info.flags              = 0;
8330     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8331     info.group_index        = 0;
8332     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8333     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8334     info.parent.status_mask = 1ull<<3 /* sli */;
8335     info.func               = __cvmx_error_display;
8336     info.user_info          = (long)
8337         "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
8338 ;
8339     fail |= cvmx_error_add(&info);
8340
8341     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8342     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8343     info.status_mask        = 1ull<<8 /* m0_up_b0 */;
8344     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8345     info.enable_mask        = 1ull<<8 /* m0_up_b0 */;
8346     info.flags              = 0;
8347     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8348     info.group_index        = 0;
8349     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8350     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8351     info.parent.status_mask = 1ull<<3 /* sli */;
8352     info.func               = __cvmx_error_display;
8353     info.user_info          = (long)
8354         "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
8355         "    This occurs when the BAR 0 address space is\n"
8356         "    disabeled.\n";
8357     fail |= cvmx_error_add(&info);
8358
8359     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8360     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8361     info.status_mask        = 1ull<<9 /* m0_up_wi */;
8362     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8363     info.enable_mask        = 1ull<<9 /* m0_up_wi */;
8364     info.flags              = 0;
8365     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8366     info.group_index        = 0;
8367     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8368     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8369     info.parent.status_mask = 1ull<<3 /* sli */;
8370     info.func               = __cvmx_error_display;
8371     info.user_info          = (long)
8372         "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
8373         "    from MAC 0. This occurs when the window registers\n"
8374         "    are disabeld and a window register access occurs.\n";
8375     fail |= cvmx_error_add(&info);
8376
8377     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8378     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8379     info.status_mask        = 1ull<<10 /* m0_un_b0 */;
8380     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8381     info.enable_mask        = 1ull<<10 /* m0_un_b0 */;
8382     info.flags              = 0;
8383     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8384     info.group_index        = 0;
8385     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8386     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8387     info.parent.status_mask = 1ull<<3 /* sli */;
8388     info.func               = __cvmx_error_display;
8389     info.user_info          = (long)
8390         "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
8391         "    This occurs when the BAR 0 address space is\n"
8392         "    disabeled.\n";
8393     fail |= cvmx_error_add(&info);
8394
8395     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8396     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8397     info.status_mask        = 1ull<<11 /* m0_un_wi */;
8398     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8399     info.enable_mask        = 1ull<<11 /* m0_un_wi */;
8400     info.flags              = 0;
8401     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8402     info.group_index        = 0;
8403     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8404     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8405     info.parent.status_mask = 1ull<<3 /* sli */;
8406     info.func               = __cvmx_error_display;
8407     info.user_info          = (long)
8408         "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
8409         "    from MAC 0. This occurs when the window registers\n"
8410         "    are disabeld and a window register access occurs.\n";
8411     fail |= cvmx_error_add(&info);
8412
8413     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8414     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8415     info.status_mask        = 1ull<<12 /* m1_up_b0 */;
8416     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8417     info.enable_mask        = 1ull<<12 /* m1_up_b0 */;
8418     info.flags              = 0;
8419     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8420     info.group_index        = 0;
8421     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8422     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8423     info.parent.status_mask = 1ull<<3 /* sli */;
8424     info.func               = __cvmx_error_display;
8425     info.user_info          = (long)
8426         "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
8427         "    This occurs when the BAR 0 address space is\n"
8428         "    disabeled.\n";
8429     fail |= cvmx_error_add(&info);
8430
8431     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8432     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8433     info.status_mask        = 1ull<<13 /* m1_up_wi */;
8434     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8435     info.enable_mask        = 1ull<<13 /* m1_up_wi */;
8436     info.flags              = 0;
8437     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8438     info.group_index        = 0;
8439     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8440     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8441     info.parent.status_mask = 1ull<<3 /* sli */;
8442     info.func               = __cvmx_error_display;
8443     info.user_info          = (long)
8444         "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
8445         "    from MAC 1. This occurs when the window registers\n"
8446         "    are disabeld and a window register access occurs.\n";
8447     fail |= cvmx_error_add(&info);
8448
8449     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8450     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8451     info.status_mask        = 1ull<<14 /* m1_un_b0 */;
8452     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8453     info.enable_mask        = 1ull<<14 /* m1_un_b0 */;
8454     info.flags              = 0;
8455     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8456     info.group_index        = 0;
8457     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8458     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8459     info.parent.status_mask = 1ull<<3 /* sli */;
8460     info.func               = __cvmx_error_display;
8461     info.user_info          = (long)
8462         "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
8463         "    This occurs when the BAR 0 address space is\n"
8464         "    disabeled.\n";
8465     fail |= cvmx_error_add(&info);
8466
8467     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8468     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8469     info.status_mask        = 1ull<<15 /* m1_un_wi */;
8470     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8471     info.enable_mask        = 1ull<<15 /* m1_un_wi */;
8472     info.flags              = 0;
8473     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8474     info.group_index        = 0;
8475     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8476     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8477     info.parent.status_mask = 1ull<<3 /* sli */;
8478     info.func               = __cvmx_error_display;
8479     info.user_info          = (long)
8480         "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
8481         "    from MAC 1. This occurs when the window registers\n"
8482         "    are disabeld and a window register access occurs.\n";
8483     fail |= cvmx_error_add(&info);
8484
8485     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8486     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8487     info.status_mask        = 1ull<<20 /* m2_up_b0 */;
8488     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8489     info.enable_mask        = 1ull<<20 /* m2_up_b0 */;
8490     info.flags              = 0;
8491     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8492     info.group_index        = 0;
8493     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8494     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8495     info.parent.status_mask = 1ull<<3 /* sli */;
8496     info.func               = __cvmx_error_display;
8497     info.user_info          = (long)
8498         "ERROR PEXP_SLI_INT_SUM[M2_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 2.\n"
8499         "    This occurs when the BAR 0 address space is\n"
8500         "    disabeled.\n";
8501     fail |= cvmx_error_add(&info);
8502
8503     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8504     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8505     info.status_mask        = 1ull<<21 /* m2_up_wi */;
8506     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8507     info.enable_mask        = 1ull<<21 /* m2_up_wi */;
8508     info.flags              = 0;
8509     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8510     info.group_index        = 0;
8511     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8512     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8513     info.parent.status_mask = 1ull<<3 /* sli */;
8514     info.func               = __cvmx_error_display;
8515     info.user_info          = (long)
8516         "ERROR PEXP_SLI_INT_SUM[M2_UP_WI]: Received Unsupported P-TLP for Window Register\n"
8517         "    from MAC 2. This occurs when the window registers\n"
8518         "    are disabeld and a window register access occurs.\n";
8519     fail |= cvmx_error_add(&info);
8520
8521     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8522     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8523     info.status_mask        = 1ull<<22 /* m2_un_b0 */;
8524     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8525     info.enable_mask        = 1ull<<22 /* m2_un_b0 */;
8526     info.flags              = 0;
8527     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8528     info.group_index        = 0;
8529     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8530     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8531     info.parent.status_mask = 1ull<<3 /* sli */;
8532     info.func               = __cvmx_error_display;
8533     info.user_info          = (long)
8534         "ERROR PEXP_SLI_INT_SUM[M2_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 2.\n"
8535         "    This occurs when the BAR 0 address space is\n"
8536         "    disabeled.\n";
8537     fail |= cvmx_error_add(&info);
8538
8539     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8540     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8541     info.status_mask        = 1ull<<23 /* m2_un_wi */;
8542     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8543     info.enable_mask        = 1ull<<23 /* m2_un_wi */;
8544     info.flags              = 0;
8545     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8546     info.group_index        = 0;
8547     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8548     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8549     info.parent.status_mask = 1ull<<3 /* sli */;
8550     info.func               = __cvmx_error_display;
8551     info.user_info          = (long)
8552         "ERROR PEXP_SLI_INT_SUM[M2_UN_WI]: Received Unsupported N-TLP for Window Register\n"
8553         "    from MAC 2. This occurs when the window registers\n"
8554         "    are disabeld and a window register access occurs.\n";
8555     fail |= cvmx_error_add(&info);
8556
8557     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8558     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8559     info.status_mask        = 1ull<<24 /* m3_up_b0 */;
8560     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8561     info.enable_mask        = 1ull<<24 /* m3_up_b0 */;
8562     info.flags              = 0;
8563     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8564     info.group_index        = 0;
8565     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8566     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8567     info.parent.status_mask = 1ull<<3 /* sli */;
8568     info.func               = __cvmx_error_display;
8569     info.user_info          = (long)
8570         "ERROR PEXP_SLI_INT_SUM[M3_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 3.\n"
8571         "    This occurs when the BAR 0 address space is\n"
8572         "    disabeled.\n";
8573     fail |= cvmx_error_add(&info);
8574
8575     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8576     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8577     info.status_mask        = 1ull<<25 /* m3_up_wi */;
8578     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8579     info.enable_mask        = 1ull<<25 /* m3_up_wi */;
8580     info.flags              = 0;
8581     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8582     info.group_index        = 0;
8583     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8584     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8585     info.parent.status_mask = 1ull<<3 /* sli */;
8586     info.func               = __cvmx_error_display;
8587     info.user_info          = (long)
8588         "ERROR PEXP_SLI_INT_SUM[M3_UP_WI]: Received Unsupported P-TLP for Window Register\n"
8589         "    from MAC 3. This occurs when the window registers\n"
8590         "    are disabeld and a window register access occurs.\n";
8591     fail |= cvmx_error_add(&info);
8592
8593     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8594     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8595     info.status_mask        = 1ull<<26 /* m3_un_b0 */;
8596     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8597     info.enable_mask        = 1ull<<26 /* m3_un_b0 */;
8598     info.flags              = 0;
8599     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8600     info.group_index        = 0;
8601     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8602     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8603     info.parent.status_mask = 1ull<<3 /* sli */;
8604     info.func               = __cvmx_error_display;
8605     info.user_info          = (long)
8606         "ERROR PEXP_SLI_INT_SUM[M3_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 3.\n"
8607         "    This occurs when the BAR 0 address space is\n"
8608         "    disabeled.\n";
8609     fail |= cvmx_error_add(&info);
8610
8611     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8612     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8613     info.status_mask        = 1ull<<27 /* m3_un_wi */;
8614     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8615     info.enable_mask        = 1ull<<27 /* m3_un_wi */;
8616     info.flags              = 0;
8617     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8618     info.group_index        = 0;
8619     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8620     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8621     info.parent.status_mask = 1ull<<3 /* sli */;
8622     info.func               = __cvmx_error_display;
8623     info.user_info          = (long)
8624         "ERROR PEXP_SLI_INT_SUM[M3_UN_WI]: Received Unsupported N-TLP for Window Register\n"
8625         "    from MAC 3. This occurs when the window registers\n"
8626         "    are disabeld and a window register access occurs.\n";
8627     fail |= cvmx_error_add(&info);
8628
8629     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8630     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8631     info.status_mask        = 1ull<<48 /* pidbof */;
8632     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8633     info.enable_mask        = 1ull<<48 /* pidbof */;
8634     info.flags              = 0;
8635     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8636     info.group_index        = 0;
8637     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8638     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8639     info.parent.status_mask = 1ull<<3 /* sli */;
8640     info.func               = __cvmx_error_display;
8641     info.user_info          = (long)
8642         "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
8643         "    doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
8644     fail |= cvmx_error_add(&info);
8645
8646     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8647     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8648     info.status_mask        = 1ull<<49 /* psldbof */;
8649     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8650     info.enable_mask        = 1ull<<49 /* psldbof */;
8651     info.flags              = 0;
8652     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8653     info.group_index        = 0;
8654     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8655     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8656     info.parent.status_mask = 1ull<<3 /* sli */;
8657     info.func               = __cvmx_error_display;
8658     info.user_info          = (long)
8659         "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
8660         "    doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
8661     fail |= cvmx_error_add(&info);
8662
8663     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8664     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8665     info.status_mask        = 1ull<<50 /* pout_err */;
8666     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8667     info.enable_mask        = 1ull<<50 /* pout_err */;
8668     info.flags              = 0;
8669     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8670     info.group_index        = 0;
8671     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8672     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8673     info.parent.status_mask = 1ull<<3 /* sli */;
8674     info.func               = __cvmx_error_display;
8675     info.user_info          = (long)
8676         "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
8677         "    set.\n";
8678     fail |= cvmx_error_add(&info);
8679
8680     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8681     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8682     info.status_mask        = 1ull<<51 /* pin_bp */;
8683     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8684     info.enable_mask        = 1ull<<51 /* pin_bp */;
8685     info.flags              = 0;
8686     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8687     info.group_index        = 0;
8688     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8689     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8690     info.parent.status_mask = 1ull<<3 /* sli */;
8691     info.func               = __cvmx_error_display;
8692     info.user_info          = (long)
8693         "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
8694         "    See SLI_PKT_IN_BP\n";
8695     fail |= cvmx_error_add(&info);
8696
8697     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8698     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8699     info.status_mask        = 1ull<<52 /* pgl_err */;
8700     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8701     info.enable_mask        = 1ull<<52 /* pgl_err */;
8702     info.flags              = 0;
8703     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8704     info.group_index        = 0;
8705     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8706     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8707     info.parent.status_mask = 1ull<<3 /* sli */;
8708     info.func               = __cvmx_error_display;
8709     info.user_info          = (long)
8710         "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
8711         "    read this bit is set.\n";
8712     fail |= cvmx_error_add(&info);
8713
8714     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8715     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8716     info.status_mask        = 1ull<<53 /* pdi_err */;
8717     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8718     info.enable_mask        = 1ull<<53 /* pdi_err */;
8719     info.flags              = 0;
8720     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8721     info.group_index        = 0;
8722     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8723     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8724     info.parent.status_mask = 1ull<<3 /* sli */;
8725     info.func               = __cvmx_error_display;
8726     info.user_info          = (long)
8727         "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
8728         "    this bit is set.\n";
8729     fail |= cvmx_error_add(&info);
8730
8731     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8732     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8733     info.status_mask        = 1ull<<54 /* pop_err */;
8734     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8735     info.enable_mask        = 1ull<<54 /* pop_err */;
8736     info.flags              = 0;
8737     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8738     info.group_index        = 0;
8739     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8740     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8741     info.parent.status_mask = 1ull<<3 /* sli */;
8742     info.func               = __cvmx_error_display;
8743     info.user_info          = (long)
8744         "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
8745         "    pointer pair this bit is set.\n";
8746     fail |= cvmx_error_add(&info);
8747
8748     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8749     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8750     info.status_mask        = 1ull<<55 /* pins_err */;
8751     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8752     info.enable_mask        = 1ull<<55 /* pins_err */;
8753     info.flags              = 0;
8754     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8755     info.group_index        = 0;
8756     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8757     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8758     info.parent.status_mask = 1ull<<3 /* sli */;
8759     info.func               = __cvmx_error_display;
8760     info.user_info          = (long)
8761         "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
8762         "    this bit is set.\n";
8763     fail |= cvmx_error_add(&info);
8764
8765     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8766     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8767     info.status_mask        = 1ull<<56 /* sprt0_err */;
8768     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8769     info.enable_mask        = 1ull<<56 /* sprt0_err */;
8770     info.flags              = 0;
8771     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8772     info.group_index        = 0;
8773     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8774     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8775     info.parent.status_mask = 1ull<<3 /* sli */;
8776     info.func               = __cvmx_error_display;
8777     info.user_info          = (long)
8778         "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
8779         "    this bit is set.\n";
8780     fail |= cvmx_error_add(&info);
8781
8782     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8783     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8784     info.status_mask        = 1ull<<57 /* sprt1_err */;
8785     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8786     info.enable_mask        = 1ull<<57 /* sprt1_err */;
8787     info.flags              = 0;
8788     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8789     info.group_index        = 0;
8790     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8791     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8792     info.parent.status_mask = 1ull<<3 /* sli */;
8793     info.func               = __cvmx_error_display;
8794     info.user_info          = (long)
8795         "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
8796         "    this bit is set.\n";
8797     fail |= cvmx_error_add(&info);
8798
8799     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8800     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8801     info.status_mask        = 1ull<<58 /* sprt2_err */;
8802     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8803     info.enable_mask        = 1ull<<58 /* sprt2_err */;
8804     info.flags              = 0;
8805     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8806     info.group_index        = 0;
8807     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8808     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8809     info.parent.status_mask = 1ull<<3 /* sli */;
8810     info.func               = __cvmx_error_display;
8811     info.user_info          = (long)
8812         "ERROR PEXP_SLI_INT_SUM[SPRT2_ERR]: When an error response received on SLI port 2\n"
8813         "    this bit is set.\n";
8814     fail |= cvmx_error_add(&info);
8815
8816     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8817     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8818     info.status_mask        = 1ull<<59 /* sprt3_err */;
8819     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8820     info.enable_mask        = 1ull<<59 /* sprt3_err */;
8821     info.flags              = 0;
8822     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8823     info.group_index        = 0;
8824     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8825     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8826     info.parent.status_mask = 1ull<<3 /* sli */;
8827     info.func               = __cvmx_error_display;
8828     info.user_info          = (long)
8829         "ERROR PEXP_SLI_INT_SUM[SPRT3_ERR]: When an error response received on SLI port 3\n"
8830         "    this bit is set.\n";
8831     fail |= cvmx_error_add(&info);
8832
8833     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8834     info.status_addr        = CVMX_PEXP_SLI_INT_SUM;
8835     info.status_mask        = 1ull<<60 /* ill_pad */;
8836     info.enable_addr        = CVMX_PEXP_SLI_INT_ENB_CIU;
8837     info.enable_mask        = 1ull<<60 /* ill_pad */;
8838     info.flags              = 0;
8839     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8840     info.group_index        = 0;
8841     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8842     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8843     info.parent.status_mask = 1ull<<3 /* sli */;
8844     info.func               = __cvmx_error_display;
8845     info.user_info          = (long)
8846         "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
8847         "    range of the Packet-CSR, but for an unused\n"
8848         "    address.\n";
8849     fail |= cvmx_error_add(&info);
8850
8851     /* CVMX_DPI_INT_REG */
8852     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8853     info.status_addr        = CVMX_DPI_INT_REG;
8854     info.status_mask        = 1ull<<0 /* nderr */;
8855     info.enable_addr        = CVMX_DPI_INT_EN;
8856     info.enable_mask        = 1ull<<0 /* nderr */;
8857     info.flags              = 0;
8858     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8859     info.group_index        = 0;
8860     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8861     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8862     info.parent.status_mask = 1ull<<41 /* dpi */;
8863     info.func               = __cvmx_error_display;
8864     info.user_info          = (long)
8865         "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
8866         "    DPI received a NCB transaction on the outbound\n"
8867         "    bus to the DPI deviceID, but the command was not\n"
8868         "    recognized.\n";
8869     fail |= cvmx_error_add(&info);
8870
8871     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8872     info.status_addr        = CVMX_DPI_INT_REG;
8873     info.status_mask        = 1ull<<1 /* nfovr */;
8874     info.enable_addr        = CVMX_DPI_INT_EN;
8875     info.enable_mask        = 1ull<<1 /* nfovr */;
8876     info.flags              = 0;
8877     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8878     info.group_index        = 0;
8879     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8880     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8881     info.parent.status_mask = 1ull<<41 /* dpi */;
8882     info.func               = __cvmx_error_display;
8883     info.user_info          = (long)
8884         "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
8885         "    DPI can store upto 16 CSR request.  The FIFO will\n"
8886         "    overflow if that number is exceeded.\n";
8887     fail |= cvmx_error_add(&info);
8888
8889     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8890     info.status_addr        = CVMX_DPI_INT_REG;
8891     info.status_mask        = 0xffull<<8 /* dmadbo */;
8892     info.enable_addr        = CVMX_DPI_INT_EN;
8893     info.enable_mask        = 0xffull<<8 /* dmadbo */;
8894     info.flags              = 0;
8895     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8896     info.group_index        = 0;
8897     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8898     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8899     info.parent.status_mask = 1ull<<41 /* dpi */;
8900     info.func               = __cvmx_error_display;
8901     info.user_info          = (long)
8902         "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
8903         "    DPI has a 32-bit counter for each request's queue\n"
8904         "    outstanding doorbell counts. Interrupt will fire\n"
8905         "    if the count overflows.\n";
8906     fail |= cvmx_error_add(&info);
8907
8908     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8909     info.status_addr        = CVMX_DPI_INT_REG;
8910     info.status_mask        = 1ull<<16 /* req_badadr */;
8911     info.enable_addr        = CVMX_DPI_INT_EN;
8912     info.enable_mask        = 1ull<<16 /* req_badadr */;
8913     info.flags              = 0;
8914     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8915     info.group_index        = 0;
8916     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8917     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8918     info.parent.status_mask = 1ull<<41 /* dpi */;
8919     info.func               = __cvmx_error_display;
8920     info.user_info          = (long)
8921         "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
8922         "    Interrupt will fire if DPI forms an instruction\n"
8923         "    fetch to the NULL pointer.\n";
8924     fail |= cvmx_error_add(&info);
8925
8926     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8927     info.status_addr        = CVMX_DPI_INT_REG;
8928     info.status_mask        = 1ull<<17 /* req_badlen */;
8929     info.enable_addr        = CVMX_DPI_INT_EN;
8930     info.enable_mask        = 1ull<<17 /* req_badlen */;
8931     info.flags              = 0;
8932     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8933     info.group_index        = 0;
8934     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8935     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8936     info.parent.status_mask = 1ull<<41 /* dpi */;
8937     info.func               = __cvmx_error_display;
8938     info.user_info          = (long)
8939         "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
8940         "    Interrupt will fire if DPI forms an instruction\n"
8941         "    fetch with length of zero.\n";
8942     fail |= cvmx_error_add(&info);
8943
8944     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8945     info.status_addr        = CVMX_DPI_INT_REG;
8946     info.status_mask        = 1ull<<18 /* req_ovrflw */;
8947     info.enable_addr        = CVMX_DPI_INT_EN;
8948     info.enable_mask        = 1ull<<18 /* req_ovrflw */;
8949     info.flags              = 0;
8950     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8951     info.group_index        = 0;
8952     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8953     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8954     info.parent.status_mask = 1ull<<41 /* dpi */;
8955     info.func               = __cvmx_error_display;
8956     info.user_info          = (long)
8957         "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
8958         "    DPI tracks outstanding instructions fetches.\n"
8959         "    Interrupt will fire when FIFO overflows.\n";
8960     fail |= cvmx_error_add(&info);
8961
8962     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8963     info.status_addr        = CVMX_DPI_INT_REG;
8964     info.status_mask        = 1ull<<19 /* req_undflw */;
8965     info.enable_addr        = CVMX_DPI_INT_EN;
8966     info.enable_mask        = 1ull<<19 /* req_undflw */;
8967     info.flags              = 0;
8968     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8969     info.group_index        = 0;
8970     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8971     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8972     info.parent.status_mask = 1ull<<41 /* dpi */;
8973     info.func               = __cvmx_error_display;
8974     info.user_info          = (long)
8975         "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
8976         "    DPI tracks outstanding instructions fetches.\n"
8977         "    Interrupt will fire when FIFO underflows.\n";
8978     fail |= cvmx_error_add(&info);
8979
8980     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8981     info.status_addr        = CVMX_DPI_INT_REG;
8982     info.status_mask        = 1ull<<20 /* req_anull */;
8983     info.enable_addr        = CVMX_DPI_INT_EN;
8984     info.enable_mask        = 1ull<<20 /* req_anull */;
8985     info.flags              = 0;
8986     info.group              = CVMX_ERROR_GROUP_INTERNAL;
8987     info.group_index        = 0;
8988     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
8989     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
8990     info.parent.status_mask = 1ull<<41 /* dpi */;
8991     info.func               = __cvmx_error_display;
8992     info.user_info          = (long)
8993         "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
8994         "    Fetched instruction word was 0.\n";
8995     fail |= cvmx_error_add(&info);
8996
8997     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
8998     info.status_addr        = CVMX_DPI_INT_REG;
8999     info.status_mask        = 1ull<<21 /* req_inull */;
9000     info.enable_addr        = CVMX_DPI_INT_EN;
9001     info.enable_mask        = 1ull<<21 /* req_inull */;
9002     info.flags              = 0;
9003     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9004     info.group_index        = 0;
9005     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9006     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9007     info.parent.status_mask = 1ull<<41 /* dpi */;
9008     info.func               = __cvmx_error_display;
9009     info.user_info          = (long)
9010         "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
9011         "    Next pointer was NULL.\n";
9012     fail |= cvmx_error_add(&info);
9013
9014     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9015     info.status_addr        = CVMX_DPI_INT_REG;
9016     info.status_mask        = 1ull<<22 /* req_badfil */;
9017     info.enable_addr        = CVMX_DPI_INT_EN;
9018     info.enable_mask        = 1ull<<22 /* req_badfil */;
9019     info.flags              = 0;
9020     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9021     info.group_index        = 0;
9022     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9023     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9024     info.parent.status_mask = 1ull<<41 /* dpi */;
9025     info.func               = __cvmx_error_display;
9026     info.user_info          = (long)
9027         "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
9028         "    Instruction fill when none outstanding.\n";
9029     fail |= cvmx_error_add(&info);
9030
9031     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9032     info.status_addr        = CVMX_DPI_INT_REG;
9033     info.status_mask        = 1ull<<24 /* sprt0_rst */;
9034     info.enable_addr        = CVMX_DPI_INT_EN;
9035     info.enable_mask        = 1ull<<24 /* sprt0_rst */;
9036     info.flags              = 0;
9037     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9038     info.group_index        = 0;
9039     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9040     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9041     info.parent.status_mask = 1ull<<41 /* dpi */;
9042     info.func               = __cvmx_error_display;
9043     info.user_info          = (long)
9044         "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
9045         "     destination port was in reset.\n"
9046         "    this bit is set.\n";
9047     fail |= cvmx_error_add(&info);
9048
9049     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9050     info.status_addr        = CVMX_DPI_INT_REG;
9051     info.status_mask        = 1ull<<25 /* sprt1_rst */;
9052     info.enable_addr        = CVMX_DPI_INT_EN;
9053     info.enable_mask        = 1ull<<25 /* sprt1_rst */;
9054     info.flags              = 0;
9055     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9056     info.group_index        = 0;
9057     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9058     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9059     info.parent.status_mask = 1ull<<41 /* dpi */;
9060     info.func               = __cvmx_error_display;
9061     info.user_info          = (long)
9062         "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
9063         "     destination port was in reset.\n"
9064         "    this bit is set.\n";
9065     fail |= cvmx_error_add(&info);
9066
9067     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9068     info.status_addr        = CVMX_DPI_INT_REG;
9069     info.status_mask        = 1ull<<26 /* sprt2_rst */;
9070     info.enable_addr        = CVMX_DPI_INT_EN;
9071     info.enable_mask        = 1ull<<26 /* sprt2_rst */;
9072     info.flags              = 0;
9073     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9074     info.group_index        = 0;
9075     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9076     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9077     info.parent.status_mask = 1ull<<41 /* dpi */;
9078     info.func               = __cvmx_error_display;
9079     info.user_info          = (long)
9080         "ERROR DPI_INT_REG[SPRT2_RST]: DMA instruction was dropped because the source or\n"
9081         "     destination port was in reset.\n"
9082         "    this bit is set.\n";
9083     fail |= cvmx_error_add(&info);
9084
9085     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9086     info.status_addr        = CVMX_DPI_INT_REG;
9087     info.status_mask        = 1ull<<27 /* sprt3_rst */;
9088     info.enable_addr        = CVMX_DPI_INT_EN;
9089     info.enable_mask        = 1ull<<27 /* sprt3_rst */;
9090     info.flags              = 0;
9091     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9092     info.group_index        = 0;
9093     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9094     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9095     info.parent.status_mask = 1ull<<41 /* dpi */;
9096     info.func               = __cvmx_error_display;
9097     info.user_info          = (long)
9098         "ERROR DPI_INT_REG[SPRT3_RST]: DMA instruction was dropped because the source or\n"
9099         "     destination port was in reset.\n"
9100         "    this bit is set.\n";
9101     fail |= cvmx_error_add(&info);
9102
9103     /* CVMX_DPI_PKT_ERR_RSP */
9104     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9105     info.status_addr        = CVMX_DPI_PKT_ERR_RSP;
9106     info.status_mask        = 1ull<<0 /* pkterr */;
9107     info.enable_addr        = 0;
9108     info.enable_mask        = 0;
9109     info.flags              = 0;
9110     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9111     info.group_index        = 0;
9112     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9113     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9114     info.parent.status_mask = 1ull<<41 /* dpi */;
9115     info.func               = __cvmx_error_display;
9116     info.user_info          = (long)
9117         "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
9118         "    the I/O subsystem.\n";
9119     fail |= cvmx_error_add(&info);
9120
9121     /* CVMX_DPI_REQ_ERR_RSP */
9122     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9123     info.status_addr        = CVMX_DPI_REQ_ERR_RSP;
9124     info.status_mask        = 0xffull<<0 /* qerr */;
9125     info.enable_addr        = 0;
9126     info.enable_mask        = 0;
9127     info.flags              = 0;
9128     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9129     info.group_index        = 0;
9130     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9131     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9132     info.parent.status_mask = 1ull<<41 /* dpi */;
9133     info.func               = __cvmx_error_display;
9134     info.user_info          = (long)
9135         "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
9136         "    ErrorResponse from the I/O subsystem.\n"
9137         "    SW must clear the bit before the the cooresponding\n"
9138         "    instruction queue will continue processing\n"
9139         "    instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
9140     fail |= cvmx_error_add(&info);
9141
9142     /* CVMX_DPI_REQ_ERR_RST */
9143     info.reg_type           = CVMX_ERROR_REGISTER_IO64;
9144     info.status_addr        = CVMX_DPI_REQ_ERR_RST;
9145     info.status_mask        = 0xffull<<0 /* qerr */;
9146     info.enable_addr        = 0;
9147     info.enable_mask        = 0;
9148     info.flags              = 0;
9149     info.group              = CVMX_ERROR_GROUP_INTERNAL;
9150     info.group_index        = 0;
9151     info.parent.reg_type    = CVMX_ERROR_REGISTER_IO64;
9152     info.parent.status_addr = CVMX_CIU_BLOCK_INT;
9153     info.parent.status_mask = 1ull<<41 /* dpi */;
9154     info.func               = __cvmx_error_display;
9155     info.user_info          = (long)
9156         "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
9157         "    instruction because the source or destination\n"
9158         "    was in reset.\n"
9159         "    SW must clear the bit before the the cooresponding\n"
9160         "    instruction queue will continue processing\n"
9161         "    instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
9162     fail |= cvmx_error_add(&info);
9163
9164     return fail;
9165 }
9166