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38 ***********************license end**************************************/
49 * Helper functions to abstract board specific data about
50 * network ports from the rest of the cvmx-helper files.
52 * <hr>$Revision: 70030 $<hr>
54 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55 #include <linux/module.h>
56 #include <asm/octeon/cvmx.h>
57 #include <asm/octeon/cvmx-bootinfo.h>
58 #include <asm/octeon/cvmx-smix-defs.h>
59 #include <asm/octeon/cvmx-gmxx-defs.h>
60 #include <asm/octeon/cvmx-asxx-defs.h>
61 #include <asm/octeon/cvmx-mdio.h>
62 #include <asm/octeon/cvmx-helper.h>
63 #include <asm/octeon/cvmx-helper-util.h>
64 #include <asm/octeon/cvmx-helper-board.h>
65 #include <asm/octeon/cvmx-twsi.h>
68 #include "cvmx-app-init.h"
69 #include "cvmx-sysinfo.h"
70 #include "cvmx-twsi.h"
71 #include "cvmx-mdio.h"
72 #include "cvmx-helper.h"
73 #include "cvmx-helper-util.h"
74 #include "cvmx-helper-board.h"
75 #include "cvmx-gpio.h"
76 #if !defined(__FreeBSD__) || !defined(_KERNEL)
80 # include "libfdt/libfdt.h"
83 #include "cvmx-swap.h"
87 * cvmx_override_board_link_get(int ipd_port) is a function
88 * pointer. It is meant to allow customization of the process of
89 * talking to a PHY to determine link speed. It is called every
90 * time a PHY must be polled for link status. Users should set
91 * this pointer to a function before calling any cvmx-helper
94 CVMX_SHARED cvmx_helper_link_info_t (*cvmx_override_board_link_get)(int ipd_port) = NULL;
96 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
98 static void cvmx_retry_i2c_write(int twsi_id, uint8_t dev_addr, uint16_t internal_addr, int num_bytes, int ia_width_bytes, uint64_t data)
103 r = cvmx_twsix_write_ia(twsi_id, dev_addr, internal_addr, num_bytes, ia_width_bytes, data);
104 } while (tries-- > 0 && r < 0);
107 static int __pip_eth_node(const void *fdt_addr, int aliases, int ipd_port)
109 char name_buffer[20];
112 int interface_num = cvmx_helper_get_interface_num(ipd_port);
113 int interface_index = cvmx_helper_get_interface_index_num(ipd_port);
115 pip_path = fdt_getprop(fdt_addr, aliases, "pip", NULL);
118 cvmx_dprintf("ERROR: pip path not found in device tree\n");
121 pip = fdt_path_offset(fdt_addr, pip_path);
124 cvmx_dprintf("ERROR: pip not found in device tree\n");
128 sprintf(name_buffer, "interface@%d", interface_num);
130 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", interface_num);
132 iface = fdt_subnode_offset(fdt_addr, pip, name_buffer);
135 cvmx_dprintf("ERROR : pip intf %d not found in device tree \n",
140 sprintf(name_buffer, "ethernet@%x", interface_index);
142 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", interface_index);
144 eth = fdt_subnode_offset(fdt_addr, iface, name_buffer);
147 cvmx_dprintf("ERROR : pip interface@%d ethernet@%d not found in device "
148 "tree\n", interface_num, interface_index);
154 static int __mix_eth_node(const void *fdt_addr, int aliases, int interface_index)
156 char name_buffer[20];
161 sprintf(name_buffer, "mix%d", interface_index);
163 snprintf(name_buffer, sizeof(name_buffer), "mix%d", interface_index);
165 mix_path = fdt_getprop(fdt_addr, aliases, name_buffer, NULL);
168 cvmx_dprintf("ERROR: mix%d path not found in device tree\n",interface_index);
170 mix = fdt_path_offset(fdt_addr, mix_path);
173 cvmx_dprintf("ERROR: %s not found in device tree\n", mix_path);
179 typedef struct cvmx_phy_info
183 cvmx_phy_type_t phy_type;
187 static int __mdiobus_addr_to_unit(uint32_t addr)
189 int unit = (addr >> 7) & 3;
190 if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
195 * Return the MII PHY address associated with the given IPD
196 * port. The phy address is obtained from the device tree.
198 * @param ipd_port Octeon IPD port to get the MII address for.
200 * @return MII PHY address and bus number or -1.
203 static cvmx_phy_info_t __get_phy_info_from_dt(int ipd_port)
205 const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr);
206 uint32_t *phy_handle;
207 int aliases, eth, phy, phy_parent, phandle, ret;
208 cvmx_phy_info_t phy_info;
210 const char *phy_comaptible_str;
211 uint32_t *phy_addr_ptr;
213 phy_info.phy_addr = -1;
214 phy_info.direct_connect = -1;
215 phy_info.phy_type = (cvmx_phy_type_t) -1;
219 cvmx_dprintf("No device tree found.\n");
222 aliases = fdt_path_offset(fdt_addr, "/aliases");
224 cvmx_dprintf("Error: No /aliases node in device tree.\n");
229 int interface_index = ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
230 eth = __mix_eth_node(fdt_addr, aliases, interface_index) ;
234 eth = __pip_eth_node(fdt_addr, aliases, ipd_port);
238 cvmx_dprintf("ERROR : cannot find interface for ipd_port=%d\n", ipd_port);
241 /* Get handle to phy */
242 phy_handle = (uint32_t *) fdt_getprop(fdt_addr, eth, "phy-handle", NULL);
245 cvmx_dprintf("ERROR : phy handle not found in device tree ipd_port=%d"
249 phandle = cvmx_be32_to_cpu(*phy_handle);
250 phy = fdt_node_offset_by_phandle(fdt_addr, phandle);
253 cvmx_dprintf("ERROR : cannot find phy for ipd_port=%d ret=%d\n",
257 phy_comaptible_str = (const char *) fdt_getprop(fdt_addr, phy,
259 if (!phy_comaptible_str)
261 cvmx_dprintf("ERROR : no compatible prop in phy\n");
264 if (memcmp("marvell", phy_comaptible_str, strlen("marvell")) == 0)
266 phy_info.phy_type = MARVELL_GENERIC_PHY;
268 else if (memcmp("broadcom", phy_comaptible_str, strlen("broadcom")) == 0)
270 phy_info.phy_type = BROADCOM_GENERIC_PHY;
274 phy_info.phy_type = -1;
277 /* Check if PHY parent is the octeon MDIO bus. Some boards are connected
278 though a MUX and for them direct_connect_to_phy will be 0 */
279 phy_parent = fdt_parent_offset(fdt_addr, phy);
282 cvmx_dprintf("ERROR : cannot find phy parent for ipd_port=%d ret=%d\n",
283 ipd_port, phy_parent);
286 ret = fdt_node_check_compatible(fdt_addr, phy_parent,
287 "cavium,octeon-3860-mdio");
290 phy_info.direct_connect = 1 ;
291 uint32_t *mdio_reg_base = (uint32_t *) fdt_getprop(fdt_addr, phy_parent,"reg",0);
292 if (mdio_reg_base == 0)
294 cvmx_dprintf("ERROR : unable to get reg property in phy mdio\n");
297 mdio_unit = __mdiobus_addr_to_unit(mdio_reg_base[1]);
298 //cvmx_dprintf("phy parent=%s reg_base=%08x unit=%d \n",
299 // fdt_get_name(fdt_addr,phy_parent, NULL), mdio_reg_base[1], mdio_unit);
303 phy_info.direct_connect = 0;
304 /* The PHY is not directly connected to the Octeon MDIO bus.
305 SE doesn't have abstractions for MDIO MUX or MDIO MUX drivers and
306 hence for the non direct cases code will be needed which is
308 For now the the MDIO Unit is defaulted to 1.
313 phy_addr_ptr = (uint32_t *) fdt_getprop(fdt_addr, phy, "reg", NULL);
314 phy_info.phy_addr = cvmx_be32_to_cpu(*phy_addr_ptr) | mdio_unit << 8;
320 * Return the MII PHY address associated with the given IPD
321 * port. The phy address is obtained from the device tree.
323 * @param ipd_port Octeon IPD port to get the MII address for.
325 * @return MII PHY address and bus number or -1.
328 int cvmx_helper_board_get_mii_address_from_dt(int ipd_port)
330 cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port);
331 return phy_info.phy_addr;
336 * Return the MII PHY address associated with the given IPD
337 * port. A result of -1 means there isn't a MII capable PHY
338 * connected to this port. On chips supporting multiple MII
339 * busses the bus number is encoded in bits <15:8>.
341 * This function must be modified for every new Octeon board.
342 * Internally it uses switch statements based on the cvmx_sysinfo
343 * data to determine board types and revisions. It replies on the
344 * fact that every Octeon board receives a unique board type
345 * enumeration from the bootloader.
347 * @param ipd_port Octeon IPD port to get the MII address for.
349 * @return MII PHY address and bus number or -1.
351 int cvmx_helper_board_get_mii_address(int ipd_port)
354 * Board types we have to know at compile-time.
356 #ifdef OCTEON_BOARD_CAPK_0100ND
363 /* XXX Switch PHY? */
371 * For board types we can determine at runtime.
373 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
375 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
376 if (cvmx_sysinfo_get()->fdt_addr)
378 cvmx_phy_info_t phy_info = __get_phy_info_from_dt(ipd_port);
379 //cvmx_dprintf("ipd_port=%d phy_addr=%d\n", ipd_port, phy_info.phy_addr);
380 if (phy_info.phy_addr >= 0) return phy_info.phy_addr;
383 switch (cvmx_sysinfo_get()->board_type)
385 case CVMX_BOARD_TYPE_SIM:
386 /* Simulator doesn't have MII */
388 #if !defined(OCTEON_VENDOR_GEFES)
389 case CVMX_BOARD_TYPE_EBT5800:
390 case CVMX_BOARD_TYPE_NICPRO2:
392 case CVMX_BOARD_TYPE_EBT3000:
393 case CVMX_BOARD_TYPE_THUNDER:
394 /* Interface 0 is SPI4, interface 1 is RGMII */
395 if ((ipd_port >= 16) && (ipd_port < 20))
396 return ipd_port - 16;
399 case CVMX_BOARD_TYPE_LANAI2_A:
404 case CVMX_BOARD_TYPE_LANAI2_U:
405 case CVMX_BOARD_TYPE_LANAI2_G:
410 case CVMX_BOARD_TYPE_KODAMA:
411 case CVMX_BOARD_TYPE_EBH3100:
412 case CVMX_BOARD_TYPE_HIKARI:
413 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
414 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
415 #if !defined(OCTEON_VENDOR_GEFES)
416 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
418 /* Port 0 is WAN connected to a PHY, Port 1 is GMII connected to a
422 else if (ipd_port == 1)
426 case CVMX_BOARD_TYPE_EBH3000:
427 /* Board has dual SPI4 and no PHYs */
429 case CVMX_BOARD_TYPE_EBT5810:
430 /* Board has 10g PHYs hooked up to the MII controller on the
431 ** IXF18201 MAC. The 10G PHYS use clause 45 MDIO which the CN58XX
432 ** does not support. All MII accesses go through the IXF part. */
434 case CVMX_BOARD_TYPE_EBH5200:
435 case CVMX_BOARD_TYPE_EBH5201:
436 case CVMX_BOARD_TYPE_EBT5200:
437 /* Board has 2 management ports */
438 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
439 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT;
440 /* Board has 4 SGMII ports. The PHYs start right after the MII
441 ports MII0 = 0, MII1 = 1, SGMII = 2-5 */
442 if ((ipd_port >= 0) && (ipd_port < 4))
446 case CVMX_BOARD_TYPE_EBH5600:
447 case CVMX_BOARD_TYPE_EBH5601:
448 case CVMX_BOARD_TYPE_EBH5610:
449 /* Board has 1 management port */
450 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
452 /* Board has 8 SGMII ports. 4 connect out, two connect to a switch,
453 and 2 loop to each other */
454 if ((ipd_port >= 0) && (ipd_port < 4))
458 case CVMX_BOARD_TYPE_EBT5600:
459 /* Board has 1 management port */
460 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
462 /* Board has 1 XAUI port connected to a switch. */
464 case CVMX_BOARD_TYPE_EBB5600:
466 static unsigned char qlm_switch_addr = 0;
468 /* Board has 1 management port */
469 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
472 /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */
473 if ((ipd_port >= 0) && (ipd_port < 4))
475 if (qlm_switch_addr != 0x3)
477 qlm_switch_addr = 0x3; /* QLM1 */
478 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
479 cvmx_wait_usec(11000); /* Let the write complete */
481 return ipd_port+1 + (1<<8);
483 else if ((ipd_port >= 16) && (ipd_port < 20))
485 if (qlm_switch_addr != 0xC)
487 qlm_switch_addr = 0xC; /* QLM3 */
488 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
489 cvmx_wait_usec(11000); /* Let the write complete */
491 return ipd_port-16+1 + (1<<8);
496 case CVMX_BOARD_TYPE_EBB6300:
497 /* Board has 2 management ports */
498 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
499 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
500 if ((ipd_port >= 0) && (ipd_port < 4))
501 return ipd_port + 1 + (1<<8);
504 case CVMX_BOARD_TYPE_EBB6800:
505 /* Board has 1 management ports */
506 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
508 if (ipd_port >= 0x800 && ipd_port < 0x900) /* QLM 0*/
509 return 0x101 + ((ipd_port >> 4) & 3); /* SMI 1*/
510 if (ipd_port >= 0xa00 && ipd_port < 0xb00) /* QLM 2*/
511 return 0x201 + ((ipd_port >> 4) & 3); /* SMI 2*/
512 if (ipd_port >= 0xb00 && ipd_port < 0xc00) /* QLM 3*/
513 return 0x301 + ((ipd_port >> 4) & 3); /* SMI 3*/
514 if (ipd_port >= 0xc00 && ipd_port < 0xd00) /* QLM 4*/
515 return 0x001 + ((ipd_port >> 4) & 3); /* SMI 0*/
517 case CVMX_BOARD_TYPE_EP6300C:
518 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
520 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT+1)
522 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
524 int interface = cvmx_helper_get_interface_num(ipd_port);
525 int mode = cvmx_helper_interface_get_mode(interface);
526 if (mode == CVMX_HELPER_INTERFACE_MODE_XAUI)
528 else if ((ipd_port >= 0) && (ipd_port < 4))
535 case CVMX_BOARD_TYPE_CUST_NB5:
540 case CVMX_BOARD_TYPE_NIC_XLE_4G:
541 /* Board has 4 SGMII ports. connected QLM3(interface 1) */
542 if ((ipd_port >= 16) && (ipd_port < 20))
543 return ipd_port - 16 + 1;
546 case CVMX_BOARD_TYPE_NIC_XLE_10G:
547 case CVMX_BOARD_TYPE_NIC10E:
548 return -1; /* We don't use clause 45 MDIO for anything */
549 case CVMX_BOARD_TYPE_NIC4E:
550 if (ipd_port >= 0 && ipd_port <= 3)
551 return (ipd_port + 0x1f) & 0x1f;
554 case CVMX_BOARD_TYPE_NIC2E:
555 if (ipd_port >= 0 && ipd_port <= 1)
556 return (ipd_port + 1);
559 case CVMX_BOARD_TYPE_REDWING:
560 return -1; /* No PHYs connected to Octeon */
561 case CVMX_BOARD_TYPE_BBGW_REF:
562 return -1; /* No PHYs are connected to Octeon, everything is through switch */
563 case CVMX_BOARD_TYPE_CUST_WSX16:
564 if (ipd_port >= 0 && ipd_port <= 3)
566 else if (ipd_port >= 16 && ipd_port <= 19)
567 return ipd_port - 16 + 4;
571 /* Private vendor-defined boards. */
572 #if defined(OCTEON_VENDOR_LANNER)
573 case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
574 /* Interface 1 is 12 BCM5482S PHYs. */
575 if ((ipd_port >= 16) && (ipd_port < 28))
576 return ipd_port - 16;
578 case CVMX_BOARD_TYPE_CUST_LANNER_MR730:
579 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
580 return (ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT) + 0x81;
581 if ((ipd_port >= 0) && (ipd_port < 4))
584 case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
585 case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
586 /* Port 0 is a Marvell 88E6161 switch, ports 1 and 2 are Marvell
587 88E1111 interfaces. */
599 #if defined(OCTEON_VENDOR_UBIQUITI)
600 case CVMX_BOARD_TYPE_CUST_UBIQUITI_E100:
601 case CVMX_BOARD_TYPE_CUST_UBIQUITI_USG:
604 return (7 - ipd_port);
606 #if defined(OCTEON_VENDOR_RADISYS)
607 case CVMX_BOARD_TYPE_CUST_RADISYS_RSYS4GBE:
611 #if defined(OCTEON_VENDOR_GEFES)
612 case CVMX_BOARD_TYPE_AT5810:
614 case CVMX_BOARD_TYPE_TNPA3804:
615 case CVMX_BOARD_TYPE_CUST_TNPA5804:
616 case CVMX_BOARD_TYPE_CUST_W5800:
617 case CVMX_BOARD_TYPE_WNPA3850:
618 case CVMX_BOARD_TYPE_W3860:
619 return -1;// RGMII boards should use inbad status
620 case CVMX_BOARD_TYPE_CUST_W5651X:
621 case CVMX_BOARD_TYPE_CUST_W5650:
622 case CVMX_BOARD_TYPE_CUST_TNPA56X4:
623 case CVMX_BOARD_TYPE_CUST_TNPA5651X:
624 case CVMX_BOARD_TYPE_CUST_W63XX:
625 return -1; /* No PHYs are connected to Octeon, PHYs inside of SFPs which is accessed over TWSI */
626 case CVMX_BOARD_TYPE_CUST_W5434:
627 /* Board has 4 SGMII ports. 4 connect out
628 * must return the MII address of the PHY connected to each IPD port
630 if ((ipd_port >= 16) && (ipd_port < 20))
631 return ipd_port - 16 + 0x40;
637 /* Some unknown board. Somebody forgot to update this function... */
638 cvmx_dprintf("%s: Unknown board type %d\n",
639 __FUNCTION__, cvmx_sysinfo_get()->board_type);
642 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
643 EXPORT_SYMBOL(cvmx_helper_board_get_mii_address);
648 * Get link state of marvell PHY
650 static cvmx_helper_link_info_t __get_marvell_phy_link_state(int phy_addr)
652 cvmx_helper_link_info_t result;
656 /*All the speed information can be read from register 17 in one go.*/
657 phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
659 /* If the resolve bit 11 isn't set, see if autoneg is turned off
660 (bit 12, reg 0). The resolve bit doesn't get set properly when
661 autoneg is off, so force it */
662 if ((phy_status & (1<<11)) == 0)
664 int auto_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0);
665 if ((auto_status & (1<<12)) == 0)
669 /* Only return a link if the PHY has finished auto negotiation
670 and set the resolved bit (bit 11) */
671 if (phy_status & (1<<11))
673 result.s.link_up = 1;
674 result.s.full_duplex = ((phy_status>>13)&1);
675 switch ((phy_status>>14)&3)
677 case 0: /* 10 Mbps */
680 case 1: /* 100 Mbps */
681 result.s.speed = 100;
684 result.s.speed = 1000;
686 case 3: /* Illegal */
696 * Get link state of broadcom PHY
698 static cvmx_helper_link_info_t __get_broadcom_phy_link_state(int phy_addr)
700 cvmx_helper_link_info_t result;
704 /* Below we are going to read SMI/MDIO register 0x19 which works
706 phy_status = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x19);
707 switch ((phy_status>>8) & 0x7)
713 result.s.link_up = 1;
714 result.s.full_duplex = 0;
718 result.s.link_up = 1;
719 result.s.full_duplex = 1;
723 result.s.link_up = 1;
724 result.s.full_duplex = 0;
725 result.s.speed = 100;
728 result.s.link_up = 1;
729 result.s.full_duplex = 1;
730 result.s.speed = 100;
733 result.s.link_up = 1;
734 result.s.full_duplex = 1;
735 result.s.speed = 100;
738 result.s.link_up = 1;
739 result.s.full_duplex = 0;
740 result.s.speed = 1000;
743 result.s.link_up = 1;
744 result.s.full_duplex = 1;
745 result.s.speed = 1000;
754 * Get link state using inband status
756 static cvmx_helper_link_info_t __get_inband_link_state(int ipd_port)
758 cvmx_helper_link_info_t result;
759 cvmx_gmxx_rxx_rx_inbnd_t inband_status;
760 int interface = cvmx_helper_get_interface_num(ipd_port);
761 int index = cvmx_helper_get_interface_index_num(ipd_port);
764 inband_status.u64 = cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
765 result.s.link_up = inband_status.s.status;
766 result.s.full_duplex = inband_status.s.duplex;
767 switch (inband_status.s.speed)
769 case 0: /* 10 Mbps */
772 case 1: /* 100 Mbps */
773 result.s.speed = 100;
776 result.s.speed = 1000;
778 case 3: /* Illegal */
785 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
788 * Switch MDIO mux to the specified port.
790 static int __switch_mdio_mux(int ipd_port)
792 /* This method is board specific and doesn't use the device tree
793 information as SE doesn't implement MDIO MUX abstration */
794 switch (cvmx_sysinfo_get()->board_type)
796 case CVMX_BOARD_TYPE_EBB5600:
798 static unsigned char qlm_switch_addr = 0;
799 /* Board has 1 management port */
800 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
802 /* Board has 8 SGMII ports. 4 connected QLM1, 4 connected QLM3 */
803 if ((ipd_port >= 0) && (ipd_port < 4))
805 if (qlm_switch_addr != 0x3)
807 qlm_switch_addr = 0x3; /* QLM1 */
808 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
809 cvmx_wait_usec(11000); /* Let the write complete */
811 return ipd_port+1 + (1<<8);
813 else if ((ipd_port >= 16) && (ipd_port < 20))
815 if (qlm_switch_addr != 0xC)
817 qlm_switch_addr = 0xC; /* QLM3 */
818 cvmx_twsix_write_ia(0, 0x71, 0, 1, 1, qlm_switch_addr);
819 cvmx_wait_usec(11000); /* Let the write complete */
821 return ipd_port-16+1 + (1<<8);
826 case CVMX_BOARD_TYPE_EBB6600:
828 static unsigned char qlm_switch_addr = 0;
829 int old_twsi_switch_reg;
830 /* Board has 2 management ports */
831 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
832 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
833 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
834 if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */
836 if (qlm_switch_addr != 2)
842 old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0);
843 } while (tries-- > 0 && old_twsi_switch_reg < 0);
844 /* Set I2C MUX to enable port expander */
845 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8);
846 /* Set selecter to QLM 1 */
847 cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xff);
848 /* disable port expander */
849 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg);
851 return 0x101 + ipd_port;
853 else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 1 */
855 if (qlm_switch_addr != 1)
861 old_twsi_switch_reg = cvmx_twsix_read8(0, 0x70, 0);
862 } while (tries-- > 0 && old_twsi_switch_reg < 0);
863 /* Set I2C MUX to enable port expander */
864 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, 8);
865 /* Set selecter to QLM 2 */
866 cvmx_retry_i2c_write(0, 0x38, 0, 1, 0, 0xf7);
867 /* disable port expander */
868 cvmx_retry_i2c_write(0, 0x70, 0, 1, 0, old_twsi_switch_reg);
870 return 0x101 + (ipd_port - 16);
874 case CVMX_BOARD_TYPE_EBB6100:
876 static char gpio_configured = 0;
878 if (!gpio_configured)
883 /* Board has 2 management ports */
884 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) &&
885 (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
886 return ipd_port - CVMX_HELPER_BOARD_MGMT_IPD_PORT + 4;
887 if ((ipd_port >= 0) && (ipd_port < 4)) /* QLM 2 */
889 cvmx_gpio_set(1ull << 3);
890 return 0x101 + ipd_port;
892 else if ((ipd_port >= 16) && (ipd_port < 20)) /* QLM 0 */
894 cvmx_gpio_clear(1ull << 3);
895 return 0x101 + (ipd_port - 16);
899 printf("%s: Unknown ipd port 0x%x\n", __func__, ipd_port);
905 cvmx_dprintf("ERROR : unexpected mdio switch for board=%08x\n",
906 cvmx_sysinfo_get()->board_type);
910 /* should never get here */
916 * This function is used ethernet ports link speed. This functions uses the
917 * device tree information to determine the phy address and type of PHY.
918 * The only supproted PHYs are Marvell and Broadcom.
920 * @param ipd_port IPD input port associated with the port we want to get link
923 * @return The ports link status. If the link isn't fully resolved, this must
927 cvmx_helper_link_info_t __cvmx_helper_board_link_get_from_dt(int ipd_port)
929 cvmx_helper_link_info_t result;
930 cvmx_phy_info_t phy_info;
933 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
935 /* The simulator gives you a simulated 1Gbps full duplex link */
936 result.s.link_up = 1;
937 result.s.full_duplex = 1;
938 result.s.speed = 1000;
941 phy_info = __get_phy_info_from_dt(ipd_port);
942 //cvmx_dprintf("ipd_port=%d phy_addr=%d dc=%d type=%d \n", ipd_port,
943 // phy_info.phy_addr, phy_info.direct_connect, phy_info.phy_type);
944 if (phy_info.phy_addr < 0) return result;
946 if (phy_info.direct_connect == 0)
947 __switch_mdio_mux(ipd_port);
948 switch(phy_info.phy_type)
950 case BROADCOM_GENERIC_PHY:
951 result = __get_broadcom_phy_link_state(phy_info.phy_addr);
953 case MARVELL_GENERIC_PHY:
954 result = __get_marvell_phy_link_state(phy_info.phy_addr);
957 result = __get_inband_link_state(ipd_port);
966 * This function invokes __cvmx_helper_board_link_get_from_dt when device tree
967 * info is available. When the device tree information is not available then
968 * this function is the board specific method of determining an
969 * ethernet ports link speed. Most Octeon boards have Marvell PHYs
970 * and are handled by the fall through case. This function must be
971 * updated for boards that don't have the normal Marvell PHYs.
973 * This function must be modified for every new Octeon board.
974 * Internally it uses switch statements based on the cvmx_sysinfo
975 * data to determine board types and revisions. It relies on the
976 * fact that every Octeon board receives a unique board type
977 * enumeration from the bootloader.
979 * @param ipd_port IPD input port associated with the port we want to get link
982 * @return The ports link status. If the link isn't fully resolved, this must
985 cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
987 cvmx_helper_link_info_t result;
989 int is_broadcom_phy = 0;
991 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
992 if (cvmx_sysinfo_get()->fdt_addr)
994 return __cvmx_helper_board_link_get_from_dt(ipd_port);
998 /* Give the user a chance to override the processing of this function */
999 if (cvmx_override_board_link_get)
1000 return cvmx_override_board_link_get(ipd_port);
1002 /* Unless we fix it later, all links are defaulted to down */
1005 #if !defined(OCTEON_BOARD_CAPK_0100ND)
1006 /* This switch statement should handle all ports that either don't use
1007 Marvell PHYS, or don't support in-band status */
1008 switch (cvmx_sysinfo_get()->board_type)
1010 case CVMX_BOARD_TYPE_SIM:
1011 /* The simulator gives you a simulated 1Gbps full duplex link */
1012 result.s.link_up = 1;
1013 result.s.full_duplex = 1;
1014 result.s.speed = 1000;
1016 case CVMX_BOARD_TYPE_LANAI2_A:
1017 case CVMX_BOARD_TYPE_LANAI2_U:
1018 case CVMX_BOARD_TYPE_LANAI2_G:
1020 case CVMX_BOARD_TYPE_EBH3100:
1021 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
1022 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
1023 #if !defined(OCTEON_VENDOR_GEFES)
1024 case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
1026 /* Port 1 on these boards is always Gigabit */
1029 result.s.link_up = 1;
1030 result.s.full_duplex = 1;
1031 result.s.speed = 1000;
1034 /* Fall through to the generic code below */
1036 case CVMX_BOARD_TYPE_EBT5600:
1037 case CVMX_BOARD_TYPE_EBH5600:
1038 case CVMX_BOARD_TYPE_EBH5601:
1039 case CVMX_BOARD_TYPE_EBH5610:
1040 /* Board has 1 management ports */
1041 if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
1042 is_broadcom_phy = 1;
1044 case CVMX_BOARD_TYPE_EBH5200:
1045 case CVMX_BOARD_TYPE_EBH5201:
1046 case CVMX_BOARD_TYPE_EBT5200:
1047 /* Board has 2 management ports */
1048 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2)))
1049 is_broadcom_phy = 1;
1051 case CVMX_BOARD_TYPE_EBB6100:
1052 case CVMX_BOARD_TYPE_EBB6300: /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/
1053 case CVMX_BOARD_TYPE_EBB6600: /* Only for MII mode, with PHY addresses 0/1. Default is RGMII*/
1054 if ((ipd_port >= CVMX_HELPER_BOARD_MGMT_IPD_PORT) && (ipd_port < (CVMX_HELPER_BOARD_MGMT_IPD_PORT + 2))
1055 && cvmx_helper_board_get_mii_address(ipd_port) >= 0 && cvmx_helper_board_get_mii_address(ipd_port) <= 1)
1056 is_broadcom_phy = 1;
1058 case CVMX_BOARD_TYPE_EP6300C:
1059 is_broadcom_phy = 1;
1061 case CVMX_BOARD_TYPE_CUST_NB5:
1062 /* Port 1 on these boards is always Gigabit */
1065 result.s.link_up = 1;
1066 result.s.full_duplex = 1;
1067 result.s.speed = 1000;
1070 else /* The other port uses a broadcom PHY */
1071 is_broadcom_phy = 1;
1073 case CVMX_BOARD_TYPE_BBGW_REF:
1074 /* Port 1 on these boards is always Gigabit */
1077 /* Port 2 is not hooked up */
1083 /* Ports 0 and 1 connect to the switch */
1084 result.s.link_up = 1;
1085 result.s.full_duplex = 1;
1086 result.s.speed = 1000;
1089 case CVMX_BOARD_TYPE_NIC4E:
1090 case CVMX_BOARD_TYPE_NIC2E:
1091 is_broadcom_phy = 1;
1093 /* Private vendor-defined boards. */
1094 #if defined(OCTEON_VENDOR_LANNER)
1095 case CVMX_BOARD_TYPE_CUST_LANNER_MR730:
1096 /* Ports are BCM5482S */
1097 is_broadcom_phy = 1;
1099 case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
1100 case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
1101 /* Port 0 connects to the switch */
1104 result.s.link_up = 1;
1105 result.s.full_duplex = 1;
1106 result.s.speed = 1000;
1111 #if defined(OCTEON_VENDOR_GEFES)
1112 case CVMX_BOARD_TYPE_CUST_TNPA5651X:
1113 /* Since we don't auto-negotiate... 1Gbps full duplex link */
1114 result.s.link_up = 1;
1115 result.s.full_duplex = 1;
1116 result.s.speed = 1000;
1123 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
1124 //cvmx_dprintf("ipd_port=%d phy_addr=%d broadcom=%d\n",
1125 // ipd_port, phy_addr, is_broadcom_phy);
1128 if (is_broadcom_phy)
1130 result = __get_broadcom_phy_link_state(phy_addr);
1134 /* This code assumes we are using a Marvell Gigabit PHY. */
1135 result = __get_marvell_phy_link_state(phy_addr);
1138 else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX)
1139 || OCTEON_IS_MODEL(OCTEON_CN50XX))
1141 /* We don't have a PHY address, so attempt to use in-band status. It is
1142 really important that boards not supporting in-band status never get
1143 here. Reading broken in-band status tends to do bad things */
1144 result = __get_inband_link_state(ipd_port);
1146 #if defined(OCTEON_VENDOR_GEFES)
1147 else if( (OCTEON_IS_MODEL(OCTEON_CN56XX)) || (OCTEON_IS_MODEL(OCTEON_CN63XX)) )
1149 int interface = cvmx_helper_get_interface_num(ipd_port);
1150 int index = cvmx_helper_get_interface_index_num(ipd_port);
1151 cvmx_pcsx_miscx_ctl_reg_t mode_type;
1152 cvmx_pcsx_mrx_status_reg_t mrx_status;
1153 cvmx_pcsx_anx_adv_reg_t anxx_adv;
1154 cvmx_pcsx_sgmx_lp_adv_reg_t sgmii_inband_status;
1156 anxx_adv.u64 = cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
1157 mrx_status.u64 = cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG(index, interface));
1159 mode_type.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
1161 /* Read Octeon's inband status */
1162 sgmii_inband_status.u64 = cvmx_read_csr(CVMX_PCSX_SGMX_LP_ADV_REG(index, interface));
1164 result.s.link_up = sgmii_inband_status.s.link;
1165 result.s.full_duplex = sgmii_inband_status.s.dup;
1166 switch (sgmii_inband_status.s.speed)
1168 case 0: /* 10 Mbps */
1169 result.s.speed = 10;
1171 case 1: /* 100 Mbps */
1172 result.s.speed = 100;
1174 case 2: /* 1 Gbps */
1175 result.s.speed = 1000;
1177 case 3: /* Illegal */
1179 result.s.link_up = 0;
1186 /* We don't have a PHY address and we don't have in-band status. There
1187 is no way to determine the link speed. Return down assuming this
1192 /* If link is down, return all fields as zero. */
1193 if (!result.s.link_up)
1201 * This function as a board specific method of changing the PHY
1202 * speed, duplex, and autonegotiation. This programs the PHY and
1203 * not Octeon. This can be used to force Octeon's links to
1204 * specific settings.
1206 * @param phy_addr The address of the PHY to program
1208 * Flags to control autonegotiation. Bit 0 is autonegotiation
1209 * enable/disable to maintain backward compatibility.
1210 * @param link_info Link speed to program. If the speed is zero and autonegotiation
1211 * is enabled, all possible negotiation speeds are advertised.
1213 * @return Zero on success, negative on failure
1215 int cvmx_helper_board_link_set_phy(int phy_addr, cvmx_helper_board_set_phy_link_flags_types_t link_flags,
1216 cvmx_helper_link_info_t link_info)
1219 /* Set the flow control settings based on link_flags */
1220 if ((link_flags & set_phy_link_flags_flow_control_mask) != set_phy_link_flags_flow_control_dont_touch)
1222 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
1223 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
1224 reg_autoneg_adver.s.asymmetric_pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable;
1225 reg_autoneg_adver.s.pause = (link_flags & set_phy_link_flags_flow_control_mask) == set_phy_link_flags_flow_control_enable;
1226 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16);
1229 /* If speed isn't set and autoneg is on advertise all supported modes */
1230 if ((link_flags & set_phy_link_flags_autoneg) && (link_info.s.speed == 0))
1232 cvmx_mdio_phy_reg_control_t reg_control;
1233 cvmx_mdio_phy_reg_status_t reg_status;
1234 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
1235 cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
1236 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
1238 reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
1239 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
1240 reg_autoneg_adver.s.advert_100base_t4 = reg_status.s.capable_100base_t4;
1241 reg_autoneg_adver.s.advert_10base_tx_full = reg_status.s.capable_10_full;
1242 reg_autoneg_adver.s.advert_10base_tx_half = reg_status.s.capable_10_half;
1243 reg_autoneg_adver.s.advert_100base_tx_full = reg_status.s.capable_100base_x_full;
1244 reg_autoneg_adver.s.advert_100base_tx_half = reg_status.s.capable_100base_x_half;
1245 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16);
1246 if (reg_status.s.capable_extended_status)
1248 reg_extended_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
1249 reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000);
1250 reg_control_1000.s.advert_1000base_t_full = reg_extended_status.s.capable_1000base_t_full;
1251 reg_control_1000.s.advert_1000base_t_half = reg_extended_status.s.capable_1000base_t_half;
1252 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16);
1254 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL);
1255 reg_control.s.autoneg_enable = 1;
1256 reg_control.s.restart_autoneg = 1;
1257 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
1259 else if ((link_flags & set_phy_link_flags_autoneg))
1261 cvmx_mdio_phy_reg_control_t reg_control;
1262 cvmx_mdio_phy_reg_status_t reg_status;
1263 cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
1264 cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
1266 reg_status.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_STATUS);
1267 reg_autoneg_adver.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
1268 reg_autoneg_adver.s.advert_100base_t4 = 0;
1269 reg_autoneg_adver.s.advert_10base_tx_full = 0;
1270 reg_autoneg_adver.s.advert_10base_tx_half = 0;
1271 reg_autoneg_adver.s.advert_100base_tx_full = 0;
1272 reg_autoneg_adver.s.advert_100base_tx_half = 0;
1273 if (reg_status.s.capable_extended_status)
1275 reg_control_1000.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000);
1276 reg_control_1000.s.advert_1000base_t_full = 0;
1277 reg_control_1000.s.advert_1000base_t_half = 0;
1279 switch (link_info.s.speed)
1282 reg_autoneg_adver.s.advert_10base_tx_full = link_info.s.full_duplex;
1283 reg_autoneg_adver.s.advert_10base_tx_half = !link_info.s.full_duplex;
1286 reg_autoneg_adver.s.advert_100base_tx_full = link_info.s.full_duplex;
1287 reg_autoneg_adver.s.advert_100base_tx_half = !link_info.s.full_duplex;
1290 reg_control_1000.s.advert_1000base_t_full = link_info.s.full_duplex;
1291 reg_control_1000.s.advert_1000base_t_half = !link_info.s.full_duplex;
1294 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_AUTONEG_ADVER, reg_autoneg_adver.u16);
1295 if (reg_status.s.capable_extended_status)
1296 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL_1000, reg_control_1000.u16);
1297 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL);
1298 reg_control.s.autoneg_enable = 1;
1299 reg_control.s.restart_autoneg = 1;
1300 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
1304 cvmx_mdio_phy_reg_control_t reg_control;
1305 reg_control.u16 = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL);
1306 reg_control.s.autoneg_enable = 0;
1307 reg_control.s.restart_autoneg = 1;
1308 reg_control.s.duplex = link_info.s.full_duplex;
1309 if (link_info.s.speed == 1000)
1311 reg_control.s.speed_msb = 1;
1312 reg_control.s.speed_lsb = 0;
1314 else if (link_info.s.speed == 100)
1316 reg_control.s.speed_msb = 0;
1317 reg_control.s.speed_lsb = 1;
1319 else if (link_info.s.speed == 10)
1321 reg_control.s.speed_msb = 0;
1322 reg_control.s.speed_lsb = 0;
1324 cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
1332 * This function is called by cvmx_helper_interface_probe() after it
1333 * determines the number of ports Octeon can support on a specific
1334 * interface. This function is the per board location to override
1335 * this value. It is called with the number of ports Octeon might
1336 * support and should return the number of actual ports on the
1339 * This function must be modified for every new Octeon board.
1340 * Internally it uses switch statements based on the cvmx_sysinfo
1341 * data to determine board types and revisions. It relies on the
1342 * fact that every Octeon board receives a unique board type
1343 * enumeration from the bootloader.
1345 * @param interface Interface to probe
1346 * @param supported_ports
1347 * Number of ports Octeon supports.
1349 * @return Number of ports the actual board supports. Many times this will
1350 * simple be "support_ports".
1352 int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
1354 switch (cvmx_sysinfo_get()->board_type)
1356 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
1357 case CVMX_BOARD_TYPE_LANAI2_A:
1358 case CVMX_BOARD_TYPE_LANAI2_U:
1359 case CVMX_BOARD_TYPE_LANAI2_G:
1363 case CVMX_BOARD_TYPE_BBGW_REF:
1367 case CVMX_BOARD_TYPE_NIC_XLE_4G:
1371 /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
1372 which we don't support. Disable ports connected to it */
1373 case CVMX_BOARD_TYPE_EBH5600:
1377 case CVMX_BOARD_TYPE_EBB5600:
1378 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
1379 if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_PICMG)
1383 case CVMX_BOARD_TYPE_EBT5600:
1384 /* Disable loopback. */
1388 case CVMX_BOARD_TYPE_EBT5810:
1389 return 1; /* Two ports on each SPI: 1 hooked to MAC, 1 loopback
1390 ** Loopback disabled by default. */
1391 case CVMX_BOARD_TYPE_NIC2E:
1394 #if defined(OCTEON_VENDOR_LANNER)
1395 case CVMX_BOARD_TYPE_CUST_LANNER_MR955:
1400 #if defined(OCTEON_VENDOR_GEFES)
1401 case CVMX_BOARD_TYPE_CUST_TNPA5651X:
1402 if (interface < 2) /* interface can be EITHER 0 or 1 */
1403 return 1;//always return 1 for XAUI and SGMII mode.
1405 case CVMX_BOARD_TYPE_CUST_TNPA56X4:
1406 if ((interface == 0) &&
1407 (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_SGMII))
1409 cvmx_pcsx_miscx_ctl_reg_t pcsx_miscx_ctl_reg;
1411 /* For this port we need to set the mode to 1000BaseX */
1412 pcsx_miscx_ctl_reg.u64 =
1413 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(0, interface));
1414 pcsx_miscx_ctl_reg.cn56xx.mode = 1;
1415 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(0, interface),
1416 pcsx_miscx_ctl_reg.u64);
1417 pcsx_miscx_ctl_reg.u64 =
1418 cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(1, interface));
1419 pcsx_miscx_ctl_reg.cn56xx.mode = 1;
1420 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(1, interface),
1421 pcsx_miscx_ctl_reg.u64);
1428 #ifdef CVMX_BUILD_FOR_UBOOT
1429 if (CVMX_HELPER_INTERFACE_MODE_SPI == cvmx_helper_interface_get_mode(interface) && getenv("disable_spi"))
1432 return supported_ports;
1438 * Enable packet input/output from the hardware. This function is
1439 * called after by cvmx_helper_packet_hardware_enable() to
1440 * perform board specific initialization. For most boards
1441 * nothing is needed.
1443 * @param interface Interface to enable
1445 * @return Zero on success, negative on failure
1447 int __cvmx_helper_board_hardware_enable(int interface)
1449 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5)
1453 /* Different config for switch port */
1454 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
1455 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
1456 /* Boards with gigabit WAN ports need a different setting that is
1457 compatible with 100 Mbit settings */
1458 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 0xc);
1459 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0xc);
1462 else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_LANAI2_U)
1466 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 16);
1467 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 16);
1470 else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3010_EVB_HS5)
1472 /* Broadcom PHYs require different ASX clocks. Unfortunately
1473 many customer don't define a new board Id and simply
1474 mangle the CN3010_EVB_HS5 */
1477 /* Some customers boards use a hacked up bootloader that identifies them as
1478 ** CN3010_EVB_HS5 evaluation boards. This leads to all kinds of configuration
1479 ** problems. Detect one case, and print warning, while trying to do the right thing.
1481 int phy_addr = cvmx_helper_board_get_mii_address(0);
1484 int phy_identifier = cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 0x2);
1485 /* Is it a Broadcom PHY? */
1486 if (phy_identifier == 0x0143)
1489 cvmx_dprintf("ERROR:\n");
1490 cvmx_dprintf("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n");
1491 cvmx_dprintf("ERROR: The board type is mis-configured, and software malfunctions are likely.\n");
1492 cvmx_dprintf("ERROR: All boards require a unique board type to identify them.\n");
1493 cvmx_dprintf("ERROR:\n");
1495 cvmx_wait(1000000000);
1496 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 5);
1497 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), 5);
1502 #if defined(OCTEON_VENDOR_UBIQUITI)
1503 else if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_UBIQUITI_E100 ||
1504 cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CUST_UBIQUITI_USG)
1506 /* Configure ASX cloks for all ports on interface 0. */
1511 for (port = 0; port < 3; port++) {
1512 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 16);
1513 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 0);
1524 * Gets the clock type used for the USB block based on board type.
1525 * Used by the USB code for auto configuration of clock type.
1527 * @return USB clock type enumeration
1529 cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
1531 #if !defined(CVMX_BUILD_FOR_LINUX_KERNEL) && (!defined(__FreeBSD__) || !defined(_KERNEL))
1532 const void *fdt_addr = CASTPTR(const void *, cvmx_sysinfo_get()->fdt_addr);
1537 const char *type = NULL;
1541 nodeoffset = fdt_path_offset(fdt_addr, "/soc/uctl");
1543 nodeoffset = fdt_path_offset(fdt_addr, "/soc/usbn");
1545 if (nodeoffset >= 0)
1547 nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-type", &len);
1548 if (nodep != NULL && len > 0)
1549 type = (const char *)nodep;
1552 nodep = fdt_getprop(fdt_addr, nodeoffset, "refclk-frequency", &len);
1553 if (nodep != NULL && len == sizeof(uint32_t))
1554 speed = fdt32_to_cpu(*(int *)nodep);
1557 if (!strcmp(type, "crystal"))
1559 if (speed == 0 || speed == 12000000)
1560 return USB_CLOCK_TYPE_CRYSTAL_12;
1562 printf("Warning: invalid crystal speed for USB clock type in FDT\n");
1564 else if (!strcmp(type, "external"))
1568 return USB_CLOCK_TYPE_REF_12;
1570 return USB_CLOCK_TYPE_REF_24;
1573 return USB_CLOCK_TYPE_REF_48;
1575 printf("Warning: invalid USB clock speed of %u hz in FDT\n", speed);
1579 printf("Warning: invalid USB reference clock type \"%s\" in FDT\n", type ? type : "NULL");
1583 switch (cvmx_sysinfo_get()->board_type)
1585 case CVMX_BOARD_TYPE_BBGW_REF:
1586 case CVMX_BOARD_TYPE_LANAI2_A:
1587 case CVMX_BOARD_TYPE_LANAI2_U:
1588 case CVMX_BOARD_TYPE_LANAI2_G:
1589 #if defined(OCTEON_VENDOR_LANNER)
1590 case CVMX_BOARD_TYPE_CUST_LANNER_MR320:
1591 case CVMX_BOARD_TYPE_CUST_LANNER_MR321X:
1593 #if defined(OCTEON_VENDOR_UBIQUITI)
1594 case CVMX_BOARD_TYPE_CUST_UBIQUITI_E100:
1595 case CVMX_BOARD_TYPE_CUST_UBIQUITI_USG:
1597 #if defined(OCTEON_BOARD_CAPK_0100ND)
1598 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
1600 #if defined(OCTEON_VENDOR_GEFES) /* All GEFES' boards use same xtal type */
1601 case CVMX_BOARD_TYPE_TNPA3804:
1602 case CVMX_BOARD_TYPE_AT5810:
1603 case CVMX_BOARD_TYPE_WNPA3850:
1604 case CVMX_BOARD_TYPE_W3860:
1605 case CVMX_BOARD_TYPE_CUST_TNPA5804:
1606 case CVMX_BOARD_TYPE_CUST_W5434:
1607 case CVMX_BOARD_TYPE_CUST_W5650:
1608 case CVMX_BOARD_TYPE_CUST_W5800:
1609 case CVMX_BOARD_TYPE_CUST_W5651X:
1610 case CVMX_BOARD_TYPE_CUST_TNPA5651X:
1611 case CVMX_BOARD_TYPE_CUST_TNPA56X4:
1612 case CVMX_BOARD_TYPE_CUST_W63XX:
1614 case CVMX_BOARD_TYPE_NIC10E_66:
1615 return USB_CLOCK_TYPE_CRYSTAL_12;
1616 case CVMX_BOARD_TYPE_NIC10E:
1617 return USB_CLOCK_TYPE_REF_12;
1621 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) /* Most boards except NIC10e use a 12MHz crystal */
1622 || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
1623 return USB_CLOCK_TYPE_CRYSTAL_12;
1624 return USB_CLOCK_TYPE_REF_48;
1630 * Adjusts the number of available USB ports on Octeon based on board
1633 * @param supported_ports expected number of ports based on chip type;
1636 * @return number of available usb ports, based on board specifics.
1637 * Return value is supported_ports if function does not
1640 int __cvmx_helper_board_usb_get_num_ports(int supported_ports)
1642 switch (cvmx_sysinfo_get()->board_type)
1644 case CVMX_BOARD_TYPE_NIC_XLE_4G:
1645 case CVMX_BOARD_TYPE_NIC2E:
1649 return supported_ports;