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49 * Fixes and workaround for Octeon chip errata. This file
50 * contains functions called by cvmx-helper to workaround known
51 * chip errata. For the most part, code doesn't need to call
52 * these functions directly.
54 * <hr>$Revision: 70030 $<hr>
56 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
57 #include <asm/octeon/cvmx.h>
58 #include <asm/octeon/cvmx-helper.h>
59 #include <asm/octeon/cvmx-helper-jtag.h>
60 #include <asm/octeon/cvmx-pko.h>
61 #include <asm/octeon/cvmx-asxx-defs.h>
62 #include <asm/octeon/cvmx-gmxx-defs.h>
64 #if !defined(__FreeBSD__) || !defined(_KERNEL)
65 #include "executive-config.h"
66 #include "cvmx-config.h"
78 #include "cvmx-sysinfo.h"
79 #include "cvmx-helper.h"
80 #include "cvmx-helper-jtag.h"
84 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
89 * Function to adjust internal IPD pointer alignments
91 * @return 0 on success
94 int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
96 #define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP)
97 #define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
98 #define FIX_IPD_OUTPORT 0
99 #define INTERFACE(port) (port >> 4) /* Ports 0-15 are interface 0, 16-31 are interface 1 */
100 #define INDEX(port) (port & 0xf)
102 cvmx_pko_command_word0_t pko_command;
103 cvmx_buf_ptr_t g_buffer, pkt_buffer;
105 int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
106 cvmx_gmxx_prtx_cfg_t gmx_cfg;
110 cvmx_helper_link_info_t link_info;
112 /* Save values for restore at end */
113 uint64_t prtx_cfg = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
114 uint64_t tx_ptr_en = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
115 uint64_t rx_ptr_en = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
116 uint64_t rxx_jabber = cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
117 uint64_t frame_max = cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
119 /* Configure port to gig FDX as required for loopback mode */
120 cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
122 /* Disable reception on all ports so if traffic is present it will not interfere. */
123 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
125 cvmx_wait(100000000ull);
127 for (retry_loop_cnt = 0;retry_loop_cnt < 10;retry_loop_cnt++)
130 wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
131 pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
134 num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
141 size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + ((num_segs-1)*FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
142 (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
144 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
148 g_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
149 if (g_buffer.s.addr == 0) {
150 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
154 g_buffer.s.pool = CVMX_FPA_WQE_POOL;
155 g_buffer.s.size = num_segs;
158 pkt_buffer.s.addr = cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
159 if (pkt_buffer.s.addr == 0) {
160 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer allocation failure.\n");
164 pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
165 pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
167 p64 = (uint64_t*) cvmx_phys_to_ptr(pkt_buffer.s.addr);
168 p64[0] = 0xffffffffffff0000ull;
169 p64[1] = 0x08004510ull;
170 p64[2] = ((uint64_t)(size-14) << 48) | 0x5ae740004000ull;
171 p64[3] = 0x3a5fc0a81073c0a8ull;
173 for (i=0;i<num_segs;i++)
176 pkt_buffer.s.size = FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
181 *(uint64_t*)cvmx_phys_to_ptr(g_buffer.s.addr + 8*i) = pkt_buffer.u64;
184 /* Build the PKO command */
186 pko_command.s.segs = num_segs;
187 pko_command.s.total_bytes = size;
188 pko_command.s.dontfree = 0;
189 pko_command.s.gather = 1;
191 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
193 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
194 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
195 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT));
197 cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
198 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4);
200 cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), CVMX_PKO_LOCK_CMD_QUEUE);
201 cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, cvmx_pko_get_base_queue(FIX_IPD_OUTPORT), pko_command, g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
206 work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
208 } while ((work == NULL) && (retry_cnt > 0));
211 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT get_work() timeout occurred.\n");
216 cvmx_helper_free_packet_data(work);
221 /* Return CSR configs to saved values */
222 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), prtx_cfg);
223 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), tx_ptr_en);
224 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), rx_ptr_en);
225 cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), rxx_jabber);
226 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), frame_max);
227 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
228 link_info.u64 = 0; /* Set link to down so autonegotiation will set it up again */
229 cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
231 /* Bring the link back up as autonegotiation is not done in user applications. */
232 cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
236 cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
244 * This function needs to be called on all Octeon chips with
247 * The Size field is 8 too large in WQE and next pointers
249 * The Size field generated by IPD is 8 larger than it should
250 * be. The Size field is <55:40> of both:
251 * - WORD3 in the work queue entry, and
252 * - the next buffer pointer (which precedes the packet data
255 * @param work Work queue entry to fix
256 * @return Zero on success. Negative on failure
258 int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
260 uint64_t number_buffers = work->word2.s.bufs;
262 /* We only need to do this if the work has buffers */
265 cvmx_buf_ptr_t buffer_ptr = work->packet_ptr;
266 /* Check for errata PKI-100 */
267 if ( (buffer_ptr.s.pool == 0) && (((uint64_t)buffer_ptr.s.size +
268 ((uint64_t)buffer_ptr.s.back << 7) + ((uint64_t)buffer_ptr.s.addr & 0x7F))
269 != (CVMX_FPA_PACKET_POOL_SIZE+8))) {
270 /* fix is not needed */
273 /* Decrement the work packet pointer */
274 buffer_ptr.s.size -= 8;
275 work->packet_ptr = buffer_ptr;
277 /* Now loop through decrementing the size for each additional buffer */
278 while (--number_buffers)
280 /* Chain pointers are 8 bytes before the data */
281 cvmx_buf_ptr_t *ptr = (cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
283 buffer_ptr.s.size -= 8;
287 /* Make sure that these write go out before other operations such as FPA frees */
292 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */
296 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
297 * 1 doesn't work properly. The following code disables 2nd order
298 * CDR for the specified QLM.
300 * @param qlm QLM to disable 2nd order CDR for.
302 void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
305 /* Apply the workaround only once. */
306 cvmx_ciu_qlm_jtgd_t qlm_jtgd;
307 qlm_jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
308 if (qlm_jtgd.s.select != 0)
311 cvmx_helper_qlm_jtag_init();
312 /* We need to load all four lanes of the QLM, a total of 1072 bits */
313 for (lane=0; lane<4; lane++)
315 /* Each lane has 268 bits. We need to set cfg_cdr_incx<67:64>=3 and
316 cfg_cdr_secord<77>=1. All other bits are zero. Bits go in LSB
317 first, so start off with the zeros for bits <63:0> */
318 cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
319 /* cfg_cdr_incx<67:64>=3 */
320 cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
321 /* Zeros for bits <76:68> */
322 cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
323 /* cfg_cdr_secord<77>=1 */
324 cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
325 /* Zeros for bits <267:78> */
326 cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
328 cvmx_helper_qlm_jtag_update(qlm);