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47 * Fixes and workaround for Octeon chip errata. This file
48 * contains functions called by cvmx-helper to workaround known
49 * chip errata. For the most part, code doesn't need to call
50 * these functions directly.
52 * <hr>$Revision: 41586 $<hr>
54 #ifndef __CVMX_HELPER_ERRATA_H__
55 #define __CVMX_HELPER_ERRATA_H__
59 * Function to adjust internal IPD pointer alignments
61 * @return 0 on success
64 extern int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
68 * Workaround ASX setup errata with CN38XX pass1
70 * @param interface Interface to setup
71 * @param port Port to setup (0..3)
73 * Chip frequency in Hertz
75 * @return Zero on success, negative on failure
77 extern int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz);
80 * This function needs to be called on all Octeon chips with
83 * The Size field is 8 too large in WQE and next pointers
85 * The Size field generated by IPD is 8 larger than it should
86 * be. The Size field is <55:40> of both:
87 * - WORD3 in the work queue entry, and
88 * - the next buffer pointer (which precedes the packet data
91 * @param work Work queue entry to fix
92 * @return Zero on success. Negative on failure
94 extern int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work);
97 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
98 * 1 doesn't work properly. The following code disables 2nd order
99 * CDR for the specified QLM.
101 * @param qlm QLM to disable 2nd order CDR for.
103 extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);