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45 * Helper utilities for qlm_jtag.
47 * <hr>$Revision: 42480 $<hr>
49 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
50 #include <asm/octeon/cvmx.h>
51 #include <asm/octeon/cvmx-clock.h>
52 #include <asm/octeon/cvmx-helper-jtag.h>
54 #if !defined(__FreeBSD__) || !defined(_KERNEL)
55 #include "executive-config.h"
56 #include "cvmx-config.h"
59 #if defined(__FreeBSD__) && defined(_KERNEL)
60 #include "cvmx-helper-jtag.h"
65 * Initialize the internal QLM JTAG logic to allow programming
66 * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
67 * These functions should only be used at the direction of Cavium
68 * Networks. Programming incorrect values into the JTAG chain
69 * can cause chip damage.
71 void cvmx_helper_qlm_jtag_init(void)
73 cvmx_ciu_qlm_jtgc_t jtgc;
77 divisor = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / (1000000 *
78 (OCTEON_IS_MODEL(OCTEON_CN68XX) ? 10 : 25));
80 divisor = (divisor-1)>>2;
81 /* Convert the divisor into a power of 2 shift */
88 /* Clock divider for QLM JTAG operations. sclk is divided by 2^(CLK_DIV + 2) */
90 jtgc.s.clk_div = clock_div;
92 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
94 else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
98 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
99 jtgc.s.bypass_ext = 1;
100 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
101 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
106 * Write up to 32bits into the QLM jtag chain. Bits are shifted
107 * into the MSB and out the LSB, so you should shift in the low
108 * order bits followed by the high order bits. The JTAG chain for
109 * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain
110 * for CN63XX is 4 * 300 bits long, or 1200.
112 * @param qlm QLM to shift value into
113 * @param bits Number of bits to shift in (1-32).
114 * @param data Data to shift in. Bit 0 enters the chain first, followed by
117 * @return The low order bits of the JTAG chain that shifted out of the
120 uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
122 cvmx_ciu_qlm_jtgc_t jtgc;
123 cvmx_ciu_qlm_jtgd_t jtgd;
125 jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
126 jtgc.s.mux_sel = qlm;
127 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && !OCTEON_IS_MODEL(OCTEON_CNF7XXX))
128 jtgc.s.bypass = 1<<qlm;
129 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
130 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
134 jtgd.s.shft_cnt = bits-1;
135 jtgd.s.shft_reg = data;
136 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
137 jtgd.s.select = 1 << qlm;
138 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
141 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
142 } while (jtgd.s.shift);
143 return jtgd.s.shft_reg >> (32-bits);
148 * Shift long sequences of zeros into the QLM JTAG chain. It is
149 * common to need to shift more than 32 bits of zeros into the
150 * chain. This function is a convience wrapper around
151 * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
154 * @param qlm QLM to shift zeros into
157 void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
164 cvmx_helper_qlm_jtag_shift(qlm, n, 0);
171 * Program the QLM JTAG chain into all lanes of the QLM. You must
172 * have already shifted in the proper number of bits into the
173 * JTAG chain. Updating invalid values can possibly cause chip damage.
175 * @param qlm QLM to program
177 void cvmx_helper_qlm_jtag_update(int qlm)
179 cvmx_ciu_qlm_jtgc_t jtgc;
180 cvmx_ciu_qlm_jtgd_t jtgd;
182 jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
183 jtgc.s.mux_sel = qlm;
184 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && !OCTEON_IS_MODEL(OCTEON_CNF7XXX))
185 jtgc.s.bypass = 1<<qlm;
187 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
188 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
190 /* Update the new data */
193 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
194 jtgd.s.select = 1 << qlm;
195 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
198 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
199 } while (jtgd.s.update);
204 * Load the QLM JTAG chain with data from all lanes of the QLM.
206 * @param qlm QLM to program
208 void cvmx_helper_qlm_jtag_capture(int qlm)
210 cvmx_ciu_qlm_jtgc_t jtgc;
211 cvmx_ciu_qlm_jtgd_t jtgd;
213 jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
214 jtgc.s.mux_sel = qlm;
215 if (!OCTEON_IS_MODEL(OCTEON_CN6XXX) && !OCTEON_IS_MODEL(OCTEON_CNF7XXX))
216 jtgc.s.bypass = 1<<qlm;
218 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
219 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
223 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
224 jtgd.s.select = 1 << qlm;
225 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
228 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
229 } while (jtgd.s.capture);