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49 * Functions for XAUI initialization, configuration,
52 * <hr>$Revision: 70030 $<hr>
54 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
55 #include <asm/octeon/cvmx.h>
56 #include <asm/octeon/cvmx-config.h>
57 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
58 #include <asm/octeon/cvmx-qlm.h>
59 #include <asm/octeon/cvmx-helper.h>
60 #include <asm/octeon/cvmx-helper-cfg.h>
62 #include <asm/octeon/cvmx-gmxx-defs.h>
63 #include <asm/octeon/cvmx-pko-defs.h>
64 #include <asm/octeon/cvmx-pcsx-defs.h>
65 #include <asm/octeon/cvmx-pcsxx-defs.h>
66 #include <asm/octeon/cvmx-ciu-defs.h>
68 #if !defined(__FreeBSD__) || !defined(_KERNEL)
69 #include "executive-config.h"
70 #include "cvmx-config.h"
72 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
75 #include "cvmx-helper.h"
76 #include "cvmx-helper-cfg.h"
81 #include "cvmx-helper.h"
86 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
88 int __cvmx_helper_xaui_enumerate(int interface)
90 union cvmx_gmxx_hg2_control gmx_hg2_control;
92 /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
93 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
94 if (gmx_hg2_control.s.hg2tx_en)
102 * Probe a XAUI interface and determine the number of ports
103 * connected to it. The XAUI interface should still be down
106 * @param interface Interface to probe
108 * @return Number of ports on the interface. Zero to disable.
110 int __cvmx_helper_xaui_probe(int interface)
113 cvmx_gmxx_inf_mode_t mode;
115 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
116 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0))
118 cvmx_ciu_qlm2_t ciu_qlm;
119 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
120 ciu_qlm.s.txbypass = 1;
121 ciu_qlm.s.txdeemph = 0x5;
122 ciu_qlm.s.txmargin = 0x1a;
123 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
126 /* CN63XX Pass 2.0 and 2.1 errata G-15273 requires the QLM De-emphasis be
127 programmed when using a 156.25Mhz ref clock */
128 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0) ||
129 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1))
131 /* Read the QLM speed pins */
132 cvmx_mio_rst_boot_t mio_rst_boot;
133 mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
135 if (mio_rst_boot.cn63xx.qlm2_spd == 0xb)
137 cvmx_ciu_qlm2_t ciu_qlm;
138 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM2);
139 ciu_qlm.s.txbypass = 1;
140 ciu_qlm.s.txdeemph = 0xa;
141 ciu_qlm.s.txmargin = 0x1f;
142 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64);
146 /* Check if QLM is configured correct for XAUI/RXAUI, verify the
147 speed as well as mode */
148 if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
152 qlm = cvmx_qlm_interface(interface);
153 status = cvmx_qlm_get_status(qlm);
154 if (status != 2 && status != 10)
158 /* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the interface
159 needs to be enabled before IPD otherwise per port backpressure
160 may not work properly */
161 mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
163 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
165 __cvmx_helper_setup_gmx(interface, 1);
167 if (!OCTEON_IS_MODEL(OCTEON_CN68XX))
169 /* Setup PKO to support 16 ports for HiGig2 virtual ports. We're pointing
170 all of the PKO packet ports for this interface to the XAUI. This allows
171 us to use HiGig2 backpressure per port */
174 cvmx_pko_mem_port_ptrs_t pko_mem_port_ptrs;
175 pko_mem_port_ptrs.u64 = 0;
176 /* We set each PKO port to have equal priority in a round robin
178 pko_mem_port_ptrs.s.static_p = 0;
179 pko_mem_port_ptrs.s.qos_mask = 0xff;
180 /* All PKO ports map to the same XAUI hardware port */
181 pko_mem_port_ptrs.s.eid = interface*4;
182 pko_mem_port_ptrs.s.pid = interface*16 + i;
183 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
187 return __cvmx_helper_xaui_enumerate(interface);
192 * Bringup XAUI interface. After this call packet I/O should be
195 * @param interface Interface to bring up
197 * @return Zero on success, negative on failure
199 static int __cvmx_helper_xaui_link_init(int interface)
201 cvmx_gmxx_prtx_cfg_t gmx_cfg;
202 cvmx_pcsxx_control1_reg_t xauiCtl;
203 cvmx_pcsxx_misc_ctl_reg_t xauiMiscCtl;
204 cvmx_gmxx_tx_xaui_ctl_t gmxXauiTxCtl;
206 /* (1) Interface has already been enabled. */
208 /* (2) Disable GMX. */
209 xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
210 xauiMiscCtl.s.gmxeno = 1;
211 cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
213 /* (3) Disable GMX and PCSX interrupts. */
214 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
215 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
216 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
218 /* (4) Bring up the PCSX and GMX reconciliation layer. */
219 /* (4)a Set polarity and lane swapping. */
221 gmxXauiTxCtl.u64 = cvmx_read_csr (CVMX_GMXX_TX_XAUI_CTL(interface));
222 gmxXauiTxCtl.s.dic_en = 1; /* Enable better IFG packing and improves performance */
223 gmxXauiTxCtl.s.uni_en = 0;
224 cvmx_write_csr (CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
226 /* (4)c Aply reset sequence */
227 xauiCtl.u64 = cvmx_read_csr (CVMX_PCSXX_CONTROL1_REG(interface));
228 xauiCtl.s.lo_pwr = 0;
230 /* Errata G-15618 requires disabling PCS soft reset in some OCTEON II models. */
231 if (!OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)
232 && !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)
233 && !OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_1)
234 && !OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X)
235 && !OCTEON_IS_MODEL(OCTEON_CN68XX))
237 cvmx_write_csr (CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
239 /* Wait for PCS to come out of reset */
240 if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_CONTROL1_REG(interface), cvmx_pcsxx_control1_reg_t, reset, ==, 0, 10000))
242 /* Wait for PCS to be aligned */
243 if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_10GBX_STATUS_REG(interface), cvmx_pcsxx_10gbx_status_reg_t, alignd, ==, 1, 10000))
245 /* Wait for RX to be ready */
246 if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_RX_XAUI_CTL(interface), cvmx_gmxx_rx_xaui_ctl_t, status, ==, 0, 10000))
249 /* (6) Configure GMX */
251 /* Wait for GMX RX to be idle */
252 if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, rx_idle, ==, 1, 10000))
254 /* Wait for GMX TX to be idle */
255 if (CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(0, interface), cvmx_gmxx_prtx_cfg_t, tx_idle, ==, 1, 10000))
259 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
261 gmx_cfg.s.speed_msb = 0;
262 gmx_cfg.s.slottime = 1;
263 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
264 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
265 cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
266 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
268 /* Wait for receive link */
269 if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS1_REG(interface), cvmx_pcsxx_status1_reg_t, rcv_lnk, ==, 1, 10000))
271 if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, xmtflt, ==, 0, 10000))
273 if (CVMX_WAIT_FOR_FIELD64(CVMX_PCSXX_STATUS2_REG(interface), cvmx_pcsxx_status2_reg_t, rcvflt, ==, 0, 10000))
276 /* (8) Enable packet reception */
277 xauiMiscCtl.s.gmxeno = 0;
278 cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
280 /* Clear all error interrupts before enabling the interface. */
281 cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0,interface), ~0x0ull);
282 cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), ~0x0ull);
283 cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), ~0x0ull);
286 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
288 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
295 * Bringup and enable a XAUI interface. After this call packet
296 * I/O should be fully functional. This is called with IPD
297 * enabled but PKO disabled.
299 * @param interface Interface to bring up
301 * @return Zero on success, negative on failure
303 int __cvmx_helper_xaui_enable(int interface)
305 /* Setup PKND and BPID */
306 if (octeon_has_feature(OCTEON_FEATURE_PKND))
308 cvmx_gmxx_bpid_msk_t bpid_msk;
309 cvmx_gmxx_bpid_mapx_t bpid_map;
310 cvmx_gmxx_prtx_cfg_t gmxx_prtx_cfg;
311 cvmx_gmxx_txx_append_t gmxx_txx_append_cfg;
314 gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
315 gmxx_prtx_cfg.s.pknd = cvmx_helper_get_pknd(interface, 0);
316 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmxx_prtx_cfg.u64);
319 bpid_map.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MAPX(0, interface));
321 bpid_map.s.bpid = cvmx_helper_get_bpid(interface, 0);
322 cvmx_write_csr(CVMX_GMXX_BPID_MAPX(0, interface), bpid_map.u64);
324 bpid_msk.u64 = cvmx_read_csr(CVMX_GMXX_BPID_MSK(interface));
325 bpid_msk.s.msk_or |= 1;
326 bpid_msk.s.msk_and &= ~1;
327 cvmx_write_csr(CVMX_GMXX_BPID_MSK(interface), bpid_msk.u64);
329 /* CN68XX adds the padding and FCS in PKO, not GMX */
330 gmxx_txx_append_cfg.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
331 gmxx_txx_append_cfg.s.fcs = 0;
332 gmxx_txx_append_cfg.s.pad = 0;
333 cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmxx_txx_append_cfg.u64);
336 __cvmx_helper_xaui_link_init(interface);
343 * Return the link state of an IPD/PKO port as returned by
344 * auto negotiation. The result of this function may not match
345 * Octeon's link config if auto negotiation has changed since
346 * the last call to cvmx_helper_link_set().
348 * @param ipd_port IPD/PKO port to query
352 cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
354 int interface = cvmx_helper_get_interface_num(ipd_port);
355 cvmx_gmxx_tx_xaui_ctl_t gmxx_tx_xaui_ctl;
356 cvmx_gmxx_rx_xaui_ctl_t gmxx_rx_xaui_ctl;
357 cvmx_pcsxx_status1_reg_t pcsxx_status1_reg;
358 cvmx_helper_link_info_t result;
360 gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
361 gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
362 pcsxx_status1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
365 /* Only return a link if both RX and TX are happy */
366 if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
367 (pcsxx_status1_reg.s.rcv_lnk == 1))
369 cvmx_pcsxx_misc_ctl_reg_t misc_ctl;
370 result.s.link_up = 1;
371 result.s.full_duplex = 1;
372 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
374 cvmx_mio_qlmx_cfg_t qlm_cfg;
376 int qlm = (interface == 1) ? 0 : interface;
378 qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
379 result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
380 lanes = (qlm_cfg.s.qlm_cfg == 7) ? 2 : 4;
381 result.s.speed *= lanes;
383 else if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
385 int qlm = cvmx_qlm_interface(interface);
386 result.s.speed = cvmx_qlm_get_gbaud_mhz(qlm) * 8 / 10;
390 result.s.speed = 10000;
391 misc_ctl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
392 if (misc_ctl.s.gmxeno)
393 __cvmx_helper_xaui_link_init(interface);
397 /* Disable GMX and PCSX interrupts. */
398 cvmx_write_csr (CVMX_GMXX_RXX_INT_EN(0,interface), 0x0);
399 cvmx_write_csr (CVMX_GMXX_TX_INT_EN(interface), 0x0);
400 cvmx_write_csr (CVMX_PCSXX_INT_EN_REG(interface), 0x0);
408 * Configure an IPD/PKO port for the specified link state. This
409 * function does not influence auto negotiation at the PHY level.
410 * The passed link state must always match the link state returned
411 * by cvmx_helper_link_get(). It is normally best to use
412 * cvmx_helper_link_autoconf() instead.
414 * @param ipd_port IPD/PKO port to configure
415 * @param link_info The new link state
417 * @return Zero on success, negative on failure
419 int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
421 int interface = cvmx_helper_get_interface_num(ipd_port);
422 cvmx_gmxx_tx_xaui_ctl_t gmxx_tx_xaui_ctl;
423 cvmx_gmxx_rx_xaui_ctl_t gmxx_rx_xaui_ctl;
425 gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
426 gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
428 /* If the link shouldn't be up, then just return */
429 if (!link_info.s.link_up)
432 /* Do nothing if both RX and TX are happy */
433 if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
436 /* Bring the link up */
437 return __cvmx_helper_xaui_link_init(interface);
443 * Configure a port for internal and/or external loopback. Internal loopback
444 * causes packets sent by the port to be received by Octeon. External loopback
445 * causes packets received from the wire to sent out again.
447 * @param ipd_port IPD/PKO port to loopback.
448 * @param enable_internal
449 * Non zero if you want internal loopback
450 * @param enable_external
451 * Non zero if you want external loopback
453 * @return Zero on success, negative on failure.
455 extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, int enable_internal, int enable_external)
457 int interface = cvmx_helper_get_interface_num(ipd_port);
458 cvmx_pcsxx_control1_reg_t pcsxx_control1_reg;
459 cvmx_gmxx_xaui_ext_loopback_t gmxx_xaui_ext_loopback;
461 /* Set the internal loop */
462 pcsxx_control1_reg.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
463 pcsxx_control1_reg.s.loopbck1 = enable_internal;
464 cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), pcsxx_control1_reg.u64);
466 /* Set the external loop */
467 gmxx_xaui_ext_loopback.u64 = cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
468 gmxx_xaui_ext_loopback.s.en = enable_external;
469 cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), gmxx_xaui_ext_loopback.u64);
471 /* Take the link through a reset */
472 return __cvmx_helper_xaui_link_init(interface);
475 #endif /* CVMX_ENABLE_PKO_FUNCTIONS */