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49 * Interface to the hardware Input Packet Data unit.
51 * <hr>$Revision: 70030 $<hr>
55 #ifndef __CVMX_IPD_H__
56 #define __CVMX_IPD_H__
58 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
59 #include <asm/octeon/cvmx.h>
60 #include <asm/octeon/cvmx-config.h>
61 #include <asm/octeon/cvmx-ipd-defs.h>
63 # ifndef CVMX_DONT_INCLUDE_CONFIG
64 # include "executive-config.h"
65 # ifdef CVMX_ENABLE_PKO_FUNCTIONS
66 # include "cvmx-config.h"
75 #ifndef CVMX_ENABLE_LEN_M8_FIX
76 #define CVMX_ENABLE_LEN_M8_FIX 0
79 /* CSR typedefs have been moved to cvmx-ipd-defs.h */
81 typedef cvmx_ipd_1st_mbuff_skip_t cvmx_ipd_mbuff_not_first_skip_t;
82 typedef cvmx_ipd_1st_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
88 * @param mbuff_size Packets buffer size in 8 byte words
89 * @param first_mbuff_skip
90 * Number of 8 byte words to skip in the first buffer
91 * @param not_first_mbuff_skip
92 * Number of 8 byte words to skip in each following buffer
93 * @param first_back Must be same as first_mbuff_skip / 128
95 * Must be same as not_first_mbuff_skip / 128
97 * FPA pool to get work entries from
99 * @param back_pres_enable_flag
100 * Enable or disable port back pressure at a global level.
101 * This should always be 1 as more accurate control can be
102 * found in IPD_PORTX_BP_PAGE_CNT[BP_ENB].
104 static inline void cvmx_ipd_config(uint64_t mbuff_size,
105 uint64_t first_mbuff_skip,
106 uint64_t not_first_mbuff_skip,
108 uint64_t second_back,
109 uint64_t wqe_fpa_pool,
110 cvmx_ipd_mode_t cache_mode,
111 uint64_t back_pres_enable_flag
114 cvmx_ipd_1st_mbuff_skip_t first_skip;
115 cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
116 cvmx_ipd_packet_mbuff_size_t size;
117 cvmx_ipd_1st_next_ptr_back_t first_back_struct;
118 cvmx_ipd_second_next_ptr_back_t second_back_struct;
119 cvmx_ipd_wqe_fpa_queue_t wqe_pool;
120 cvmx_ipd_ctl_status_t ipd_ctl_reg;
123 first_skip.s.skip_sz = first_mbuff_skip;
124 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
126 not_first_skip.u64 = 0;
127 not_first_skip.s.skip_sz = not_first_mbuff_skip;
128 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
131 size.s.mb_size = mbuff_size;
132 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
134 first_back_struct.u64 = 0;
135 first_back_struct.s.back = first_back;
136 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
138 second_back_struct.u64 = 0;
139 second_back_struct.s.back = second_back;
140 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK,second_back_struct.u64);
143 wqe_pool.s.wqe_pool = wqe_fpa_pool;
144 cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
146 ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
147 ipd_ctl_reg.s.opc_mode = cache_mode;
148 ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
149 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
151 /* Note: the example RED code that used to be here has been moved to
152 cvmx_helper_setup_red */
159 static inline void cvmx_ipd_enable(void)
161 cvmx_ipd_ctl_status_t ipd_reg;
163 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
166 * busy-waiting for rst_done in o68
168 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
169 while(ipd_reg.s.rst_done != 0)
170 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
172 if (ipd_reg.s.ipd_en)
173 cvmx_dprintf("Warning: Enabling IPD when IPD already enabled.\n");
175 ipd_reg.s.ipd_en = 1;
177 #if CVMX_ENABLE_LEN_M8_FIX
178 if(!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
179 ipd_reg.s.len_m8 = 1;
182 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
189 static inline void cvmx_ipd_disable(void)
191 cvmx_ipd_ctl_status_t ipd_reg;
192 ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
193 ipd_reg.s.ipd_en = 0;
194 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
197 extern void __cvmx_ipd_free_ptr(void);
203 #endif /* __CVMX_IPD_H__ */