1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_KEY_DEFS_H__
53 #define __CVMX_KEY_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC()
57 static inline uint64_t CVMX_KEY_BIST_REG_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
60 cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180020000018ull);
64 #define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC()
68 static inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
71 cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180020000010ull);
75 #define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC()
79 static inline uint64_t CVMX_KEY_INT_ENB_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
82 cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180020000008ull);
86 #define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC()
90 static inline uint64_t CVMX_KEY_INT_SUM_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
93 cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180020000000ull);
97 #define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull))
103 * KEY_BIST_REG = KEY's BIST Status Register
105 * The KEY's BIST status for memories.
107 union cvmx_key_bist_reg {
109 struct cvmx_key_bist_reg_s {
110 #ifdef __BIG_ENDIAN_BITFIELD
111 uint64_t reserved_3_63 : 61;
112 uint64_t rrc : 1; /**< RRC bist status. */
113 uint64_t mem1 : 1; /**< MEM - 1 bist status. */
114 uint64_t mem0 : 1; /**< MEM - 0 bist status. */
119 uint64_t reserved_3_63 : 61;
122 struct cvmx_key_bist_reg_s cn38xx;
123 struct cvmx_key_bist_reg_s cn38xxp2;
124 struct cvmx_key_bist_reg_s cn56xx;
125 struct cvmx_key_bist_reg_s cn56xxp1;
126 struct cvmx_key_bist_reg_s cn58xx;
127 struct cvmx_key_bist_reg_s cn58xxp1;
128 struct cvmx_key_bist_reg_s cn61xx;
129 struct cvmx_key_bist_reg_s cn63xx;
130 struct cvmx_key_bist_reg_s cn63xxp1;
131 struct cvmx_key_bist_reg_s cn66xx;
132 struct cvmx_key_bist_reg_s cn68xx;
133 struct cvmx_key_bist_reg_s cn68xxp1;
134 struct cvmx_key_bist_reg_s cnf71xx;
136 typedef union cvmx_key_bist_reg cvmx_key_bist_reg_t;
139 * cvmx_key_ctl_status
141 * KEY_CTL_STATUS = KEY's Control/Status Register
143 * The KEY's interrupt enable register.
145 union cvmx_key_ctl_status {
147 struct cvmx_key_ctl_status_s {
148 #ifdef __BIG_ENDIAN_BITFIELD
149 uint64_t reserved_14_63 : 50;
150 uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32
151 respective to bit 13:7 of this field, for FPF
153 uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32
154 respective to bit 6:0 of this field, for FPF
157 uint64_t mem0_err : 7;
158 uint64_t mem1_err : 7;
159 uint64_t reserved_14_63 : 50;
162 struct cvmx_key_ctl_status_s cn38xx;
163 struct cvmx_key_ctl_status_s cn38xxp2;
164 struct cvmx_key_ctl_status_s cn56xx;
165 struct cvmx_key_ctl_status_s cn56xxp1;
166 struct cvmx_key_ctl_status_s cn58xx;
167 struct cvmx_key_ctl_status_s cn58xxp1;
168 struct cvmx_key_ctl_status_s cn61xx;
169 struct cvmx_key_ctl_status_s cn63xx;
170 struct cvmx_key_ctl_status_s cn63xxp1;
171 struct cvmx_key_ctl_status_s cn66xx;
172 struct cvmx_key_ctl_status_s cn68xx;
173 struct cvmx_key_ctl_status_s cn68xxp1;
174 struct cvmx_key_ctl_status_s cnf71xx;
176 typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t;
181 * KEY_INT_ENB = KEY's Interrupt Enable
183 * The KEY's interrupt enable register.
185 union cvmx_key_int_enb {
187 struct cvmx_key_int_enb_s {
188 #ifdef __BIG_ENDIAN_BITFIELD
189 uint64_t reserved_4_63 : 60;
190 uint64_t ked1_dbe : 1; /**< When set (1) and bit 3 of the KEY_INT_SUM
191 register is asserted the KEY will assert an
193 uint64_t ked1_sbe : 1; /**< When set (1) and bit 2 of the KEY_INT_SUM
194 register is asserted the KEY will assert an
196 uint64_t ked0_dbe : 1; /**< When set (1) and bit 1 of the KEY_INT_SUM
197 register is asserted the KEY will assert an
199 uint64_t ked0_sbe : 1; /**< When set (1) and bit 0 of the KEY_INT_SUM
200 register is asserted the KEY will assert an
203 uint64_t ked0_sbe : 1;
204 uint64_t ked0_dbe : 1;
205 uint64_t ked1_sbe : 1;
206 uint64_t ked1_dbe : 1;
207 uint64_t reserved_4_63 : 60;
210 struct cvmx_key_int_enb_s cn38xx;
211 struct cvmx_key_int_enb_s cn38xxp2;
212 struct cvmx_key_int_enb_s cn56xx;
213 struct cvmx_key_int_enb_s cn56xxp1;
214 struct cvmx_key_int_enb_s cn58xx;
215 struct cvmx_key_int_enb_s cn58xxp1;
216 struct cvmx_key_int_enb_s cn61xx;
217 struct cvmx_key_int_enb_s cn63xx;
218 struct cvmx_key_int_enb_s cn63xxp1;
219 struct cvmx_key_int_enb_s cn66xx;
220 struct cvmx_key_int_enb_s cn68xx;
221 struct cvmx_key_int_enb_s cn68xxp1;
222 struct cvmx_key_int_enb_s cnf71xx;
224 typedef union cvmx_key_int_enb cvmx_key_int_enb_t;
229 * KEY_INT_SUM = KEY's Interrupt Summary Register
231 * Contains the diffrent interrupt summary bits of the KEY.
233 union cvmx_key_int_sum {
235 struct cvmx_key_int_sum_s {
236 #ifdef __BIG_ENDIAN_BITFIELD
237 uint64_t reserved_4_63 : 60;
238 uint64_t ked1_dbe : 1;
239 uint64_t ked1_sbe : 1;
240 uint64_t ked0_dbe : 1;
241 uint64_t ked0_sbe : 1;
243 uint64_t ked0_sbe : 1;
244 uint64_t ked0_dbe : 1;
245 uint64_t ked1_sbe : 1;
246 uint64_t ked1_dbe : 1;
247 uint64_t reserved_4_63 : 60;
250 struct cvmx_key_int_sum_s cn38xx;
251 struct cvmx_key_int_sum_s cn38xxp2;
252 struct cvmx_key_int_sum_s cn56xx;
253 struct cvmx_key_int_sum_s cn56xxp1;
254 struct cvmx_key_int_sum_s cn58xx;
255 struct cvmx_key_int_sum_s cn58xxp1;
256 struct cvmx_key_int_sum_s cn61xx;
257 struct cvmx_key_int_sum_s cn63xx;
258 struct cvmx_key_int_sum_s cn63xxp1;
259 struct cvmx_key_int_sum_s cn66xx;
260 struct cvmx_key_int_sum_s cn68xx;
261 struct cvmx_key_int_sum_s cn68xxp1;
262 struct cvmx_key_int_sum_s cnf71xx;
264 typedef union cvmx_key_int_sum cvmx_key_int_sum_t;