1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Inc. nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_L2D_DEFS_H__
53 #define __CVMX_L2D_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_L2D_BST0 CVMX_L2D_BST0_FUNC()
57 static inline uint64_t CVMX_L2D_BST0_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
60 cvmx_warn("CVMX_L2D_BST0 not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180080000780ull);
64 #define CVMX_L2D_BST0 (CVMX_ADD_IO_SEG(0x0001180080000780ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_L2D_BST1 CVMX_L2D_BST1_FUNC()
68 static inline uint64_t CVMX_L2D_BST1_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
71 cvmx_warn("CVMX_L2D_BST1 not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180080000788ull);
75 #define CVMX_L2D_BST1 (CVMX_ADD_IO_SEG(0x0001180080000788ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_L2D_BST2 CVMX_L2D_BST2_FUNC()
79 static inline uint64_t CVMX_L2D_BST2_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
82 cvmx_warn("CVMX_L2D_BST2 not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001180080000790ull);
86 #define CVMX_L2D_BST2 (CVMX_ADD_IO_SEG(0x0001180080000790ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_L2D_BST3 CVMX_L2D_BST3_FUNC()
90 static inline uint64_t CVMX_L2D_BST3_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
93 cvmx_warn("CVMX_L2D_BST3 not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001180080000798ull);
97 #define CVMX_L2D_BST3 (CVMX_ADD_IO_SEG(0x0001180080000798ull))
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_L2D_ERR CVMX_L2D_ERR_FUNC()
101 static inline uint64_t CVMX_L2D_ERR_FUNC(void)
103 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
104 cvmx_warn("CVMX_L2D_ERR not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001180080000010ull);
108 #define CVMX_L2D_ERR (CVMX_ADD_IO_SEG(0x0001180080000010ull))
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_L2D_FADR CVMX_L2D_FADR_FUNC()
112 static inline uint64_t CVMX_L2D_FADR_FUNC(void)
114 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
115 cvmx_warn("CVMX_L2D_FADR not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001180080000018ull);
119 #define CVMX_L2D_FADR (CVMX_ADD_IO_SEG(0x0001180080000018ull))
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_L2D_FSYN0 CVMX_L2D_FSYN0_FUNC()
123 static inline uint64_t CVMX_L2D_FSYN0_FUNC(void)
125 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
126 cvmx_warn("CVMX_L2D_FSYN0 not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001180080000020ull);
130 #define CVMX_L2D_FSYN0 (CVMX_ADD_IO_SEG(0x0001180080000020ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_L2D_FSYN1 CVMX_L2D_FSYN1_FUNC()
134 static inline uint64_t CVMX_L2D_FSYN1_FUNC(void)
136 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
137 cvmx_warn("CVMX_L2D_FSYN1 not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001180080000028ull);
141 #define CVMX_L2D_FSYN1 (CVMX_ADD_IO_SEG(0x0001180080000028ull))
143 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
144 #define CVMX_L2D_FUS0 CVMX_L2D_FUS0_FUNC()
145 static inline uint64_t CVMX_L2D_FUS0_FUNC(void)
147 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
148 cvmx_warn("CVMX_L2D_FUS0 not supported on this chip\n");
149 return CVMX_ADD_IO_SEG(0x00011800800007A0ull);
152 #define CVMX_L2D_FUS0 (CVMX_ADD_IO_SEG(0x00011800800007A0ull))
154 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
155 #define CVMX_L2D_FUS1 CVMX_L2D_FUS1_FUNC()
156 static inline uint64_t CVMX_L2D_FUS1_FUNC(void)
158 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
159 cvmx_warn("CVMX_L2D_FUS1 not supported on this chip\n");
160 return CVMX_ADD_IO_SEG(0x00011800800007A8ull);
163 #define CVMX_L2D_FUS1 (CVMX_ADD_IO_SEG(0x00011800800007A8ull))
165 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
166 #define CVMX_L2D_FUS2 CVMX_L2D_FUS2_FUNC()
167 static inline uint64_t CVMX_L2D_FUS2_FUNC(void)
169 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
170 cvmx_warn("CVMX_L2D_FUS2 not supported on this chip\n");
171 return CVMX_ADD_IO_SEG(0x00011800800007B0ull);
174 #define CVMX_L2D_FUS2 (CVMX_ADD_IO_SEG(0x00011800800007B0ull))
176 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
177 #define CVMX_L2D_FUS3 CVMX_L2D_FUS3_FUNC()
178 static inline uint64_t CVMX_L2D_FUS3_FUNC(void)
180 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)))
181 cvmx_warn("CVMX_L2D_FUS3 not supported on this chip\n");
182 return CVMX_ADD_IO_SEG(0x00011800800007B8ull);
185 #define CVMX_L2D_FUS3 (CVMX_ADD_IO_SEG(0x00011800800007B8ull))
191 * L2D_BST0 = L2C Data Store QUAD0 BIST Status Register
194 union cvmx_l2d_bst0 {
196 struct cvmx_l2d_bst0_s {
197 #ifdef __BIG_ENDIAN_BITFIELD
198 uint64_t reserved_35_63 : 29;
199 uint64_t ftl : 1; /**< L2C Data Store Fatal Defect(across all QUADs)
200 2 or more columns were detected bad across all
201 QUADs[0-3]. Please refer to individual quad failures
202 for bad column = 0x7e to determine which QUAD was in
204 uint64_t q0stat : 34; /**< Bist Results for QUAD0
207 [13:7] bad high column
211 [30:24] bad high column
212 [23:17] bad low column
213 NOTES: For bad high/low column reporting:
215 0x7e: Fatal Defect: 2 or more bad columns
217 NOTE: If there are less than 2 failures then the
218 bad bank will be 0x7. */
220 uint64_t q0stat : 34;
222 uint64_t reserved_35_63 : 29;
225 struct cvmx_l2d_bst0_s cn30xx;
226 struct cvmx_l2d_bst0_s cn31xx;
227 struct cvmx_l2d_bst0_s cn38xx;
228 struct cvmx_l2d_bst0_s cn38xxp2;
229 struct cvmx_l2d_bst0_s cn50xx;
230 struct cvmx_l2d_bst0_s cn52xx;
231 struct cvmx_l2d_bst0_s cn52xxp1;
232 struct cvmx_l2d_bst0_s cn56xx;
233 struct cvmx_l2d_bst0_s cn56xxp1;
234 struct cvmx_l2d_bst0_s cn58xx;
235 struct cvmx_l2d_bst0_s cn58xxp1;
237 typedef union cvmx_l2d_bst0 cvmx_l2d_bst0_t;
242 * L2D_BST1 = L2C Data Store QUAD1 BIST Status Register
245 union cvmx_l2d_bst1 {
247 struct cvmx_l2d_bst1_s {
248 #ifdef __BIG_ENDIAN_BITFIELD
249 uint64_t reserved_34_63 : 30;
250 uint64_t q1stat : 34; /**< Bist Results for QUAD1
253 [13:7] bad high column
257 [30:24] bad high column
258 [23:17] bad low column
259 NOTES: For bad high/low column reporting:
261 0x7e: Fatal Defect: 2 or more bad columns
263 NOTE: If there are less than 2 failures then the
264 bad bank will be 0x7. */
266 uint64_t q1stat : 34;
267 uint64_t reserved_34_63 : 30;
270 struct cvmx_l2d_bst1_s cn30xx;
271 struct cvmx_l2d_bst1_s cn31xx;
272 struct cvmx_l2d_bst1_s cn38xx;
273 struct cvmx_l2d_bst1_s cn38xxp2;
274 struct cvmx_l2d_bst1_s cn50xx;
275 struct cvmx_l2d_bst1_s cn52xx;
276 struct cvmx_l2d_bst1_s cn52xxp1;
277 struct cvmx_l2d_bst1_s cn56xx;
278 struct cvmx_l2d_bst1_s cn56xxp1;
279 struct cvmx_l2d_bst1_s cn58xx;
280 struct cvmx_l2d_bst1_s cn58xxp1;
282 typedef union cvmx_l2d_bst1 cvmx_l2d_bst1_t;
287 * L2D_BST2 = L2C Data Store QUAD2 BIST Status Register
290 union cvmx_l2d_bst2 {
292 struct cvmx_l2d_bst2_s {
293 #ifdef __BIG_ENDIAN_BITFIELD
294 uint64_t reserved_34_63 : 30;
295 uint64_t q2stat : 34; /**< Bist Results for QUAD2
298 [13:7] bad high column
302 [30:24] bad high column
303 [23:17] bad low column
304 NOTES: For bad high/low column reporting:
306 0x7e: Fatal Defect: 2 or more bad columns
308 NOTE: If there are less than 2 failures then the
309 bad bank will be 0x7. */
311 uint64_t q2stat : 34;
312 uint64_t reserved_34_63 : 30;
315 struct cvmx_l2d_bst2_s cn30xx;
316 struct cvmx_l2d_bst2_s cn31xx;
317 struct cvmx_l2d_bst2_s cn38xx;
318 struct cvmx_l2d_bst2_s cn38xxp2;
319 struct cvmx_l2d_bst2_s cn50xx;
320 struct cvmx_l2d_bst2_s cn52xx;
321 struct cvmx_l2d_bst2_s cn52xxp1;
322 struct cvmx_l2d_bst2_s cn56xx;
323 struct cvmx_l2d_bst2_s cn56xxp1;
324 struct cvmx_l2d_bst2_s cn58xx;
325 struct cvmx_l2d_bst2_s cn58xxp1;
327 typedef union cvmx_l2d_bst2 cvmx_l2d_bst2_t;
332 * L2D_BST3 = L2C Data Store QUAD3 BIST Status Register
335 union cvmx_l2d_bst3 {
337 struct cvmx_l2d_bst3_s {
338 #ifdef __BIG_ENDIAN_BITFIELD
339 uint64_t reserved_34_63 : 30;
340 uint64_t q3stat : 34; /**< Bist Results for QUAD3
343 [13:7] bad high column
347 [30:24] bad high column
348 [23:17] bad low column
349 NOTES: For bad high/low column reporting:
351 0x7e: Fatal Defect: 2 or more bad columns
353 NOTE: If there are less than 2 failures then the
354 bad bank will be 0x7. */
356 uint64_t q3stat : 34;
357 uint64_t reserved_34_63 : 30;
360 struct cvmx_l2d_bst3_s cn30xx;
361 struct cvmx_l2d_bst3_s cn31xx;
362 struct cvmx_l2d_bst3_s cn38xx;
363 struct cvmx_l2d_bst3_s cn38xxp2;
364 struct cvmx_l2d_bst3_s cn50xx;
365 struct cvmx_l2d_bst3_s cn52xx;
366 struct cvmx_l2d_bst3_s cn52xxp1;
367 struct cvmx_l2d_bst3_s cn56xx;
368 struct cvmx_l2d_bst3_s cn56xxp1;
369 struct cvmx_l2d_bst3_s cn58xx;
370 struct cvmx_l2d_bst3_s cn58xxp1;
372 typedef union cvmx_l2d_bst3 cvmx_l2d_bst3_t;
377 * L2D_ERR = L2 Data Errors
379 * Description: L2 Data ECC SEC/DED Errors and Interrupt Enable
383 struct cvmx_l2d_err_s {
384 #ifdef __BIG_ENDIAN_BITFIELD
385 uint64_t reserved_6_63 : 58;
386 uint64_t bmhclsel : 1; /**< L2 Bit Map Half CacheLine ECC Selector
388 When L2C_DBG[L2T]=1/L2D_ERR[ECC_ENA]=0, the BMHCLSEL selects
389 which half cacheline to conditionally latch into
390 the L2D_FSYN0/L2D_FSYN1 registers when an LDD command
391 is detected from the diagnostic PP (see L2C_DBG[PPNUM]).
392 - 0: OW[0-3] ECC (from first 1/2 cacheline) is selected to
393 be conditionally latched into the L2D_FSYN0/1 CSRs.
394 - 1: OW[4-7] ECC (from last 1/2 cacheline) is selected to
395 be conditionally latched into
396 the L2D_FSYN0/1 CSRs. */
397 uint64_t ded_err : 1; /**< L2D Double Error detected (DED) */
398 uint64_t sec_err : 1; /**< L2D Single Error corrected (SEC) */
399 uint64_t ded_intena : 1; /**< L2 Data ECC Double Error Detect(DED) Interrupt Enable bit
400 When set, allows interrupts to be reported on double bit
401 (uncorrectable) errors from the L2 Data Arrays. */
402 uint64_t sec_intena : 1; /**< L2 Data ECC Single Error Correct(SEC) Interrupt Enable bit
403 When set, allows interrupts to be reported on single bit
404 (correctable) errors from the L2 Data Arrays. */
405 uint64_t ecc_ena : 1; /**< L2 Data ECC Enable
406 When set, enables 10-bit SEC/DED codeword for 128bit L2
409 uint64_t ecc_ena : 1;
410 uint64_t sec_intena : 1;
411 uint64_t ded_intena : 1;
412 uint64_t sec_err : 1;
413 uint64_t ded_err : 1;
414 uint64_t bmhclsel : 1;
415 uint64_t reserved_6_63 : 58;
418 struct cvmx_l2d_err_s cn30xx;
419 struct cvmx_l2d_err_s cn31xx;
420 struct cvmx_l2d_err_s cn38xx;
421 struct cvmx_l2d_err_s cn38xxp2;
422 struct cvmx_l2d_err_s cn50xx;
423 struct cvmx_l2d_err_s cn52xx;
424 struct cvmx_l2d_err_s cn52xxp1;
425 struct cvmx_l2d_err_s cn56xx;
426 struct cvmx_l2d_err_s cn56xxp1;
427 struct cvmx_l2d_err_s cn58xx;
428 struct cvmx_l2d_err_s cn58xxp1;
430 typedef union cvmx_l2d_err cvmx_l2d_err_t;
435 * L2D_FADR = L2 Failing Address
437 * Description: L2 Data ECC SEC/DED Failing Address
440 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data store index.
441 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
443 union cvmx_l2d_fadr {
445 struct cvmx_l2d_fadr_s {
446 #ifdef __BIG_ENDIAN_BITFIELD
447 uint64_t reserved_19_63 : 45;
448 uint64_t fadru : 1; /**< Failing L2 Data Store Upper Index bit(MSB) */
449 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
451 uint64_t fset : 3; /**< Failing SET# */
452 uint64_t fadr : 11; /**< Failing L2 Data Store Lower Index bits
453 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
454 [FADRU, FADR[10:1]]: cacheline index[17:7]
455 FADR[0]: 1/2 cacheline index
456 NOTE: FADR[1] is used to select between upper/lower 1MB
457 physical L2 Data Store banks. */
463 uint64_t reserved_19_63 : 45;
466 struct cvmx_l2d_fadr_cn30xx {
467 #ifdef __BIG_ENDIAN_BITFIELD
468 uint64_t reserved_18_63 : 46;
469 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
471 uint64_t reserved_13_13 : 1;
472 uint64_t fset : 2; /**< Failing SET# */
473 uint64_t reserved_9_10 : 2;
474 uint64_t fadr : 9; /**< Failing L2 Data Store Index(1of512 = 1/2 CL address) */
477 uint64_t reserved_9_10 : 2;
479 uint64_t reserved_13_13 : 1;
481 uint64_t reserved_18_63 : 46;
484 struct cvmx_l2d_fadr_cn31xx {
485 #ifdef __BIG_ENDIAN_BITFIELD
486 uint64_t reserved_18_63 : 46;
487 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
489 uint64_t reserved_13_13 : 1;
490 uint64_t fset : 2; /**< Failing SET# */
491 uint64_t reserved_10_10 : 1;
492 uint64_t fadr : 10; /**< Failing L2 Data Store Index
493 (1 of 1024 = half cacheline indices) */
496 uint64_t reserved_10_10 : 1;
498 uint64_t reserved_13_13 : 1;
500 uint64_t reserved_18_63 : 46;
503 struct cvmx_l2d_fadr_cn38xx {
504 #ifdef __BIG_ENDIAN_BITFIELD
505 uint64_t reserved_18_63 : 46;
506 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
508 uint64_t fset : 3; /**< Failing SET# */
509 uint64_t fadr : 11; /**< Failing L2 Data Store Index (1of2K = 1/2 CL address) */
514 uint64_t reserved_18_63 : 46;
517 struct cvmx_l2d_fadr_cn38xx cn38xxp2;
518 struct cvmx_l2d_fadr_cn50xx {
519 #ifdef __BIG_ENDIAN_BITFIELD
520 uint64_t reserved_18_63 : 46;
521 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
523 uint64_t fset : 3; /**< Failing SET# */
524 uint64_t reserved_8_10 : 3;
525 uint64_t fadr : 8; /**< Failing L2 Data Store Lower Index bits
526 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
527 FADR[7:1]: cacheline index[13:7]
528 FADR[0]: 1/2 cacheline index */
531 uint64_t reserved_8_10 : 3;
534 uint64_t reserved_18_63 : 46;
537 struct cvmx_l2d_fadr_cn52xx {
538 #ifdef __BIG_ENDIAN_BITFIELD
539 uint64_t reserved_18_63 : 46;
540 uint64_t fowmsk : 4; /**< Failing OW Mask (which one of 4 OWs contained SEC/DED
542 uint64_t fset : 3; /**< Failing SET# */
543 uint64_t reserved_10_10 : 1;
544 uint64_t fadr : 10; /**< Failing L2 Data Store Lower Index bits
545 (NOTE: L2 Data Store Index is for each 1/2 cacheline)
546 FADR[9:1]: cacheline index[15:7]
547 FADR[0]: 1/2 cacheline index */
550 uint64_t reserved_10_10 : 1;
553 uint64_t reserved_18_63 : 46;
556 struct cvmx_l2d_fadr_cn52xx cn52xxp1;
557 struct cvmx_l2d_fadr_s cn56xx;
558 struct cvmx_l2d_fadr_s cn56xxp1;
559 struct cvmx_l2d_fadr_s cn58xx;
560 struct cvmx_l2d_fadr_s cn58xxp1;
562 typedef union cvmx_l2d_fadr cvmx_l2d_fadr_t;
567 * L2D_FSYN0 = L2 Failing Syndrome [OW0,4 / OW1,5]
569 * Description: L2 Data ECC SEC/DED Failing Syndrome for lower cache line
572 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
573 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
575 union cvmx_l2d_fsyn0 {
577 struct cvmx_l2d_fsyn0_s {
578 #ifdef __BIG_ENDIAN_BITFIELD
579 uint64_t reserved_20_63 : 44;
580 uint64_t fsyn_ow1 : 10; /**< Failing L2 Data Store SYNDROME OW[1,5]
581 When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
582 or L2D_ERR[DED_ERR] are set, this field represents
583 the failing OWECC syndrome for the half cacheline
584 indexed by L2D_FADR[FADR].
585 NOTE: The L2D_FADR[FOWMSK] further qualifies which
586 OW lane(1of4) detected the error.
587 When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
588 command from the diagnostic PP will conditionally latch
589 the raw OWECC for the selected half cacheline.
590 (see: L2D_ERR[BMHCLSEL] */
591 uint64_t fsyn_ow0 : 10; /**< Failing L2 Data Store SYNDROME OW[0,4]
592 When L2D_ERR[ECC_ENA]=1 and either L2D_ERR[SEC_ERR]
593 or L2D_ERR[DED_ERR] are set, this field represents
594 the failing OWECC syndrome for the half cacheline
595 indexed by L2D_FADR[FADR].
596 NOTE: The L2D_FADR[FOWMSK] further qualifies which
597 OW lane(1of4) detected the error.
598 When L2C_DBG[L2T]=1 and L2D_ERR[ECC_ENA]=0, an LDD
599 (L1 load-miss) from the diagnostic PP will conditionally
600 latch the raw OWECC for the selected half cacheline.
601 (see: L2D_ERR[BMHCLSEL] */
603 uint64_t fsyn_ow0 : 10;
604 uint64_t fsyn_ow1 : 10;
605 uint64_t reserved_20_63 : 44;
608 struct cvmx_l2d_fsyn0_s cn30xx;
609 struct cvmx_l2d_fsyn0_s cn31xx;
610 struct cvmx_l2d_fsyn0_s cn38xx;
611 struct cvmx_l2d_fsyn0_s cn38xxp2;
612 struct cvmx_l2d_fsyn0_s cn50xx;
613 struct cvmx_l2d_fsyn0_s cn52xx;
614 struct cvmx_l2d_fsyn0_s cn52xxp1;
615 struct cvmx_l2d_fsyn0_s cn56xx;
616 struct cvmx_l2d_fsyn0_s cn56xxp1;
617 struct cvmx_l2d_fsyn0_s cn58xx;
618 struct cvmx_l2d_fsyn0_s cn58xxp1;
620 typedef union cvmx_l2d_fsyn0 cvmx_l2d_fsyn0_t;
625 * L2D_FSYN1 = L2 Failing Syndrome [OW2,6 / OW3,7]
627 * Description: L2 Data ECC SEC/DED Failing Syndrome for upper cache line
630 * When L2D_SEC_ERR or L2D_DED_ERR are set, this field contains the failing L2 Data ECC 10b syndrome.
631 * (A DED Error will always overwrite a SEC Error SYNDROME and FADR).
633 union cvmx_l2d_fsyn1 {
635 struct cvmx_l2d_fsyn1_s {
636 #ifdef __BIG_ENDIAN_BITFIELD
637 uint64_t reserved_20_63 : 44;
638 uint64_t fsyn_ow3 : 10; /**< Failing L2 Data Store SYNDROME OW[3,7] */
639 uint64_t fsyn_ow2 : 10; /**< Failing L2 Data Store SYNDROME OW[2,5] */
641 uint64_t fsyn_ow2 : 10;
642 uint64_t fsyn_ow3 : 10;
643 uint64_t reserved_20_63 : 44;
646 struct cvmx_l2d_fsyn1_s cn30xx;
647 struct cvmx_l2d_fsyn1_s cn31xx;
648 struct cvmx_l2d_fsyn1_s cn38xx;
649 struct cvmx_l2d_fsyn1_s cn38xxp2;
650 struct cvmx_l2d_fsyn1_s cn50xx;
651 struct cvmx_l2d_fsyn1_s cn52xx;
652 struct cvmx_l2d_fsyn1_s cn52xxp1;
653 struct cvmx_l2d_fsyn1_s cn56xx;
654 struct cvmx_l2d_fsyn1_s cn56xxp1;
655 struct cvmx_l2d_fsyn1_s cn58xx;
656 struct cvmx_l2d_fsyn1_s cn58xxp1;
658 typedef union cvmx_l2d_fsyn1 cvmx_l2d_fsyn1_t;
663 * L2D_FUS0 = L2C Data Store QUAD0 Fuse Register
666 union cvmx_l2d_fus0 {
668 struct cvmx_l2d_fus0_s {
669 #ifdef __BIG_ENDIAN_BITFIELD
670 uint64_t reserved_34_63 : 30;
671 uint64_t q0fus : 34; /**< Fuse Register for QUAD0
672 This is purely for debug and not needed in the general
674 Note that the fuse are complementary (Assigning a
675 fuse to 1 will read as a zero). This means the case
676 where no fuses are blown result in these csr's showing
678 Failure \#1 Fuse Mapping
680 [13:7] bad high column
682 Failure \#2 Fuse Mapping
684 [30:24] bad high column
685 [23:17] bad low column */
688 uint64_t reserved_34_63 : 30;
691 struct cvmx_l2d_fus0_s cn30xx;
692 struct cvmx_l2d_fus0_s cn31xx;
693 struct cvmx_l2d_fus0_s cn38xx;
694 struct cvmx_l2d_fus0_s cn38xxp2;
695 struct cvmx_l2d_fus0_s cn50xx;
696 struct cvmx_l2d_fus0_s cn52xx;
697 struct cvmx_l2d_fus0_s cn52xxp1;
698 struct cvmx_l2d_fus0_s cn56xx;
699 struct cvmx_l2d_fus0_s cn56xxp1;
700 struct cvmx_l2d_fus0_s cn58xx;
701 struct cvmx_l2d_fus0_s cn58xxp1;
703 typedef union cvmx_l2d_fus0 cvmx_l2d_fus0_t;
708 * L2D_FUS1 = L2C Data Store QUAD1 Fuse Register
711 union cvmx_l2d_fus1 {
713 struct cvmx_l2d_fus1_s {
714 #ifdef __BIG_ENDIAN_BITFIELD
715 uint64_t reserved_34_63 : 30;
716 uint64_t q1fus : 34; /**< Fuse Register for QUAD1
717 This is purely for debug and not needed in the general
719 Note that the fuse are complementary (Assigning a
720 fuse to 1 will read as a zero). This means the case
721 where no fuses are blown result in these csr's showing
723 Failure \#1 Fuse Mapping
725 [13:7] bad high column
727 Failure \#2 Fuse Mapping
729 [30:24] bad high column
730 [23:17] bad low column */
733 uint64_t reserved_34_63 : 30;
736 struct cvmx_l2d_fus1_s cn30xx;
737 struct cvmx_l2d_fus1_s cn31xx;
738 struct cvmx_l2d_fus1_s cn38xx;
739 struct cvmx_l2d_fus1_s cn38xxp2;
740 struct cvmx_l2d_fus1_s cn50xx;
741 struct cvmx_l2d_fus1_s cn52xx;
742 struct cvmx_l2d_fus1_s cn52xxp1;
743 struct cvmx_l2d_fus1_s cn56xx;
744 struct cvmx_l2d_fus1_s cn56xxp1;
745 struct cvmx_l2d_fus1_s cn58xx;
746 struct cvmx_l2d_fus1_s cn58xxp1;
748 typedef union cvmx_l2d_fus1 cvmx_l2d_fus1_t;
753 * L2D_FUS2 = L2C Data Store QUAD2 Fuse Register
756 union cvmx_l2d_fus2 {
758 struct cvmx_l2d_fus2_s {
759 #ifdef __BIG_ENDIAN_BITFIELD
760 uint64_t reserved_34_63 : 30;
761 uint64_t q2fus : 34; /**< Fuse Register for QUAD2
762 This is purely for debug and not needed in the general
764 Note that the fuse are complementary (Assigning a
765 fuse to 1 will read as a zero). This means the case
766 where no fuses are blown result in these csr's showing
768 Failure \#1 Fuse Mapping
770 [13:7] bad high column
772 Failure \#2 Fuse Mapping
774 [30:24] bad high column
775 [23:17] bad low column */
778 uint64_t reserved_34_63 : 30;
781 struct cvmx_l2d_fus2_s cn30xx;
782 struct cvmx_l2d_fus2_s cn31xx;
783 struct cvmx_l2d_fus2_s cn38xx;
784 struct cvmx_l2d_fus2_s cn38xxp2;
785 struct cvmx_l2d_fus2_s cn50xx;
786 struct cvmx_l2d_fus2_s cn52xx;
787 struct cvmx_l2d_fus2_s cn52xxp1;
788 struct cvmx_l2d_fus2_s cn56xx;
789 struct cvmx_l2d_fus2_s cn56xxp1;
790 struct cvmx_l2d_fus2_s cn58xx;
791 struct cvmx_l2d_fus2_s cn58xxp1;
793 typedef union cvmx_l2d_fus2 cvmx_l2d_fus2_t;
798 * L2D_FUS3 = L2C Data Store QUAD3 Fuse Register
801 union cvmx_l2d_fus3 {
803 struct cvmx_l2d_fus3_s {
804 #ifdef __BIG_ENDIAN_BITFIELD
805 uint64_t reserved_40_63 : 24;
806 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
807 These bits are used to 'observe' the EMA[1:0] inputs
808 for the L2 Data Store RAMs which are controlled by
809 either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
810 From poweron (dc_ok), the EMA_CTL are driven from
811 FUSE[141:140]. However after the 1st CSR write to the
812 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
813 from the MIO_FUSE_EMA[EMA] register permanently
815 uint64_t reserved_34_36 : 3;
816 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
817 This is purely for debug and not needed in the general
819 Note that the fuses are complementary (Assigning a
820 fuse to 1 will read as a zero). This means the case
821 where no fuses are blown result in these csr's showing
823 Failure \#1 Fuse Mapping
825 [13:7] bad high column
827 Failure \#2 Fuse Mapping
829 [30:24] bad high column
830 [23:17] bad low column */
833 uint64_t reserved_34_36 : 3;
834 uint64_t ema_ctl : 3;
835 uint64_t reserved_40_63 : 24;
838 struct cvmx_l2d_fus3_cn30xx {
839 #ifdef __BIG_ENDIAN_BITFIELD
840 uint64_t reserved_35_63 : 29;
841 uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general
843 If the FUSE is not-blown, then this bit should read
844 as 0. If the FUSE is blown, then this bit should read
846 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
847 This is purely for debug and not needed in the general
849 Note that the fuses are complementary (Assigning a
850 fuse to 1 will read as a zero). This means the case
851 where no fuses are blown result in these csr's showing
853 Failure \#1 Fuse Mapping
856 [13:7] bad high column
858 Failure \#2 Fuse Mapping
861 [30:24] bad high column
862 [23:17] bad low column */
865 uint64_t crip_64k : 1;
866 uint64_t reserved_35_63 : 29;
869 struct cvmx_l2d_fus3_cn31xx {
870 #ifdef __BIG_ENDIAN_BITFIELD
871 uint64_t reserved_35_63 : 29;
872 uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general
874 If the FUSE is not-blown, then this bit should read
875 as 0. If the FUSE is blown, then this bit should read
877 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
878 This is purely for debug and not needed in the general
880 Note that the fuses are complementary (Assigning a
881 fuse to 1 will read as a zero). This means the case
882 where no fuses are blown result in these csr's showing
884 Failure \#1 Fuse Mapping
887 [13:7] bad high column
889 Failure \#2 Fuse Mapping
892 [30:24] bad high column
893 [23:17] bad low column */
896 uint64_t crip_128k : 1;
897 uint64_t reserved_35_63 : 29;
900 struct cvmx_l2d_fus3_cn38xx {
901 #ifdef __BIG_ENDIAN_BITFIELD
902 uint64_t reserved_36_63 : 28;
903 uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general
905 If the FUSE is not-blown, then this bit should read
906 as 0. If the FUSE is blown, then this bit should read
908 *** NOTE: Pass2 Addition */
909 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
911 If the FUSE is not-blown, then this bit should read
912 as 0. If the FUSE is blown, then this bit should read
914 *** NOTE: Pass2 Addition */
915 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
916 This is purely for debug and not needed in the general
918 Note that the fuses are complementary (Assigning a
919 fuse to 1 will read as a zero). This means the case
920 where no fuses are blown result in these csr's showing
922 Failure \#1 Fuse Mapping
924 [13:7] bad high column
926 Failure \#2 Fuse Mapping
928 [30:24] bad high column
929 [23:17] bad low column */
932 uint64_t crip_512k : 1;
933 uint64_t crip_256k : 1;
934 uint64_t reserved_36_63 : 28;
937 struct cvmx_l2d_fus3_cn38xx cn38xxp2;
938 struct cvmx_l2d_fus3_cn50xx {
939 #ifdef __BIG_ENDIAN_BITFIELD
940 uint64_t reserved_40_63 : 24;
941 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
942 These bits are used to 'observe' the EMA[2:0] inputs
943 for the L2 Data Store RAMs which are controlled by
944 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
945 From poweron (dc_ok), the EMA_CTL are driven from
946 FUSE[141:140]. However after the 1st CSR write to the
947 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
948 from the MIO_FUSE_EMA[EMA] register permanently
950 uint64_t reserved_36_36 : 1;
951 uint64_t crip_32k : 1; /**< This is purely for debug and not needed in the general
953 If the FUSE is not-blown, then this bit should read
954 as 0. If the FUSE is blown, then this bit should read
956 uint64_t crip_64k : 1; /**< This is purely for debug and not needed in the general
958 If the FUSE is not-blown, then this bit should read
959 as 0. If the FUSE is blown, then this bit should read
961 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
962 This is purely for debug and not needed in the general
964 Note that the fuses are complementary (Assigning a
965 fuse to 1 will read as a zero). This means the case
966 where no fuses are blown result in these csr's showing
968 Failure \#1 Fuse Mapping
969 [16:14] UNUSED (5020 uses single physical bank per quad)
970 [13:7] bad high column
972 Failure \#2 Fuse Mapping
973 [33:31] UNUSED (5020 uses single physical bank per quad)
974 [30:24] bad high column
975 [23:17] bad low column */
978 uint64_t crip_64k : 1;
979 uint64_t crip_32k : 1;
980 uint64_t reserved_36_36 : 1;
981 uint64_t ema_ctl : 3;
982 uint64_t reserved_40_63 : 24;
985 struct cvmx_l2d_fus3_cn52xx {
986 #ifdef __BIG_ENDIAN_BITFIELD
987 uint64_t reserved_40_63 : 24;
988 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
989 These bits are used to 'observe' the EMA[2:0] inputs
990 for the L2 Data Store RAMs which are controlled by
991 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
992 From poweron (dc_ok), the EMA_CTL are driven from
993 FUSE[141:140]. However after the 1st CSR write to the
994 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
995 from the MIO_FUSE_EMA[EMA] register permanently
997 uint64_t reserved_36_36 : 1;
998 uint64_t crip_128k : 1; /**< This is purely for debug and not needed in the general
1000 If the FUSE is not-blown, then this bit should read
1001 as 0. If the FUSE is blown, then this bit should read
1003 uint64_t crip_256k : 1; /**< This is purely for debug and not needed in the general
1005 If the FUSE is not-blown, then this bit should read
1006 as 0. If the FUSE is blown, then this bit should read
1008 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1009 This is purely for debug and not needed in the general
1011 Note that the fuses are complementary (Assigning a
1012 fuse to 1 will read as a zero). This means the case
1013 where no fuses are blown result in these csr's showing
1015 Failure \#1 Fuse Mapping
1016 [16:14] UNUSED (5020 uses single physical bank per quad)
1017 [13:7] bad high column
1018 [6:0] bad low column
1019 Failure \#2 Fuse Mapping
1020 [33:31] UNUSED (5020 uses single physical bank per quad)
1021 [30:24] bad high column
1022 [23:17] bad low column */
1024 uint64_t q3fus : 34;
1025 uint64_t crip_256k : 1;
1026 uint64_t crip_128k : 1;
1027 uint64_t reserved_36_36 : 1;
1028 uint64_t ema_ctl : 3;
1029 uint64_t reserved_40_63 : 24;
1032 struct cvmx_l2d_fus3_cn52xx cn52xxp1;
1033 struct cvmx_l2d_fus3_cn56xx {
1034 #ifdef __BIG_ENDIAN_BITFIELD
1035 uint64_t reserved_40_63 : 24;
1036 uint64_t ema_ctl : 3; /**< L2 Data Store EMA Control
1037 These bits are used to 'observe' the EMA[2:0] inputs
1038 for the L2 Data Store RAMs which are controlled by
1039 either FUSES[142:140] or by MIO_FUSE_EMA[EMA] CSR.
1040 From poweron (dc_ok), the EMA_CTL are driven from
1041 FUSE[141:140]. However after the 1st CSR write to the
1042 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
1043 from the MIO_FUSE_EMA[EMA] register permanently
1045 uint64_t reserved_36_36 : 1;
1046 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
1048 If the FUSE is not-blown, then this bit should read
1049 as 0. If the FUSE is blown, then this bit should read
1051 *** NOTE: Pass2 Addition */
1052 uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general
1054 If the FUSE is not-blown, then this bit should read
1055 as 0. If the FUSE is blown, then this bit should read
1057 *** NOTE: Pass2 Addition */
1058 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1059 This is purely for debug and not needed in the general
1061 Note that the fuses are complementary (Assigning a
1062 fuse to 1 will read as a zero). This means the case
1063 where no fuses are blown result in these csr's showing
1065 Failure \#1 Fuse Mapping
1067 [13:7] bad high column
1068 [6:0] bad low column
1069 Failure \#2 Fuse Mapping
1071 [30:24] bad high column
1072 [23:17] bad low column */
1074 uint64_t q3fus : 34;
1075 uint64_t crip_1024k : 1;
1076 uint64_t crip_512k : 1;
1077 uint64_t reserved_36_36 : 1;
1078 uint64_t ema_ctl : 3;
1079 uint64_t reserved_40_63 : 24;
1082 struct cvmx_l2d_fus3_cn56xx cn56xxp1;
1083 struct cvmx_l2d_fus3_cn58xx {
1084 #ifdef __BIG_ENDIAN_BITFIELD
1085 uint64_t reserved_39_63 : 25;
1086 uint64_t ema_ctl : 2; /**< L2 Data Store EMA Control
1087 These bits are used to 'observe' the EMA[1:0] inputs
1088 for the L2 Data Store RAMs which are controlled by
1089 either FUSES[141:140] or by MIO_FUSE_EMA[EMA] CSR.
1090 From poweron (dc_ok), the EMA_CTL are driven from
1091 FUSE[141:140]. However after the 1st CSR write to the
1092 MIO_FUSE_EMA[EMA] bits, the EMA_CTL will source
1093 from the MIO_FUSE_EMA[EMA] register permanently
1095 uint64_t reserved_36_36 : 1;
1096 uint64_t crip_512k : 1; /**< This is purely for debug and not needed in the general
1098 If the FUSE is not-blown, then this bit should read
1099 as 0. If the FUSE is blown, then this bit should read
1101 *** NOTE: Pass2 Addition */
1102 uint64_t crip_1024k : 1; /**< This is purely for debug and not needed in the general
1104 If the FUSE is not-blown, then this bit should read
1105 as 0. If the FUSE is blown, then this bit should read
1107 *** NOTE: Pass2 Addition */
1108 uint64_t q3fus : 34; /**< Fuse Register for QUAD3
1109 This is purely for debug and not needed in the general
1111 Note that the fuses are complementary (Assigning a
1112 fuse to 1 will read as a zero). This means the case
1113 where no fuses are blown result in these csr's showing
1115 Failure \#1 Fuse Mapping
1117 [13:7] bad high column
1118 [6:0] bad low column
1119 Failure \#2 Fuse Mapping
1121 [30:24] bad high column
1122 [23:17] bad low column */
1124 uint64_t q3fus : 34;
1125 uint64_t crip_1024k : 1;
1126 uint64_t crip_512k : 1;
1127 uint64_t reserved_36_36 : 1;
1128 uint64_t ema_ctl : 2;
1129 uint64_t reserved_39_63 : 25;
1132 struct cvmx_l2d_fus3_cn58xx cn58xxp1;
1134 typedef union cvmx_l2d_fus3 cvmx_l2d_fus3_t;